 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| TABLE OF CONTENTS LCD SEGMENT / COMMON DRIVER WITH CONTROLLER ..................................................................... 1 FEATURES ................................................................................................................................................... 1 ORDERING INFORMATION ........................................................................................................................ 2 BLOCK DIAGRAM ....................................................................................................................................... 3 DIE PAD ARRANGEMENT .......................................................................................................................... 4 DIE PAD ARRANGEMENT .......................................................................................................................... 4 PIN DESCRIPTION....................................................................................................................................... 6 MSTAT..................................................................................................................................................... 6 M .............................................................................................................................................................. 7 CL ............................................................................................................................................................ 7 DOF DOF.................................................................................................................................................. 7 CS1 , CS2 ................................................................................................................................................ 7 RES RES ................................................................................................................................................. 7 SA0, SCL, SDAout, SDAin ........................................................................................................................ 7 VDD ........................................................................................................................................................... 7 VSS ............................................................................................................................................................ 7 VSS1 .......................................................................................................................................................... 7 VEE ............................................................................................................................................................ 7 C1P, C1N, C2N, C2P C3N and C4N................................................................................................................. 7 VL2, VL3, VL4 and VL5 ................................................................................................................................ 8 VL6 ............................................................................................................................................................ 8 M/ S ......................................................................................................................................................... 8 VF ............................................................................................................................................................. 8 CLS .......................................................................................................................................................... 8 IIC1 , IIC2 ................................................................................................................................................. 8 i C1, C0 ...................................................................................................................................................... 9 ROW0 - ROW63 ...................................................................................................................................... 9 SEG0 - SEG103....................................................................................................................................... 9 ICONS...................................................................................................................................................... 9 IRS ........................................................................................................................................................... 9 TEST0-TEST7 ......................................................................................................................................... 9 NC/T0 - T6 .............................................................................................................................................. 9 FUNCTIONAL BLOCK DESCRIPTIONS................................................................................................... 11 IIC Communication Interface .............................................................................................................. 11 Command Decoder .............................................................................................................................. 11 Graphic Display Data RAM (GDDRAM).............................................................................................. 11 LCD Driving Voltage Generator and Regulator ................................................................................ 13 Oscillator Circuit .................................................................................................................................. 15 Reset Circuit ......................................................................................................................................... 16 Display Data Latch............................................................................................................................... 16 HV Buffer Cell (Level Shifter).............................................................................................................. 16 Level Selector....................................................................................................................................... 16 LCD Panel Driving Waveform ............................................................................................................. 17 COMMAND TABLE .................................................................................................................................... 17 COMMAND TABLE .................................................................................................................................... 18 I C-bus Write data and read register status ...................................................................................... 21 COMMAND DESCRIPTIONS ..................................................................................................................... 24 Set Lower Column Address ................................................................................................................ 24 Set Higher Column Address ............................................................................................................... 24 Set Internal Regulator Resistors Ratio .............................................................................................. 24 Set Power Control Register ................................................................................................................ 24 Set Display Start Line .......................................................................................................................... 24 Set Contrast Control Register ............................................................................................................ 24 Set Segment Re-map ........................................................................................................................... 25 2 ii Set LCD Bias ........................................................................................................................................ 25 Set Entire Display On/Off .................................................................................................................... 25 Set Normal/Inverse Display ................................................................................................................ 25 Set Display On/Off ............................................................................................................................... 25 Set Page Address ................................................................................................................................ 25 Set COM Output Scan Direction......................................................................................................... 25 Set Read-Modify-Write Mode .............................................................................................................. 25 Software Reset ..................................................................................................................................... 26 Set End of Read-Modify-Write Mode.................................................................................................. 26 Set Indicator On/Off ............................................................................................................................. 26 NOP ....................................................................................................................................................... 26 Set Test Mode....................................................................................................................................... 26 Set Power Save Mode.......................................................................................................................... 26 EXTENDED COMMANDS..................................................................................................................... 26 Set Multiplex Ratio............................................................................................................................... 27 Set Bias Ratio....................................................................................................................................... 27 Set Temperature Coefficient (TC) Value ............................................................................................ 27 Modify Oscillator Frequency .............................................................................................................. 27 Set 1/4 Bias Ratio................................................................................................................................. 27 Set Total Frame Phases ...................................................................................................................... 27 Set Display Offset ................................................................................................................................ 28 Enable Band Gap Reference Circuit .................................................................................................. 28 MAXIMUM RATINGS ................................................................................................................................. 30 DC CHARACTERISTICS............................................................................................................................ 31 AC CHARACTERISTICS............................................................................................................................ 33 APPLICATION EXAMPLES ....................................................................................................................... 36 INITIALIZATION ROUTINE ........................................................................................................................ 39 iii SOLOMON SYSTECH LIMITED SEMICONDUCTOR TECHNICAL DATA SSD0817 Advance Information CMOS LCD Segment / Common Driver with Controller SSD0817 is a single-chip CMOS LCD driver with controllers for dot-matrix graphic liquid crystal display system. It consists of 169 high-voltage driving outputs for driving maximum 104 Segments, 64 Commons and 1 icon line. SSD0817 consists of 104 x 65 bits Graphic Display Data RAM (GDDRAM). Data/Commands are sent 2 from common MCU through I C-bus Interface. SSD0817 embeds DC-DC Converter with booster capacitors, On-Chip Oscillator and Bias Divider so as to reduce the number of external components. With the advanced design for low power consumption, stable LCD operating voltage and flexible die layout, SSD0817 is suitable for any portable battery-driven applications requiring long operation period with compact size. FEATURES 104 x 64 + 1 Icon Line Single Supply Operation, 2.4 V - 3.5V Minimum -12.0V LCD Driving Output Voltage Low Current Sleep Mode On-Chip Voltage Generator or External LCD Driving Power Supply Selectable 2X / 3X / 4X/ 5X On-Chip DC-DC Converter On-Chip Oscillator On-Chip Bias Divider Programmable bias ratio [1/4 - 1/9] 2 I C-bus Interface On-Chip 104 X 65 Graphic Display Data RAM Row Re-mapping and Column Re-mapping Vertical Scrolling Display Offset Control 64 Levels Internal Contrast Control & External Contrast Control Programmable MUX ratio [2-64 MUX] (Partial display mode) Programmable LCD Driving Voltage Temperature Coefficients Available in Gold Bump Die This document contains information on a new product. Specification and information herein are subject to change without notice. Copyright 2003 SOLOMON Systech Limited Rev 1.3 01/2003 ORDERING INFORMATION Table 1 - Ordering Information Ordering Part Number SSD0817Z SEG 104 COM 64 + 1 Default Bias 1/9, 1/7 Package Form Gold Bump Die Reference SOLOMON Rev 1.3 01/2003 SSD0817 Series 2 BLOCK DIAGRAM ICONS ROW0 ~ ROW63 SEG0 ~SEG103 HV Buffer Cell Level Shifter Level Selector VL6 VL5 VL4 Display Data Latch MSTAT M DOF M/S CL CLS VL3 VL2 VDD Display Timing Generator Oscillator LCD Driving Voltage Generator 2X/ 3X/ 4X/ 5X DC/ DC Converter, Voltage Regulator, Contrast Control, Bias Divider with integrated capacitors, Temperature Compensation VF V EE V SS1 C4N C3N C 1P C1N C 2N C 2P IRS GDDRAM 104 X 65 Bits V SS VDD C0 C1 Command Decoder IIC communication interface /CS1 Test pins (TEST0 -TEST7), (T0 - T6) CS2 /RES /IIC1 IIC2 SDA out SDA in SCL SA 0 Figure 1 - SSD0817 Block Diagram 3 SSD0817 Series Rev 1.3 01/2003 SOLOMON DIE PAD ARRANGEMENT 26.25 ROW11 ROW12 ROW13 ROW14 ROW15 ROW16 ROW17 ROW18 ROW19 ROW20 ROW21 ROW22 ROW23 ROW24 ROW25 ROW26 ROW27 ROW28 ROW29 ROW30 ROW31 NC 26.25 26.25 26.25 26.25 26.25 NC 26.25 26.25 Center: 2751.9625, 323.6625 ROW10 ROW9 ROW8 ROW7 ROW6 ROW5 ROW4 ROW3 ROW2 ROW1 ROW0 ICONS SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 126 125 104 103 (2755.725, 237.475) SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 ROW32 ROW33 ROW34 ROW35 ROW36 ROW37 ROW38 ROW39 ROW40 ROW41 ROW42 ROW43 277 (-3878.7, 237.475) 254 255 276 1 T5 T4 VF IIC2 VSS IRS VDD C1 VSS Center (-3876.1625, 323.6625) C0 VDD /IIC1 TEST7 VSS CLS M/S VDD 8.75 T6 35 VL6 VL6 VL6 VL5 VL5 (-3878.7, 237.475) VL5 VL4 VL4 VL4 VEE VL3 VL3 VL3 VL2 VL2 VL2 VEE C4N C4N C4N C2P C2P C2P C2N C2N C2N VEE C1N C1N C1N C1P C1P C1P C3N C3N C3N T2 VEE VEE VEE VEE VEE VEE VSS1 VSS1 VSS1 VSS1 VSS1 VSS VSS VSS T1 T0 VDD VDD VDD VDD VDD VDD VDD TEST6 TEST5 SA0 SCL TEST4 TEST3 SDA in SDA out VDD TEST2 TEST1 VSS TEST0 VEE VEE /RES VDD CS2 /CS1 VSS /DOF CL M MSTAT X 26.25 26.25 X Center (2751.9625, 323.6625) 52.5 8.75 35 X X (2755.725, 237.475) Note: 1. The gold bumps face up in this diagram 2. All dimensions in m and (0,0) is the center of the chip 8.66 mm X 1.48 mm 550 +/- 25 um 60 um [Min] Nominal 18 um < 4 um within die < 8 um within lot Die Size: Die Thickness: Bump Pitch: Bump Height: Tolerance Center: -3875.55, 149.275 Size: 88.2 x 88.2 Gold Bump Alignment Mark This alignment mark contains gold bump for IC bumping process alignment and IC identifications. No conductive tracks should be laid underneath this mark to avoid short circuit. Center: -3876.1625, 323.6625 16.8 13.65 12.6 PIN #1 16.8 13.65 12.6 73.5 Center (3875.55, 149.275) 73.5 Figure 2 - SSD0817 Pin Assignment SOLOMON Rev 1.3 01/2003 SSD0817 Series 4 Table 2 - SSD0817 Series Bump Die Pad Coordinates (Bump center) Pad # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Signal MSTAT M CL /DOF VSS /CS1 CS2 VDD /RES VEE VEE TEST0 VSS TEST1 TEST2 VDD SDA out SDA in TEST3 TEST4 SCL SA0 TEST5 TEST6 VDD VDD VDD VDD VDD VDD VDD T0 T1 VSS VSS VSS VSS1 VSS1 VSS1 VSS1 VSS1 VEE VEE VEE VEE VEE VEE T2 C3N C3N X-pos -3873.80 -3797.50 -3721.20 -3644.90 -3568.60 -3492.30 -3416.00 -3339.70 -3263.40 -3178.35 -3102.05 -3017.00 -2940.70 -2864.40 -2788.10 -2711.80 -2635.50 -2557.63 -2481.33 -2403.10 -2325.23 -2248.93 -2172.63 -2096.33 -2020.03 -1943.73 -1867.43 -1791.13 -1714.83 -1638.53 -1562.23 -1485.93 -1409.63 -1333.33 -1257.03 -1180.73 -1095.68 -1019.38 -943.08 -866.78 -790.48 -714.18 -637.88 -561.58 -485.28 -408.98 -332.68 -256.38 -180.08 -103.78 Y-pos -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 Pad # 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Signal C3N C1P C1P C1P C1N C1N C1N VEE C2N C2N C2N C2P C2P C2P C4N C4N C4N VEE VL2 VL2 VL2 VL3 VL3 VL3 VEE VL4 VL4 VL4 VL5 VL5 VL5 VL6 VL6 VL6 T6 VDD M/S CLS VSS TEST7 /IIC1 VDD C0 VSS C1 VDD IRS VSS IIC2 VF X-pos -27.48 48.83 125.13 201.43 277.73 354.03 430.33 506.63 582.93 659.23 735.53 811.83 888.13 964.43 1040.73 1117.03 1193.33 1269.63 1345.93 1422.23 1498.53 1574.83 1651.13 1727.43 1803.73 1880.03 1956.33 2032.63 2108.93 2185.23 2261.53 2337.83 2414.13 2490.60 2566.73 2651.78 2728.08 2804.38 2880.68 2956.98 3033.28 3109.58 3185.88 3262.18 3338.48 3414.78 3491.08 3567.38 3643.68 3723.65 Y-pos -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 Pad # 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Signal T4 T5 NC ROW31 ROW30 ROW29 ROW28 ROW27 ROW26 ROW25 ROW24 ROW23 ROW22 ROW21 ROW20 ROW19 ROW18 ROW17 ROW16 ROW15 ROW14 ROW13 ROW12 ROW11 NC ROW10 ROW9 ROW8 ROW7 ROW6 ROW5 ROW4 ROW3 ROW2 ROW1 ROW0 ICONS SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 X-pos 3799.95 3876.25 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 3834.60 3774.40 3714.20 3654.00 3593.80 3533.60 3473.40 3413.20 3353.00 3292.80 3232.60 3172.40 3112.20 3052.00 2991.80 2931.60 2871.40 2811.20 2751.00 2690.80 2630.60 2570.40 2510.20 2450.00 2389.80 Y-pos -581.35 -581.35 -655.03 -594.83 -534.63 -474.43 -414.23 -354.03 -293.83 -233.63 -173.43 -113.23 -53.03 7.18 67.38 127.58 187.78 247.98 308.18 368.38 428.58 488.78 548.98 609.18 663.25 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 5 SSD0817 Series Rev 1.3 01/2003 SOLOMON Pad # 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 195 196 197 198 199 200 Signal SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 X-pos 2329.60 2269.40 2209.20 2149.00 2088.80 2028.60 1968.40 1908.20 1848.00 1787.80 1727.60 1667.40 1607.20 1547.00 1486.80 1426.60 1366.40 1306.20 1246.00 1185.80 1125.60 1065.40 1005.20 945.00 884.80 824.60 764.40 644.00 583.80 523.60 463.40 403.20 343.00 282.80 222.60 162.40 102.20 42.00 -18.20 -78.40 -138.60 -198.80 -319.20 -379.40 -439.60 -499.80 -560.00 -620.20 Y-pos 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 Pad # 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 245 246 247 248 249 250 Signal SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 ROW32 ROW33 ROW35 ROW36 ROW37 ROW38 ROW39 ROW40 X-pos -680.40 -740.60 -800.80 -861.00 -921.20 -981.40 -1041.60 -1101.80 -1162.00 -1222.20 -1282.40 -1342.60 -1402.80 -1463.00 -1523.20 -1583.40 -1643.60 -1703.80 -1764.00 -1824.20 -1884.40 -1944.60 -2004.80 -2065.00 -2125.20 -2185.40 -2245.60 -2366.00 -2426.20 -2486.40 -2546.60 -2606.80 -2667.00 -2727.20 -2787.40 -2847.60 -2907.80 -2968.00 -3028.20 -3088.40 -3148.60 -3208.80 -3329.20 -3389.40 -3449.60 -3509.80 -3570.00 -3630.20 Y-pos 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 Pad # 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 Signal ROW41 ROW42 ROW43 NC ROW44 ROW45 ROW46 ROW47 ROW48 ROW49 ROW50 ROW51 ROW52 ROW53 ROW54 ROW55 ROW56 ROW57 ROW58 ROW59 ROW60 ROW61 ROW62 ROW63 ICONS NC NC X-pos -3690.40 -3750.60 -3810.80 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -3875.55 Y-pos 587.83 587.83 587.83 663.25 609.18 548.98 488.78 428.58 368.38 308.18 247.98 187.78 127.58 67.38 7.18 -53.03 -113.23 -173.43 -233.63 -293.83 -354.03 -414.23 -474.43 -534.63 -594.83 -655.03 149.28 Bump Size PAD# 1 - 102 103 - 124 125 126 - 253 254 255 - 276 277 X [um] 50.05 66.675 66.675 40.95 66.675 66.675 88.2 Y [um] 50.05 40.95 28.7 66.675 28.7 40.95 88.2 PIN DESCRIPTION MSTAT This pin is the static indicator driving output. It is only active in master operation. The frame signal output pin, M, should be used as the back plane signal for the static indicator. The duration of overlapping can be programmable. This pin, MSTAT, becomes high impedance if the chip is operating in slave mode. Please see the Extended Command Table for reference. 6 SOLOMON Rev 1.3 01/2003 SSD0817 Series M This pin is the frame signal input/output. In master mode, this pin supplies the frame signal to slave devices. In slave mode, this pin receives the frame signal from the master device. CL This pin is the system clock input/output. When both the internal oscillator (CLS pin pulled high) and the master mode (M/S pin pulled high) are enabled, the CL pin will supplies system clock signal to the slave device. When both internal oscillator and the slave mode are enabled, the CL pin receives system clock signal from either the master device or the external clock source. DOF DOF This pin is the display blanking signal control pin. In master mode, the DOF pin supplies "display on" or "display off" signal (blanking signal) to the slave devices. In slave mode, the DOF pin receives "display on" or "display off" signal from the master device. CS1 , CS2 These pins are the chip selection inputs. The chip is enabled for MCU communication only when CS1 is pulled low and CS2 is pulled high. RES RES This pin is the reset signal input. Initialization of the chip is started once the reset pin is pulled low. The minimum pulse width for completion of the reset procedure is 5 -10 us. SA0, SCL, SDAout, SDAin These pins are bi-directional data bus to be connected to the MCU in I C-bus interface. Please refer 2 to the section: I C Communication interface on page 11 for detail pin descriptions. 2 VDD The VDD is the Chip's Power Supply pins. VDD is also acted as a reference level of both the DC-DC Converter and the LCD driving output. VSS The Vss is the grounding of the chip. Vss is also acted as a reference level of the logic input/output. VSS1 The VSS1 is the input of the internal DC-DC converter. The generated voltage from the internal DC-DC converter, VEE, is equal to the multiple factors (2X, 3X, 4X, 5X) times the potential different between VSS1, and VDD. The multiple factors, 2X, 3X, 4X or 5X are selected by different arrangements of the external boosting capacitors. Note: the potential at this input pin must lower than or equal to VSS. VEE This is the most negative voltage supply pin of the chip. It can be supplied externally or generated by the internal DC-DC converter. If the internal DC-DC converter generates the voltage level at VEE, the voltage level is used for internal referencing only. The voltage level at VEE pins is not used for driving external circuitry. C1P, C1N, C2N, C2P C3N and C4N When internal DC-DC voltage converter is used, external capacitor(s) is/are connected between these pins. Different connections result in different DC-DC converter multiple factors, for example, 2X, 3X, 4X or 5X. Please refer to the voltage converter section in the functional block description for detail description. 7 SSD0817 Series Rev 1.3 01/2003 SOLOMON VL2, VL3, VL4 and VL5 These pins are outputs with voltage levels equal to the LCD driving voltage. All these voltage levels are referenced to VDD. The voltage levels can be supplied externally or generated by the internal bias divider. The bias divider is turned on once the output op-amp buffers are enabled. Please refer to the Set Power Control Register command for detail description. The voltage potential relationship is given as: VDD > VL2 > VL3 > VL4 > VL5 > VL6 In addition, assume the bias factor is known as a, VL2 - VDD = 1/a * (VL6 - VDD) VL3 - VDD = 2/a * (VL6 - VDD) VL4 - VDD = (a-2)/a * (VL6 - VDD) VL5 - VDD = (a-1)/a * (VL6 - VDD) VL6 This pin outputs the most negative LCD driving voltage level. The VL6 can be supplied externally or generated by the internal regulator. Please refer to the Set Power Control Register command for detail description. M/ S This pin is the master/slave mode selection input. When this pin is pulled high, master mode is selected. CL, M, MSTAT and DOF signals will become output pins of the slave devices. When this pin is pulled low, slave mode is selected. CL, M, DOF will become input pins. The CL, M, DOF signals are received from the master device. The MSTAT pin will stay at high impedance state. VF This pin is the input of the built-in voltage regulator for generating VL6. When external resistor network is selected (IRS pulled low) to generate the LCD driving level, VL6, two external resistors should be added. R1 should be connected between VDD and VF. R2 should be connected between VF and VL6. CLS This pin is the internal clock enable pin. When this pin is pulled high, the internal clock is enabled. The internal clock will be disabled when CLS is pulled low. Under such circumstances, an external clock source must be fed into the CL pin. IIC1 , IIC2 2 These pins are I C-bus interface selection inputs. The IIC communication interface is enabled only when IIC1is pulled low and IIC2 is pulled high. SOLOMON Rev 1.3 01/2003 SSD0817 Series 8 C1, C0 These two pins are the Chip Mode Selection input. The chip mode is determined by multiplex ratio. Altogether there are four chip modes. Please see the following list for reference. C1 0 0 1 1 C0 0 1 0 1 Chip Mode 48 MUX Mode 54 MUX Mode 32 MUX Mode 64 MUX Mode ROW0 - ROW63 These pins provide the driving signals, COMMON, to the LCD panel. Please refer to the Table 3 on Page 10 for the COM signal mapping in different MUX. SEG0 - SEG103 These pins provide the LCD driving signals, SEGMENT, to the LCD panel. The output voltage level of these pins is VDD during sleep mode or standby mode. ICONS There are two ICONS pins (pin137 and 275) on the chip. Both pins output exactly the same signal. The duplicated ICON pins will enhance the flexibility of the LCD layout. IRS This is the input pin to enable the internal resistors network for the voltage regulator. When this pin is pulled high, the internal feedback resistors of the internal regulator for generating VL6 will be enabled. When it is pulled low, external resistors, R1 should be connected to VDD and VF. R2 should be connected between VF and VL6, respectively. TEST0-TEST7 These are input pins that reserved for testing purpose. These pins should be connected to VDD. NC/T0 - T6 These are the No Connection pins. These pins should be left open and they are prohibited to have any connections with one another. 9 SSD0817 Series Rev 1.3 01/2003 SOLOMON Table 3 - Example of ROW pin assignment for different programmable MUX of SSD0817 ROW0 ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 ROW8 ROW9 ROW10 ROW11 ROW12 ROW13 ROW14 ROW15 ROW16 ROW17 ROW18 ROW19 ROW20 ROW21 ROW22 ROW23 ROW24 ROW25 ROW26 ROW27 ROW28 ROW29 ROW30 ROW31 ROW32 ROW33 ROW34 ROW35 ROW36 ROW37 ROW38 ROW39 ROW40 ROW41 ROW42 ROW43 ROW44 ROW45 ROW46 ROW47 ROW48 ROW49 ROW50 ROW51 ROW52 ROW53 ROW54 ROW55 ROW56 ROW57 ROW58 ROW59 ROW60 ROW61 ROW62 ROW63 48 MUX Mode COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 NC NC NC NC NC NC NC NC COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 NC NC NC NC NC NC NC NC 54 MUX Mode COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 NC NC NC NC NC COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 NC NC NC NC NC 32 MUX Mode COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC 64 MUX Mode COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 (Note: X - output non-selected COM signal) SOLOMON Rev 1.3 01/2003 SSD0817 Series 10 FUNCTIONAL BLOCK DESCRIPTIONS IIC communication Interface The IIC communication interface consists of slave address bit (SA0), I C-bus data signal (SDA) and 2 I C-bus clock signal (SCL). Both the SDA and the SCL must be connected to pull-up resistors. There are also five input signals including, RES , CS1 , IIC1, CS2, IIC2, which is used for the initialization of device. a) Slave address bit (SA0) SSD0817 have to recognize the slave address before transmitting or receiving any 2 information by the I C-bus. The device will responds to the slave address following by the slave address bit ("SA0" bit) and the read/write select bit ("R/W " bit) with the following byte format, b7 b6 b5 b4 b3 b2 b1 b0 0 1 1 1 1 0 SA0 R/W "SA0" bit provides an extension bit for the slave address. Either "0111100" or "0111101", can be selected as the slave address of SSD0817. 2 "R/W " bit determines the I C-bus interface is operating at either write mode or read status mode. 2 b) I C-bus data signal (SDA) SDA acts as a communication channel between the transmitter and the receiver. The data and the acknowledgement are sent through the SDA. If SDA in is connected to the "SDA out", the device becomes fully IIC bus compatible. It should be noticed that the ITO track resistance and the pulled-up resistance at "SDA" pin becomes a voltage potential divider. As a result, the acknowledgement would not be possible to attain a valid logic 0 level in "SDA". The "SDA out" pin may be disconnected from the "SDA in" pin. With such arrangement, the 2 acknowledgement signal will be ignored in the I C-bus. 2 c) I C-bus clock signal (SCL) 2 The transmission of information in the I C-bus is following a clock signal, SCL. Each transmission of data bit is taken place during a single clock period of SCL. 2 Command Decoder Input is directed to the command decoder based on the input of control byte which consists of a 2 D/ C bit and a R/W bit. For further information about the control byte, please refer to the section "I Cbus Write data and read register status" on page 21. If both the D/ C bit and the R/W bit are low, the input signal is interpreted as a Command. It will be decoded and written to the corresponding command register. If the D/ C bit is high and the R/W bit is low, input signal is written to Graphic Display Data RAM (GDDRAM). Graphic Display Data RAM (GDDRAM) The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is 104 x 65 = 6760 bits. Table 4 on Page 12 is a description of the GDDRAM address map. For mechanical flexibility, re-mapping on both Segment and Common outputs can be selected by software. During the vertical scrolling of the display, an internal register (display start line register) stores the address of the display start line. The re-mapping operation can be started at the address of the display start line according to the internal register. Table 4 on Page 12 shows the case in which the display start line register is set to 38h. For those GDDRAM out of the display common range, they can be accessed for either the preparation of vertical scrolling data or the system usage. 11 SSD0817 Series Rev 1.3 01/2003 SOLOMON Common Pins 48 MUX Mode RAM Row 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh Page 8 Page 7 Page 6 Page 5 Page 4 Page 3 Page 2 Page 1 Page 0 RAM Column Normal Remapped D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) D0 (LSB) Segment Pins 0 1 2 3 00h 67h 01h 66h 02h 65h 03h 64h ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** 100 101 102 103 64h 03h 65h 02h 66h 01h 67h 00h Normal 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 X X X X X X X X X X X X X X X X 0 1 2 3 4 5 6 7 ICONS Remapped 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X 47 46 45 44 43 42 41 40 ICONS 54 MUX Mode Normal 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 X X X X X X X X X X 0 1 2 3 4 5 6 7 ICONS Remapped 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X 53 52 51 50 49 48 47 46 ICONS 32 MUX Mode Normal 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 2 3 4 5 6 7 ICONS Remapped 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 31 30 29 28 27 26 25 24 ICONS 64 MUX Mode Normal 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 0 1 2 3 4 5 6 7 ICONS Remapped 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 63 62 61 60 59 58 57 56 ICONS Remarks : DB0 - DB7 represent the data bit of the GDDRAM Table 4 - Graphic Display Data RAM (GDDRAM) Address Map with Display Start Line set to 38h LCD Driving Voltage Generator and Regulator SOLOMON Rev 1.3 01/2003 SSD0817 Series 12 LCD Driving Voltage Generator and Regulator This module generates the LCD voltage required for display driving output. With reference to VDD, it takes a single supply input, VSS, and generates all the necessary voltage levels. This block consists of: 1. 2X, 3X, 4X and 5X DC-DC voltage converter The built-in DC-DC voltage converter is used to generate the negative voltage with reference to VDD from the voltage input (VSS1). For SSD0817, it is possible to produce 2X, 3X, 4X or 5X boosting from the potential different between VSS1 - VDD. Detailed configurations of the DC-DC converter for different boosting multiples are given in Figure 3. SSD0817 VSS1 VEE C3N C1P C1N C2N C2P C4N + C1 + C1 + C1 + C1 + C1 5X Boosting Configuration VSS1 VEE SSD0817 C3N C1P C1N C2N C2P C4N + C1 + C1 + C1 + C1 4X Boosting Configuration SSD0817 C1P C1N VSS1 VEE C3N C2N C2P C4N + C1 + C1 C1 + 3X Boosting Configuration VSS1 VEE C3N SSD0817 C1P C1N C2N C2P C4N + C1 + C1 2X Boosting Configuration Remarks: 1. C1= 0.47 - 4.7uF 2. Boosting input from VSS1 3. VSS1 should be lower potential than or equal to VSS 4. All voltages are referenced to VDD Figure 3 - DC-DC Converter Configurations 2. Voltage Regulator (Voltages referenced to VDD) Internal (IRS pin = H) feedback gain can control the LCD driving contrast curves. If internal resistor network is enabled, eight settings can be selected through software command. If external control is selected, external resistors are connected between VDD and VF (R1), and between VF and VL6 (R2). 3. Contrast Control (Voltage referenced to VDD) Software control of the 64-contrast voltage levels at each voltage regulator feedback gain. The equation of calculating the LCD driving voltage is given as: 13 SSD0817 Series Rev 1.3 01/2003 SOLOMON VL6 -VDD = Gain * [1 + (18 + )] * Vref stands for the contrast set (0 to 63) 81 Gain = (1 + Rb/Ra), the reference value is shown in table 5. Register ratio Thermal Gradient o D2 D1 D0 = -0.07 %/ C 000 2.92 001 3.40 010 3.89 011 4.37 100 4.85 101 5.23 110 5.72 111 6.19 Table 5 Gain value at different register ratio and thermal gradient settings o Vref is a fixed IC-internal voltage supply and its voltage at room temperature (25 C) is shown in table 6 for reference. Type Thermal Vref Gradient o TC 0 -0.07 %/ C -1.08V TC 2 TC 4 TC 7 -0.13 %/ C -0.26 %/ C -0.29 %/ C o o o o -1.12V -1.09V -1.10V External resistor -0.07 %/ C -1.08V gain mode [Gain = 5.00] @ TC0 Table 6 Vref values at different thermal gradient settings The voltage regulator output for different gain/contrast settings is shown in figure 4. Figure 4 - Voltage Regulator Output for different Gain/Contrast Settings 4. Bias Ratio Selection circuitry The bias ratios can be software selected from 1/4, 1/5, 1/6, 1/7, 1/8 and 1/9. Since there will be slightly different in command pattern for different MUX, please refer to Command Descriptions section of this data sheet. If the output op-amp buffer option in Set Power Control Register command is enabled, this circuit block will divide the regulator output (VL6) to give the LCD driving levels (VL2 ~ VL5). A low power consumption circuit design in this bias divider saves most of the display current comparing to the traditional design. Stabilizing Capacitors (0.1uF ~ 0.47uF) are SOLOMON Rev 1.3 01/2003 SSD0817 Series 14 required to be connected between these voltage level pins (VL2 ~ VL5) and (VDD). If the LCD panel loading is heavy, four additional resistors are suggested to add to the application circuit as follows: SSD0817 SSD1815B VDD VL2 V L3 V L4 V L5 V L6 R3 R4 R2 R1 V DD C5 C4 C3 C2 C1 + + + + Remark: 1. C1C5 = 0.1uF ~ 0.47uF Remark: 1. C1 ~ ~ C5 = 0.01 ~ 0.47uF 2. R1 ~ R4~ R4 = 100k~ 1M 2. R1 = 100k ~1M 5. Self adjust temperature compensation circuitry This block provides 4 different compensation settings to satisfy various liquid crystal temperature grades by software control. The default temperature coefficient (TC) setting is TC0. Oscillator Circuit This module is an On-Chip low power RC oscillator circuitry (Figure 5). The oscillator generates the clock for the DC-DC voltage converter. This clock is also used in the Display Timing Generator. Oscillator enable enable Oscillation Circuit enable Buffer (CL) Internal resistor OSC1 OSC2 Figure 5 - On-Chip low power RC oscillator circuitry 15 + SSD0817 Series Rev 1.3 01/2003 SOLOMON Reset Circuit This block includes Power On Reset (POR) circuitry and the hardware reset pin, RES . The POR and Hardware reset performs the same reset function. Once RES receives a reset pulse, all internal circuitry will start to initialize. Minimum pulse width the reset sequence is 5 -10us. Status of the chip after reset is given by: Display is turned OFF Default Display Mode 64 MUX: 104 x 64 + 1 Icon Line Normal segment and display data column address mapping (Seg0 mapped to Row address 00h) Read-modify-write mode is OFF Power control register is set to 000b 2 Register data clear in I C-bus interface Bias ratio is set to default 64 MUX: 1/9 Static indicator is turned OFF Display start line is set to GDDRAM column 0 Column address counter is set to 00h Page address is set to 0 Normal scan direction of the COM outputs Contrast control register is set to 20h Test mode is turned OFF Temperature Coefficient is set to TC0 Display Data Latch This block is a series of latches carrying the display signal information. These latches hold the data, which will be fed to the HV Buffer Cell and Level Selector to output the required voltage level. The numbers of latches of different members are given by: 64 MUX: 104 + 65 = 169 HV Buffer Cell (Level Shifter) HV Buffer Cell works as a level shifter which translates the low voltage output signal to the required driving voltage. The output is shifted out with reference to the internal FRM clock which comes from the Display Timing Generator. The voltage levels are given by the level selector which is synchronized with the internal M signal. Level Selector Level Selector is a control of the display synchronization. Display voltage levels can be separated into two sets and used with different cycles. Synchronization is important since it selects the required LCD voltage level to the HV Buffer Cell, which in turn outputs the COM or SEG LCD waveform. SOLOMON Rev 1.3 01/2003 SSD0817 Series 16 LCD Panel Driving Waveform Figure 6 is an example of how the Common and Segment drivers may be connected to a LCD panel. The waveforms illustrate the desired multiplex scheme. COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 01234 GGGGG EEEEE * N+1 1 2 3 4 5 6 7 8 9 N+1 ... * TIME SLOT 1 2 3 4 5 6 7 89 * . . . N+1 1 2 3 4 5 6 7 8 9 N+1 1 2 3 4 5 6 7 8 9 . . .. * VDD VL2 COM0 VL3 VL4 VL5 VL6 VDD VL2 COM1 VL3 VL4 VL5 VL6 VDD VL2 SEG0 VL3 VL4 VL5 VL6 VDD VL2 SEG1 VL3 VL4 VL5 VL6 M * Note 1: N+1 is the number of multiplex ratio including Icon. Figure 6 - LCD Driving Waveform for Displaying "0" 17 SSD0817 Series Rev 1.3 01/2003 SOLOMON COMMAND TABLE Bit Pattern Command 0000X3X2X1X0 0001X3X2X1X0 00100X2X1X0 Set Lower Column Address Set Higher Column Address Set Internal Regulator Resistor Ratio 00101X2X1X0 Set Power Control Register 01X5X4X3X2X1X0 Set Display Start Line 10000001 ** X5X4X3X2X1X0 Set Contrast Control Register 1010000X0 Set Segment Re-map 1010001X0 Set LCD Bias Description Set the lower nibble of the column address register using X3X2X1X0 as data bits. The lower nibble of column address is reset to 0000b after POR Set the higher nibble of the column address register using X3X2X1X0 as data bits. The higher nibble of column address is reset to 0000b after POR. Feedback gain of the internal regulator generating VL6 increases as X2X1X0 increased from 000b to 111b. After POR, X2X1X0 = 100b X0=0: turns off the output op-amp buffer (POR) X0=1: turns on the output op-amp buffer X1=0: turns off the internal regulator (POR) X1=1: turns on the internal regulator X2=0: turns off the internal voltage booster (POR) X2=1: turns on the internal voltage booster Set GDDRAM display start line register from 0-63 using X5X4X3X2X1X0. Display start line register is reset to 000000 after POR. Select contrast level from 64 contrast steps. Contrast increases (VL6 decreases) as X5X4X3X2X1X0 is increased from 000000b to 111111b. X5X4X3X2X1X0 = 100000b after POR X0=0: column address 00h is mapped to SEG0 (POR) X0=1: column address 67h is mapped to SEG0 Refer to Table 4 on page 12 for example. X0=0: POR default bias 48 MUX Mode: 1/8 54 MUX Mode: 1/8.4 32 MUX Mode: 1/6 64 MUX Mode: 1/9 X0=1: alternate bias 48 MUX Mode: 1/6 54 MUX Mode: 1/6 32 MUX Mode: 1/5 64 MUX Mode: 1/7 1010010X0 1010011X0 1010111X0 1011X3X2X1X0 Set Entire Display On/Off Set Normal/Inverse Display Set Display On/Off Set Page Address 1100X3 * * * Set COM Output Scan Direction 11100000 11100010 11101110 1010110X0 SOLOMON Set Read-Modify-Write Mode Software Reset Set End of Read-Modify-Write Mode Indicator Display Mode For other bias ratio settings, see "Set 1/4 Bias Ratio" and "Set Bias Ratio" in Extended Command Set. X0=0: normal display (POR) X0=1: entire display on X0=0: normal display (POR) X0=1: inverse display X0=0: turns off LCD panel (POR) X0=1: turns on LCD panel Set GDDRAM Page Address (0-8) for read/write using X3X2X1X0 X3=0: normal mode (POR) X3=1: remapped mode, COM 0 to COM [N-1] becomes COM [N-1] to COM 0 when Multiplex ratio is equal to N. See Figure 5 on page 17 for detail mapping. Read-Modify-Write mode will be entered in which the column address will not be increased during display data read. After POR, Read-modify-write mode is turned OFF. Initialize internal status registers Exit Read-Modify-Write mode. RAM Column address before entering the mode will be restored. After POR, Read-modify-write mode is OFF. This second byte command is required ONLY when Rev 1.3 01/2003 SSD0817 Series 18 * * * * * * X1X0 Set Indicator On/Off 11100011 11110000 1111 * * * * 10101110 10100101 NOP Test Mode Reset Set Test Mode Set Power Save Mode "Set Indicator On" command is sent. X0 = 0: indicator off (POR, second command byte is not required) X0 = 1: indicator on (second command byte required) X1X0 = 00: indicator off X1X0 = 01: indicator on and blinking at ~1 second interval X1X0 = 10: indicator on and blinking at ~1/2 second interval X1X0 = 11: indicator on constantly Command result in No Operation Reserved for IC testing. Do NOT use Reserved for IC testing. Do NOT use. (Standby or Sleep) Standby or sleep mode will be entered using compound commands. Issue compound commands "Set Display Off" followed by "Set Entire Display On". Table 7 - Write Command Table (D/ C =0, R/W =0) Bit Pattern Command Description To select multiplex ratio N from 2 to the maximum multiplex ratio (POR value) for each member (including icon line). Max. MUX ratio: 64 MUX: 65 N = X5X4X3X2X1X0 + 2, e.g. N = 001111b + 2 = 17 For 64 MUX Mode X1X0 = 00(POR) 01 10 11 1/9 or 1/7 1/5 1/6 1/8 10101000 00X5X4X3X2X1X0 Set Multiplex Ratio Set Bias Ratio (X1X0) For 54 MUX Mode X1X0 = 00(POR) 01 10 11 1/8.4 or 1/6 1/5 1/6 1/8 For 48 MUX Mode X1X0 = 00(POR) 01 10 11 1/8 or 1/6 1/5 1/6 1/8 For 32 MUX Mode X1X0 = 00(POR) 01 10 1/6 or 1/5 1/5 1/6 Set TC Value (X4X3X2) 10101001 X7X6X5X4X3X2X1X0 11 1/8 o X4X3X2 = 000: (TC0) Typ. -0.07%/ C o X4X3X2 = 010: (TC1) Typ. -0.13%/ C o X4X3X2 = 100: (TC5) Typ. -0.26%/ C o X4X3X2 = 111: (TC7) Typ. -0.29%/ C X4X3X2 = 001, 011, 101, 110: Reserved Increase the value of X7X6X5 will increase the oscillator frequency and vice versa. Default Mode: X7X6X5 = 011 (POR for 48 MUX Mode, 54 MUX Mode) : Typ. 31.5kHz X7X6X5 = 011 (POR for 32 MUX Mode, 64 MUX Mode) : Typ. 18.7Hz Modify Osc. Freq. (X7X6X5) 19 SSD0817 Series Rev 1.3 01/2003 SOLOMON 1010101X0 Set 1/4 Bias Ratio Remarks: By software program the multiplex ratio, the typical oscillator frequency is listed above. X0 = 0: use normal setting (POR) X0 = 1: fixed at 1/4 bias regardless of other bias setting commands The On/Off of the Static Icon is given by 3 phases / 1 phase overlapping of the M and MSTAT signals. This command set total phases of the M/MSTAT signals for each frame. The more the total phases, the less the overlapping time and thus the lower the effective driving voltage. X5X4 = 00: 5 phases X5X4 = 01: 7 phases X5X4 = 10: 9 phases (POR) X5X4 = 11: 16 phases After POR, X5X4X3X2X1X0 = 0 After setting MUX ratio less than default value, data will be displayed at Center of display matrix. To move display towards Row 0 by L, X5X4X3X2X1X0 = L To move display away from Row 0 by L, X5X4X3X2X1X0 = 64-L Note: max. value of L = (POR default MUX ratio - display MUX)/2 X1X0 = 00 01 10 11(POR) 100 ms 200 ms 400 ms 800 ms Approx. band gap clock period This command should execute if divider is used without capacitor at VL2 to VL5. Recommendation: set the band gap clock period to approx. 200ms 11010100 00X5X40000 Set Total Frame Phases 11010011 00X5X4X3X2X1X0 Set Display Offset 11010110 001111X1X0 Enable Band Gap Reference Circuit Table 8 - Extended Command Table Note: Command patterns other than that given in Command Table and Extended Command Table are prohibited. Otherwise, unexpected result will occur. SOLOMON Rev 1.3 01/2003 SSD0817 Series 20 I2C-bus Write data and read register status The I C-bus interface gives access to write data and command into the device. Please refer to figure 2 7 for the write mode of I C-bus in chronological order. Note: Co - Continuation bit 2 D/ C - Data / Command Selection bit Write mode ACK - Acknowledgement SA0 - Slave address bit R/W - Read / Write Selection bit S - Start Condition / P - Stop Condition D/C Co ACK R/W SA0 ACK D/C Co ACK ACK P ACK S S 011110 Control byte Data byte Control byte Data byte Slave Address m 0 words 1 byte n 0 bytes MSB ...................LSB R/W SA0 011110 Read mode 011110 Status bytes SSD0817 Slave Address D/C Co ACK 000000 Slave Address Control byte ACK R/W SA0 P ACK Figure 7 I C-bus data format Write mode 1) The master device initiates the data communication by a start condition. The definition of the start condition is shown in figure 8 on page 22. The start condition is established by pulling the SDA from high to low while the SCL stays high. 2) The slave address is following the start condition for recognition use. For the SSD0817, the slave address is either "b0111100" or "b0111101" by changing the SA0 to high or low. 3) The write mode is established by setting the R/W bit to logic "0". 4) An acknowledgement signal will be generated after receiving one byte of data, including the slave address and the R/W bit. Please refer to the figure 9 on page 22 for the graphical representation of the acknowledge signal. The acknowledge bit is defined as the SDA line is pulled down during the high period of the acknowledgement related clock pulse. 5) After the transmission of the slave address, either the control byte or the data byte may be sent across the SDA. A control byte mainly consists of Co and D/ C bits following by six "0" `s. a. If the Co bit is set as logic "0", the transmission of the following information will contain data bytes only. 2 21 SSD0817 Series Rev 1.3 01/2003 SOLOMON b. The D/ C bit determines the next data byte is acted as a command or a data. If the D/ C bit is set to logic "0", it defines the following data byte as a command. If the D/ C bit is set to logic "1", it defines the following data byte as a data which will be stored at the GDDRAM. The GDDRAM column address pointer will be increased by one automatically after each data write. 6) Acknowledge bit will be generated after receiving each control byte or data byte. 7) The write mode will be finished when a stop condition is applied. The stop condition is also defined in figure 8 on page 22. The stop condition is established by pulling the "SDA in" from low to high while the "SCL" stays high. TDH, START TDS, STOP SDA SDA SCL S START condition P STOP condition SCL Figure 8 Definition of the start and stop condition DATA OUTPUT BY TRANSMITTER Non-acknowledge DATA OUTPUT BY RECEIVER Acknowledge SCL FROM MASTER S START Condition Clock pulse for acknowledgement 1 2 8 9 Figure 9 Definition of the acknowledgement condition Please be noted that the transmission of the data bit has some limitations. 1. The data bit, which is transmitted during each SCL pulse, must keep at a stable state within the "high" period of the clock pulse. Please refer to the figure 10 for graphical representations. Except in start or stop conditions, the data line can be switched only when the SCL is low. 2. Both the data line (SDA) and the clock line (SCL) should be pulled up by external resistors. SOLOMON Rev 1.3 01/2003 SSD0817 Series 22 SDA SCL data line is stable; data is valid Change of data is allowed Figure 10 Definition of the data transfer condition Read mode (Read status register) 1) The master device firstly initiates the data communication by a start condition. The definition of the start condition is shown in figure 8 on page 22. 2) The slave address is following the start condition for recognition use. For the SSD0817, the slave address is either "b0111100" or "b0111101". 3) The read mode is established by setting R/W bit to logic "1". The read mode allows the MCU to monitor the internal status of the chip. 4) An acknowledgement signal will be generated after sending one byte of data, including the slave address and the R/W bit. Please refer to the figure 9 on page 22 for the graphical representation of the acknowledge signal. 5) The status of the register will be read at the next status byte. Please refer to the Table 9 for the explanation of the status byte. 6) The read mode will be finished when a stop condition is applied. The stop condition is also defined in figure 8 on page 22. S7=0: indicates the driver is ready for command. S7=1: indicates the driver is Busy. S6=0: indicates reverse segment mapping with column address. S6=1: indicates normal segment mapping with column address. S5=0: indicates the display is ON. S5=1: indicates the display is OFF. S4=0: initialization is completed. S4=1: initialization process is in progress after RES or software reset. S3S2S1S0 = 1001, the 4-bit is fixed to 1001 which could be used to identify as Solomon-Systech Device. S7S6S5S4S3S2S1S0 Status Register Read Table 9 - Read Command Table (R/W bit =1) 23 SSD0817 Series Rev 1.3 01/2003 SOLOMON COMMAND DESCRIPTIONS Set Lower Column Address This command specifies the lower nibble of the 8-bit column address of the display data RAM. The column address will be increased by each data access after it is pre-set by the MCU. Set Higher Column Address This command specifies the higher nibble of the 8-bit column address of the display data RAM. The column address will be increased by each data access after it is pre-set by the MCU. Set Internal Regulator Resistors Ratio This command is to enable any one of the eight internal resistor sets for different regulator gain when using internal regulator resistor network (IRS pin pulled high). In other words, this command is used to select which contrast curve from the eight possible selections. Please refer to Functional Block Descriptions section for detail calculation of the LCD driving voltage. Set Power Control Register This command turns on/off the various power circuits associated with the chip. There are three related power sub-circuits could be turned on/off by this command. Internal voltage booster is used to generate the negative voltage supply (VEE) from the voltage input (VSS1 - VDD). An external negative power supply is required if this option is turned off. Internal regulator is used to generate the LCD driving voltage, VL6, from the negative power supply, VEE. Output op-amp buffer is the internal divider for dividing the different voltage levels (VL2, VL3, VL4, VL5) from the internal regulator output, VL6. External voltage sources should be fed into this driver if this circuit is turned off. Set Display Start Line This command is to set Display Start Line register to determine starting address of display RAM to be displayed by selecting a value from 0 to 63. With value equals to 0, D0 of Page 0 is mapped to COM0. With value equals to 1, D1 of Page0 is mapped to COM0 and so on. Display start line values of 0 to 63 are assigned to Page 0 to 7. Please refer to Table 4 on Page 12 as an example for display start line set to 56 (38h). Set Contrast Control Register This command adjusts the contrast of the LCD panel by changing the LCD driving voltage, VL6, provided by the On-Chip power circuits. VL6 is set with 64 steps (6-bit) in the contrast control register by a set of compound commands. See Figure 11 for the contrast control flow. Set Contrast Control Register Contrast Level Data No Changes Complete? Yes Figure 11 - Contrast Control Flow SOLOMON Rev 1.3 01/2003 SSD0817 Series 24 Set Segment Re-map This command changes the mapping between the display data column addresses and segment drivers. It allows flexibility in mechanical layout of LCD glass design. Please refer to Table 4 on Page 12 for example. Set LCD Bias This command is used to select a suitable bias ratio required for driving the particular LCD panel in use. The selectable values of this command for 64 MUX are 1/9 or 1/7. For other bias ratio settings, extended commands should be used. Set Entire Display On/Off This command forces the entire display, including the icon row, to be illuminated regardless of the contents of the GDDRAM. In addition, this command has higher priority than the normal/inverse display. This command is used together with "Set Display ON/OFF" command to form a compound command for entering power save mode. See "Set Power Save Mode" later in this section. Set Normal/Inverse Display This command turns the display to be either normal or inverse. In normal display mode, a RAM data of 1 indicates an illumination on the corresponding pixel. In inverse display mode, a RAM data of 0 will turn on the pixel. It should be noted that the icon line is not affect. The icon line is not inversed by this command. Set Display On/Off This command is used to turn the display on or off. When display off is issued with entire display is on, power save mode will be entered. See "Set Power Save Mode" later in this section for details. Set Page Address This command enters the page address from 0 to 8 to the RAM page register for read/write operations. Please refer to Table 4 on Page 12 for detail mapping. Set COM Output Scan Direction This command sets the scan direction of the COM output allowing layout flexibility in LCD module assembly. See Table 4 on Page 12 for the relationship between turning on or off of this feature. In addition, the display will have immediate effect once this command is issued. That is, if this command is sent during normal display, the graphic display will have vertical flipping effect. Set Read-Modify-Write Mode This command puts the chip in read-modify-write mode in which: 1. The column address is saved before entering the mode 2. The column address is increased only after display data write but not after display data read. This Read-Modify-Write mode is used to save the MCU 's loading when a very portion of display area is being updated frequently. As reading the data will not change the column address, it could be get back from the chip and do some operation in the MCU. Then the updated data could be written back to the GDDRAM with automatic address increment. After updating the area, "Set End of Read-Modify-Write Mode" is sent to restore the column address and ready for next update sequence. 25 SSD0817 Series Rev 1.3 01/2003 SOLOMON Software Reset Issuing this command causes some of the chip's internal status registers to be initialized: Read-Modify-Write mode is off Static indicator is turned OFF Display start line register is cleared to 0 Column address counter is cleared to 0 Page address is cleared to 0 Normal scanning direction of the COM outputs Internal regulator resistors Ratio is set to 4 Contrast control register is set to 20h Set End of Read-Modify-Write Mode This command relieves the chip from read-modify-write mode. The column address before entering read-modify-write mode will be restored no matter how much modification during the read-modifywrite mode. Set Indicator On/Off This command turns on or off the static indicator driven by the M and MSTAT pins. When the "Set Indicator On" command is sent, the second command byte "Indicator Display Mode" must be followed. However, the "Set Indicator Off" command is a single byte command and no second byte command is required. The status of static indicator also controls whether standby mode or sleep mode will be entered, after issuing the power save compound command. See "Set Power Save Mode" later in this section. NOP A command causing the chip takes No Operation. Set Test Mode This command forces the driver chip into its test mode for internal testing of the chip. Under normal operation, users should NOT use this command. Set Power Save Mode The Standby or Sleep Mode operation should be executed by a compound command. The compound command is composed of "Set Display ON/OFF" and "Set Entire Display ON/OFF" commands. When the "Set Entire Display" is ON and the "Set display" is OFF, either Standby Mode or Sleep Mode will be entered. The status of the Static Indicator will determine which power save mode is entered. If static indicator is off, the Sleep Mode will be entered: Internal oscillator and LCD power supply circuits are stopped Segment and Common drivers output VDD level The display data and operation mode before sleep are held Internal display RAM can still be accessed If the static indicator is on, the chip enters Standby Mode, which is similar to sleep mode except addition with: Internal oscillator is on Static drive system is on Please also be noted that during Standby Mode, if the "software reset" command is issued, Sleep Mode will be entered. Both power save modes can be exited by the issue of a new software command or by pulling Low at hardware pin RES . EXTENDED COMMANDS These commands are used, in addition to basic commands, to trigger the enhanced features designed for the chip. SOLOMON Rev 1.3 01/2003 SSD0817 Series 26 Set Multiplex Ratio This command switches default multiplex ratio to any multiplex mode from 2 to the maximum multiplex ratio (POR value), including the icon line. Max. MUX ratio: 65 The chip pins ROW0-ROW63 will be switched to corresponding COM signal output, see Table 10 on Page 29 for examples of 18 multiplex (including icon line) settings with and without 7 lines display offset for different MUX. Remarks: After changing the display multiplex ratio, the bias ratio may be adjusted in order to make display contrast consistent. Set Bias Ratio Except the 1/4 bias, all other available bias ratios could be selected using this command plus the "Set LCD Bias" command. For detail setting values and POR default, please refer to the extended command table, Table 8 on Page 19. Set Temperature Coefficient (TC) Value One out of four different temperature coefficient settings is selected by this command in order to match various liquid crystal temperature grades. Please refer to the extended command table, Table 8 on Page 19, for detailed TC values. Modify Oscillator Frequency The oscillator frequency can be fine tuned by applying this command. Since the oscillator frequency will be affected by some other factors, this command is not recommended for general usage. Please contact SOLOMON-Systech Limited application engineers for more detail explanation on this command. Set 1/4 Bias Ratio This command sets the bias ratio directly to 1/4. This bias ratio is especially designed for use in under 12 MUX display. In order to restore to other bias ratio, this command must be executed, with LSB=0, before the "Set Multiplex ratio" or "Set LCD Bias" command is sent. Set Total Frame Phases The total number of phases for one display frame is set by this command. The Static Icon is generated by overlapping the M and the MSTAT signals. These two pins output either VSS or VDD at same frequency but with phase different. To turn on the Static Icon, 3 phases overlapping is applied to these signals, while 1 phase overlapping is given to the "Off "status. With the increase in the total number of phases in a single frame, the overlapping time decreases. Thus the lower the effective driving voltage at the Static Icon on the LCD panel. 27 SSD0817 Series Rev 1.3 01/2003 SOLOMON Set Display Offset This command should be sent ONLY when the multiplex ratio is set less than the default value. When a lesser multiplex ratio is set, the display will be mapped in the middle (y-direction) of the LCD, see the no offset columns on Table 10 on Page 29. Use this command could move the display vertically within the 64 commons. To make the Reduced-MUX Com 0 (Com 0 after reducing the multiplex ratio) towards the Row 0 direction for L lines, the 6-bit data in second command should be given by L. An example for 7 lines moving towards to Com0 direction is given on Table 10 on Page 29. To move in the other direction by L lines, the 6-bit data should be given by 64-L. Please note that the display is confined within the default multiplex value. That is the maximum value of L is given by the half of the default value minus the reduced-multiplex ratio. For an odd display MUX after reduction, moving away from Row 0 direction will has 1 more step. Enable Band Gap Reference Circuit This command enables or disables the band gap reference circuit. It should be noticed that this command should be executed if divider is used without capacitor at VL2 to VL5. There are four selections on the band gap clock period. We recommended to set the band gap clock period to 200ms in normal operation. SOLOMON Rev 1.3 01/2003 SSD0817 Series 28 48 MUX Mode No Offset ROW0 ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 ROW8 ROW9 ROW10 ROW11 ROW12 ROW13 ROW14 ROW15 ROW16 ROW17 ROW18 ROW19 ROW20 ROW21 ROW22 ROW23 ROW24 ROW25 ROW26 ROW27 ROW28 ROW29 ROW30 ROW31 ROW32 ROW33 ROW34 ROW35 ROW36 ROW37 ROW38 ROW39 ROW40 ROW41 ROW42 ROW43 ROW44 ROW45 ROW46 ROW47 ROW48 ROW49 ROW50 ROW51 ROW52 ROW53 ROW54 ROW55 ROW56 ROW57 ROW58 ROW59 ROW60 ROW61 ROW62 ROW63 X X X X X X X X X X X X X X X COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 NC NC NC NC NC NC NC NC COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 X X X X X X X X X X X X X X X X NC NC NC NC NC NC NC NC 7 lines Offset X X X X X X X X COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 NC NC NC NC NC NC NC NC COM16 X X X X X X X X X X X X X X X X X X X X X X X NC NC NC NC NC NC NC NC 54 MUX Mode No Offset X X X X X X X X X X X X X X X X X X COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 NC NC NC NC NC COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 X X X X X X X X X X X X X X X X X X X NC NC NC NC NC 7 lines Offset X X X X X X X X X X X COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 NC NC NC NC NC COM16 X X X X X X X X X X X X X X X X X X X X X X X X X X NC NC NC NC NC 32 MUX Mode No Offset X X X X X X X COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 X X X X X X X X NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC 7 lines Offset COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC COM16 X X X X X X X X X X X X X X X NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC 64 MUX Mode No Offset X X X X X X X X X X X X X X X X X X X X X X X COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 X X X X X X X X X X X X X X X X X X X X X X X X 7 lines Offset X X X X X X X X X X X X X X X X COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Table 10 - ROW pin assignment for COM signals for SSD0817 in an 18 MUX display (including icon line) without/with 7 lines display offset towards ROW0 Note: X-Row pin will output non-selected COM signal 29 SSD0817 Series Rev 1.3 01/2003 SOLOMON MAXIMUM RATINGS Table 11 - Maximum Ratings (Voltage Referenced to VSS) Symbol VDD VEE Parameter Value -0.3 to +4.0 0 to -12.0 VSS-0.3 to VDD+0.3 Unit V V Supply Voltage Input Voltage Current Drain Per Pin Excluding VDD and VSS Operating Temperature Storage Temperature Vin I TA Tstg V mA o o 25 -30 to +85 -65 to +150 C C Maximum ratings are those values beyond which damages to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Description section This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions to be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Vin and VEE be constrained to the range VSS < or = (Vin or Vout) < or = VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. This device may be light sensitive. Caution should be taken to avoid exposure of this device to any light source during normal operation. This device is not radiation protected. SOLOMON Rev 1.3 01/2003 SSD0817 Series 30 DC CHARACTERISTICS Table 12 - DC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 2.4 to 3.5V, TA = -30 to 85C) Symbol VDD IAC IDP1 IDP2 ISB ISLEEP VEE VLCD VOH1 VOL1 VL6 VL6 VIH1 VIL1 Parameter Test Condition Logic Circuit Supply Voltage Recommend Operating Voltage Range Possible Operating Voltage VDD = 2.7V, Voltage Generator On, 4X DC-DC Converter Access Mode Supply Enabled, Write accessing, Tcyc Current Drain (VDD Pins) =3.3MHz, Typ. Osc. Freq., Display On, no panel attached. VDD = 2.7V, VEE = -8.1V, Voltage Generator Disabled, R/W ( WR ) Display Mode Supply Halt, Typ. Osc. Freq., Display Current Drain (VDD Pins) On, VL6 - VDD = -9V, no panel attached. VDD = 2.7V, VEE = -8.1V, Voltage Generator On, 4x DC-DC Display Mode Supply Converter Enabled, R/W ( WR ) Current Drain (VDD Pins) Halt, Typ. Osc. Freq., Display On, VL6 - VDD = -9V, no panel attached. VDD = 2.7V, LCD Driving Standby Mode Supply Waveform Off, Typ. Osc. Freq., Current Drain (VDD Pins) R/W ( WR ) halt. VDD = 2.7V, LCD Driving Sleep Mode Supply Current Waveform Off, Oscillator Off, Drain (VDD Pins) R/W ( WR ) halt. Display On, Voltage Generator Enabled, DC-DC Converter LCD Driving Voltage Enabled, Typ. Osc. Freq., Generator Output (VEE Pin) Regulator Enabled, Divider Enabled. LCD Driving Voltage Input Voltage Generator Disabled. (VEE Pin) Logic High Output Voltage Iout=-100mA Logic Low Output Voltage Iout=100mA Regulator Enabled (VL6 voltage LCD Driving Voltage Source depends on Int/Ext Contrast (VL6 Pin) Control) LCD Driving Voltage Source Regulator Disable (VL6 Pin) Logic High Input voltage Logic Low Input voltage Min 2.4 Typ 2.7 Max Unit V 3.5 V 600 A - 480 - 50 100 A - 120 200 A - 5 10 A - 1 5 A -12.0 - -2.4 V -12.0 0 - -2.4 VDD 0.1* VDD VDD V V V V V V V 0.9*VDD - VEE-0.5 0 floating VDD 0.2* VDD 0.8*VDD - 31 SSD0817 Series Rev 1.3 01/2003 SOLOMON VL2 VL3 VL4 VL5 VL6 VL2 VL3 VL4 VL5 VL6 IOH IOL IOZ IIL/IIH CIN VL6 Voltage reference to VDD, Bias LCD Display Voltage Output Divider Enabled, 1:a bias ratio (VL2, VL3, VL4, VL5, VL6 Pins) VL3 VL4 VL5 VL6 -12V 50 -1 -1 Regulator Enabled, Internal Contrast Control Enabled, Set Contrast Control Register = 0 -3 LCD Display Voltage Input (VL2, VL3,VL4, VL5, VL6 Pins) Logic High Output Current Source Logic Low Output Current Drain Logic Output Tri-state Current Drain Source Logic Input Current Logic Pins Input Capacitance Variation of VL6 Output (VDD is fixed) Temperature Coefficient Voltage reference to VDD, External Voltage Generator, Bias Divider Disabled Vout = VDD-0.4V Vout = 0.4V 1/a*VL6 2/a*VL6 (a-2)/a *VL6 (a-1)/a *VL6 VL6 5 0 VDD VL2 VL3 VL4 VL5 -50 1 1 7.5 3 V V V V V V V V V V A A A A pF % TC0 Compensation Flat Temperature Coefficient Voltage Regulator Enabled (POR) Temperature Coefficient 2* Temperature Coefficient 4* Temperature Coefficient 7* 0 -0.07 -0.11 %/ C o TC2 TC4 TC7 -0.11 -0.15 -0.28 -0.13 -0.26 -0.29 -0.15 -0.28 -0.30 %/ C o %/ C o %/ C o The formula for the temperature coefficient is: TC(%) = Vref at 50 C - Vref at 0 C x o o 50 C - 0 C o o 1 o Vref at 25 C x 100 % SOLOMON Rev 1.3 01/2003 SSD0817 Series 32 AC CHARACTERISTICS Table 13 - AC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 2.4 to 3.5V, TA = -30 to 85C) Symbol Fosc Parameter Oscillation Frequency of Display Timing Generator 64 Mux Mode FFRM 54 Mux Mode Frame Frequency 64 Mux Mode 104 x 64 Graphic Display Mode, Display ON, Internal Oscillator Enabled 104 x 64 Graphic Display Mode, Display ON, Internal Oscillator Disabled, External clock with freq., Fext, feeding to CL pin. 54 Mux Mode 104 x 54 Graphic Display Mode, Display ON, Internal Oscillator Enabled 104 x 54 Graphic Display Mode, Display ON, Internal Oscillator Disabled, External clock with freq., Fext, feeding to CL pin. 104 x 48 Graphic Display Mode, Display ON, Internal Oscillator Enabled 104 x 48 Graphic Display Mode, Display ON, Internal Oscillator Disabled, External clock with freq., Fext, feeding to CL pin. 104 x 32 Graphic Display Mode, Display ON, Internal Oscillator Enabled Test Condition Internal Oscillator Enabled (default), VDD = 2.7V Remark: Oscillator Frequency vs. Temperature change (-20C to 70C): -0.5%/C * Min Typ Max Unit 15.9 26.4 18.7 31.5 Fosc 4x65 Fext 4x65 25.7 kHz 42.72 kHz Hz Hz Fosc 8x54 Fext 8x54 Hz Hz 48 Mux Mode Fosc 8x49 Fext 4x49 Hz Hz 32 Mux Mode Fosc 8x33 Fext 4x33 Hz Hz 104 x 32 Graphic Display Mode, Display ON, Internal Oscillator Disabled, External clock with freq., Fext, feeding to CL pin. Remarks: Fext stands for the frequency value of external clock feeding to the CL pin Fosc stands for the frequency value of internal oscillator Frequency limits are based on the software command: set multiplex ratio to 32/48/54/64 Table 14 - I C-bus timing Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 2.4 to 3.5V, TA = 25C) 2 33 SSD0817 Series Rev 1.3 01/2003 SOLOMON Symbol FSCL TCLKL TCLKH TDSW TDHW TR TF CBUS TDH, START TDS, STOP Parameter 2 I C-bus Clock frequency, SCL 2 I C-bus Clock Low period, SCL I C-bus Clock high period, SCL I C-bus Data Setup time, SDA 2 I C-bus Data Hold time, SDA Rise time between SDA & SCL Fall time between SDA & SCL 2 Capacitive loadings at each I C-bus channel 2 I C-bus Setup time, START condition 2 I C-bus Hold time, STOP condition 2 2 Min 0 960 960 120 0 32 32 180 180 Typ Max Unit 500 kHz ns 0.98 350 350 400 ns ns us ns ns pF ns ns SOLOMON Rev 1.3 01/2003 SSD0817 Series 34 Symbol Tcycle TDSW TDHW TCLKL TCLKH TR TF TDH, START TDS, STOP Parameter Clock Cycle Time Write Data Setup Time Write Data Hold Time Clock Low Time Clock High Time Rise Time Fall Time Hold time, start condition Setup time, stop condition Min 2.0 120 0 960 960 0.18 0.18 Typ 200 200 2.5 2.5 Max 0.98 350 350 - Unit us ns us ns ns ns ns us us Table 15 - Interface Timing Characteristics (VDD - VSS = 2.4 to 3.5V, TA = 25C) Figure 12 - IIC data bus Interface driving waveform 35 SDA SCL T DH , S T A RT T D HW T C y c le T CL K H T DS , S TO P T DS W TR TF T CL K L SSD0817 Series Rev 1.3 01/2003 SOLOMON APPLICATION EXAMPLES ICONS COM0 : : COM10 COM11 : : COM30 COM31 DISPLAY PANEL SIZE 104 x 64 + 1 ICONS LINE COM32 COM33 : : : : COM63 ICONS SEG0................................SEG103 Segment Remapped [Command: A1] COM43.......COM32 SEG 103............................................................................SEG0 ICONS COM0 .... COM10 COM44 COM11 COM45 : : : SSD0817IC : COM18 64 MUX : COM19 : : : : COM63 COM30 ICONS COM31 VL6 VL5 VL4 VL3 VL2 Remapped COM SCAN Directiion [Command: C8] Remapped COM SCAN Directiion [Command: C8] /RES SDA in SCL VSS[GND] VEE SDA out Capacitor value: 0.1uF ~ 0.47 uF VDD = 2.775V External Vneg = -9.5V Logic pin connections not specified above: Pins connected to VDD: IRS, CS2, M/ S , CLS, IIC2, TEST0 - TEST7 Pins connected to VSS: VSS1, CS1 , IIC1 Pins floating: DOF , CL, T0-T6 Pin connected to either VDD or VSS by user defined: C0, C1 and SA0 SDA in & SCL should be pulled high by a pair of resistors: 100k ohm Figure 13 - Application Circuit of 104 x 64plus an icon line using SSD0817, configured with: external VEE, internal regulator, divider mode enabled (Command: 2B), IIC data bus interface, internal oscillator and master mode SOLOMON Rev 1.3 01/2003 SSD0817 Series 36 ICONS COM0 : : COM10 COM11 : : COM30 COM31 DISPLAY PANEL SIZE 104 x 64 + 1 ICONS LINE COM32 COM33 : : : : COM63 ICONS SEG0.................................SEG103 Segment Remapped [Command: A1] COM43..........COM32 SEG103........................................................................SEG0 ICONS COM0 ... COM10 COM44 COM11 COM45 : : : SSD0817 IC : COM18 64 MUX COM19 : (DIE FACE UP) : : : : COM63 COM30 VL6 VL5 VL4 VL3 VL2 COM31 ICONS VSS VEE C3N C1P C1N C2N C2P C4N /RES Remapped COM SCAN Directiion [Command: C8] Remapped COM SCAN Directiion [Command: C8] SDAin SCL 0.47 - 1uF x 5 5X boosting Optional for SDAin & SDAout are shorted Capacitor value: 0.1uF ~ 0.47 uF VDD = 2.775V SDAout VSS [GND] Logic pin connections not specified above: Pins connected to VDD:, M/ S , CS2, CLS, IIC2, IRS, TEST0-TEST7 Pins connected to VSS: VSS1, IIC1, CS1 Pins floating: DOF , CL, T0 - T6 Pin connected to either VDD or VSS by user defined :SA0 Pin connected together: SDAin & SDAout SDA in and SCl should be pulled high by a pair of resistors: value = 100 k ohm Figure 14 - Application Circuit of 104 x 64plus an icon line using SSD0817, configured with all internal power control circuit enabled, fully IIC data bus interface, internal oscillator and master mode. 37 SSD0817 Series Rev 1.3 01/2003 SOLOMON ICONS COM0 : : COM10 COM11 : : COM30 COM31 DISPLAY PANEL SIZE 104 x 64 + 1 ICONS LINE COM32 COM33 : : : : COM63 ICONS SEG0.................................SEG103 Segment Remapped [Command: A1] COM10 COM43.......COM32 SEG103..............................................................................SEG0 ICONS COM0 .... COM44 COM11 COM45 : : : SSD0817 IC : COM18 64 MUX : COM19 (DIE FACE UP) : : : : COM63 COM30 VL6 VL5 VL4 VL3 VL2 COM31 ICONS /RES Remapped COM SCAN Directiion [Command: C8] Remapped COM SCAN Directiion [Command: C8] SDAin SCL Capacitor value: 0.1uF ~ 0.47 uF VEE = -9.5V VSS [GND] VDD = 2.775V Logic pin connections not specified above: Pins connected to VDD: CS2, M/ S , CLS, IIC2, D2, D3, D6, D7, IRS Pins connected to VSS: VSS1, IIC1, TEST0 - TEST7, CS1 Pins floating: DOF , CL, T0 - T6 Pin connected to either VDD or VSS by user defined :SA0 Pin connected together: SDAin & SDAout SDA in and SCl should be pulled high by a pair of resistors: value = 100 k ohm Figure 15 - Application Circuit of 104 x 64plus an icon line using SSD0817, configured with all external power control circuit enabled, fully IIC data bus interface, internal oscillator, internal contrast gain and master mode. (Minimum pin outlets) SOLOMON Rev 1.3 01/2003 SSD0817 Series 38 Initialization Routine Command (Hex) (Refer to Figure 11: All internal power control circuit enable) Command (Hex) (Refer to Figure 12: External VEE, Internal regulator and divider enable) Description 1 2 3 4 5 E2 2F 24 81 20 D6 2D E2 2B 24 81 20 D6 2D A0 C0 A4 A6 AF External booster, Internal regulator and divider are enabled. VOP = approx. -8.593V with reference to VDD Software Reset Set power control register Set internal resistor gain = 24h Set contrast level = 20h Enable band gap reference circuit Set band gap clock period = 200ms Set Column address is map to SEG0 Set Row address is map to COM0 Set entire display on/off = Normal display Set normal / reverse display = Normal display Set Display On 6 7 8 9 10 Example A0 C0 A4 A6 AF Internal booster, regulator and divider are enabled. VOP = approx. -8.735V with reference to VDD 39 SSD0817 Series Rev 1.3 01/2003 SOLOMON Solomon Systech reserves the right to make changes without further notice to any products herein. Solomon Systech makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Solomon Systech does not convey any license under its patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Solomon Systech product could create a situation where personal injury or death may occur. Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of the part. SOLOMON Rev 1.3 01/2003 SSD0817 Series 40 |
Price & Availability of SSD0817
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |