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ICS333
QTClock Triple Output Clock
Description
The ICS333 is a low cost frequency generator that is factory programmable. Using analog/digital Phase-Locked-Loop (PLL) techniques, the device uses a standard fundamental mode, inexpensive crystal or clock input to produce three output clocks. One or more of the outputs can be programmed to implement spread spectrum for EMI reductions. The device also has a power down feature that tri-states the clock outputs and turns off the PLL when the PDTS pin is taken low. This datasheet is to be used with the one-page programming information for the complete specification on the device.
Features
* * * * * * * * * * *
8 pin SOIC package Zero ppm synthesis error Input crystal frequency from 5 to 27 MHz Input clock frequency from 3 to 50 MHz Three output clocks Spread spectrum capability for low EMI Output clock frequencies up to 200 MHz Duty cycle of 45/55 3.3 V operating voltage (consult ICS for 5V) Advanced, low power CMOS process For one output clock (lowest jitter), use the ICS331. For two output clocks, see the ICS332. For more than three outputs, see the ICS355 or ICS388.
Block Diagram
Crystal or Clock Input X 1/IC LK
X2
w
w
w
O TP ROM w ith P LL D ivider V alues
.D
t a
S a
e h
t e
U 4
.c
m o
P LL C lock S ynthesis and Control C ircuitry
C LK 1 C LK 2 C LK 3
C rystal O scillator
P D TS (all outputs and P LL)
MDS 333 D
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Revision 020102
Integrated Circuit Systems, Inc. q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q www.icst.com
www..com
ICS333 QTClock Triple Output Clock
Pin Assignment
X1/ CLK VDD GND CLK1 1 2 3 4 8 7 6 5 X2 PDTS CLK3 CLK2
Output Clock Selection Table
CLK1
Output frequency Spread amount Spread direction
CLK2
TBD (MHz) TBD (%) TBD
CLK3
TBD (MHz) TBD (%) TBD
TBD (MHz) TBD (%) TBD
Note: The output clock frequencies and spread amount are determined when the device is programmed.
8 pin (150 mil) SOIC
Pin Descriptions
Pin
1 2 3 4 5 6 7 8
Pin
X1/CLK VDD GND CLK1 CLK2 CLK3 PDTS X2
Pin
XI Power Power Output Output Output Input XO
Pin Description
Crystal Input. Connect this pin to a 5 to 27 MHz fundamental crystal or clock input. Connect to +3.3V. Connect to ground. CMOS level clock output. Weak internal pull-down when tri-state. CMOS level clock output. Weak internal pull-down when tri-state. CMOS level clock output. Weak internal pull-down when tri-state. Powers down entire chip. Tri-states CLK outputs when low. Internal pull-up. Crystal Input. Connect this pin to a 5 to 27 MHz fundamental crystal. Float for clock input.
MDS 333 D
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Revision 020102
Integrated Circuit Systems, Inc. q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q www.icst.com
ICS333 QTClock Triple Output Clock
External Components
Series Termination Resistor
Clock output traces over one inch should use series termination. To series terminate a 50 trace (a commonly used trace impedance), place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20.
load capacitance, each crystal capacitor would be 20 pF [(16-6) x 2] = 20.
PCB Layout Recommendations
For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) The 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 2) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 3) To minimize EMI the 33 series termination resistor, if needed, should be placed close to the clock output. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). Other signal traces should be routed away from the ICS333. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device.
Decoupling Capacitor
As with any high performance mixed-signal IC, the ICS333 must be isolated from system power supply noise to perform optimally. A decoupling capacitor of 0.01F must be connected between VDD and the PCB ground plane.
Crystal Load Capacitors
The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) been the crystal and device. Crystal capacitors must be connected from each of the pins X1 and X1 to ground. The value (in pF) of these crystal caps should equal (CL -6pF)*2. In this equation, CL= crystal load capacitance in pF. Example: For a crystal with a 16 pF
MDS 333 D
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Revision 020102
Integrated Circuit Systems, Inc. q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q www.icst.com
ICS333 QTClock Triple Output Clock
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS333. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature 7V
Rating
-0.5V to VDD+0.5V 0 to +70C -65 to +150C 175C 260C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured in respect to GND)
Min.
0 +3.15
Typ.
- +3.3
Max.
+70 +3.47
Units
C V
MDS 333 D
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Revision 020102
Integrated Circuit Systems, Inc. q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q www.icst.com
ICS333 QTClock Triple Output Clock
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V 5%, Ambient Temperature 0 to +70C
Parameter
Operating Voltage Supply Current Input High Voltage, PDTS Input Low Voltage, PDTS Input High Voltage, ICLK Input Low Voltage, ICLK Output High Voltage (CMOS High) Output High Voltage Output Low Voltage Short Circuit Current
Symbol
VDD IDD VIH VIL VIH VIL VOH VOH VOL IOS
Conditions
No load, Note 1 - - - - IOH = -8 mA IOH = -12 mA IOL = 12mA
Min.
3.15 2 -
VDD/2+1
Typ.
3.3 TBD - - - -
Max.
3.47 - 0.4 -
VDD/2-1
Units
V mA V V V V V V
- VDD-0.4 2.4 -
- 70
0.4
V mA
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V 5%, Ambient Temperature 0 to +70 C
Parameter
Output Rise Time Output Fall Time Cycle Jitter (short term jitter) Input Frequency, crystal input Input Frequency, clock input Output Frequency Output Frequency Synthesis Error Output Enable Time, PDTS high to output on Output Disable Time, PDTS low to tri-state
Symbol
tOR tOF tja
Conditions
0.8 to 2.0V 2.0 to 0.8V Note 1
Min.
Typ.
1 1 TBD
Max. Units
ns ns ps 27 50 200 MHz MHz MHz ppm ms ms
5 3 TBD Note 1 0
TBD TBD TBD
Note 1: Values dependent on programming
MDS 333 D
5
Revision 020102
Integrated Circuit Systems, Inc. q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q www.icst.com
ICS333 QTClock Triple Output Clock
Package Outline and Package Dimensions (8 pin SOIC, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters Symbol Min Max
Inches Min Max
A A1 B C D E
In d e x A re a
1.35 1.10 0.33 0.19 4.80 3.80 5.80 0.25 0.40 0
1.75 0.25 0.51 0.25 5.00 4.00 6.20 0.50 1.27 8
0.0532 0.0040 0.013 0.0075 .1890 0.1497 0.2284 0.010 0.016 0
0.0688 0.0098 0.020 0.0098 .1968 0.1574 0.2440 0.020 0.050 8
e
E H
1.27 Basic
0.050 Basic
H h L a
P in 1
D
h x 450
A Q e b c
Ordering Information
Part / Order Number
ICS333M-xx ICS333M-xxT
Marking
ICS333M-xx ICS333M-xx
Shipping packaging
Tubes Tape and Reel
Package
8 pin SOIC 8 pin SOIC
Temperature
0 to +70 C 0 to +70 C
The -xx indicates a two character programming code, which must be specified when ordering parts.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 333 D
6
Revision 020102
Integrated Circuit Systems, Inc. q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q www.icst.com

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