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| HEX D-LATCH SY100S350 FEATURES s s s s s s s s s s s Max. transparent propagation delay of 900ps Min. Master Reset and Enable pulse widths of 100ps IEE min. of -98mA Industry standard 100K ECL levels Extended supply voltage option: VEE = -4.2V to -5.5V Voltage and temperature compensation for improved noise immunity Internal 75K input pull-down resistors More than 40% faster than Fairchild Approximately 30% lower power than Fairchild Function and pinout compatible with Fairchild F100K Available in 24-pin CERPACK and 28-pin PLCC packages DESCRIPTION The SY100S350 offers six high-speed D-Latches with both true and complement outputs, and is performance compatible for use with high-performance ECL systems. When both enable signals (Ea and Eb) are at a logic LOW, the latches are transparent and the input signals( D0-D5) appear at the outputs (Q0-Q5) after a propagation delay. If either or both of the enable signals are at a logic HIGH, then the latches store the last valid data present on its inputs before Ea or Eb went to a logic HIGH. The Master Reset (MR) overrides all other input signals and takes the outputs to a logic LOW state. All inputs have 75K pull-down resistors. PIN CONFIGURATIONS D0 Q0 VEES Q0 Q1 Q1 4 3 2 1 28 27 26 19 20 21 22 23 24 25 11 10 9 8 7 6 5 D2 D3 VEE VEES MR Ea Eb 12 13 14 15 16 17 18 Q2 Q2 VCCA VCC VCC Q3 Q3 BLOCK DIAGRAM D5 Eb Ea MR D4 D E R Q5 Q5 D1 Top View PLCC J28-1 D5 Q5 VEES Q5 Q4 D4 Q4 Ea MR VEE Eb D3 D E R Q4 Q4 D3 D E R Q3 Q3 D4 D5 Q5 Q5 Q4 Q4 1 2 3 4 5 6 24 23 22 21 20 19 18 Top View Flatpack F24-1 17 16 15 14 D2 D1 D0 Q0 Q0 Q1 Q1 D2 D E R Q2 Q2 13 7 8 9 10 11 12 Q3 VCC VCCA Q3 Q2 Q2 D1 D E R Q1 Q1 D0 D E R Q0 Q0 Rev.: G Amendment: /0 1 Issue Date: July, 1999 Micrel SY100S350 PIN NAMES Pin D0 -- D5 Ea, Eb MR Q0 -- Q5 Q0 -- Q5 VEES VCCA Data Inputs Common Enable Inputs (Active LOW) Asynchronous Master Reset Input Data Outputs Complementary Data Outputs VEE Substrate VCCO for ECL Outputs Function TRUTH TABLE(1) Each Latch Inputs Dn H L X X X Ea L L X H X Eb L L H X X MR L L L L H Qn H L Latched(2) Latched(2) L Outputs Qn L H Latched(2) Latched(2) H Operating Mode Latch Asynchronous NOTES: 1. H = HIGH State L = LOW State X = Don't Care 2. Retains data that is present before E positive transition. DC ELECTRICAL CHARACTERISTICS VEE = -4.2V to -5.5V unless otherwise specified; VCC = VCCA = GND Symbol IIH Parameter Input HIGH Current MR Dn Ea, Eb Power Supply Current Min. -- -- -- -98 Typ. -- -- -- -78 Max. 250 250 250 -49 mA Inputs Open Unit A Condition VIN = VIH (Max.) IEE 2 Micrel SY100S350 AC ELECTRICAL CHARACTERISTICS CERPACK VEE = -4.2V to -5.5V unless otherwise specified; VCC = VCCA = GND TA = 0C Symbol tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tS tH tr tPW (L) tPW (H) Parameter Propagation Delay Dn to Output Propagation Delay Ea, Eb to Output Propagation Delay MR to Output Transition Time 20% to 80%, 80% to 20% Set-up Time, Dn to En Hold Time, Dn to En Release Time, MR to En Pulse Width, Ea, Eb Pulse Width, MR Min. 300 300 300 300 500 500 1000 1000 1000 Max. 1000 1100 1250 900 -- -- -- -- -- TA = +25C Min. 300 300 300 300 500 500 1000 1000 1000 Max. 1000 1100 1250 900 -- -- -- -- -- TA = +85C Min. 300 300 300 300 500 500 1000 1000 1000 Max. 1000 1100 1250 900 -- -- -- -- -- Unit ps ps ps ps ps ps ps ps ps Condition PLCC VEE = -4.2V to -5.5V unless otherwise specified; VCC = VCCA = GND TA = 0C Symbol tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tS tH tr tPW (L) tPW (H) Parameter Propagation Delay Dn to Output Propagation Delay Ea, Eb to Output Propagation Delay MR to Output Transition Time 20% to 80%, 80% to 20% Set-up Time, Dn to En Hold Time, Dn to En Release Time, MR to En Pulse Width, Ea, Eb Pulse Width, MR Min. 300 300 300 300 500 500 1000 1000 1000 Max. 900 1000 1200 900 -- -- -- -- -- TA = +25C Min. 300 300 300 300 500 500 1000 1000 1000 Max. 900 1000 1200 900 -- -- -- -- -- TA = +85C Min. 300 300 300 300 500 500 1000 1000 1000 Max. 900 1000 1200 900 -- -- -- -- -- Unit ps ps ps ps ps ps ps ps ps Condition 3 Micrel SY100S350 TIMING DIAGRAMS 0.7 0.1 ns -0.95V DATA -1.69V tW(L) -0.95V ENABLE TRANSPARENT tPHL, tPLH OUTPUT LATCHES tPHL, tPLH TRANSPARENT -1.69V tPHL, tPLH 80% 50% 20% tTHL, tTLH Enable Timing NOTE: VEE = -4.2V to -5.5V unless otherwise specified; VCC = VCCA = GND DATA ENABLE TRANSPARENT LATCHED TRANSPARENT tR RELEASE TIME MR tPHL, tPLH OUTPUT tW(L) tPHL, tPLH tPHL, tPLH Reset Timing 4 Micrel SY100S350 TIMING DIAGRAMS DATA tS ENABLE th Data Set-up and Hold Times NOTES: tS is the minimum time before the transition of the clock that information must be present at the data input. tH is the minimum time after the transition of the clock that information must remain unchanged at the data input. PRODUCT ORDERING CODE Ordering Code SY100S350FC SY100S350JC SY100S350JCTR Package Type F24-1 J28-1 J28-1 Operating Range Commercial Commercial Commercial 5 Micrel SY100S350 24 LEAD CERPACK (F24-1) Rev. 03 6 Micrel SY100S350 28 LEAD PLCC (J28-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA FAX + 1 (408) 980-9191 + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated 7 |
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