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Philips Semiconductors
Product specification
PowerMOS transistor Logic level FET
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope The device is intended for use in automotive and general purpose switching applications.
BUK554-60H
QUICK REFERENCE DATA
SYMBOL VDS ID Ptot Tj RDS(ON) PARAMETER Drain-source voltage Drain current (DC) Total power dissipation Junction temperature Drain-source on-state resistance; VGS = 5 V MAX. 60 39 125 175 42 UNIT V A W C m
PINNING - TO220AB
PIN 1 2 3 tab gate drain DESCRIPTION
PIN CONFIGURATION
tab
SYMBOL
d
g
source drain
1 23
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDGR VGS VGSM ID ID IDM Ptot Tstg Tj PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage Non-repetitive gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage temperature Junction temperature CONDITIONS RGS = 20 k tp 50 s Tmb = 25 C Tmb = 100 C Tmb = 25 C Tmb = 25 C MIN. - 55 MAX. 60 60 15 20 39 28 156 125 175 175 UNIT V V V V A A A W C C
THERMAL RESISTANCES
SYMBOL Rth j-mb Rth j-a PARAMETER Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS TYP. 60 MAX. 1.2 UNIT K/W K/W
August 1996
1
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor Logic level FET
STATIC CHARACTERISTICS
Tmb = 25 C unless otherwise specified SYMBOL V(BR)DSS VGS(TO) IDSS IDSS IGSS RDS(ON) PARAMETER Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current Zero gate voltage drain current Gate source leakage current Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 0.25 mA VDS = VGS; ID = 1 mA VDS = 60 V; VGS = 0 V; Tj = 25 C VDS = 60 V; VGS = 0 V; Tj =125 C VGS = 15 V; VDS = 0 V VGS = 5 V; ID = 20 A MIN. 60 1.0 -
BUK554-60H
TYP. 1.5 1 0.1 10 35
MAX. 2.0 10 1.0 100 42
UNIT V V A mA nA m
DYNAMIC CHARACTERISTICS
Tmb = 25 C unless otherwise specified SYMBOL gfs Ciss Coss Crss td on tr td off tf Ld Ld Ls PARAMETER Forward transconductance Input capacitance Output capacitance Feedback capacitance Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal drain inductance Internal source inductance CONDITIONS VDS = 25 V; ID = 20 A VGS = 0 V; VDS = 25 V; f = 1 MHz MIN. 10 TYP. 18 1100 420 160 25 110 150 100 3.5 4.5 7.5 MAX. 1750 600 275 40 150 220 145 UNIT S pF pF pF ns ns ns ns nH nH nH
VDD = 30 V; ID = 3 A; VGS = 5 V; RGS = 50 ; Rgen = 50 Measured from contact screw on tab to centre of die Measured from drain lead 6 mm from package to centre of die Measured from source lead 6 mm from package to source bond pad
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tmb = 25 C unless otherwise specified SYMBOL IDR IDRM VSD trr Qrr PARAMETER Continuous reverse drain current Pulsed reverse drain current Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS IF = 39 A ; VGS = 0 V IF = 39 A; -dIF/dt = 100 A/s; VGS = 0 V; VR = 30 V MIN. TYP. 0.95 60 0.30 MAX. 39 156 2.0 UNIT A A V ns C
AVALANCHE LIMITING VALUE
Tmb = 25 C unless otherwise specified SYMBOL WDSS PARAMETER Drain-source non-repetitive unclamped inductive turn-off energy CONDITIONS ID = 39 A ; VDD 25 V ; VGS = 5 V ; RGS = 50 MIN. TYP. MAX. 90 UNIT mJ
August 1996
2
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor Logic level FET
BUK554-60H
120 110 100 90 80 70 60 50 40 30 20 10 0
PD%
Normalised Power Derating
10
Zth(j-mb) K/W
BUK464-60H
D= 1 0.5 0.2 0.1 0.05 0.02 0.01 0
P D tp D= tp T t
0.1
0
20
40
60
80 100 Tmb / C
120
140
160
180
0.001 1E-07
T
1E-05
1E-03 tp / sec
1E-01
1E+01
Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tmb)
ID% Normalised Current Derating
Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T
ID / A 100 BUK564-60H 10 8 6 80 VGS / V = 5 4.5 40 4 3.5 20 3 2.5 0 1 2 VDS / V 3 4 5
120 110 100 90 80 70 60 50 40 30 20 10 0
60
0
20
40
60
80 100 Tmb / C
120
140
160
180
0
Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tmb); conditions: VGS 5 V
ID / A 1000
Fig.5. Typical output characteristics, Tj = 25 C. ID = f(VDS); parameter VGS
RDS(ON) / Ohm 0.1 0.08 2.5 3 3.5 4
BUK564-60H
BUK564-60H 4.5 5 VGS / V =
100
RD
10
O S(
N)
=V
/ DS
ID
tp = 10 us 100 us
0.06 0.04
6 8 10
1 ms DC 10 ms 100 ms 100 VDS / V
0.02 0
1
1
10
0
20
40 ID / A
60
80
100
Fig.3. Safe operating area. Tmb = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(ID); parameter VGS
August 1996
3
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor Logic level FET
BUK554-60H
80
ID / A
BUK564-60H
2
VGS(TO) / V max.
60 Tj / C = 40 25 20
1
-40
150
typ.
min.
0
0
0
2
4 VGS / V
6
8
10
-60
-20
20
60 Tj / C
100
140
180
Fig.7. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
gfs / S BUK564-60H -40 20 25
Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
ID / A SUB-THRESHOLD CONDUCTION
1E-01
1E-02
1E-03
2%
typ
98 %
Tj / C = 150 10
1E-04
1E-05
0
1E-06
0
20
40 ID / A
60
80
0
1
2 VGS / V
3
4
Fig.8. Typical transconductance, Tj = 25 C. gfs = f(ID); conditions: VDS = 25 V
a
Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS
C / pF BUK564-60H
2.0
Normalised RDS(ON) = f(Tj)
10000
1.5
1.0
1000
Ciss Coss
0.5
Crss
0 -60 -20 20 60 Tj / C 100 140 180
100
0
20 VDS / V
40
Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 C = f(Tj); ID = 20 A; VGS = 5 V
Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
August 1996
4
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor Logic level FET
BUK554-60H
12 10 8 6 4 2 0
VGS / V
BUK564-60H
120 110 100 90
WDSS%
VDS / = 12 48
80 70 60 50 40 30 20 10 0
0
10
20 QG / nC
30
40
20
40
60
80
100 120 Tmb / C
140
160
180
Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 39 A; parameter VDS
IF / A 100
Fig.15. Normalised avalanche energy rating. WDSS% = f(Tmb); conditions: ID = 39 A
BUK564-60H
+
80
VDD
L VDS
60
VGS
40 Tj / C = 150 -40
-ID/100 T.U.T. R 01 shunt
0
25
20
RGS
0 1 VSDS / V 2
0
Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
Fig.16. Avalanche energy test circuit. 2 WDSS = 0.5 LID BVDSS /(BVDSS - VDD )
August 1996
5
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor Logic level FET
MECHANICAL DATA
Dimensions in mm Net Mass: 2 g
BUK554-60H
4,5 max 10,3 max
1,3
3,7 2,8
5,9 min
15,8 max
3,0 max not tinned
3,0
13,5 min
1,3 max 1 2 3 (2x)
2,54 2,54
0,9 max (3x)
0,6 2,4
Fig.17. TO220AB; pin 2 connected to mounting base.
Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for TO220 envelopes. 3. Epoxy meets UL94 V0 at 1/8".
August 1996
6
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor Logic level FET
DEFINITIONS
Data sheet status Objective specification Product specification Limiting values
BUK554-60H
This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1996 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
August 1996
7
Rev 1.000

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