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DA9191A.000 July 31, 1997
MAS9191A
Single Chip AMPS/ETACS/NAMPS Audio/Data Processor
* * * *
DESCRIPTION
The MAS9191A is a high integration BeCMOS IC for implementing the audio and data signal processing in AMPS, ETACS or NAMPS cellular phones. The power consumption of the device is very low due to several automatic and software controlled power down modes as well as the low power characteristics of the BeCMOS process. DTMF receiver is also included to enable answering machine functions for the cellular phone. Only a minimal number of external components are needed to meet typical baseband requirements.
Single chip solution for all audio and data processing Low power consumption with several power down modes SAT decoding and transponding circuitry Simple 4-wire serial interface
FEATURES
* * * * * * * Voice signal processing including compressor, expander, de-emphasis and pre-emphasis filters and digital gain adjustments DTMF and ST generators and DTMF receiver Busy/Idle extraction and arbitration with TX block, voting, BCH, data buffering and framing, DCC coding with hardware Three 8-bit DACs and two operational amplifiers On-chip oscillator with clock output for uP 3.3V or 5V operation with low power consumption(RX block at 2mA/3.3V) 64-pin TQFP package, -40..85oC operation range * *
APPLICATIONS
AMPS/ETACS Cellular phone NAMPS Cellular phone
BLOCK DIAGRAM
AMPLIFIER ANTI ALIASING GAIN CONTROL LOWPASS FI LTER HIGHPASS FI LTER COMPRESSOR GAIN CONTROL PRE-EMPHASIS GAIN CONTROL LIMITER LOWPASS FILTER GAIN CONTROL LOWPASS FILTER GAIN CONTROL LOWPASS FILTER
MIC
GAIN CONTROL LOWPASS FILTER AMPLIFIER
TX
DTMF Genera tor SCL STB SRxD STxD Serial Interface
TX Buffer
BCH Coding
DCC Conversion
Framing
Manchester coding SAT Generation
SIGNALLING TONE
XSTAL1 XSTAL2
SYS1 (NAMPS)
BUSY / I DLE
COMPARATOR
BANDPASS FILTER
SAT Detection
SYS1 (NAMPS)
3 8-bit DACs
AMPLIFIER
RX Buffer
BCH Decoding
Voting
Frame Decoding
Manchester Decoder
COMPARATOR
SIDETONE
AMPLIFIER
2 Utility Operational Amplifiers
DPLL
BUZZER
AMPLIFIER LO WPASS FILTER GAIN CONTROL LOWPASS FILTER EXPANDER BANDPASS FILTER DE-EMPHASI S
DTMF Receiver
LOWPASS FI LTER LOWPASS FILTER GAIN CONTROL
SPEAKER
RX
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DA9191A.000 July 31, 1997
PIN CONFIGURATION
DACOUT2 DACOUT1 64 XINT DACOUT3 CLKOUT TXCTRL TEST2 TEST1 XTAL1 VDD VSS XTAL2 TXON BUSY
RX ALP
62 63
60 61
58 59
56 57
54 55
52 53
50 51
49
AGND TX TAUDOUT TAUDIN LPFIN VSAT VDAT TXACCIN
1 2 3 4 5 6 7
48 VREF 47 DEOUT 46 RBPFIN 45 RBPFOUT 44 VSAR 43 VDAR 42 EXPIN 41 EAMPOUT 40 EWCIN 39 EXPOUT 38 RXACCIN 37 RXACCOUT 36 RAUDIN 35 EST 34 STGT 33 EINR
8 TXACCOUT 9 PREIN 10 COUT 11 CAMP2I 12 CWCIN CAMP20 COMPIN MICOUT 13 14 15 16
21 XRESET 20 EXTMIC 19 MICFB 18 MIC 17 MICSGND
26 BUZFB 25 SRxD 24 STxD 23 STB 22 SCL
30 EARP1 29 EARP2 28 EXTERP 27 BUZOUT
32 SIDETONE 31 SIDEFB
TQFP64 package
PIN DESCRIPTION
Pin name AGND TX TAUDOUT TAUDIN LPFIN VSAT VDAT TXACCIN TXACCOUT PREIN COUT Pin 1 2 3 4 5 6 7 8 9 10 11 Type AO AO AO AI AI G P AI AO AI AO Function Signal ground. The signal ground is generated internally and is equal to VDD/2. The analog ground needs an external capacitor connected to system ground. Transmitted data signal output. Connect this output through a 22nF capacitor to the transmitter. TX audio output from the TX audio block.. TX audio input. The input for the TX audio signal, normally connected through a 22nF capacitor to TAUDOUT Input for TX limiter, lowpass filter or GC6 depending on the position of switches S15 and S16. The pin is normally left unconnected. Ground for TX. Connect to system ground. Power supply for TX block. Use a bypass capacitor between pins VSAT and VDAT. TX block extra Op Amp input. See application note in the APPLICATIONS section. TX block Op Amp output. Pre-emphasis filter input. Filter has a +6dB/octave (1dB) frequency response in the range 300Hz...3kHz. Compressor output signal. The compression ratio is 2:1
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DA9191A.000 July 31, 1997
PIN DESCRIPTION
Pin name CAMP2I CWCIN CAMP2O COMPIN MICOUT MICSGND MIC Pin 12 13 14 15 16 17 18 Type AI AI AO AI AO AO AI Function Compressor 2nd amplifier input as well as GC4 input. Use an external 22nF capacitor between COUT and this pin. Compressor window comparator input. Use an external 22nF capacitor between CAMP2O and this pin. Compressor 2nd amplifier output. Compressor input. The input is connected through a 22nF capacitor to MICOUT. Microphone amplifier output. See COMPIN. This output is used as a source for the side tone and for detection of the TX audio level. Microphone signal ground. This is the internal signal ground VDD/2. If noise appears on the microphone signal an external capacitor may be needed between this pin and system ground. Microphone amplifier input. Using this pin and the MICFB output the microphone amplifier frequency response can be adjusted according to the microphone used. The level at this input should be in the range 5..10mVrms. The maximum gain of the microphone amplifier is 30 dB. Microphone amplifier feedback output External microphone input. The level should be 100mVrms at 1kHz. Master reset. Active low. Serial interface clock input. The data is transferred in both directions at the rising edge of this signal. Serial interface strobe signal. With strobe signal the MAS9191A stores the given address from the serial interface buffer and enters the data mode. The serial interface stays in the data mode until eight SCL pulses are received after the strobe signal. Serial interface transmit data output. Serial interface receive data input Buzzer feedback is the input for the buzzer driver. Buzzer output. Output for external accessories Earpiece differential outputs of earpiece amplifier. The outputs are capable of driving a ceramic earpiece directly.
MICFB EXTMIC XRESET SCL STB
19 20 21 22 23
AO AI I I I
STxD SRxD BUZFB BUZOUT EXTERP EARP1 EARP2 SIDEFB SIDETONE EINR STGT EST RAUDIN RXACCOUT
24 25 26 27 28 29 30 31 32 33 34 35 36 37
O I AI AO AO AO AO AO AI AI AI AO AI AO
Side tone feedback output Side tone input. The level of the side tone is controlled with external components. External RX input. Steering control input for DTMF receiver. When the level at this input changes from below VDD/2 to above VDD/2 the pin is pulled up internally. When this occurs the DTMF tone is stored and an interrupt is generated. Enable Steering output. This pin is high when the DTMF receiver has detected a valid DTMF tone. Input for filter 6. Connect through a 22nF capacitor to the expander output (EXPOUT). Output of uncommitted Op Amp in MAS9191A. The Op Amp is normally used for RX audio level detection. The application circuit for this function is in the APPLICATIONS section. Connect the level detected by the circuit to the A/D converter of the general purpose micro controller.
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DA9191A.000 July 31, 1997
PIN DESCRIPTION
Pin name RXACCIN EXPOUT EWCIN EAMPOUT EXPIN VDAR VSAR RBPFOUT RBPFIN DEOUT VREF RX ALP TEST2 TEST1 CLKOUT TXCTRL VSS XTAL2 XTAL1 VDD TXON BUSY XINT DACOUT3 DACOUT2 DACOUT2 Pin 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Type AI AO AI AO AI P G AO AI AO AO AI AI I I O AO G O I P O O O AO AO AO Function RX block extra Op Amp input Expander output. The expander ratio is 1:2. Expander window comparator input. Connect a 22nF capacitor between EWCIN and EAMPOUT. Expander amplifier output. Expander input. Connect a 22nF capacitor between EXPIN and RBPFOUT. Power supply for RX audio block. Use a bypass capacitor between VDAR and VSAR. Ground for RX block. Connect to system ground. RX bandpass filter output. RX bandpass filter input. Connect a 22nF capacitor between this pin and DEOUT RX de-emphasis filter output. The filter has a -6dB/octave (1dB) frequency response in the range 300Hz...3kHz. Reference voltage. Connect a capacitor between this pin and system ground. RX input from RF. This level is 100mVrms at 1kHz. Audio loop input. Connect through a 22nF capacitor to the TX pin. Test input. Connect to ground during normal operation. Test input. Connect to ground during normal operation. If connected to VDD and TEST2 is connected to ground, the external clock can then be connected to XTAL1. 4.8 MHz clock output from oscillator circuit. Transmission control output. If a TX collision occurs this open-collector output is set to low. The TXCTRL will remain low until the TX block is reset with the TXRST bit or with XRESET. Digital ground. Connect a bypass capacitor between VSS and VDD. Crystal oscillator output. Crystal oscillator input or external clock input if TEST1 is high and TEST2 is low. Power supply input for digital block. Transmission detection for debugging. This output indicates when a transmission is occurring. Busy/Idle output. Indicates the state of the busy/idle bit. Active low interrupt output to micro controller. The interrupt is active until status register 10HEX is read. Output of DAC 3. The DAC output is connected to ground if the DAC is in power down mode. The output of the DAC is controlled by register 18HEX. Enter the values in two's complement form into the DAC register. Output of the DAC 2. The control register is located at 17HEX. Output of the DAC 1. The control register is located at 16HEX.
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DA9191A.000 July 31, 1997
ABSOLUTE MAXIMUM RATINGS
(GND = 0V)
Parameter Supply voltage* Storage temperature*
Symbol VDD Ts
Conditions
Min -55
Max 6.0 +125
Unit V
o
C
RECOMMENDED OPERATION CONDITIONS
(GND = 0V)
Parameter Supply voltage* Supply current Operating temperature*
Symbol VDD IDD Ta
Conditions Ta=-40...85 C Ta=-40...85 C, VDD=3.3V5%
o o
Min 3.0 1.0 -40
Typ 3.3 2.5
Max 3.6 23 +85
Unit V mA
o
C
ELECTRICAL CHARACTERISTICS
Digital inputs
(Ta=-40...85 C)
o
Parameter Input high voltage* Input low voltage* Input leakage current Input capacitance load*
Symbol VIH VIL IIL CI
Conditions
Min 0.7VDD
Typ
Max 0.7VDD
Unit V V uA pF
-10
+10 1
Digital outputs
(VDD = 3.3V5%, Ta=-40...85 C)
o
Parameter Output low voltage* Output high voltage*
Symbol VOL VOH
Conditions XINT @ +0.4mA XINT @ -0.4mA
Min 0.9VDD
Typ
Max 0.1VDD
Unit V V
Analog inputs
(Ta=-40...85 C)
o
Parameter External microphone level* Microphone level* RX input level* * Guaranteed by design only.
Symbol VEXTMIC VMIC VRX
Conditions
Min
Typ 100 10 100
Max
Unit mVrms mVrms mVrms
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DA9191A.000 July 31, 1997
ELECTRICAL CHARACTERISTICS
Analog outputs
(Ta=-40...85 C)
o
Parameter Signal ground Reference voltage Earpiece output impedance* Earpiece load resistance* Earpiece series load capacitance* External earpiece load resistance* External earpiece load capacitance* Earpiece amplifier gain Rx level Earpiece level non-differential* Earpiece level differential* TX level DTMF signal levels at TX SAT signal level at TX Data signal level at TX (AMPS/ETACS) ST signal level at TX (AMPS/ETACS) Data, ST, SAT level at TX DACs, output level DACs, differential nonlinearity DACs, integral nonlinearity DACs, settling time* DACs, load resistance* DACs, load capacitance* OP AMPs, load capacitance* * Guaranteed by design only.
Symbol AGND Vref ZO RL CL RL CL Avol VO VO VO VO VO VO VO VO VO VO DNL INL
Conditions
Min VDD/20.1V
Typ
Max VDD/2+ 0.1V
Unit V V
AGND +1.2V 500 1 120 30 1 1.26 RX level 100mVrms RX level 100mVrms RX level 100mVrms EXTMIC level 100mVrms f = 697 ... 941 Hz f = 1209 ... 1633 Hz ETACS AMPS -1 -1 131 123 470 488 NAMPS, DTX mode off NAMPS, DTX mode on 81 325 0.3V -0.95 -2.0 Vdac 1% 30 80 1 148 138 556 556 93 373 200 70 155 200 +1 +1 163 152 612 612 105 421 VDD0.3 +0.95 +2.0 10 3.26
k nF k nF dB mVrms mVrms mVrms mVrms dB mVrms mVrms mVrms mVrms V LSB LSB ms k pF nF
RL CL CL
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DA9191A.000 July 31, 1997
ELECTRICAL CHARACTERISTICS Expander
(Ta=-40...85 C)
o
Parameter Expanding ratio* Operation range input* Operation range output* Gain step* Integral nonlinearity Attack time* Decay time*
Conditions
Min -24 -48
Typ 1:2
Max +10 +20
Unit dB dB dB dB ms ms
1.333 -0.5 7.4 9.5 9.2 11.9 +0.5 14.3 14.3
Compressor
(Ta=-40...85 C)
o
Parameter Compressing ratio* Operation range input* Operation range output* Gain step* Integral nonlinearity Attack time* Decay time*
Conditions
Min -39.4 -19.7
Typ 2:1
Max +20 +10
Unit dB dB dB dB ms ms
1.333 -0.5 2.9 13 3.9 16.9 +0.5 4.6 20
AC Characteristics
(Ta=-40...85 C)
o
Parameter RX S/N ratio TX S/N ratio RX THD TX THD Crosstalk RX to TX* Crosstalk TX to RX* Mute attenuation * Guaranteed by design only.
Conditions Psophometric weighting
Min 48 50
Typ
Max
Unit dB dB
34 34 50 50 50
dB dB dB dB dB
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DA9191A.000 July 31, 1997
ELECTRICAL CHARACTERISTICS
20.0 dB 16.0 dB 12.0 dB 8.0 dB 4.0 dB 0.0 dB -4.0 dB -8.0 dB -12.0 dB -16.0 dB -20.0 dB -24.0 dB -28.0 dB -32.0 dB -36.0 dB -40.0 dB -44.0 dB -48.0 dB -52.0 dB -56.0 dB -60.0 dB 100H z 1kH z 10kH z
RX Total frequency response
20.0 dB 16.0 dB 12.0 dB 8.0 dB 4.0 dB 0.0 dB -4.0 dB -8.0 dB -12.0 dB -16.0 dB -20.0 dB -24.0 dB -28.0 dB -32.0 dB -36.0 dB -40.0 dB -44.0 dB -48.0 dB -52.0 dB -56.0 dB -60.0 dB 100 H z 1kH z 10kH z
TX Total frequency response
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DA9191A.000 July 31, 1997
ELECTRICAL CHARACTERISTICS
20.0 dB 17.0 dB 14.0 dB 11.0 dB 8.0 dB 5.0 dB 2.0 dB -1.0 dB -4.0 dB -7.0 dB -10.0 dB -13.0 dB -16.0 dB -19.0 dB -22.0 dB -25.0 dB -28.0 dB -31.0 dB -34.0 dB -37.0 dB -40.0 dB 100Hz 1kH z 10kH z
Filter F2 frequency response
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DA9191A.000 July 31, 1997
ELECTRICAL CHARACTERISTICS
Timing
(Ta=-40...85 C)
o
Parameter SCL cycle Data setup time Data hold time STB rising edge after SCL falling edge STB width MSB data bit valid after STB falling edge SCL rising edge after SCL falling edge Next data bit valid after SCL falling edge Ready for next address
Symbol T1 T2 T3 T4 T5 T6 T7 T8 T9
Conditions
Min 0.5 60 20 10 5
Typ
Max
Unit us ns ns ns us
Register read Register read Register read 5 30 7
5
us us ns us
Timing Diagram
T3
T1
T4
T5 T6
T7
T8
T9
T2
STB SCL SRxD STxD
R /W
A6
A5
A4
A3
A2 A1
A0
D7 D7
D6 D5 D6
D4 D3
D2
D1 D0 D1 D0
R/W
D5 D4
D3 D2
10
COMPIN LPFIN CAMP2I COUT TAUDIN PREIN GC7 S19 F13 GC9 F14 TX
2:1 F9HP LPFIN TAUDIN
TAUDOUT
CAMP2O CWCIN
MICOUT
FUNCTIONS Schematic diagram
A6
SYS0 SYS1
M2 F9HP
SYS0 SYS1 F10
F8
SYS0 SYS1
GC3 S12 S13 GC4 S14 GC5 F11 S15
F9LP
6 S16 GC
MIC
TXTST LIMITER
MICSGND
MICFB
COMPRESSOR
EXTMIC
F9HP LPFIN
S18 S20 F15
GC8
F12
OSC
SIGNALING TONE
TXTST
DTMF Generator BCH Coding DCC Conversion Framing
S17 SYS1 SATEN
TX-Buffer
SCL
Manchester coding TXDATA
CLKOUT TXCTRL TXON
STB
Serial Interface SAT Generation
C2 F2
BUSY / IDLE
SRxD
BUSY
STxD
8-bit DAC 8-bit DAC
DACOUT1 DACOUT2
XRESET
XINT
SYS1
SAT Detection
C1
A2
S9
8-bit DAC
SIDETONE
RX-Buffer
DACOUT3 RXACCIN - A1 + RXACCOUT TXACCIN
BCH Decoding
Voting
Frame Decoding
DPLL
Manchester Decoder
SIDEFB
A3 S7
M1
BUZOUT
DTMF Receiver
EST STGT
SGND
- A7 +
TXACCOUT AGND VREF S2 RXTST F1 F4 F3 RXMUTE GC1 S1 ALP RX
BUZFB
EARP2 GC2 F6 S5 S4 F5 EXPANDER S3
A4
S10
F7
EARP1
A5
1:2
S11
EXTERP S8
EST
EINR EXPOUT RAUDIN EAMPOUT EWCIN
STGT
DEOUT RBPFIN
RBPFOUT EXPIN
DA9191A.000 July 31, 1997
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DA9191A.000 July 31, 1997
FUNCTIONS
Data Reception The data reception block is in the power down state after a reset. The power down mode of the block is controlled by the RXSIP bit in register 07HEX. The Manchester encoded data is received through the RX pin. The data is amplified with GC1 and filtered with filter F1. The comparator C1 is used to convert data to a digital signal. The digital PLL circuit recovers the bit clock from the Manchester encoded data. The bit clock is 8kHz in the ETACS mode and 10kHz in the AMPS mode. The mode is set with the SYS0 bit of register 12HEX. The recovered bit clock is used in the Manchester decoder and the data is then transmitted to the frame decoding block. The frame decoding
Busy/ Idle 1 Bit Sync 10 Busy/ Idle 1 Word Sync 11 Busy/ Idle 1 Data 10
block finds dotting sequences, busy/idle bits and word syncs from the data. To avoid data being generated by random noise, the frame decoding block enters the data reception mode only after it has received two consecutive word syncs (11100010010) separated by 463 bits in the forward control channel and 77 bits in the forward voice channel. In this case the voting and BCH block are activated. When the frame decoding block loses five consecutive synchronization patterns it rejects the data reception mode and sets the voting and BCH blocks in power down state. The voice and control channel modes are selected with the CTCV bit of register 12HEX. Busy/ Idle 1 Busy/ Data Idle 10 1 10 1. Repeat of word A Busy/ Idle 1 Data Data Busy/ Idle 1 Data 10
Forward control channel data format. The numbers under the frames show the number of bits in each section.
Busy/ Idle 1
Data 10
Busy/ Idle 1
Busy/ Data Idle 10 1 10 1. Repeat of word B Busy/ Idle 1 Data
Data
Busy/ Idle 1
Data 10
Busy/ Data Idle 10 1 10 2. Repeat of word A Bit Sync 10 Busy/ Idle 1
Busy/ Idle 1
bit sync
Data 10
Busy/ Data Idle 10 1 10 5. Repeat of word B
Busy/ Idle 1
Data 10
Busy/ Idle 1
= 1010101010
word sync = 11100010010
The busy/idle bits are extracted from the data. Busy/idle bits are used to indicate the current status of the reverse control channel (RECC). The RECC is busy if the busy/idle bit is low and idle if the busy/idle
Forward voice channel data format.
bit is high. The state determination is made with 2-out-of-3 voting. The TX block uses the busy/idle indication for arbitration. The STR bit of register 12HEX selects the words from stream A or stream B. 2.Word repeat 40 Word Sync 11 Bit Sync 37 10.Word repeat 40 Word Sync 11 Bit Sync 37 3.Word repeat 40 Word Sync 11
Bit Sync 101
Word Sync 11 Bit Sync 37
1.Word repeat 40 Word Sync 11
Bit Sync 37 9.Word repeat 40
Word Sync 11 Bit Sync 37
11.Word repeat 40
On the forward voice channel after bit synchronization and word synchronization are received and the AUMUT bit in register 13HEX is set to high, the RX audio block will be muted until the 920 bits are received. The repeated words are transferred to the voting block. The voting is done bit by bit, 3-out-of-5. If three consecutive words are identical, the receiver is powered down and no remaining words are read. After the voting block the data is transmitted to the BCH block. This block performs decoding of the received BCH coded data. The following polynomial is used: G(x) = x12 + x10 + x8 + x5 + x4 + x3 + x0
If only one error occurs in data the BCH block can correct it. If more than one error occurs the BCH block cannot correct them and the BCHER bit of register 11HEX is set to high. The BCH block transfers the data to the RX buffer. When the buffer is full the RXWRD bit of register 10HEX is set to high and this causes interrupt line XINT to go active. When register 10HEX is read the interrupt is cleared. The data buffer can be read by reading register 15HEX four times. If the next word is coming and the previous word has not been read from the buffer, the word is missed. The new and the old words are compared.
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DA9191A.000 July 31, 1997
After a reset the TX block is in power down. The power down mode is controlled by bit TXSIP (TX section in power down) in register 07HEX. The TXRST bit located in register 12 HEX is used every time a TX collision occurs or for any other TX block reset causes. When the device is ready to receive data, the TXWRD bit of register 10HEX is high. If five bytes are written into register 19HEX the data transmission begins. The data is transferred from the serial interface to the TX buffer and the TXWRD bit is set high again, which causes XINT to become active. DCC(1:0) 00 01 10 11
FUNCTIONS Data Transmission
When the block comes out of power down mode the XINT is active because the device is ready to receive data (TXWRD goes high). The lower nibble of the fifth byte is ignored. The 36 bits of data are coded by the BCH coder with following polynomial: G(x) = x12 + x10 + x8 + x5 + x4 + x3 + x0 The BCH coder adds 12 parity bits to the data and the data is transferred to the DCC coding block. The DCC coder adds a digital color code on the reverse control channel (RECC) according following table. Coded DCC 0000000 0011111 1100011 1111100
The framing block adds bit sync (101010...10) and word sync (11100010010) sequences to the frames and performs needed repeats depending on the mode. Reverse control channel data format. The numbers under the frames show the number of bits in each section. Bit sync Word sync Coded DCC First word Second word repeated 5 times repeated 5 times 30 11 7 240 240 Reverse voice channel data format. 1.Repeat Bit Sync Word of word 1 Sync 101 11 48 5.Repeat Bit Sync Word of word 1 Sync 37 11 48 5.Repeat Bit Sync Word of word 2 Sync 37 11 48 Bit Sync 37 Bit Sync 37 Word Sync 11 Word Sync 11
2.Repeat of word 1
Bit Sync 37 Bit Sync 37
48
1.Repeat of word 2
48
Word Sync 11 Word Sync 11
The Manchester encoder block encodes the data into a Manchester coded format with bit clock. The bit clock is 8kHz in the ETACS mode and 10kHz in the AMPS mode. The mode can be controlled by bit SYS0 of register 12HEX. The data polarity can be inverted with bit INVTX of register 13HEX.If the BUSY bit does not go active between 56 and 104 bits of the transmitted message a transmission collision occurs. In this case the data which is in the TX block and the data that the user is writing to the device will not be
transmitted. The TXCOL bit of register 10HEX will go high in this case and cause an interrupt. The TXCOL will remain active until the TX block is reset with the TXRST bit of register 12HEX. If the TXCTREN bit is active in register 12HEX the TXCTRL output turns the transmitter off when a TX collision occurs. If the AUMUT bit in register 13HEX is set to high the TX audio block is muted with switch S19 on the voice channel while data transmission is occurring.
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DA9191A.000 July 31, 1997
FUNCTIONS Data Reception in Narrow Band mode
Forward voice channel data format for narrow band. DSAT Sync word 24 30 Sync word = 011001010110101001100110100110 Data 40 DSAT 24
DSAT = Digital Supervisory Audio Tone is one of seven 24-bit digital sequences added to the voice transmission. DSAT is transmitted at 200 NRZ bits/second. The following is a list of the seven DSAT sequences. DSAT sequence 0 1 2 3 4 5 6 2556CBHEX 255B2BHEX 256A9BHEX 25AD4DHEX 26AB2BHEX 26B2ADHEX 2669ABHEX
The 40-bit long data sequence is generated at a 100 Manchester bits/second rate. The data sequence contains 28 bits of data and 12 parity bits. The incoming data is captured by two 8-bit shift registers. When one shift register is full the RXWRD flag is set and an interrupt is generated. The captured data must be read by the micro controller within 20ms after the interrupt. Meanwhile, the other shift register is being filled and when it is full a new interrupt is generated. The shift registers are clocked in at 400 Hz. Two samples of each state of both the 200 NRZ bits/second data and the 100 Manchester bits/second data are loaded into the registers. Note that there are as many transitions in the 200 NRZ bits/second data as in the 100 Manchester bits/second data. The micro controller will then be used to filter the digital bit sequence and detect the DSAT, SYNC WORD and DATA out of the bit stream. The DATA must be checked with following algorithm: G(x) = x12 + x10 + x8 + x5 + x4 + x3 + x0
400 Hz 8-bit shift register STxD SCL 8-bit shift register 400 Hz SCL
C1
Rx
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DA9191A.000 July 31, 1997
FUNCTIONS Data Transmission in Narrow Band mode
Reverse voice channel data format for narrow band. DSAT/DST Sync word 24 30 Sync word = 011001010110101001100110100110 The data contains 36 data bits and 12 parity bits. The transmitted data is 100 bits/sec Manchester code. DSAT, DST and SYNC WORD are transmitted as 200 bits/sec NRZ code. The DSAT on the TX side is similar to the DSAT on RX side. However, under certain conditions the inverted DSAT, or DST (Digital Signaling Tone), must be transmitted. The DST is one of seven 24-bit digital sequences consisting of DSAT 0 1 2 3 4 5 6 2556CBHEX 255B2BHEX 256A9BHEX 25AD4DHEX 26AB2BHEX 26B2ADHEX 2669ABHEX Data 40 DSAT/DST 24
the logical inverse of the seven DSAT sequences. The conversions DSAT/ DST and DST/DSAT must be made without disturbing the phase of the DSAT. There is also a special 24-bit digital mask for each of the seven sequences. The mask defines the first bit to be inverted when converting from DSAT to DST or vice versa. Only when the bit in the mask is one can the polarity be changed. DST DAA934HEX DAA4D4HEX DA9564HEX DA52B2HEX D954D4HEX D94D52HEX D69654HEX MASK FF003EHEX 0BBF82HEX BD780FHEX 3FF118HEX 0AE6F6HEX 8001FFHEX 1C0FCDHEX
MAS9191A does not include frame coding logic for narrow band operation. The DSAT, DST, SYNC WORD and DATA must be generated by micro controller. The BCH function must also be performed by the micro controller using the following algorithm: G(x) = x12 + x10 + x8 + x5 + x4 + x3 + x0
The generated bit sequence is written into shift register 19HEX 8 bits at a time. While the next byte is written to one of the 8-bit shift registers the other is clocked out with a 200Hz clock. Each time the contents of a shift register transmitted, the TXWRD flag is set and an interrupt is generated. Note that 200 NRZ bits/second data has as many transitions as 100 Manchester bits/second data.
200 Hz SCL 8-bit shift register
GC8
F12
Tx
SRxD SCL 200 Hz 8-bit shift register
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DA9191A.000 July 31, 1997
SAT detection is active on voice channel in AMPS or TACS mode (SYS1=0). The supervisory audio tone is detected with a digital PLL. The detector compares the received SAT to the given SAT color code (SCC). When the given SAT is detected the SATDET bit of register 11HEX is set to high. If SATINTEN bit of register 13HEX is on the rising and falling edge of SATDET will cause the interrupt SATINT. On the voice
SCC1 0 0 1 1 SCC0 0 1 0 1
FUNCTIONS SAT detection & regeneration
channel the SAT regeneration can be enabled with bit SATEN of register 14HEX. By setting bit NOMSAT of register 14HEX nominal SAT frequency is generated. Otherwise, the SAT output frequency will follow received SAT frequency. The block is in power down mode when the TXSIP (transmit section in power down) bit is active in register 07HEX. After a reset the block is in power down mode.
SAT frequency 5970 Hz 6000 Hz 6030 Hz invalid code
The SAT and signaling tone (ST) are sent only on the voice channel in AMPS or TACS mode (SYS1=0). The SATEN and STON can be used to control the SAT and ST transmission. However, the device will automatically stop transmitting SAT and ST signals whenever data is being transmitted, even though SATEN or STON is high. The signaling tone is 8kHz in ETACS and 10kHz in AMPS. Also, switch S17 for TX data and switch S18 for ST can be used to disable the transmission. The switches must be on during transmission. The control bits for these switches are located in register 0DHEX. The SAT, TXDATA and the ST are summed and amplified with For enabling answering machine functions, the chip has an internal DTMF receiver. The receiver is in power down mode after a reset. The DTMFRP bit of register 07HEX controls the receiver power down mode. The receiver has two separate filters for separation of the low and high frequencies. The comparator and logic section measures the low and high frequency periods with an averaging algorithm. When the valid DTMF tone is detected the external steering logic output pin EST is set to high. With an external RC time constant the tone detect time and tone dropout times can be adjusted. The STGT input/output pin has an internal comparator and pullup and pull-down transistors. When EST is active and STGT goes from below to above the Vref level (VDD/2) the STGT is pulled up with an internal transistor. This causes the STD signal to go high, which causes the XINT line to become active. At the same time the detected DTMF tone is stored in register 04HEX. When the DTMF tone is not present the EST will go low, which causes the STGT to fall. When the STGT falls below the Vref level (VDD/2) the internal logic pulls the input down. The external RC circuit will filter out very short gaps in the received DTMF tone. The interrupt caused by the
SAT, ST or Data Transmission
GC8. The gain of the amplifier is -3.75dB...+3.75dB with 16 steps. The adjustment is made with bits 0..3 of register 0DHEX. After being amplified the signal is filtered with 4th order SC filter F12. The cutoff frequency of the filter is 19kHz in AMPS, 15kHz in ETACS and 200Hz in NAMPS (SYS1=1). The gain of the filter at 1kHz is 0dB. In the NAMPS mode, the signal is then fed to low pass filter F15, which is a 2nd order RC type filter. After filtering the signal is summed to the TX audio signal depending on the state of switch S20. The switch is controlled by bit 6 of register 01HEX .Register 07HEX bit AUDIOP is used to set these blocks into power down mode. DTMF detector is cleared by reading status register 10HEX. If the interrupt is cleared but register 04HEX is not read until the next DTMF tone is received, then the previous tone will be lost. The formula below can be used to calculate tone present and tone absent times. By adding diodes to the external circuit the tone present and tone dropout times can be altered. If one of the diodes is removed, the absent and present times are calculated using the parallel combination of R1 and R2.
C STGT STGT C
DTMF Receiver
R1
R1
R2
EST
EST
Time = R*C ln(VDD/VREF)
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DA9191A.000 July 31, 1997
The RX audio block starts with switch S1. The switch is controlled by bit S1 of register 0EHEX. The input ALP is used for enabling the audio loopback mode. In normal operation RX is used. Behind the switch is amplifier GC1 with adjustable gain from -3dB to +3dB. The gain is controlled with bits 0..3 in register 0EHEX.The amplifier output is connected to the second order lowpass filter F1. The cutoff frequency of the filter is 50 kHz and the gain at 1kHz is 0dB. The filter output is connected to data comparator C1 and to the SAT bandpass filter F2 and to the rest of the RX audio block. The polarity of the received data can be inverted with bit INVRX, which is located in register 13HEX. The data comparator output is connected to the DPLL and Manchester decoder blocks. The filter F2 is a 6kHz bandpass filter for supervisory audio tone. The filter is a second order SC filter. The filter output is connected to SAT comparator C2 and the SAT detection block. The signal from F1 is connected to filter F3 through a switch which is used by the internal logic when the AUMUT bit of register 13HEX is active. In this case if
C1 C2 F2 S2 RXTST0 RXTST1 S4 F5 F4
+
FUNCTIONS RX Audio
the data is received on the voice channel the lowpass filter F3 input is grounded automatically with this switch. With switches S6 and S7 the received audio and transmitted audio can be summed. The control bits of the switches are located in register 03HEX. This signal is fed to F4 and to the DTMF receiver. The function of the DTMF receiver is described in the next section RX de-emphasis filter F4 has a -6dB/octave (1dB) frequency response in the range 300Hz ... 3kHz. The filter can be bypassed with S2-RXTST0-RXTST1. Switch S2-RXTST0RXTST1 is connected to the DEOUT pin. The performance of C1, C2 and F2 can be monitored with switch S2-RXTST0-RXTST1. Bits 5 and 6 in register 02HEX and bit 5 in register 0EHEX control this switch. An external capacitor is needed between DEOUT and RBPFIN. The RBPFIN input is connected to filter F5, which is a 6th order bandpass filter. The gain of this filter is 0dB at 1kHz. The filter can be bypassed with switch S4. After S4 the signal is connected to the RBPFOUT pin. An external capacitor is used to connect the signal to the EXPIN input.
MICOUT RX data, SAT
S7 F3 S6 RXMUTE
F1
GC1 S1 ALP RX
DTMF Receiver
DEOUT
RBPFIN A2
STGT
EST
SIDETONE SIDEFB BUZOUT BUZFB EARP2
S9
A3 M1
+
GC2
+
F6 S5 S8
EXPANDER
A4 EARP1 EXTERP A5
S10
1:2
F7
EAMPOUT
RBPFOUT
EWCIN
S11
EXPIN
EXPOUT
RAUDIN
Audio Receive Path
EINR
17
DA9191A.000 July 31, 1997
FUNCTIONS
The signal is fed to the SC-type audio expander with expansion ratio 1:2. The expander can also be bypassed with switch S5. The switch is controlled with bit S5 in register 03HEX. After switch S5 the signal goes to the EXPOUT output pin. An external capacitor is used to connect the signal to the RAUDIN input and to filter F6. Filter F6 is a 4th order SC-type lowpass filter. The gain at 1kHz is 0dB. After filtering the signal and the external accessory input EINR can be summed with switch S8. The control bit for the switch is in register 03HEX. The summed signal is amplified with GC2, which has a -15dB...+15dB gain with 16 steps. The gain is controlled with bits 0..3 in register 03HEX. The amplified signal can be summed with SIDETONE. The side tone can be switched on with S9, which has a control bit in register 02HEX. The side tone input has an internal Op Amp with feedback signal SIDEFB. The gain of the Op Amp is controlled by external components. COMPIN is normally used as an input for the side tone amplifier circuit. Filter F7 is a second order low pass filter. The cutoff frequency is 20kHz and the gain at 1kHz is 0dB. After filtering the signal can be connected to three amplifiers with switches M1, S10 and S11. The control bits are located in registers 02HEX and 03HEX. A4 is the earphone amplifier, which is a single input differential output amplifier. Amplifier A5 is for external accessories and is capable of driving a capacitive load. The load capacitance is 1nF and the block has a 4.82dB gain. The third amplifier A3 is a buzzer driver. It drives the signal to the power transistor, which drives the buzzer. The buzzer represents a high inductive load of 1.2mH/25ohm. The block stabilizes the current flow through the external buzzer which depends on the current gain factor of the external bipolar transistor. The emitter resistor of the transistor must be 6.8 ohms. Three current values (peak values) can be chosen with switch M1:10mA, 66mA and 160mA. The tolerance of the external resistor will directly affect the buzzer current. The RX audio block can be set into power down mode together with the TX audio block. The AUDIOP bit in Register 07HEX is used for this purpose. The blocks are in power down mode after a reset.
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DA9191A.000 July 31, 1997
The TX audio block is in the power down mode after a reset. The block is set to the operation mode with the AUDIOP bit of register 07HEX. The same bit also controls the RX audio block. The TX audio block starts with switch M2, which is controlled by bits 4 and 5 in register 00HEX. Switch M2 connects one of the following blocks as an input source: 1) After a reset the input source is connected to signal ground. 2) In the second position the input is connected to the microphone amplifier A6. The gain of amplifier A6 is determined with external components. The maximum gain is 30 dB. 3) In the third position the input is connected to EXTMIC, which is for external accessories. 4) The fourth position selects the DTMF generator. The DTMF generator is controlled with registers 05HEX and 06HEX. Register 05HEX controls the low frequencies and register 06HEX controls the high frequencies. A detailed description of how to use these registers is in the REGISTERS section. The DTMF generator is in the power down mode after a reset and can be set up with the DTMFTP bit of register 07HEX. The signal is then filtered with anti-aliasing filter F8. The gain at 1kHz is 0dB and the cutoff frequency is 15kHz. After the filter the signal is amplified with
FUNCTION TX Audio
GC3. The gain is -3dB...+3dB with 16 steps according to bits 0..3 in register 00HEX. The amplified signal is then fed to lowpass filter F9LP and highpass filter F9HP, which are 4th order SC filters. During normal operation the output of filter F9HP is connected to output MICOUT. With switch SYS0SYS1 the highpass filter can be transferred to the output of GC5 after the signal has been compressed and pre-emphasized. Bit 6 in register 12HEX and bit 6 in register 14HEX control switch SYS0-SYS1. Connect MICOUT through a 22nF capacitor to the compressor input COMPIN. The MICOUT can also be used as a source for the side tone amplifier and for detecting the audio level with the uncommitted Op Amp (See APPLICATIONS section). The compressor is an SC audio type with a 2:1 compressing ratio. The detailed values are found in the ELECTRICAL CHARACTERISTICS section under Compressor. The compressor can be bypassed internally with switch S12 or externally with S13. The bypass gain is 0dB (100 mVrms). The compressor requires one external 22nF capacitor between pins CAMP20 and CWCIN. Another 22nF capacitor is needed between pins CAMP2IN and COUT. This capacitor also serves as an external DC blocking capacitor between the compressor output and gain control GC4 input.
CAMP2O COMPIN CWCIN MICOUT CAMP2I COUT PREIN GC4 S13
DTMF Generator MIC MICSGND MICFB EXTMIC A6 F8 GC3 F9HP F9LP SYS0 SYS1 SYS0 SYS1
2:1
S12
F10
S14
M2
COMPRESSOR S7
PRE-EMPHASIS
TAUDOUT
LPFIN
TAUDIN
GC6 GC5 LIMITER S15 F11 S16
GC7
S19 TXTST
F13
+
GC9
F14 TX
SYS0 SYS1 TX data, ST S20
Audio Transmit Path
19
DA9191A.000 July 31, 1997
FUNCTIONS
The gain of GC4 can be adjusted in the range 0.67..+5.33dB with bits 0..3 in register 0AHEX. After GC4 the signal is filtered with pre-emphasis filter F10, which has a +6dB/octave (1dB) frequency response at the range 300Hz..3kHz. At 1kHz the gain is 0dB. The pre-emphasis filter can be bypassed with switch S14.The signal is then amplified with GC5. Gain control GC5 is an SC-type with a programmable gain adjustment. The range is 0dB..20 dB with 16 steps according to bits 0..3 in register 0AHEX. At the output of GC5 is output pin LPFIN (or highpass filter F9HP) and a SC-type limiter. The limiting level is 439mVp and the tolerance is 5%. The 0dB level is 370mVp. The limiter can be bypassed with switch S15. The lowpass filter F11 with a 6kHz notch follows the limiter. The gain of the filter is 2.94dB at 1kHz. The filter and the limiter can be bypassed with switch S16. GC6 and GC7 are continuous time programmable gain adjustment blocks. The gain of GC6 is -3dB ... +3dB with 16 step according to bits 0..3 in register 0BHEX. The gain of GC7 is adjustable within - 3dB ... +1dB with bits 0..3 in register 0BHEX in 16 steps. GC7 output is connected to pin TAUDOUT through switch TXTST. The data transmission signal can be examined at TAUDOUT with this switch. Also with switch TXTST, the performance of GC8, 3.75..3.75dB., F12 and F15 can be observed with an input at TAUDIN. An external capacitor between pins TADOUT and TAUDIN is required. The TAUDIN input is connected to switch S19. The switch can be used to mute the TX audio block. S19 is controlled with bit 5 in register 01HEX. Switch S19 is also controlled by the TX framing block. During data transmission on the voice channel and with the AUMUT bit in register 13HEX set to high the TX audio block is muted with S19. Following S19 is a second order lowpass filter F13 with 15kHz cutoff frequency. After filtering the signal is summed with the data signal and amplified with GC9. The gain of the amplifier GC9 is adjustable with bits 0..3 located in register 0CHEX. The adjustment is done in 16 steps in the range -3.0.. +3.0dB .The output of the amplifier GC9 is then filtered with F14. The filter is a third order lowpass filter with 54kHz cutoff frequency. The gain at 1kHz is 0dB. DTX bit of the regiter 0DHEX is used to set DATA, DSAT and DST deviation. When the device is not in DTX (Discontinous Transmission) the DTX = 0 and there is nominal level at TX, 93 mVrms. If DTX is on, the level is increased to 373 mVrms.
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DA9191A.000 July 31, 1997
The device has three 8-bit DACs. The DACs can be set to the power down mode by using bits XPDDAC1, XPDDAC2 and XPDDAC3. The DACs are in power down mode after a reset. The Vref for the DACs is VDD/2. The output values of the DACs are entered in 8-bit two's complement form into
FUNCTIONS DACs
registers 16HEX, 17HEX and 18HEX. The typical step size is 13 mV and the DC output level is in the range 0.3V..VDD-0.3V. The differential nonlinearity is 0.5 LSB and the integral 2LSB. The settling time is 10ms (max). The minimum load resistance is 30k and the maximum load capacitance is 80pF.
Op Amps There are two uncommitted inverting operational amplifiers in the device. The input pins are RXACCIN and TXACCIN. The output pins are RXACCOUT and Serial Interface
The serial interface has three inputs: SCL (serial clock), STB (strobe) and SRxD(received data). Output pin STxD is used for transmitting data. The data is latched with the rising edge of the SCL signal. The MSB is received first and the LSB last. Before the STB signal, eight address bits must first be shifted in. The STB signal sets the device into the data mode. The MSB of the address byte defines the read/write operation. If the MSB is high the data is read from the device. If the MSB is low, the data is written to the device. After the STB the written data is
ADDRESS
TXACCOUT. The Op Amps are capable of driving capacitive loads up to 1nF.
shifted in with the rising edge of the SCL. If the data is to be read from the device, the STxD output is in the state of MSB data bit after the STB signal. The falling edge of the SCL shifts the next data bit to the STxD output. Eight data bits must be shifted out at which time the device exits the data mode. Because the serial interface transmit buffer is dynamic, data will be valid on the buffer only 200 uS after the STB signal appears. This means that the SCL frequency must be at least 5kHz.
DATA
STB SCL SRxD STxD A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 R/W
ADDRESS STB SCL SRxD STxD A6 A5 A4 A3 A2 A1 A0 D7 D6 D5
DATA
R/W D4 D3 D2 D1 D0
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DA9191A.000 July 31, 1997
FUNCTIONS Registers
Address 00HEX 01HEX 02HEX 03HEX 04HEX (84HEX) 05HEX 06HEX 07HEX 0AHEX 0BHEX 0CHEX 0DHEX 0EHEX 10HEX (90HEX) 11HEX (11HEX) 12HEX 13HEX 14HEX 15HEX (95HEX) AMPS I/O Write Write Write Write Write Read Write Write Write Write Write Write Write Write Read Read Write Write Write Read Bit 7 0 0 0 S8 0 X 0
XPDDAC3
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 M2[1:0] GC3[3:0] S20 S19 S16 S15 S14 S13 S12 RXTST[1:0] S9 S11 S10 M1[1:0] S7 S6 S5 GC2[3:0] Vref[2:0] 0 0 0 0 X X X DTMF[3:0] 0 LOWF[5:0] HIGHF[7:0]
XPDDAC2 XPDDAC1
RXSIP
TXSIP
AUDIOP
DTMFRP
DTMFTP
GC4[3:0] GC7[3:0] 0 0 S4
X X SATEN SATINTE NOMSAT
0 S18 S3
X BCHERR SYS0 STDE SYS1
0 S17 S2
BUSY STR RXINTE 0
TXTST DTX S1
SATINT TXON RXRST AUMUT 0 TXCOL WSYNC TXRST INVRX 0
GC5[3:0[ GC6[3:0] GC9[3:0] GC8[3:0] GC1[3:0]
TXWRD DOT TXCTRE INVTX 0 RXWRD SATDET CTCV DCC[1:0] SCC[1:0] STD X STON
15HEX (95HEX) NAMPS 16HEX 17HEX 18HEX 19HEX AMPS
Read Write Write Write Write
1ST RX[0:7] 2ND RX[8:15] 3RD RX[16:23] 4TH RX[24:27] 0 0 0 8 bits of captured data after comparator with shift register clocked at 400Hz DAC1[7:0] DAC2[7:0] DAC3[7:0] 1ST TX[0:7] 2ND TX[8:15] 3RD TX[16:23] 4TH TX[24:31] 5TH TX[32:35] 0 0 0 8 bit sequence to be transmitted with shift register clocked at 200Hz
0
0
19HEX NAMPS
Write
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DA9191A.000 July 31, 1997
FUNCTIONS
Register 00HEX (write only) Bit 3-0 Name GC3[3:0] State 0000-1111 0000 0001 0010 ....... 1111 1000 5-4 M2[1:0] 00 01 10 11 6 7 reserved reserved 0 0 +3.0dB +0.2dB default value AGND A6-OUT EXTMIC DTMFGEN reserved for future use, set to 0 reserved for future use, set to 0 Connected to F8 input Function Control range for GC3: -3.0dB ... +3.0dB, 0.4dB/step -3.0dB -2.6dB -2.2dB
Register 01HEX (write only) Bit 0 1 2 3 4 5 6 Name S12 S13 S14 S15 S16 S19 S20 State 0 1 0 1 0 1 0 1 0 1 0 1 0 (SYS1 = 0) 1 (SYS1 = 1) 0 (SYS1 = 0) 1 (SYS1 = 1) 0 Function Compressor output Compressor input COUT PREIN F10 output F10 input Limiter output Limiter input F11 output Limiter input AGND TAUDIN AGND F12 output AGND F15 output reserved for future use, set to 0 summed to GC9 input connected to F13 input connected to GC6 input connected to F11 input connected to GC5 input connected to GC4 input connected to COUT
7
reserved
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DA9191A.000 July 31, 1997
FUNCTIONS
Register 02HEX (write only) Bit 1-0 Name M1[1:0] State 00 01 10 11 2 3 4 6-5 S10 S11 S9 RXTST0RXTST1 0 1 0 1 0 1 00 01 10 11 7 reserved 0 Function AGND 10mA gain 66mA gain 160mA gain AGND Filter F7 output AGND Filter F7 output AGND Amplifier A2 output determined by S2 C1 F2 C2 reserved for future use, set to 0 connected to DEOUT summed to F7 input connected to amplifier A5 input connected to amplifier A4 input connected to amplifier A3 input
Register 03HEX (write only) Bit 3-0 Name GC2[3:0] State 0000-1111 0000 0001 0010 ....... 1111 1000 4 5 6 7 S5 S6 S7 S8 0 1 0 1 0 1 0 1 +15.0dB +1.0dB default value EXPOUT EXPIN AGND RAUDIN AGND COMPIN AGND EINR summed into GC2 input summed into F6 input connected to EXPOUT Function Control range for GC2: -15.0dB ... +15.0dB, 2.0dB/step -15.0dB -13.0dB -11.0dB
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DA9191A.000 July 31, 1997
FUNCTIONS
Register 04HEX (bits 7-4 write only, bits 3-0 read only) Bit Name State Function 3-0 DTMF[3:0] 0001 `1' Tone detected 0010 `2' Tone detected 0011 `3' Tone detected 0100 `4' Tone detected 0101 `5' Tone detected 0110 `6' Tone detected 0111 `7' Tone detected 1000 `8' Tone detected 1001 `9' Tone detected 1010 `0' Tone detected 1011 `*' Tone detected 1100 `#' Tone detected 1101 `A' Tone detected 1110 `B' Tone detected 1111 `C' Tone detected 0000 `D' Tone detected Internal reference voltage adjustment 000 +0.75dB 001 +0.50dB 010 +0.25dB 011 0.00dB default value 100 -0.25dB 101 -0.50dB 110 -0.75dB 111 -1.00dB 0 reserved for future use, set to 0
6-4
Vref[2:0]
7
reserved
Register 05HEX (write only) Bit 5-0 Name LOWF[5:0] State 00H-3FH 000000 100110 101010 101111 110011 7-6 reserved 00 Function Transmitted low frequency DTMF tone Nominal No signal 697 Hz 770 Hz 852 Hz 941 Hz reserved for future use, set to 0 Real frequency No signal 695.8 Hz 769.0 Hz 860.6 Hz 933.8 Hz
25
DA9191A.000 July 31, 1997 The register value for other frequencies may be calculated with the formula: LG[5:0] = (fOUT * 217) / 2.4MHz.
FUNCTIONS
Register 06HEX (write only) Bit 7-0 Name HIGHF[7:0] State 00H-FFH 00000000 01000010 01001001 01010001 01011001 Function Transmitted high frequency DTMF tone Nominal No signal 1209 Hz 1336 Hz 1477 Hz 1633 Hz Real frequency No signal 1208.5 Hz 1336.7 Hz 1483.2 Hz 1629.6 Hz
The register value for other frequencies may be calculated with the formula: HG[7:0] = (fOUT * 217) / 2.4MHz.
Register 07HEX (write only) Bit 0 1 2 3 4 5 6 7 Name DTMFTP DTMFRP AUDIOP TXSIP RXSIP XPDDAC1 XPDDAC2 XPDDAC3 State 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function DTMF transmitter in power down DTMF transmitter active DTMF receiver in power down DTMF receiver active AUDIO in power down AUDIO active Digital TX section in power down Digital TX section active Digital RX section in power down Digital RX section active DAC1 in power down DAC1 active DAC2 in power down DAC2 active DAC3 in power down DAC3 active
26
DA9191A.000 July 31, 1997
FUNCTIONS
Register 0AHEX (write only) Bit 3-0 Name GC5[3:0] State 0000-1111 0000 0001 0010 ....... 1111 0000 7-4 GC4[3:0] 0000-1111 0000 0001 0010 ....... 1111 1000 +5.33dB +2.53dB default value -20.0dB 0.0dB default value Control range for GC4: -0.67dB ... +5.33dB, 0.4.0dB/step -0.67dB -0.27dB +0.13dB Function Control range for GC5: 0.0dB ... -20.0dB, 1.33.0dB/step 0.0dB -1.33dB -2.67dB
Register 0BHEX (write only) Bit 3-0 Name GC6[3:0] State 0000-1111 0000 0001 0010 ....... 1111 1000 7-4 GC7[3:0] 0000-1111 0000 0001 0010 ....... 1111 1011 +1.0dB -0.067dB default value +3.0dB +0.2dB default value Control range for GC7: -3.0dB ... +1.0dB, 0.266.0dB/step -3.0dB -2.6dB -2.2dB Function Control range for GC6: -3.0dB ... +3.0dB, 0.4dB/step -3.0dB -2.6dB -2.2dB
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DA9191A.000 July 31, 1997
FUNCTIONS
Register 0CHEX (write only) Bit 3-0 Name GC9[3:0] State 0000-1111 0000 0001 0010 ....... 1111 1000 4 TXTST 0 1 7-5 reserved 000 +3.0dB +0.2dB default value GC7 output connected to TAUDOUT ST, SAT and TXDATA connected to GC8 input ST, SAT and TXDATA connected to TAUDOUT TAUDIN connected to GC8 input reserved for future use, set to 0 Function Control range for GC9: -3.0dB ... +3.0dB, 0.4dB/step -3.0dB -2.6dB -2.2dB
Register 0DHEX (write only) Bit 3-0 Name GC8[3:0] State 0000-1111 0000 0001 0010 ....... 1111 1000 4 5 DTX S17 0 1 0 (SYS1 = 0) 1 (SYS1 = 0) 0 (SYS1 = 1) 1 (SYS1 = 1) 0 1 7 reserved 0 +3.75dB +0.25dB default value Discontinuous transmission disabled Discontinuous transmission enabled AGND TXDATA signal AGND TX Buffer output signal AGND Signaling Tone reserved for future use, set to 0 Summed into GC8 input Function Control range for GC8: -3.75dB ... +3.75dB, 0.5dB/step -3.75dB -3.25dB -2.75dB
6
S18
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DA9191A.000 July 31, 1997
FUNCTIONS
Register 0EHEX (write only) Bit 3-0 Name GC1[3:0] State 0000-1111 0000 0001 0010 ....... 1111 1000 4 5 6 7 S1 S2 S3 S4 0 1 0 1 0 1 0 1 +3.0dB +0.2dB default value RX ALP F4 output F4 input signal from S2-RXTST0-RXTST1 RBPFIN F5 output F5 input connected to RBPFOUT connected to F5 input connected to DEOUT connected to GC1 input Function Control range for GC1: -3.0dB ... +3.0dB, 0.4dB/step -3.0dB -2.6dB -2.2dB
Register 10HEX (read only) Bit 0 1 Name STD RXWRD State 0 1 0 1 2 3 4 7-5 TXWRD TXCOL SATINT reserved 0 1 0 1 0 1 0,1 Function DTMF tone not received DTMF tone received RX buffer empty RX word received (SYS1 = 0) Next captured byte ready (SYS1 = 1) Transmitting previous byte or word TX buffer empty No TX collision detected TX collision detected SATDET signal stable rising or falling edge of SATDET detected not in use
The rising edge of the signals STD, RXWRD, TXWRD, TXCOL and SATINT activates the interrupt line XINT. If the signal(s) changes when register 10HEX or one of the other registers is read, the interrupt line will be activated right after the register read. Reading this register sets the interrupt line inactive. If a new interrupt is generated during register read , the interrupt line will be activated again right after register is read.
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DA9191A.000 July 31, 1997
FUNCTIONS
Register 11HEX (read only) Bit 0 1 2 3 4 5 6 7 Name reserved SATDET DOT WSYNC TXON BUSY BCHERR reserved State 0,1 0 1 0 1 0 1 0 1 0 1 0 1 0,1 Function not in use Invalid SAT frequency received Valid SAT frequency received. See SCC in register 14HEX. No dotting sequence detected Dotting sequence detected No word sync detected Word sync detected No transmission Word transmission on BUSY bit detected IDLE bit detected No BCH error detected BCH error detected not in use
Register 12HEX (write only) Bit 0 1 2 3 4 5 6 Name STON CTCV TXCTREN TXRST RXRST STR SYS0 State 0 1 0 1 0 1 0 1 0 1 0 1 0 (SYS1 = 0) 1 (SYS1 = 0) 0 (SYS1 = 1) 1 (SYS1 = 1) 0 1 Function No signaling tone transmission Signaling transmission on Control channel Voice channel TX control disabled TX control active. TXCTRL output pin can be used to control transmitter Digital TX section operating Digital TX section reset Digital RX section operating Digital RX section reset Stream A Stream B ETACS mode AMPS mode F9HP input connected to F9LP output. NAMPS mode F9HP input connected to GC5 output. NAMPS mode SAT transmission disabled SAT transmission enabled
7
SATEN
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DA9191A.000 July 31, 1997
FUNCTIONS
Register 13HEX (write only) Bit 1-0 Name DCC[1:0] State 00-11 00 01 10 11 2 3 4 5 6 7 INVTX INVRX AUMUT RINTE STDE SATINTE 0 1 0 1 0 1 0 1 0 1 0 1 TXDATA not inverted Invert TXDATA polarity RX input not inverted Invert RX input polarity No automatic mute TX and RX audio muted automatically on the voice channel RX interrupts disabled RX interrupts enabled STDE (DTMF receiver) interrupts disabled STDE (DTMF receiver) interrupts enabled SAT detection interrupts disabled SAT detection interrupts enabled Function Digital color code 0000000 0011111 1100011 1111100
Register 14HEX (write only) Bit 1-0 Name SCC[1:0] State 00 01 10 11 5-2 6 7 reserved SYS1 NOMSAT 0000 0 1 0 1 Function 5958Hz-5982Hz SAT frequency expected 5988Hz-6012Hz SAT frequency expected 6018Hz-6042Hz SAT frequency expected Invalid state reserved for future use, set to 0 Wide band mode (AMPS/ETACS) Narrow band mode (NAMPS) Transmitted SAT will follow received SAT Nominal SAT frequency transmitted
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DA9191A.000 July 31, 1997
FUNCTIONS
Register 15HEX (read only) Bit 7-0 Name RX byte SYS1 = 0 State 00H-FFH 1st byte 2 byte 3rd byte 4 byte 7-0 RX byte SYS1 = 1 00H-FFH
th nd
Function When RXWRD is high b0 b8 b16 b24 b1 b9 b17 b25 b2 b10 b18 b26 b3 b11 b19 b27 b4 b12 b20 0 b5 b13 b21 0 b6 b14 b22 0 b7 b15 b23 0
Captured byte with 400Hz after data comparator. MSB = first captured bit.
The received word is read by reading register 15HEX four times.
Register 16HEX (write only) Bit 7-0 Name DAC1[7:0] State 00H-FFH 80H FFH 00H 7FH Function Control port for DAC1 output level 100mVDC 100mVDC + 7FH x 13mVDC 100mVDC + 80H x 13mVDC 100mVDC + FFH x 13mVDC
Register 17HEX (write only) Bit 7-0 Name DAC2[7:0] State 00H-FFH 80H FFH 00H 7FH Function Control port for DAC2 output level 100mVDC 100mVDC + 7FH x 13mVDC 100mVDC + 80H x 13mVDC 100mVDC + FFH x 13mVDC
Register 18HEX (write only) Bit 7-0 Name DAC3[7:0] State 00H-FFH 80H FFH 00H 7FH Function Control port for DAC3 output level 100mVDC 100mVDC + 7FH x 13mVDC 100mVDC + 80H x 13mVDC 100mVDC + FFH x 13mVDC
32
DA9191A.000 July 31, 1997
FUNCTIONS
Register 19HEX (write only) Bit 7-0 Name TX byte SYS1 = 0 State 00H-FFH 1st byte 2 byte 3rd byte 4 byte 5 byte 7-0 TX byte SYS1 = 1 00H-FFH
th th nd
Function When TXWRD is high b0 b8 b16 b24 b32 b1 b9 b17 b25 b33 b2 b10 b18 b26 b34 b3 b11 b19 b27 b35 b4 b12 b20 b28 0 b5 b13 b21 b29 0 b6 b14 b22 b30 0 b7 b15 b23 b31 0
Byte for transmitter. Byte is shifted out with 200Hz clock. MSB will be transmitted first.
The transmitted word is written by writing to register 19HEX five times.
33
DA9191A.000 July 31, 1997
APPLICATION INFORMATION
RF FRONT END IF DEMODULATO R
RX
MAS9191A
RX VCO
Interfaces - DISPLAY - KEYPAD
AUDIO/DATA PROCESSOR
DUPLEX FILTER DUAL SYNTHESIZER VCXO
DAC
MICRO CONTROLLER
POWER AMP
TX VCO
TX
MEMORY
Typical MAS9191A application in AMPS/ETACS cellular system.
TEST CIRCUIT
side tone
22nF 22nF 22nF 22nF
19
R R
22nF
16
15
13
14
11
12
4
3
2
RF Modulator
22pF
C
MIC
C 18
100nF
1
EXTMIC micro controller Serial bus
17 20
A6
57
4.8MHz 1M 22pF
56
22nF
31 2 C
side tone R R
C 32 A6
MAS 9191A
100nF
buzzer
100
27 26 29
3
A3
1
100nF
6.8
48 A4 49
DTMF Receiver
22nF
earphone
100nF 100nF 1nF
30
IF
EXTEARP
28
34
R C VDD
35
36
39
40
41
42
45
46
47
4
22nF
22nF
22nF
22nF
1 2 3 4
components determine the gain of microphone amplifier A6 components determine the gain of SIDETONE amplifier A2 NPN transistor for the buzzer components determine RC time constant if DTMF receiver is used
34
DA9191A.000 July 31, 1997
PACKAGE OUTLINES
64 LEAD TQFP OUTLINE
1.60 MAX
0.80 TYPICAL
0.09 0.20
SEATING PLANE
0-7
1.35 1.45
0.05 0.15
0.30 0.45 16.00 TYPICAL 14.00 TYPICAL
0.45 0.75
ALL MEASUREMENTS IN mm
14.00 TYPICAL
16.00 TYPICAL
35
DA9191A.000 July 31, 1997
ORDERING INFORMATION
Product Code MAS9191AJ MAS9191AJ-T Product AMPS/ETACS single chip audio/data processor AMPS/ETACS single chip audio/data processor Package TQFP64 TQFP64 Comments
Tape and Reel
LOCAL DISTRIBUTOR
MICRO ANALOG SYSTEMS OY CONTACTS
Micro Analog Systems Oy Kamreerintie 2, P.O. Box 51 FIN-02771 Espoo, FINLAND Tel. +358 9 80 521 Fax +358 9 805 3213 http://www.mas-oy.com
NOTICE Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Micro Analog Systems Oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.
36

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