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S6A0071
32 COM / 60 SEG DRIVER & CONTROLLER FOR STN LCD
Jan. 2002. Ver. 0.1
Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team. Precautions for Light Light has characteristics to move electrons in the integrated circuitry of semiconductors, therefore may change the characteristics of semiconductor devices when irradiated with light. Consequently, the users of the packages which may expose chips to external light such as COB, COG, TCP and COF must consider effective methods to block out light from reaching the IC on all parts of the surface area, the top, bottom and the sides of the chip. Follow the precautions below when using the products. 1. Consider and verify the protection of penetrating light to the IC at substrate (board or glass) or product design stage. Always test and inspect products under the environment with no penetration of light.
2.
32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0071
S6A0071 Specification Revision History Version 0.0 0.1 Original Modify a pad coordinates value(R/W). Content Date Feb.1999 Jan.2002
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S6A0071
32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
INTRODUCTION
The S6A0071 is a dot matrix LCD controller & driver LSI which is fabricated by low power CMOS technology. It can display 1 line x 24 characters or 2 line x 24 characters with 5 x 7 dots format.
FEATURES
-- -- -- -- -- -- -- -- --
Character type dot matrix single chip LCD controller & driver Internal driver: 32 common and 60 segment signal output Easy interface with 4-bit or 8-bit MPU Display character pattern: 5 x 7 dots format (240 kinds) The Special character pattern is programmable by character generator RAM directly. A customer character pattern is programmable by mask option. Various instruction functions Built-in automatic power on reset Driving method is B-type (frame inversion)
FEATURES
Internal Memory
-- -- --
Character Generator ROM (CGROM): 8,400 bits (240 characters x 5 x 7 dots) Character Generator RAM (CGRAM): 64 x 8 bits (8 characters x 5 x 8 dots) Display Data RAM (DDRAM): 80 x 8 bits ( 80 characters max.)
Low Power Operation
-- --
Power supply voltage range (V DD): 2.4 to 5.5V LCD drive voltage range (V DD - V5): 3.0 to 12.0V
Voltage doubler generates about double from signals power supply On chip generation of LCD supply voltage from voltage doubler (external supply also possible) Programmable duty cycle
-- --
1/16 duty: 1 line x 5 x 7 dots + cursor x 24 characters 1/32 duty: 2 lines x 5 x 7 dots + cursor x 24 characters
Internal oscillator with an external resistor 118 TCP or bare chip available
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S6A0071
32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
BLOCK DIAGRAM
VDD GND V1 V2 V3 V4 V5 Busy Flag
Parallel/Serial Data Conversion Circuit 5 Character Generator ROM (CGROM) 8400 bits 8 5 Character Generator RAM (CGRAM) 512 bits 8 8 8 8 Instruction 8 Register (IR) 7 Address Counter (AC) 32-bit Shift Register Common 32 Driver COM1COM32 Instruction Decoder 7 Display Data RAM (DDRAM) 7 640 bits Cursor & Blink Controller Circuit
R/W 8 RS E Input/ Output Buffer
Data Register (DR)
DB0-DB3
60-bit Shift Register
60-bit Latch Circuit
Seg60 ment Driver SEG1SEG60 D
DB4-DB7
OSC1 OSC2
Timing Generator Circuit
Voltage Doubler
Vci C1 C2 V5out
T1 T2
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32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0071
PAD DIAGRAM
SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 S6A0071
SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17
Y
(0, 0)
X
Chip size: 3920 x 5080 Pad size: 100 x 100 Unit: m
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59
SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24
NOTE:
"S6A0071" marking is to make the PAD No. 95 easy to find.
VSS OSC1 OSC2 V1 V2 V3 V4 V5 V5OUT C1 C2 VCI VDD RS R/W E DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 T2 T1
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58
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S6A0071
32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
PAD CENTER COORDINATES
Pad Num. Pad Name Coordinate X Y Pad Num. Pad Name Coordinate X Y Pad Num. Pad Name Coordinate X Y
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32
-1794 -1794 -1794 -1794 -1794 -1794 -1794 -1794 -1794 -1794 -1794 -1794 -1794 -1794 -1794 -1794 -1794 -1794 -1794 -1794 -1794 -1794 -1794 -1794 -1794 -1794 -1794 -1794 -1794 -1794 -1794 -1794
2170 2030 1890 1750 1610 1470 1330 1190 1050 910 770 630 490 350 210 70 -70 -210 -350 -490 -630 -770 -910 -1050 -1190 -1330 -1470 -1610 -1750 -1890 -2030 -2170
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
V5OUT C1 C2 VCI VDD RS R/W E DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 T2 T1 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM8 COM7 COM6 COM5 COM4 COM3
-562 -438 -312 -188 -62 62 188 312 438 562 688 812 938 1062 1188 1312 1438 1562 1794 1794 1794 1794 1794 1794 1794 1794 1794 1794 1794 1794 1794 1794
-2374 -2374 -2374 -2374 -2374 -2374 -2374 -2374 -2374 -2374 -2374 -2374 -2374 -2374 -2374 -2374 -2374 -2374 -2170 -2030 -1890 -1750 -1610 -1470 -1330 -1190 -1050 -910 -770 -630 -490 -350
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112
SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38
1794 1794 1794 1794 1794 1794 1794 1794 1794 1794 1686 1561 1436 1311 1186 1061 936 811 686 561 436 311 186 61 -64 -189 -314 -439 -564 -689 -814 -939
910 1050 1190 1330 1470 1610 1750 1890 2030 2170 2374 2374 2374 2374 2374 2374 2374 2374 2374 2374 2374 2374 2374 2374 2374 2374 2374 2374 2374 2374 2374 2374
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32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0071
PAD CENTER COORDINATES (Continued)
Pad Num. Pad Name Coordinate X Y Pad Num. Pad Name Coordinate X Y Pad Num. Pad Name Coordinate X Y
33 34 35 36 37 38 39 40
VSS OSC1 OSC2 V1 V2 V3 V4 V5
-1562 -1438 -1312 -1188 -1062 -938 -812 -688
-2374 -2374 -2374 -2374 -2374 -2374 -2374 -2374
73 74 75 76 77 78 79 80
COM2 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6
1794 1794 1794 1794 1794 1794 1794 1794
-210 -70 70 210 350 490 630 770
113 114 115 116 117 118
SEG39 SEG40 SEG41 SEG42 SEG43 SEG44
-1064 -1189 -1314 -1439 -1564 -1689
2374 2374 2374 2374 2374 2374
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S6A0071
32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
PAD DESCRIPTION
Pad ( No.) VDD VSS V1-V5 S1-S60 C1-C8 C9-C16 C17-C24 C25-C32 OSC1 OSC2 RS Pad No. 45 33 36-40 75-118, 1-16 74-67, 17-24, 66-59, 25-32, 34 35 46 O O Segment output Common output I/O Name Supply voltage Description For logical circuit (+3V, 5V) Ground (0V) Bias voltage level for LCD driving Segment signal output for LCD drive Common signal output for LCD drive LCD LCD Interface Power supply
I O I
Oscillator Oscillator Register select
When using internal oscillator, connect external Rf resistor. If external clock is used, connect it to OSC1. Used as register selection input. When RS = 1, Data register is selected. When RS = 0, Instruction register is selected. Used as read/write selection input. When RW = 1, read operation. When RW = 0, write operation. Used as read/write enable signal. In 8-bit bus mode, used as low order bi-directional data bus. In 4-bit bus mode, open these pins. In 8-bit bus mode, used as high order bi-directional data bus. In 4-bit bus mode, used as both high and low order. DB7 used for busy flag output. Input terminal for voltage doubler. (normally Vci = VDD) Capacitor for voltage doubler connecting terminal (+). Capacitor for voltage doubler connecting terminal (-). Voltage doubler output terminal connected to LCD supply voltage. Maker testing terminal (normally open)
External resistor OSC1/OSC2 External clock (OSC1) MPU
R/W
47
I
Read/write
MPU
E DB0 - DB3
48 49 - 52
I I/O
Read/write Enable Data bus 0-7
MPU MPU
DB4 - DB7
53 - 56
I/O
Data bus 0-7
MPU
Vci C1,C2
44 42, 43
I I
Voltage doubler output Capacitor
Power supply Capacitor
V5OUT T1, T2
41 58, 57
O I
Voltage doubler output Test pin
V5
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32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0071
FUNCTION DESCRIPTION
System Interface This chip has both kinds of interface type with MPU: 4-bit bus and 8-bit bus. 4-bit bus and 8-bit bus are selected by the DL bit in the instruction register. During read or write operation, two 8-bit registers are used. One is the data register (DR), and the other is the instruction register (IR). The data register (DR) is used as a temporary data storage place for being written into or read from DDRAW/CGRAM . Target RAM is selected by RAM address setting instruction. Each internal operation, reading from or writing into RAM, is done automatically. Thus, after MPU reads DR data, the data in the next DDRAM/CGRAM address is transferred into DR automatically. Also, after MPU writes data to DR, the data in DR is transferred into DDRAM/CGRAM automatically. The instruction register (IR) is used only to store instruction codes transferred from MPU. MPU cannot use it to read instruction data. To select a register, you can use the RS input pin in 4-bit/8-bit bus mode. Table 1. Various Kinds of Operations to RS and R/W Bits RS 0 0 1 1 R/W 0 1 0 1 Operation Instruction Write operation (MPU writes instruction code into IR) Read Busy flag (DB7) and address counter (DB0 - DB7) Data Write operation (MPU writes data into DR) Data Read operation (MPU reads data into DR)
Busy Flag (BF) When BF = 1, it indicates that the internal operation is being processed. So during this time the next instruction cannot be accepted. BF can be read through DB7 port, when RS = 0, and R/W = 1. (Read Instruction Operation). Before executing the next instruction, be sure that BF is not 1.
Address Counter (AC) The Address Counter (AC) stores DDRAM/CGRAM addresses, transferred from IR. After writing into (reading from) DDRAM/CGRAM. AC is automatically increased (decreased) by 1. When RS = 0 and R/W = 1, AC can be read through ports DB0 - DB6.
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S6A0071
32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
Display Data RAM (DDRAM) The DDRAM stores display data of maximum 80 x 8 bits (80 characters). The DDRAM address is set in the address counter (AC) as a hexadecimal number. (Refer to fig-1).
MSB AC6 AC5 AC4 AC3 AC2 AC1
LSB AC0
Figure 1. DDRAM Address 1) 1-line Display In case of a 1-line display, the address range of DDRAM is 00H - 04H.
Display position 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0F 17 10 18 11 19 12 20 13 21 14 22 15 23 16 24 17
COM1 00 01 02 03 04 05 06 07 08 09 0A 0B COM8
SEG1 S6A0071 SEG60
0C 0D 0E SEG1
COM9 COM16
S6A0071 DDRAM Address
SEG60
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 0F
16 10
17 11
18 12
19 13
20 14
21 15
22 16
23 17
24 18
COM1 01 02 03 04 05 06 07 08 09 0A 0B 0C COM8
0D 0E
COM9 COM16
(After Shift Left) 1 2 3 4 5 6 7 8 9 10 11 12 13 0B 14 15 16 17 0F 18 10 19 11 20 12 21 13 22 14 23 15 24 16
COM1 4F 00 01 02 03 04 05 06 07 08 09 0A COM8
0C 0D 0E
COM9 COM16
(After Shift Right)
Figure 2. 1-line x 24 char. Display
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32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0071
2) 2-line Display In case of a 2-line display, the address range of DDRAM is 00H - 27H and 40H - 67H.
Display position 1 2 01 3 02 4 03 5 04 6 05 7 06 8 07 9 08 10 09 11 12 13 14 15 16 17 10 18 11 19 12 20 13 21 14 22 15 23 16 24 17
COM1 COM8 COM17 COM24
00
0A 0B
0C 0D 0E 0F
COM9 COM16 COM25 COM32
DDRAM Address 40 41 42 43 44 45 46 47 48 49 4A 4B SEG60 4C 4D 4E 4F SEG1 50 51 52 53 54 55 56 57
SEG1
S6A0071
S6A0071
SEG60
1
2 02
3 03
4 04
5 05
6 06
7 07
8 08
9 09
10 0A
11
12
13
14
15 0F
16 10
17 11
18 12
19 13
20 14
21 15
22 16
23 17
24 18
COM1 COM8 COM17 COM24
01
0B 0C
0D 0E
COM9 COM16
41
42
43
44
45
46
47
48
49
4A
4B 4C
4D 4E
4F
50
51
52
53
54
55
56
57
58
COM25 COM32
(After Shift Left) 1 2 00 3 01 4 02 5 03 6 04 7 05 8 06 9 07 10 08 11 09 12 0A 13 0B 14 15 16 17 0F 18 10 19 11 20 12 21 13 22 14 23 15 24 16
COM1 COM8 COM17 COM24
27
0C 0D 0E
COM9 COM16 COM25 COM32
67
40
41
42
43
44
45
46
47
48
49
4A
4B
4C 4D 4E
4F
50
51
52
53
54
55
56
(After Shift Right)
Figure 3. 2-line x 24 char. Display with 60 SEG. Extension Driver
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S6A0071
32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
CGROM (Characteristic Generator ROM) CGROM has a 5 x 7 dots 240 character pattern. CGRAM (Character Generator RAM) CGRAM has up to 5 x 8 dots 8 characters. By writing font data to CGRAM, user defined characters can be used (Refer to Table 3). Timing Generation Circuit The timing generation circuit generates clock signals for the internal operations. LCD Driver Circuit LCD Driver circuit has 32 common and 60 segment signals for LCD driving. Data from CGRAM/CGROM is transferred to an 60-bit segment latch serially, and then stored to an 60-bit shift latch. When each com is selected by a 32-bit common register, segment data is also outputs through the segment driver from and 60-bit segment latch. In case of a 1-line display mode, COM1 - COM16 have 1/16 duty, and in 2-line display mode, COM1 - COM32 have 1/32 duty ratio. Cursor/Blink Control Circuit It controls cursor/blink ON/OFF at cursor position.
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32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0071
Table 3. Relationship Between Character Code (DDRAM) and Character Pattern (CGROM)
Character Code (DDRAM data) CGRAM Address CGRAM Data D7 D6 D5 D4 D3 D2 D1 D0 A5 A4 A3 A2 A1 A0 P7 P6 P5 P4 P3 P2 P1 P0 0000x 000000000x x x 01110 001 10001 010 10001 . . . 011 11111 . . . . . . 100 10001 . . . 101 10001 . . . 110 10001 1 . . . . . 0 0 0 0 x 1 1 1 1 1 . . . . . 1 1 1 0 . . . . . 1 1 1 1 1 1 1 0 0 0 0 0 . . . . . Pattern 8 Pattern number Pattern 1
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
x
x
x
0 0 0 1 0 0 0 0
0 0 0 1 0 0 0 0
0 0 0 1 0 0 0 0
1 1 1 1 1 1 1 0
. . . . .
. . . . .
. . . . .
"X": Don't care.
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S6A0071
32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
INSTRUCTION DESCRIPTION
OUTLINE To overcome the speed difference between internal clock of S6A0071 and MPU clock, S6A0071 performs internal operation by storing control information to IR or DR. The internal operation is determined according to the signal from MPU, composed of read/write and data bus. (refer to Table 5 ) Instruction can be divided largely four kinds, (1) S6A0071 function set instructions ( set display methods, set data length, etc.) (2) Address set instructions to internal RAM (3) Data transfer instructions with internal RAM (4) Others. The address of internal RAM is automatically increased or decreased by 1. NOTE During internal operation, Busy Flag (DB7) is read "1". Busy Flag check must be precede by the next instruction. When you make an MPU program with checking the Busy Flag (DB7) is made, it must be necessary 1/2 fosc for executing the next instruction by falling E signal after the Busy Flag (DB7) goes to "0". CONTENTS Clear Display RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1
Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to "00H" into AC (address counter). Return cursor to the original status, namely, bring the cursor to the left edge on first line of the display. Make entry mode increment (I/D = "1"). Return Home RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 x * "x": don't care Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. Return cursor to its original site and return display to its original status, if shifted. Contents of DDRAM does not change.
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32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0071
Entry Mode Set RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 1 DB1 I/D DB0 SH
Set the moving direction of cursor and display. I/D: Increment/Decrement of DDRAM Address (Cursor or Blink) When I/D = "1", cursor/blink moves to right and DDRAM address is increased by 1. When I/D = "0", cursor/blink moves to left and DDRAM address is decreased by 1. * CGRAM operates the same as DDRAM, when reading from or writing to CGRAM. SH: Shift of Entire Display When DDRAM is in the read (CGRAM read/write) operation or SH = "0", shift of entire display is not performed. If SH = "1" and DDRAM is in the write operation, shift of entire display is performed according to I/D value (I/D = "1" : shift left, I/D = "0" : shift right). Display ON/OFF Control RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 D DB1 C DB0 B
Control display/cursor/blink ON/OFF 1 bit register. D: Display ON/OFF Control Bit When D = "1", entire display is turned on. When D = "0", display is turned off, but display data remained in DDRAM. C: Cursor ON/OFF Control Bit When C = "1", cursor is turned on. When C = "0", cursor is disappeared in current display, but I/D register preserves its data. B: Cursor Blink ON/OFF Control Bit When B = "1", cursor blink is on, which performs alternate between all the "1" data and display character at the cursor position. When B = "0", blink is off.
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S6A0071
32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
Cursor or Display Shift RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 S/C DB2 R/L DB1 x DB0 x
Without waiting or reading the display data, shift right/left cursor position or display. This instruction is used to correct or search display data (Refer to table 6). During 2-line mode display, cursor moves to the 2nd line after the 40th digit of the 1st line. Note that display shift is performed simultaneously for the whole line. When displayed data is shifted repeatedly, each line is shifts individually. When display shift is performed, the contents of the address counter are not changed. Table 6. Shift Patterns According to S/C and R/L Bits S/C 0 0 1 1 R/L 0 1 0 1 Operation Shift cursor to the left, AC is decreased by 1 Shift cursor to the right, AC is increased by 1 Shift all the display to the left, cursor moves according to the display Shift all the display to the right, cursor moves according to the display
Function Set RS 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 DL DB3 N DB2 x DB1 x DB0 x
DL: Interface data length control bit When DL = "1", it means 8-bit bus mode with MPU. When DL = "0", it means 4-bit bus mode with MPU. Hence, DL is a signal to select 8-bit or 4-bit bus mode. When 4bit bus mode, it needs to transfer 4-bit data by two times. N: Display line number control bit When N = "0", it means 1-line display mode. When N = "1", 2-line display mode is set. Set CGRAM Address RS 0 R/W 0 DB7 0 DB6 1 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0
Set CGRAM address to AC. This instruction makes CGRAM data available from MPU.
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32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0071
Set DDRAM Address RS 0 R/W 0 DB7 1 DB6 AC6 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0
Set DDRAM address to AC. This instruction makes DDRAM data available from MPU. When 1-line display mode (N = 0), DDRAM address is from "00H" to "4FH". In 2-line display mode (N = 1), DDRAM address in the 1st line is from "00H" to "27H", and DDRAM address in the 2nd line is from "40H" to "67H". Read Busy Flag & Address RS 0 R/W 1 DB7 BF DB6 AC6 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0
This instruction shows whether S6A0071 is in internal operation or not. If the resultant BF is "1", it means the internal operation is in progress and you have to wait until BF to be Low, and then the next instruction can be performed. In this instruction you can read also the value of address counter. Write data to RAM RS 1 R/W 0 DB7 D7 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0
Write binary 8-bit data to DDRAM/CGRAM. The selection of RAM from DDRAM, and CGRAM, is set by the previous address set instruction: (DDRAM address set, CGRAM address set). RAM set instruction can also determine the AC direction to RAM. After write operation, the address is automatically increased/decreased by 1, according to the entry mode. Read data from RAM RS 1 R/W 1 DB7 D7 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0
Read binary 8-bit data from DDRAM/CGRAM. The selection of RAM is set by the previous address set instruction. If the address set instruction of RAM is not performed before this instruction, the data that is read first is invalid, because the direction of AC is not determined. If you read RAM data several times without RAM address set instruction before read operation, you can get correct RAM data from the second, but the first data would be incorrect, because there is no time margin to transfer RAM data. In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address set instruction; it also transfer RAM data to output data register. After read operation address counter is automatically increased/decreased by 1 according to the entry mode. After CGRAM read operation, display shift may not be executed correctly.
NOTE: In case of RAM write operation, AC is increased/decreased by 1 like read operation. In this time, AC indicates the next address position, but you can read only the previous data by read instruction.
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S6A0071
32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
Table 6. Instruction Table
Instruction
RS R/W DB7
Instruction Code
DB6 DB5 DB4 DB3 DB2 DB1 DB0
Description Instruction Code
Write "20H" to DDRAM. and set DDRAM address to "00H" from AC. Set DDRAM address to "00H" from the AC and return cursor to its original position if shifted. The contents of DDRAM are not change. Assign cursor moving direction and make shift of entire display possible. Set display(D), cursor(C), and blinking of cursor(B) on/off control bit. Set cursor moving and display shift control bit, and the direction, without changing of the AC. Set interface data length (DL : 4bit/8-bit), numbers of display line (N : 1-line/2-line). Set CGRAM address in address counter. Set DDRAM address in address counter. Whether during internal operation or not can be known by reading BF. The contents of address counter can also be read. Write data into internal RAM (DDRAM/CGRAM). Read data from internal RAM (DDRAM/CGRAM).
Execution time (fsoc=270)
1.53ms
Clear Display
0
0
0
0
0
0
0
0
0
1
Return Home
0
0
0
0
0
0
0
0
1
X
1.53ms
Entry Mode Set
0
0
0
0
0
0
0
1
I/D
SH
39s
Display ON/OFF Control Cursor or Display Shift
0
0
0
0
0
0
1
D
C
B
39s
0
0
0
0
0
1
S/C
R/L
X
X
39s
Function Set
0
0
0
0
1
DL
N
X
X
X
39s
Set CGRAM Address Set DDRAM Address Read Busy Flag and Address
0
0
0
1
AC5
AC4
AC3
AC2
AC1
AC0
39s
0
0
1
AC6
AC5
AC4
AC3
AC2
AC1
AC0
39s
0
1
BF
AC6
AC5
AC4
AC3
AC2
AC1
AC0
0s
Write Data to RAM Read Data from RAM
1
0
D7
D6
D5
D4
D3
D2
D1
D0
43s
1
1
D7
D6
D5
D4
D3
D2
D1
D0
43s
*"x": don't care NOTE: When you make an MPU program, checking the Busy Flag (DB7), a time margin of 1/2 fOSC is necessary for executing the next instruction by the falling edge of the 'E' signal after the Busy Flag (DB7) goes to "0".
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32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0071
INTERFACE WITH MPU Interface with 8-bit MPU When the interfacing data length are 8-bit, transfer is performed all at once through 8 ports, from DB0 to DB7. An example of the timing sequence is shown below.
RS R/W
E Internal signal DB7 DATA
Internal Operation No Busy
Busy
Busy
DATA
Instruction
Busy Flag Check Busy Flag Check
Busy Flag Check
Instruction
Figure 4. Example of 8-bit Bus Mode Timing Diagram Interface with 4-bit MPU When interfacing data length is 4-bit, only 4 ports, from DB4 to DB7, are used as data bus. At first higher 4-bit (in the case of 8-bit bus mode, the contents of DB4 - DB7), and then lower 4-bit (in case of 8-bit bus mode, the contents of DB0 - DB3) are transferred. So transfer is performed twice Busy Flag outputs "high" after the second transfer are ended. An example of timing sequence is shown below.
RS R/W E Internal signal DB7 D7 D3
Internal Operation No Busy
Busy
AC3
AC3
D7
D3
Instruction
Busy Flag Check
Busy Flag Check
Instruction
Figure 5. Example of 4-bit Bus Mode Timing Diagram
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S6A0071
32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
APPLICATION INFORMATION ACCORDING TO LCD PANEL LCD Panel: 24 character x 1-line character format: 5 x 7 dots + 1 cursor line (1/5 bias, 1/16 duty)
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 SEG1 SEG2 SEG3 SEG4 SEG5 S6A0071 SEG6 SEG7 SEG8 SEG9 SEG10 SEG58 SEG59 SEG60 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 ..
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32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0071
LCD Panel: 24 character x 2-line character format: 5 x 7 dots + 1 cursor line (1/6.7 bias, 1/32 duty)
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 SEG1 SEG2 SEG3 SEG4 SEG5 SEG58 SEG59 SEG60 COM32 COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 ..
S6A0071
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S6A0071
32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
POWER SUPPLY FOR DRIVING LCD PANEL
When an external power supply is used
V5OUT VSS
Open Open
C1 C2
VDD V1 V2 V3 V4 V5
VDD R R R0 R R
VEE
When an internal booster is use d (Boosting twice)
VDD VR 4.7F + Vci C1 + C2 4.7F V5OUT VSS + VDD V1 V2 V3 V4 V5 R R R0 R R VDD 4.7F + Vci C1 + C2 4.7F V5OUT VSS + VR: Contrast Control Resistor VDD V1 V2 V3 V4 V5 R R R0 R R VR 4.7F 4.7F
NOTES: 1. Boosted output voltage should not exceed the maximum value (11V) of the LCD driving voltage. 2. A voltage of over 5.5V should not be input into the reference voltage (Vci) when boosting twice. 3. The value of resistance, according to the number of lines, duty ratio and the bias, is shown below. (Refer to table 8)
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32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0071
Table 8. Duty Ratio and Power Supply for LCD Driving Item Number Duty Ratio Bias Divided Resistance R R0 1 1/16 1/5 R R Data 2 1/32 1/6.7 R 2.7R
INITIALIZING When the power is turned on, S6A0071 is initialized automatically by power on reset circuit. During the initialization, the following instructions are executed, and BF(Busy Flag) is kept "High"(busy state) to the end of initialization. (1) Display Clear instruction: Write "20H" to all DDRAM (2) Set Functions instruction DL = 1 : 8-bit bus mode N = 1 : 2-line display mode (3) Control Display ON/OFF instruction D = 0 : Display OFF C = 0 : Cursor OFF B = 0 : Blink OFF (4) Set Entry Mode instruction I/D = 1 : Increment by 1 SH = 0 : No entire display shift
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S6A0071
32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
FRAME FREQUENCY B-Type Waveform (Frame Inversion) 1) 1/16 Duty Cycle
1-line selection period 1 VDD V1 ... V4 V5 1 Frame 1 Frame COM1 2 3 4 ... 15 16 1 2 3 ... 15 16
Item 1-line selection period Frame frequency
Clock/Frequency 120 clocks 140.7Hz * fOSC = 270kHz (1 clock = 3.7s)
2) 1/32 duty cycle
1-line selection period 1 VDD V1 COM1 V4 V5 1 Frame 1 Frame ... 2 3 4 ... 31 32 1 2 3 ... 31 32
Item Line Selection Period Frame Frequency
Clock/Frequency 120 clocks 70.4Hz * fOSC = 270kHz (1 clock = 3.7s)
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32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0071
INITIALIZING BY INSTRUCTION
8-bit Interface mode
Power On
Wait for more than 20ms after V DD rises to 4.5V Wait for more than 30ms after V DD rises to 2.7V DL Function Set RS 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 DL(1) DB3 N DB2 X DB1 X DB0
Condition: fosc = 270kHz 0 1 0 X N 1 2-line mode 4-bit interface 8-bit interface 1-line mode
Wait for more than 39 s D
0 1
Display off Display on Cursor off Cursor on Blink off Blink on
Display ON/OFF Control RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 D DB1 C DB0 C B 1 0 B 1 0
Wait for more than 39 s
Display Clear RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1
Wait for more than 1.53 ms 0 I/D Entry Mode Set RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 1 DB1 I/D DB0 0 SH SH 1 Initialization End Entire shift on Entire shift off 1 Increment mode Decrement mode
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S6A0071
32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
4-bit Interface mode
Power On
Wait for more than 20ms after DD rises to 4.5V V Wait for more than 30ms after DD rises to 2.7V V Condition: fosc = 270kHz Function Set DL RS 0 R/W DB7 0 0 DB6 0 DB5 1 DB4 DL(0) DB3 X DB2 X DB1 X DB0 X 0 F Wait for more than 39s 1 2-line mode 1-line mode 1 8-bit interface 0 4-bit interface
Function Set RS 0 0 R/W DB7 0 0 0 N DB6 0 X DB5 1 X DB4 0 X DB3 X X DB2 X X DB1 X X DB0 X X
Wait for more than 39s 0 D Display ON/OFF Control RS 0 0 R/W DB7 0 0 0 1 DB6 0 D DB5 0 C DB4 0 B DB3 X X DB2 X X DB1 X X DB0 0 X X 0 Wait for more than 39s B 1 Blink on Blink off C 1 Cursor on Cursor off 1 Display on Display off
Clear Display RS 0 0 R/W DB7 0 0 0 0 DB6 0 0 DB5 0 0 DB4 0 1 DB3 X X DB2 X X DB1 X X DB0 X X
Wait for more than 1.53 s m
Entry Mode Set I/D RS 0 0 R/W DB7 0 0 0 0 DB6 0 1 DB5 0 I/D DB4 0 SH DB3 X X DB2 X X DB1 X X DB0 X
0 1 0 X SH 1
Decrement mode Increment mode Entire shift off Entire shift on
Initialization End
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32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0071
MAXIMUM ABSOLUTE LIMIT RATING
Maximum Absolute Power Ratings Description Power Supply Voltage (1) Power Supply Voltage (2) Input Voltage
NOTE:
Symbol VDD VLCD VIN
Unit V V V - 0.3 to +7.0
Value
VDD-13.5 to VDD+3.0 -0.3 to VDD+0.3
Voltage greater than above may damage the circuit. (VDD V1 2 V3 V4 V5)
Temperature Characteristics Description Operating Temperature Storage Temperature Symbol TOPR TSTG Unit C C Value - 3.0 to +85 - 55 to +125
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S6A0071
32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
ELECTRICAL CHARACTERISTICS
DC Characteristics ( VDD = +5V 10%, TA = -30 to +85C) Characteristic Operating voltage Supply current Symbol VDD IDD Condition - Internal oscillation or external clock operation. (V DD = 5V, fOSC = 270 kHz) - - - - IOH = -0.205mA IOL = 1.6mA IO = -40A IO = 40A IO = 0.1mA Min 4.5 - Typ 5.0 0.6 Max 5.5 1.0 Unit V mA
Input voltage (1) (except OSC1) Input voltage (2) (OSC1) Output voltage (1) (DB0 to DB7) Output voltage (2) (OSC2) Voltage drop
VIH1 VIL1 VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 VdCOM VdSEG
2.3 - VDD-1.0 - 2.4 - 0.9V DD - - -
- - - - - - - - - - - - -125 270 250 50 - -4.7 99.9 - -
VDD 0.8 VDD 1.0 - 0.4 - 0.1V DD 1 1 1 5 -250 350 350 55 0.2 - - 5.5 13.5
V
V
V
V
V
Input Leakage Current (1) E Input leakage current(2) (R/W, RS, DB0 to DB7) Low Input Current (R/W, RS, DB0 to DB7) Internal Clock (external Rf)
IIL1 IIL2 IIN fIC fEC
VIN = 0V to VDD VIN = VDD VIN = 0V, VDD = 5V (pull up) Rf = 91k 2% (V DD = 5V) -
-1 -5 -50 190 160 45 -
A
kHz kHz % s V % V V
External Clock
duty tR, tF V5out Iout = 1mA, Ta = 25C RL = Input voltage VDD-V5 (1/5, 1/6.7 bias)
-4.5 95 2.5 3.0
Voltage Doubler
VEF Vci
LCD Driving Voltage
VLCD
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32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0071
DC Characteristics (V DD = +3V 20%, TA = -30 to +85C) Characteristic Operating voltage Supply current Symbol VDD IDD Condition - Internal oscillation or external clock. (V DD = 3V, fOSC = 270kHz) - - - - IOH = -0.205mA IOL = 1.6mA IO = -40A IO = 40A IO = 0.1mA Min 2.4 - Typ 3.0 0.2 Max 3.6 0.3 Unit V mA
Input voltage (1) (except OSC1) Input voltage (2) (OSC1) Output voltage (1) (DB0 to DB7) Output voltage (2) (OSC2) Voltage drop
VIH1 VIL1 VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 VdCOM VdSEG
0.8V DD - VDD-1.0 - 2.0 - 0.9V DD - - -
- - - - - - - - - - - - -25 240 -2.75 99.9 - -
VDD 0.2V DD VDD 1.0 - 0.5 - 0.1V DD 1 1 1 5 -50 320 - - VDD 12.0
V
V
V
V
V
Input Leakage Current (1) E Input leakage current(2) (R/W, RS, DB0 to DB7) Low Input Current (R/W, RS, DB0 to DB7) Internal Clock (external Rf)
IIL1 IIL2 IIN fIC V5out
VIN = 0V to VDD VIN = VDD VIN = 0V, VDD = 3V (pull up) Rf = 91k 2% (V DD = 3V) Iout = 1mA, Ta = 25C RL = Input voltage VDD-V5 (1/5, 1/6.7 bias)
-1 -5 -10 160 -2.5 95 1.8 3.0
A
kHz V % V V
Voltage Doubler
VEF Vci
LCD Driving Voltage
VLCD
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S6A0071
32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
AC Characteristics (V DD = 4.5 to 5.5V, TA = -30 to +85C) Mode Write Mode (Refer to figure 6) Characteristic E Cycle Time E Rise Time/Fall Time E Pulse Width ( High, Low ) R/W and RS Setup Time R/W and RS Hold Time Data Setup Time Data Hold Time Read Mode (Refer to figure 7) E Cycle Time E Rise Time/Fall Time E Pulse Width ( High, Low ) R/W and RS Setup Time R/W and RS Hold Time Data Output Delay Time Data Hold Time Symbol tC tR, tF tW tSU1 th1 tSU2 th2 tC tR, tF tW tSU th tD tDH Min 500 - 220 40 10 60 10 500 - 220 40 10 - 10 Typ - - - - - - - - - - - - - - Max - 20 - - - - - - 20 - - - 120 - ns ns Unit
AC Characteristics (V DD = 2.4 to 3.6V, TA = -30 to +85C) Mode Write Mode (Refer to figure 6) Characteristic E Cycle Time E Rise Time/Fall Time E Pulse Width ( High, Low ) R/W and RS Setup Time R/W and RS Hold Time Data Setup Time Data Hold Time Read Mode (Refer to figure 7) E Cycle Time E Rise Time/Fall Time E Pulse Width ( High, Low ) R/W and RS Setup Time Symbol tC tR, tF tW tSU1 th1 tSU2 th2 tC tR, tF tW tSU Min 1400 - 500 70 10 195 10 1400 - 500 70 Typ - - - - - - - - - - - Max - 20 - - - - - - 20 - - ns ns Unit
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32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0071
R/W and RS Hold Time Data Output Delay Time Data Hold Time
th tD tDH
10 - 20
- - -
- 600 -
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S6A0071
32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
RS
VIH1 VIL1 tSU1 VIL1 tW
t H1 VIL1 tH1 tf VIH1 VIL1 tSU2 Valid Data tC
R/W
E tR DB0 - DB7
VIH1 VIL1 VIH1 VIL1
tH2 VIH1 VIL1
VIL1
Figure 6. Write Mode Timing Diagram
RS
VIH1 VIL1 tSU VIH1 tW
tH VIH1 tH1 tF VIH1 VIL1 tD VIH1 VIL1 t DH Valid Data tC VIH1 VIL1
R/W
E tR DB0 - DB7
VIH1 VIL1
VIL1
Figure 7. Read Mode Timing Diagram
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32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0071
NOTES
31

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