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| PRELIMINARY ElanTMSC520 Microcontroller Integrated 32-Bit Microcontroller with PC/AT-Compatible Peripherals, PCI Host Bridge, and Synchronous DRAM Controller DISTINCTIVE CHARACTERISTICS s Industry-standard Am5x86(R) CPU with floating s ROM/Flash controller for 8-, 16-, and 32-bit devices s Enhanced PC/AT-compatible peripherals s s s s s point unit (FPU) and 16-Kbyte write-back cache - 100-MHz and 133-MHz operating frequencies - Low-voltage operation (core VCC = 2.5 V) - 5-V tolerant I/O (3.3-V output levels) E86TM family of x86 embedded processors - Part of a software-compatible family of microprocessors and microcontrollers well supported by a wide variety of development tools Integrated PCI host bridge controller leverages standard peripherals and software - 33 MHz, 32-bit PCI bus Revision 2.2-compliant - High-throughput 132-Mbyte/s peak transfer - Supports up to five external PCI masters - Integrated write-posting and read-buffering for high-throughput applications Synchronous DRAM (SDRAM) controller - Supports 16-, 64-, 128-, and 256-Mbit SDRAM - Supports 4 banks for a total of 256 Mbytes - Error Correction Code provides system reliability - Buffers improve read and write performance AMDebugTM technology offers a low-cost solution for the advanced debugging capabilities required by embedded designers - Allows instruction tracing during execution from the Am5x86 CPU's internal cache - Uses an enhanced JTAG port for low-cost debugging - Parallel debug port for high-speed data exchange during in-circuit emulation General-Purpose (GP) bus with programmable timing for 8- and 16-bit devices provides good performance at low cost provide improved performance - Enhanced programmable interrupt controller (PIC) prioritizes 22 interrupt levels (up to 15 external sources) with flexible routing - Enhanced DMA controller includes double buffer chaining, extended address and transfer counts, and flexible channel routing - Two 16550-compatible UARTs operate at baud rates up to 1.15 Mbit/s with optional DMA interface s Standard PC/AT-compatible peripherals - Programmable interval timer (PIT) - Real-time clock (RTC) with battery backup capability and 114 bytes of RAM s Additional integrated peripherals - Three general-purpose 16-bit timers provide flexible cascading for 32-bit operation - Watchdog timer guards against runaway software - Software timer - Synchronous serial interface (SSI) offers full-duplex or half-duplex operation - Flexible address decoding for programmable memory and I/O mapping and system addressing configuration s 32 programmable input/output (PIO) pins s Native support for pSOS, QNX, RTXC, VxWorks, and Windows(R) CE operating systems s Industry-standard BIOS support s Plastic Ball Grid Array (PBGA388) package GENERAL DESCRIPTION The ElanTMSC520 microcontroller is a full-featured microcontroller developed for the general embedded market. The ELANSC520 microcontroller combines a 32-bit, low-voltage Am5 x86 CPU with a set of integrated peripherals suitable for both real-time and PC/ AT-compatible embedded applications. An integrated PCI host bridge, SDRAM controller, enhanced PC/AT-compatible peripherals, and advanced debugging features provide the system designer with a wide range of on-chip resources, allowing support for legacy devices as well as new devices available in the current PC marketplace. (c) Copyright 2001 Advanced Micro Devices, Inc. All rights reserved. Designed for medium- to high-performance applications in the telecommunications, data communications, and information appliance markets, the ELANSC520 microcontroller is particularly well suited for applications requiring high throughput combined with low latency. The compact Plastic Ball Grid Array (PBGA) package provides a high degree of functionality in a very small form factor, making it cost-effective for many applications. A 0.25-micron CMOS manufacturing process allows for low power consumption along with high performance. Final Draft# 22003 Rev: B Amendment/0 Issue Date: March 2001 PRELIMINARY ORDERING INFORMATION ELANSC520 -133 A C TEMPERATURE RANGE C= Commercial (TC =0C to +85C) where: TC = case temperature PACKAGE TYPE A = 388-Pin Plastic Ball Grid Array (PBGA) SPEED OPTION -100 = 100 MHz -133 = 133 MHz DEVICE NUMBER/DESCRIPTION ELANSC520 integrated 32-bit microcontroller with PC/AT-compatible peripherals, PCI host bridge, and synchronous DRAM controller Valid Combinations ELANSC520-100 ELANSC520-133 AC Valid Combinations Valid combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. 2 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY TABLE OF CONTENTS Distinctive Characteristics ............................................................................................................ 1 General Description ..................................................................................................................... 1 Ordering Information .................................................................................................................... 2 Logic Diagram by Interface ........................................................................................................... 6 Logic Diagram by Default Pin Function ........................................................................................ 7 Connection Diagram .................................................................................................................... 8 Pin Designations ........................................................................................................................ 10 Pin Designations (Pin Number) ............................................................................................. 11 Pin Designations (Pin Name) ................................................................................................ 13 Signal Descriptions ..................................................................................................................... 16 Architectural Overview ............................................................................................................... 28 Industry-Standard x86 Architecture ....................................................................................... 30 AMDebugTM Technology for Advanced Debugging .............................................................. 30 Industry-Standard PCI Bus Interface .................................................................................... 30 High-Performance SDRAM Controller ................................................................................. 30 ROM/Flash Controller ........................................................................................................... 30 Flexible Address-Mapping Hardware .................................................................................... 31 Easy-to-Use GP Bus Interface .............................................................................................. 31 Clock Generation .................................................................................................................. 31 Integrated Peripherals ........................................................................................................... 31 JTAG Boundary Scan Test Interface .................................................................................... 32 System Test and Debug Features ........................................................................................ 32 Applications ............................................................................................................................... 33 Clock Generation and Control ................................................................................................... 38 Internal Clocks ...................................................................................................................... 39 Clock Specifications .............................................................................................................. 40 Clock Pin Loading ................................................................................................................. 40 Selecting a Crystal ................................................................................................................ 41 32.768-kHz Crystal Selection ........................................................................................... 41 33-MHz Crystal Selection................................................................................................. 42 Third Overtone Crystal Component Selection .................................................................. 42 Running the ElanTMSC520 Microcontroller at 33.333 MHz ........................................................... 43 Bypassing Internal Oscillators ............................................................................................... 44 RTC Voltage Monitor ................................................................................................................. 45 Backup Battery Considerations ............................................................................................. 46 Using an External RTC Backup Battery ........................................................................... 46 Not Using an External RTC Backup Battery..................................................................... 46 Absolute Maximum Ratings ....................................................................................................... 48 Operating Ranges at Commercial Temperatures ...................................................................... 48 Voltage Levels for Non-PCI Interface Pins ................................................................................ 49 Voltage Levels for PCI Interface Pins ........................................................................................ 49 DC Characteristics Over Commercial Operating Ranges .......................................................... 50 Capacitance ............................................................................................................................... 51 Non-PCI Interface Pin Capacitance ...................................................................................... 51 PCI Interface Pin Capacitance .............................................................................................. 51 Crystal Capacitance .............................................................................................................. 51 Derating Curves .................................................................................................................... 51 Power Characteristics ................................................................................................................ 56 Thermal Characteristics ...................................................................................................................56 388-Pin PBGA Package .............................................................................................................56 Switching Characteristics and Waveforms ................................................................................ 58 Key to Switching Waveforms ................................................................................................ 58 ElanTMSC520 Microcontroller Data Sheet 3 PRELIMINARY AC Switching Test Waveforms .................................................................................................. 58 Non-PCI Bus Interface Pins .................................................................................................. 58 PCI Bus Interface Pins .......................................................................................................... 58 Switching Characteristics over Commercial Operating Ranges ....................................................................59 Power-On Reset Timing ........................................................................................................ 59 Reset Timing with Power Applied ......................................................................................... 61 ROM Timing .......................................................................................................................... 63 PCI Bus Timing ..................................................................................................................... 65 SDRAM Timing ..................................................................................................................... 66 SDRAM Clock Timing ........................................................................................................... 68 GP Bus Timing ...................................................................................................................... 69 GP Bus DMA Read Cycle Timing ......................................................................................... 71 GP Bus DMA Write Cycle Timing .......................................................................................... 72 SSI Timing ............................................................................................................................. 73 JTAG Timing ......................................................................................................................... 74 Appendix A: Pin Tables ............................................................................................................A-1 Pin List Summary Table Column Definitions ............................................................................ A-6 Appendix B: Physical Dimensions ............................................................................................B-1 388-Pin Plastic BGA (PBGA) Package ................................................................................B-1 Top View ..............................................................................................................................B-1 Bottom View ........................................................................................................................B-2 Circuit Board Layout Considerations ....................................................................................B-3 Appendix C: Customer Support ................................................................................................C-1 Related Documents ..............................................................................................................C-2 Additional Information ..........................................................................................................C-2 Customer Development Platform .........................................................................................C-2 Third-Party Development Support Products .................................................................................C-2 Customer Service .................................................................................................................C-3 Hotline and World Wide Web Support............................................................................. C-3 Corporate Applications Hotline........................................................................................ C-3 World Wide Web Home Page ......................................................................................... C-3 Documentation and Literature ......................................................................................... C-3 Literature Ordering .......................................................................................................... C-3 Index ................................................................................................................................... Index-1 LIST OF FIGURES Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. 4 ElanTMSC520 Microcontroller Block Diagram ....................................................... 29 ElanTMSC520 Microcontroller-Based Smart Residential Gateway Reference Design ................................................................................................. 34 ElanTMSC520 Microcontroller-Based Thin Client Reference Design .................... 35 ElanTMSC520 Microcontroller-Based Digital Set Top Box Reference Design ....... 36 ElanTMSC520 Microcontroller-Based Telephone Line Concentrator Reference Design ................................................................................................. 37 System Clock Distribution Block Diagram ............................................................. 38 Clock Source Block Diagram ................................................................................ 39 32.768-kHz Crystal Circuit .................................................................................... 41 33.333-MHz Third Overtone Crystal Implementation ............................................ 43 Bypassing the 32.768-kHz Oscillator .................................................................... 44 Bypassing the 33-MHz Oscillator .......................................................................... 44 RTC Voltage Monitor Block Diagram .................................................................... 45 Circuit with Backup Battery ................................................................................... 47 Circuit without Backup Battery .............................................................................. 47 I/O Drive 6-mA Rise Time ..................................................................................... 52 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. I/O Drive 6-mA Fall Time ....................................................................................... 52 I/O Drive 12-mA Rise Time ................................................................................... 53 I/O Drive 12-mA Fall Time ..................................................................................... 53 I/O Drive 24-mA Rise Time ................................................................................... 54 I/O Drive 24-mA Fall Time ..................................................................................... 54 PCI Pads Rise Time with 1-ns Rise/Fall ............................................................... 55 PCI Pads Fall Time with 1-ns Rise/Fall ................................................................. 55 Thermal Resistance (C/Watt) .............................................................................. 56 Thermal Characteristics Equations ....................................................................... 57 AC Switching Test Waveforms .............................................................................. 58 Power-Up Timing Sequence ................................................................................. 60 PWRGOOD Timing for RTC Standalone Mode .................................................... 60 External System Reset Timing with Power Applied .............................................. 61 PRGRESET Timing ............................................................................................... 62 Internal System Reset Timing ............................................................................... 62 Non-Burst ROM Read Cycle Timing ..................................................................... 64 Page-Mode ROM Read Cycle Timing ................................................................... 64 Flash Write Cycle Timing ...................................................................................... 65 SDRAM Write and Read Timing ........................................................................... 67 SDRAM Clock Timing ........................................................................................... 68 GP Bus Non-DMA Cycle Timing ........................................................................... 70 GP-DMA Read Cycle Timing ................................................................................ 71 GP-DMA Write Cycle Timing ................................................................................. 72 SSI Timing ............................................................................................................. 73 JTAG Boundary Scan Timing ................................................................................ 74 BGA Ball Pad Layout ...........................................................................................B-3 LIST OF TABLES Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Signal Descriptions Table Definitions..................................................................... 16 Signal Descriptions ............................................................................................... 17 Clock Jitter Specifications ..................................................................................... 40 Clock Startup and Lock Times .............................................................................. 40 Oscillator Input Specifications ............................................................................... 40 Analog VCC (VCC_ANLG) Specifications ............................................................ 40 PLL1 Loop Filter Components .............................................................................. 41 Timing Error as It Translates to Clock Accuracy .................................................... 41 32.768-kHz Crystal Specifications ........................................................................ 42 33-MHz Crystal Specifications .............................................................................. 42 RTC Voltage Monitor Component Specifications .................................................. 46 Device Power Dissipation ..................................................................................... 56 VCC_ANLG and VCC_RTC Power Dissipation .................................................... 56 Thermal Resistance (C/W) qJC and qJA for BGA Package with 6-Layer Board ... 57 Maximum TA for Plastic BGA Package with 6-Layer Board with TCASE = 85C .... 57 Multiplexed Signal Trade-Offs ..............................................................................A-2 PIOs Sorted by PIO Number ................................................................................A-4 PIOs Sorted by Signal Name ...............................................................................A-5 Pin List Summary Table Abbreviations .................................................................A-6 Pin List Summary .................................................................................................A-7 Related AMD Products--E86TM Family Devices ..................................................C-1 ElanTMSC520 Microcontroller Data Sheet 5 PRELIMINARY LOGIC DIAGRAM BY INTERFACE1 GPA25-GPA0 GP Bus PCI Bus GPD15-GPD0 AD31-AD0 CBE3-CBE0 PAR SERR PERR FRAME TRDY IRDY STOP DEVSEL CLKPCIOUT CLKPCIIN RST INTA-INTD REQ4-REQ0 GNT4-GNT0 GPRESET GPIORD GPIOWR GPMEMRD GPMEMWR GPALE GPBHE GPRDY GPAEN GPTC GPDRQ3-GPDRQ0 GPDACK3-GPDACK0 GPIRQ10-GPIRQ0 GPDBUFOE GPIOCS16 GPMEMCS16 SDRAM MA12-MA0 BA1-BA0 MD31-MD0 SCS3-SCS0 CLKMEMOUT CLKMEMIN SRASA-SRASB SCASA-SCASB SWEA-SWEB SDQM3-SDQM0 MECC6-MECC0 GPCS7-GPCS0 GPA25-GPA0* GPD15-GPD0* MD31-MD0* BOOTCS ROMCS2-ROMCS1 ROMRD FLASHWR ROMBUFOE TMRIN1-TMRIN0 TMROUT1-TMROUT0 ROM/Flash Timers Serial Ports: UART 1 UART 2 SSI SOUT2-SOUT1 SIN2-SIN1 RTS2-RTS1 CTS2-CTS1 DSR2-DSR1 DTR2-DTR1 DCD2-DCD1 RIN2-RIN1 SSI_CLK SSI_DO SSI_DI PITGATE2 PITOUT2 JTAG_TRST JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS CMDACK BR/TC STOP/TX TRIG/TRACE WBMSTR2-WBMSTR0 CF_DRAM JTAG AMDebug Programmable Input/Output Clocks and Reset PIO31-PIO0 System Test 32KXTAL2-32KXTAL1 33MXTAL2-33MXTAL1 LF_PLL1 CLKTIMER CLKTEST PWRGOOD PRGRESET BBATSEN DATASTRB CF_ROM_GPCS DEBUG_ENTER INST_TRCE AMDEBUG_DIS CFG3-CFG0 RSTLD7-RSTLD0 Configuration Notes: 1. Pins noted with asterisks are duplicated in this diagram to clarify which signals are used for each interface. 6 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY LOGIC DIAGRAM BY DEFAULT PIN FUNCTION1 PCI Bus AD31-AD0 CBE3-CBE0 PAR SERR PERR FRAME TRDY IRDY STOP DEVSEL CLKPCIOUT CLKPCIIN RST INTA-INTD REQ4-REQ0 GNT4-GNT0 MA12-MA0 GPA25 {DEBUG_ENTER} GPA24 {INST_TRCE} GPA23 {AMDEBUG_DIS} GPA22-GPA15 {RSTLD7-RSTLD0} GPA13-GPA0 GPD15-GPD0 GPRESET GPIORD GPIOWR GPMEMRD GPMEMWR PIO0 [GPALE] PIO1 [GPBHE] PIO2 [GPRDY] PIO3 [GPAEN] PIO4 [GPTC] PIO5-PIO8 [GPDRQ3-GPDRQ0] PIO9-PIO12 [GPDACK3-GPDACK0] PIO13-PIO23 [GPIRQ10-GPIRQ0] PIO24 [GPDBUFOE] PIO25 [GPIOCS16] PIO26 [GPMEMCS16] PIO27 [GPCS0] GP Bus SDRAM BA1-BA0 MD31-MD0 SCS3-SCS0 CLKMEMOUT CLKMEMIN SRASA-SRASB SCASA-SCASB SWEA-SWEB SDQM3-SDQM0 MECC6-MECC0 SOUT2-SOUT1 SIN2-SIN1 RTS2-RTS1 CTS1 DSR1 DTR2-DTR1 DCD1 RIN1 PIO28 [CTS2] PIO29 [DSR2] PIO30 [DCD2] PIO31 [RIN2] SSI_CLK SSI_DO SSI_DI GPA25-GPA0* GPD15-GPD0* MD31-MD0* BOOTCS ROMCS2-ROMCS1 [GPCS2-GPCS1] ROMRD ROM/Flash Serial Ports: UART 1 UART 2 SSI FLASHWR ROMBUFOE TMRIN1-TMRIN0 [GPCS4-GPCS5] TMROUT1-TMROUT0 [GPCS6-GPCS7] PITGATE2 [GPCS3] PITOUT2 {CFG3} Timers JTAG_TRST JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG CMDACK BR/TC AMDebug Clocks and Reset 32KXTAL2-32KXTAL1 32MXTAL2-32MXTAL1 LF_PLL1 CLKTIMER [CLKTEST] PWRGOOD PRGRESET BBATSEN STOP/TX TRIG/TRACE CF_DRAM [WBMSTR2] {CFG2} DATASTRB [WBMSTR1] {CFG1} CF_ROM_GPCS [WBMSTR0] {CFG0} System Test Notes: 1. Pin names in bold indicate the default pin function. Brackets, [ ], indicate alternate, multiplexed functions. Braces, { }, indicate pinstrap pins. Pins noted with asterisks are duplicated in this diagram to clarify which signals are used for each interface. ElanTMSC520 Microcontroller Data Sheet 7 PRELIMINARY CONNECTION DIAGRAM 388-Pin Plastic BGA Package Top View 1 A AD30 B AD29 C GPA6 2 AD31 AD28 GPA9 NC NC 3 4 CLKMEMIN RST NC GPD1 NC 5 6 CLKPCIOUT NC NC 7 8 9 MD17 MD2 GPD4 10 MD3 MD18 GPD7 11 MD19 MD4 GPD8 12 MD5 MD20 GPD9 13 MD21 MD6 GPD10 A B C CLKTIMER MD1 [CLKTEST] MD0 GPD2 MD16 GPD3 GPD0 GPA25 {DEBUG_ ENTER} GPA24 GPA23 {AMDEBUG {INST _TRCE} _DIS} NC VCC_CORE D AD26 AD27 VCC_I/O VCC_I/O VCC_I/O VCC_I/O GPD5 GPD6 VCC_CORE VCC_CORE GPD11 D E AD25 F AD23 AD24 CBE3 AD21 AD20 AD17 AD16 IRDY TRDY PERR SERR AD15 AD14 AD11 AD10 CBE0 E F G H J K GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND L M N P R T U V W GPA22 VCC_CORE {RSTLD7} CLKPCIIN GPA1 INTC INTB INTA REQ0 GNT0 REQ1 GNT2 REQ3 GNT3 REQ4 CTS1 DTR1 INTD VCC_I/O VCC_I/O VCC_I/O VCC_I/O GNT1 REQ2 VCC_CORE VCC_CORE GNT4 DCD1 RTS1 G AD22 H AD19 J AD18 K CBE2 L FRAME M DEVSEL N STOP P PAR R CBE1 T AD13 U AD12 V AD9 W AD8 Y AD6 AA AD5 AB AD2 AC AD1 AD7 AD4 AD3 AD0 DSR1 RIN1 NC NC VCC_I/O VCC_I/O NC VCC_CORE VCC_CORE VCC_CORE PIO12 PIO11 VCC_I/O PIO25 [GPDACK0] [GPDACK1] [GPIOCS16] PIO26 [GPMEMCS16] PIO27 [GPCS0] PIO28 [CTS2] 4 PIO24 [GPDBUFOE] VCC_I/O NC TRIG/ TRACE NC Y AA AB AC AD NC NC PIO31 [RIN2] PIO19 PIO18 PIO13 PIO10 PIO5 PIO4 [GPIRQ4] [GPIRQ5] [GPIRQ10] [GPDACK2] [GPDRQ3] [GPTC] NC AD AE NC AF NC 1 SIN1 SOUT1 2 PIO30 [DCD2] PIO29 [DSR2] 3 PIO23 PIO20 PIO17 PIO14 PIO9 PIO6 PIO3 [GPIRQ0] [GPIRQ3] [GPIRQ6] [GPIRQ9] [GPDACK3] [GPDRQ2] [GPAEN] PIO22 PIO21 PIO16 PIO15 PIO8 PIO7 PIO2 [GPIRQ1] [GPIRQ2] [GPIRQ7] [GPIRQ8] [GPDRQ0] [GPDRQ1] [GPRDY] 5 6 7 8 9 10 11 PIO0 [GPALE] PIO1 [GPBHE] 12 NC NC 13 AE AF 8 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY CONNECTION DIAGRAM (Continued) 388-Pin Plastic BGA Package Top View 14 A MD7 B MD22 15 MD23 MD8 16 MD9 MD24 GPIOWR 17 MD25 MD10 GPD14 18 MD11 MD26 19 MD27 20 MD28 21 MD13 MD29 22 MD14 23 MD30 24 MD31 25 26 A GND_ANLG VCC_RTC CLKMD12 MEMOUT GPA18 MD15 {RSTLD3} ROMCS1 BBATSEN VCC_ANLG B [GPCS1] MECC4 C C GPA20 GPD13 {RSTLD5} D GPD12 VCC_I/O GPMEMWR GPA21 PWRGOOD GPA19 NC {RSTLD6} {RSTLD4} VCC_CORE VCC_CORE PRGRESET VCC_I/O VCC_I/O MECC0 ROMCS2 GPA15 [GPCS2] {RSTLD0} NC GPA16 MECC5 {RSTLD1} GPA17 SWEB {RSTLD2} GPMEMRD SCASA SDQM0 SDQM3 SCS2 SRASA MA0 MA3 MA4 MA7 MA8 BA0 VCC_I/O GPD15 MECC1 D E F G H J K L M N P R T U V W GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NC GPA7 SWEA SCASB SDQM2 SDQM1 SCS3 SRASB MA1 MA2 MA5 MA6 MA9 MA10 MA11 MA12 MECC2 E F G H J K L M N P R T U V W VCC_CORE GPIORD VCC_CORE GPA5 GPA3 VCC_I/O VCC_I/O GPA10 GPA11 GPA0 GPA2 GPA4 GPA8 GPA12 VCC_CORE GPA13 VCC_CORE GPA14 NC SOUT2 VCC_I/O VCC_I/O NC CMDACK BA1 SIN2 SCS0 CF_DRAM SCS1 [WBMSTR2] {CFG2} PITOUT2 {CFG3} TMRIN1 [GPCS4] MECC3 Y AA AB AC VCC_CORE VCC_CORE NC NC VCC_I/O VCC_I/O TMRIN0 [GPCS5] VCC_I/O VCC_I/O ROMRD MECC6 Y AA ROMBUFOE NC FLASHWR BOOTCS 33MXTAL1 AB 33MXTAL2 AC PITGATE2 GPRESET TMROUT1 DATASTRB NC [GPCS3] [GPCS6] [WBMSTR1] {CFG1} TMROUT0 BR/TC [GPCS7] NC AD NC NC NC NC NC SSI_CLK CF_ROM_ JTAG_TCK RTS2 GPCS [WBMSTR0] {CFG0} NC NC 20 NC AD AE NC AF NC 14 NC NC 15 NC NC 16 NC NC SSI_DI SSI_DO 18 19 JTAG_TMS JTAG_TRST DTR2 JTAG_TDI JTAG_TDO NC 21 22 23 NC LF_PLL1 24 NC NC 25 32KXTAL2 AE 32KXTAL1 AF 26 STOP/TX NC 17 ElanTMSC520 Microcontroller Data Sheet 9 PRELIMINARY PIN DESIGNATIONS This section identifies the pins of the ELANSC520 microcontroller and lists the signals associated with each pin. In all tables the brackets, [ ], indicate alternate, multiplexed functions, and braces, { }, indicate reset configuration pins (pinstraps). The line over a pin name indicates an active Low signal. The word pin refers to the physical wire; the word signal refers to the electrical signal that flows through it. s Pin designations are listed in the "Pin Designations Refer to Appendix A, "Pin Tables," on page A-1 for an additional group of tables with the following information: s Multiplexed signal tradeoffs--Table 16 on page A-2. s Programmable I/O pins ordered by 1) PIO pin (Pin Number)" table on page 11 and the Pin Designations (Pin Name) table on page 13. s Table 2, "Signal Descriptions" on page 17 contains n u m b e r a n d 2 ) m u l t i p l exe d s i g n a l n a m e , respectively, including pin numbers, multiplexed functions, and pin configuration following system reset--Table 17 on page A-4 and Table 18 on page A-5. s Comprehensive pin and signal summary showing a descr iption of the microcontroller signals organized alphabetically by functional group. Table 1 on page 16 defines terms used in Table 2. The table includes columns listing the multiplexed functions and I/O type. signal name and alternate function, pin number, I/O type, maximum load values, power-on reset default function, reset state, power-on reset default operati on, hol d s ta te, an d vol tag e--Ta bl e 2 0 o n page A-7. 10 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY Pin Designations (Pin Number1) Pin # A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 Signal Name AD30 AD31 NC CLKMEMIN RST CLKPCIOUT CLKTIMER [CLKTEST] MD1 MD17 MD3 MD19 MD5 MD21 MD7 MD23 MD9 MD25 MD11 MD27 MD28 MD13 MD14 MD30 MD31 GND_ANLG VCC_RTC AD29 AD28 NC NC GPD1 NC MD0 MD16 MD2 MD18 MD4 MD20 MD6 MD22 MD8 MD24 MD10 MD26 Pin # B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 Signal Name CLKMEMOUT MD12 MD29 GPA18{RSTLD3} MD15 ROMCS1[GPCS1] BBATSEN VCC_ANLG GPA6 GPA9 GPA25 {DEBUG_ENTER} GPD0 NC NC GPD2 GPD3 GPD4 GPD7 GPD8 GPD9 GPD10 GPA20{RSTLD5} GPD13 GPIOWR GPD14 GPMEMWR GPA21{RSTLD6} PWRGOOD GPA19{RSTLD4} NC ROMCS2[GPCS2] GPA15{RSTLD0} MECC0 MECC4 AD26 AD27 GPA23 {AMDEBUG_DIS} GPA24 {INST_TRCE} VCC_I/O VCC_I/O VCC_I/O VCC_I/O GPD5 GPD6 Pin # D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E1 E2 E3 E4 E23 E24 E25 E26 F1 F2 F3 F4 F23 F24 F25 F26 G1 G2 G3 G4 G23 G24 G25 G26 H1 H2 H3 H4 Signal Name VCC_CORE VCC_CORE GPD11 GPD12 VCC_I/O VCC_I/O GPD15 VCC_CORE VCC_CORE PRGRESET VCC_I/O VCC_I/O NC GPA16{RSTLD1} MECC5 MECC1 AD25 AD24 NC VCC_CORE NC GPA17{RSTLD2} SWEB SWEA AD23 CBE3 GPA22{RSTLD7} VCC_CORE GPA7 GPMEMRD SCASA SCASB AD22 AD21 CLKPCIIN GPA1 VCC_CORE GPIORD SDQM0 SDQM2 AD19 AD20 INTC INTD Pin # H23 H24 H25 H26 J1 J2 J3 J4 J23 J24 J25 J26 K1 K2 K3 K4 K23 K24 K25 K26 L1 L2 L3 L4 L11 L12 L13 L14 L15 L16 L23 L24 L25 L26 M1 M2 M3 M4 M11 M12 M13 M14 M15 M16 Signal Name VCC_CORE GPA5 SDQM3 SDQM1 AD18 AD17 INTB VCC_I/O GPA3 GPA0 SCS2 SCS3 CBE2 AD16 INTA VCC_I/O VCC_I/O GPA2 SRASA SRASB FRAME IRDY REQ0 VCC_I/O GND GND GND GND GND GND VCC_I/O GPA4 MA0 MA1 DEVSEL TRDY GNT0 VCC_I/O GND GND GND GND GND GND Pin # M23 M24 M25 M26 N1 N2 N3 N4 N11 N12 N13 N14 N15 N16 N23 N24 N25 N26 P1 P2 P3 P4 P11 P12 P13 P14 P15 P16 P23 P24 P25 P26 R1 R2 R3 R4 R11 R12 R13 R14 R15 R16 R23 R24 Signal Name GPA10 GPA8 MA3 MA2 STOP PERR REQ1 GNT1 GND GND GND GND GND GND GPA11 GPA12 MA4 MA5 PAR SERR GNT2 REQ2 GND GND GND GND GND GND VCC_CORE GPA13 MA7 MA6 CBE1 AD15 REQ3 VCC_CORE GND GND GND GND GND GND VCC_CORE GPA14 ElanTMSC520 Microcontroller Data Sheet 11 PRELIMINARY Pin Designations (Pin Number1) (Continued) Pin # R25 R26 T1 T2 T3 T4 T11 T12 T13 T14 T15 T16 T23 T24 T25 T26 U1 U2 U3 U4 U23 U24 U25 U26 V1 V2 V3 V4 V23 V24 V25 V26 W1 W2 Signal Name MA8 MA9 AD13 AD14 GNT3 VCC_CORE GND GND GND GND GND GND NC NC BA0 MA10 AD12 AD11 REQ4 GNT4 SOUT2 CMDACK BA1 MA11 AD9 AD10 CTS1 DCD1 VCC_I/O SIN2 SCS0 MA12 AD8 CBE0 Pin # W3 W4 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y23 Y24 Y25 Y26 AA1 AA2 AA3 AA4 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 Signal Name DTR1 RTS1 VCC_I/O CF_DRAM [WBMSTR2]{CFG2} SCS1 MECC2 AD6 AD7 DSR1 VCC_I/O VCC_I/O PITOUT2{CFG3} MECC3 MECC6 AD5 AD4 RIN1 VCC_I/O VCC_I/O TMRIN1[GPCS4] ROMBUFOE NC AD2 AD3 NC NC ROMRD FLASHWR BOOTCS 33MXTAL1 AD1 AD0 NC PIO25 [GPIOCS16] Pin # AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 Signal Name VCC_CORE VCC_CORE VCC_CORE PIO12 [GPDACK0] PIO11[GPDACK1] VCC_I/O VCC_I/O NC TRIG/TRACE VCC_CORE VCC_CORE NC NC VCC_I/O VCC_I/O TMRIN0[GPCS5] PITGATE2[GPCS3] GPRESET TMROUT1[GPCS6] DATASTRB [WBMSTR1]{CFG1} NC 33MXTAL2 NC NC PIO31[RIN2] PIO26 [GPMEMCS16] PIO24[GPDBUFOE] PIO19[GPIRQ4] PIO18[GPIRQ5] PIO13[GPIRQ10] PIO10[GPDACK2] PIO5[GPDRQ3] PIO4[GPTC] NC Pin # AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 Signal Name NC NC NC NC NC NC SSI_CLK CF_ROM_GPCS [WBMSTR0]{CFG0} JTAG_TCK RTS2 TMROUT0 [GPCS7] BR/TC NC NC NC SIN1 PIO30[DCD2] PIO27[GPCS0] PIO23[GPIRQ0] PIO20[GPIRQ3] PIO17[GPIRQ6] PIO14[GPIRQ9] PIO9[GPDACK3] PIO6[GPDRQ2] PIO3[GPAEN] PIO0[GPALE] NC NC NC NC NC NC SSI_DI NC Pin # AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 Signal Name JTAG_TMS JTAG_TRST DTR2 NC NC 32KXTAL2 NC SOUT1 PIO29[DSR2] PIO28[CTS2] PIO22[GPIRQ1] PIO21[GPIRQ2] PIO16[GPIRQ7] PIO15[GPIRQ8] PIO8[GPDRQ0] PIO7[GPDRQ1] PIO2[GPRDY] PIO1[GPBHE] NC NC NC NC STOP/TX NC SSI_DO NC JTAG_TDI JTAG_TDO NC LF_PLL1 NC 32KXTAL1 Notes: 1. See Table 17 on page A-4 for PIOs sorted by pin number. 12 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY Pin Designations (Pin Name1) Signal Name 32KXTAL1 32KXTAL2 33MXTAL1 33MXTAL2 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 Pin # AF26 AE26 AB26 AC26 AC2 AC1 AB1 AB2 AA2 AA1 Y1 Y2 W1 Signal Name {AMDEBUG_DIS} GPA23 BA0 BA1 BBATSEN BOOTCS BR/TC CBE0 CBE1 CBE2 CBE3 CF_DRAM [WBMSTR2]{CFG2} CF_ROM_GPCS [WBMSTR0]{CFG0} {CFG0} CF_ROM_GPCS [WBMSTR0] {CFG1}DATASTRB [WBMSTR1] {CFG2]CF_DRAM [WBMSTR2} {CFG3}PITOUT2 CLKMEMIN CLKMEMOUT CLKPCIIN CLKPCIOUT CLKTEST [CLKTIMER] [CLKTIMER] CLKTEST CMDACK CTS1 [CTS2]PIO28 DATASTRB [WBMSTR1]{CFG1} DCD1 [DCD2]PIO30 {DEBUG_ENTER} GPA25 DEVSEL DSR1 [DSR2]PIO29 DTR1 DTR2 FLASHWR FRAME Pin # D3 T25 U25 B25 AB25 AD24 W2 R1 K1 F2 W24 AD20 AD20 Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND Pin # L11 L12 L13 L14 L15 L16 M11 M12 M13 M14 M15 M16 N11 Signal Name GND_ANLG GNT0 GNT1 GNT2 GNT3 GNT4 GPA0 GPA1 GPA2 GPA3 GPA4 GPA5 GPA6 Pin # A25 M3 N4 P3 T3 U4 J24 G4 K24 J23 L24 H24 C1 Signal Name [GPCS1]ROMCS1 [GPCS2]ROMCS2 [GPCS3]PITGATE2 [GPCS4]TMRIN1 [GPCS5]TMRIN0 [GPCS6]TMROUT1 [GPCS7]TMROUT0 GPD0 GPD1 GPD2 GPD3 GPD4 GPD5 Pin # B24 C23 AC21 AA24 AC20 AC23 AD23 C4 B5 C7 C8 C9 D9 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 V1 V2 U2 U1 T1 T2 R2 K2 J2 J1 H1 H2 G2 G1 F1 E2 E1 D1 D2 B2 B1 A1 A2 AC24 W24 Y24 A4 B19 G3 A6 A7 A7 U24 V3 AF4 AC24 V4 AE3 C3 M1 Y3 AF3 W3 AE23 AB24 L1 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND N12 N13 N14 N15 N16 P11 P12 P13 P14 P15 P16 R11 R12 R13 R14 R15 R16 T11 T12 T13 T14 T15 T16 GPA7 GPA8 GPA9 GPA10 GPA11 GPA12 GPA13 GPA14 GPA15{RSTLD0} GPA16{RSTLD1} GPA17{RSTLD2} GPA18{RSTLD3} GPA19{RSTLD4] GPA20{RSTLD5} GPA21[RSTLD6} GPA22{RSTLD7} GPA23 {AMDEBUG_DIS} GPA24 {INST_TRCE] GPA25 {DEBUG_ENTER] [GPAEN]PIO3 [GPALE]PIO0 [GPBHE]PIO1 [GPCS0]PIO27 F23 M24 C2 M23 N23 N24 P24 R24 C24 D24 E24 B22 C21 C14 C19 F3 D3 D4 C3 AE11 AE12 AF12 AE4 GPD6 GPD7 GPD8 GPD9 GPD10 GPD11 GPD12 GPD13 GPD14 GPD15 [GPDACK0]PIO12 [GPDACK1]PIO11 [GPDACK2]PIO10 [GPDACK3]PIO9 [GPDBUFOE] PIO24 [GPDRQ0]PIO8 [GPDRQ1]PIO7 [GPDRQ2]PIO6 [GPDRQ3]PIO5 [GPIOCS16]PIO25 GPIORD GPIOWR [GPIRQ0]PIO23 D10 C10 C11 C12 C13 D13 D14 C15 C17 D17 AC8 AC9 AD9 AE9 AD5 AF9 AF10 AE10 AD10 AC4 G24 C16 AE5 ElanTMSC520 Microcontroller Data Sheet 13 PRELIMINARY Pin Designations (Pin Name1) (Continued) Signal Name [GPIRQ1]PIO22 [GPIRQ2]PIO21 [GPIRQ3]PIO20 [GPIRQ4]PIO19 [GPIRQ5]PIO18 [GPIRQ6]PIO17 [GPIRQ7]PIO16 [GPIRQ8]PIO15 [GPIRQ9]PIO14 [GPIRQ10]PIO13 [GPMEMCS16] PIO26 GPMEMRD GPMEMWR [GPRDY]PIO2 GPRESET [GPTC]PIO4 {INST_TRCE} GPA24 INTA INTB INTC INTD IRDY JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST LF_PLL1 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 Pin # AF5 AF6 AE6 AD6 AD7 AE7 AF7 AF8 AE8 AD8 AD4 F24 C18 AF11 AC22 AD11 D4 K3 J3 H3 H4 L2 AD21 AF21 AF22 AE21 AE22 AF24 L25 L26 M26 M25 N25 N26 P26 P25 Signal Name MA8 MA9 MA10 MA11 MA12 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD30 Pin # R25 R26 T26 U26 V26 B7 A8 B9 A10 B11 A12 B13 A14 B15 A16 B17 A18 B20 A21 A22 B23 B8 A9 B10 A11 B12 A13 B14 A15 B16 A17 B18 A19 A20 B21 A23 Signal Name MD31 MECC0 MECC1 MECC2 MECC3 MECC4 MECC5 MECC6 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Pin # A24 C25 D26 W26 Y25 C26 D25 Y26 A3 AA26 AB3 AB4 AC3 AC12 AC16 AC17 AC25 AD1 AD2 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD25 AD26 AE1 AE13 AE14 AE15 AE16 AE17 AE18 AE20 Signal Name NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC PAR PERR PIO0[GPALE] PIO1[GPBHE] PIO2[GPRDY] PIO3[GPAEN] PIO4[GPTC] PIO5[GPDRQ3] PIO6[GPDRQ2] PIO7[GPDRQ1] PIO8[GPDRQ0] PIO9[GPDACK3] PIO10[GPDACK2] PIO11[GPDACK1] Pin # AE24 AE25 AF1 AF13 AF14 AF15 AF16 AF18 AF20 AF23 AF25 B3 B4 B6 C5 C6 C22 D23 E3 E23 T23 T24 P1 N2 AE12 AF12 AF11 AE11 AD11 AD10 AE10 AF10 AF9 AE9 AD9 AC9 Signal Name PIO12[GPDACK0] PIO13[GPIRQ10] PIO14[GPIRQ9] PIO15[GPIRQ8] PIO16[GPIRQ7] PIO17[GPIRQ6] PIO18[GPIRQ5] PIO19[GPIRQ4] PIO20[GPIRQ3] PIO21[GPIRQ2] PIO22[GPIRQ1] PIO23[GPIRQ0] PIO24 [GPDBUFOE] PIO25 [GPIOCS16] PIO26 [GPMEMCS16] PIO27[GPCS0] PIO28[CTS2] PIO29[DSR2] PIO30[DCD2] PIO31[RIN2] PITGATE2 [GPCS3] PITOUT2{CFG3} PRGRESET PWRGOOD REQ0 REQ1 REQ2 REQ3 REQ4 RIN1 [RIN2]PIO31 ROMBUFOE ROMCS1[GPCS1] ROMCS2 [GPCS2 ] ROMRD RST Pin # AC8 AD8 AE8 AF8 AF7 AE7 AD7 AD6 AE6 AF6 AF5 AE5 AD5 AC4 AD4 AE4 AF4 AF3 AE3 AD3 AC21 Y24 D20 C20 L3 N3 P4 R3 U3 AA3 AD3 AA25 B24 C23 AB23 A5 14 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY Pin Designations (Pin Name1) (Continued) Signal Name {RSTLD0}GPA15 {RSTLD1}GPA16 {RSTLD2}GPA17 {RSTLD3}GPA18 {RSTLD4}GPA19 {RSTLD5}GPA20 {RSTLD6}GPA21 {RSTLD7}GPA22 RTS1 RTS2 SCASA SCASB SCS0 SCS1 SCS2 SCS3 SDQM0 Pin # C24 D24 E24 B22 C21 C14 C19 F3 W4 AD22 F25 F26 V25 W25 J25 J26 G25 Signal Name SDQM1 SDQM2 SDQM3 SERR SIN1 SIN2 SOUT1 SOUT2 SRASA SRASB SSI_CLK SSI_DI SSI_DO STOP STOP/TX SWEA SWEB Pin # H26 G26 H25 P2 AE2 V24 AF2 U23 K25 K26 AD19 AE19 AF19 N1 AF17 E26 E25 Signal Name TMRIN0[GPCS5] TMRIN1[GPCS4] TMROUT0 [GPCS7] TMROUT1 [GPCS6] TRDY TRIG/TRACE VCC_ANLG VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE Pin # AC20 AA24 AD23 AC23 M2 AC13 B26 AC5 AC6 AC7 AC14 AC15 D11 D12 D18 D19 E4 Signal Name VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O Pin # F4 G23 H23 P23 R23 R4 T4 AA23 AA4 AC10 AC11 AC18 AC19 D5 D6 D7 D8 Signal Name VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_RTC [WBMSTR0]{CFG0} CF_ROM_GPCS [WBMSTR1]{CFG1} DATASTRB [WBMSTR2]{CFG2} CF_DRAM Pin # D15 D16 D21 D22 J4 K23 K4 L4 L23 M4 V23 W23 Y4 Y23 A26 AD20 AC24 W24 Notes: 1. See Table 17 on page A-4 for PIOs sorted by pin number. ElanTMSC520 Microcontroller Data Sheet 15 PRELIMINARY SIGNAL DESCRIPTIONS Table 2, "Signal Descriptions" on page 17 contains a description of the ELANSC520 microcontroller signals. The microcontroller contains 258 signal pins in addition to power and ground pins in a Plastic Ball Grid Array (PBGA) package. Table 1 describes the terms used in the signal description table. The signals are organized alphabetically within the following functional groups: s Synchronous DRAM (page 17) s ROM/Flash (page 18) s PCI bus (page 18) s GP bus (page 19) s Serial ports (page 21) s Clocks and reset (page 22) s JTAG (page 23) s AMDebugTM Interface (page 23) s System test (page 23) s Chip selects (page 24) s Programmable I/O (PIO) (page 25) s Timers (page 25) s Configuration (page 26) s Power (page 27) Table 1. Term [] Signal Descriptions Table Definitions Definition Indicates the pin alternate function; a pin defaults to the signal named without the brackets. Indicates the reset configuration pin (pinstrap). Refers to the physical wire. Refers to the electrical signal that flows across a pin. A line over a signal name indicates that the signal is active Low; a signal name without a line is active High. Analog voltage Bidirectional High Input Programmable to hold last state of pin Totem pole output Totem pole output/three-state output Open-drain output Open-drain output or totem pole output Oscillator Internal pulldown resistor (~100-150 kW) Power pins Internal pullup resistor (~100-150 kW) Schmitt trigger input Schmitt trigger input or open-drain output Three-state output General Terms {} pin signal SIGNAL Signal Types Analog B H I LS O O/TS OD OD-O Osc PD Power PU STI STI-OD TS 16 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY Table 2. Signal Descriptions Signal Synchronous DRAM BA1-BA0 CLKMEMIN -- -- O I Bank Address is the SDRAM bank address bus. SDRAM Clock Input is the SDRAM clock return signal used to minimize skew between the internal SDRAM clock and the CLKMEMOUT signal provided to the SDRAM devices. This signal compensates for buffer and load delays introduced by the board design. SDRAM Clock Output is the 66-MHz clock that provides clock signaling for the synchronous DRAM devices. This clock may require an external Low skew buffer for system implementations that result in heavy loading on the SDRAM clock signal. SDRAM Address is the SDRAM multiplexed address bus. SDRAM Data Bus inputs data during SDRAM read cycles and outputs data during SDRAM write cycles. Memory Error Correction Code contains the ECC checksum (syndrome) bits used to validate and correct data errors. Column Address Strobes are used in combination with the SRASA- SRASB and SWEA-SWEB to encode the SDRAM command type. SCASA and SCASB are the same signal provided on two different pins to reduce the total load connected to CAS. Suggested system connection: SCASA for SDRAM banks 0 and 1 SCASB for SDRAM banks 2 and 3 SCS3-SCS0 -- O SDRAM Chip Selects are the SDRAM chip-select outputs. These signals are asserted to select a bank of SDRAM devices. The chipselect signals enable the SDRAM devices to decode the commands asserted via SRASA-SRASB, SCASA-SCASB, and SWEA-SWEB. Data Input/Output Masks make SDRAM data output high-impedance and blocks data input on SDRAM while active. Each of the four SDQM3-SDQM0 signals is associated with one byte of four throughout the array. Each SDQMx signal provides an input mask signal for write accesses and an output enable signal for read accesses. Row Address Strobes are used in combination with the SCASA- SCASB and SWEA-SWEB to encode the SDRAM command type. SRASA and SRASB are the same signal provided on two different pins to reduce the total load connected to RAS. Suggested system connection: SRASA for SDRAM banks 0 and 1 SRASB for SDRAM banks 2 and 3 SWEA-SWEB -- O SDRAM Memory Write Enables are used in combination with the SRASA-SRASB and SCASA-SCASB to encode the SDRAM command type. SWEA and SWEB are the same signal provided on two different pins to reduce the total load connected to WE. Suggested system connection: SWEA for SDRAM banks 0 and 1 SWEB for SDRAM banks 2 and 3 Multiplexed Signal Type Description CLKMEMOUT -- O MA12-MA0 MD31-MD0 MECC6-MECC0 SCASA-SCASB -- -- -- -- O B B O SDQM3-SDQM0 -- O SRASA-SRASB -- O ElanTMSC520 Microcontroller Data Sheet 17 PRELIMINARY Table 2. Signal Descriptions (Continued) Signal ROM/Flash BOOTCS -- O ROM/Flash Boot Chip Select is an active Low output that provides the chip select for the startup ROM and/or the ROM/Flash array (BIOS, HAL, O/S, etc.). The BOOTCS signal asserts for accesses made to the 64-Kbyte segment that contains the Am5x86 CPU boot vector: addresses 3FF0000h-3FFFFFFh. In addition to this linear decode region, BOOTCS asserts in response to accesses to userprogrammable address regions. Flash Write indicates that the current cycle is a write of the selected Flash device. When this signal is asserted, the selected Flash device can latch data from the data bus. General-Purpose Address Bus provides the address to the system's ROM/Flash devices. It is also the address bus for the GP bus devices. Twenty-six address lines provide a maximum addressable space of 64 Mbytes for each ROM chip select. General-Purpose Data Bus inputs data during memory and I/O read cycles and outputs data during memory and I/O write cycles. A reset configuration pin (CFG2) allows the GP bus to be used for the boot chip-select ROM interface. Configuration registers are used to select whether ROMCS2 and ROMCS1 use the GP bus data bus or the MD data bus. The GP data bus supports 16-bit or 8-bit ROM interfaces. Two data buses are selectable to facilitate the use of ROM in a mixed voltage system. MD31-MD0 -- B Memory Data Bus inputs data during SDRAM read cycles and outputs data during SDRAM write cycles. Configuration registers are used to select whether ROMCS2 and ROMCS1 use the GP bus data bus or the MD data bus. A reset configuration pin (CFG2) allows the GP data bus to be used for BOOTCS. The memory data bus supports an 8-, 16-, or 32-bit ROM interface. ROM Buffer Output Enable is an optional signal used to enable a buffer to the ROM/Flash devices if they need to be isolated from the ELANSC520 microcontroller, other GP bus devices, or SDRAM system for voltage or loading considerations. This signal asserts for all accesses through the ROM controller. The buffer direction is controlled by the ROMRD or FLASHWR signal. ROM/Flash Chip Selects are signals that can be programmed to be asserted for accesses to user-programmable address regions. ROM/Flash Read indicates that the current cycle is a read of the selected ROM/Flash device. When this signal is asserted, the selected ROM device can drive data onto the data bus. PCI Address Data Bus is the PCI time-multiplexed address/data bus. Command or Byte-Enable Bus functions 1) as a time-multiplexed bus command that defines the type of transaction on the AD bus, or 2) as byte enables: CBE0 for AD7-AD0 CBE1 for AD15-AD8 CBE2 for AD23-AD16 CBE3 for AD31-AD24 PCI Bus Clock Input is the 33-MHz PCI bus clock. This pin can be connected to the CLKPCIOUT pin for systems where the ELANSC520 microcontroller is the source of the PCI bus clock. Multiplexed Signal Type Description FLASHWR -- O GPA25-GPA0 -- O GPD15-GPD0 -- B ROMBUFOE -- O ROMCS2 ROMCS1 ROMRD [GPCS2] [GPCS1] -- O O O Peripheral Component Interconnect (PCI) Bus AD31-AD0 CBE3-CBE0 -- -- B B CLKPCIIN -- I 18 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY Table 2. Signal Descriptions (Continued) Signal CLKPCIOUT Multiplexed Signal -- Type O Description PCI Bus Clock Output is a 33-MHz clock output for the PCI bus devices. This signal is derived from the 33MXTAL1/33MXTAL2 interface. Device Select is asserted by the target when it has decoded its address as the target of the current transaction. Frame is driven by the transaction initiator to indicate the start and duration of the transaction. Bus Grants are asserted by the ELANSC520 microcontroller to grant access to the bus. Interrupt Requests are asserted to request an interrupt. These four interrupts are the same type of interrupt as the GPIRQ10-GPIRQ0 signals, and they go to the same interrupt controller. They are named INTx to match the common PCI interrupt naming convention. Configuration registers allow inversion of these interrupt requests to recognize active low interrupt requests. These interrupt requests can be routed to generate NMI. IRDY -- B Initiator Ready is asserted by the current bus master to indicate that data is ready on the bus (write) or that the master is ready to accept data (read). PCI Parity is driven by the initiator or target to indicate parity on the AD31-AD0 and CBE3-CBE0 buses. Parity Error is asserted to indicate a PCI bus data parity error in the previous clock cycle. Bus Requests are asserted by the master to request access to the bus. Reset is asserted to reset the PCI devices. System Error is used for reporting address parity errors or any other system error where the result is catastrophic. Stop is asserted by the target to request that the current bus transaction be stopped. Target Ready is asserted by the currently addressed target to indicate its ability to complete the current data phase of a transaction. General-Purpose Address Bus outputs the physical memory or I/O port address. Twenty-six address lines provide a maximum addressable space of 64 Mbytes. This bus also provides the address to the system's ROM/Flash devices. DEVSEL FRAME GNT4-GNT0 INTA-INTD -- -- -- -- B B O I PAR PERR REQ4-REQ0 RST SERR STOP TRDY -- -- -- -- -- -- -- B B I O I B B General-Purpose Bus (GP Bus) GPA14-GPA0 GPA15 GPA16 GPA17 GPA18 GPA19 GPA20 GPA21 GPA22 GPA23 GPA24 GPA25 -- {RSTLD0} {RSTLD1} {RSTLD2} {RSTLD3} {RSTLD4} {RSTLD5} {RSTLD6} {RSTLD7} {AMDEBUG_DIS} {INST_TRCE} {DEBUG_ENTER} O O{I} O{I} O{I} O{I} O{I} O{I} O{I} O{I} O{I} O{I} O{I} ElanTMSC520 Microcontroller Data Sheet 19 PRELIMINARY Table 2. Signal Descriptions (Continued) Signal [GPAEN] Multiplexed Signal PIO3 Type O Description GP Bus Address Enable indicates that the current address on the GPA25-GPA0 address bus is a memory address, and that the current cycle is a DMA cycle. All I/O devices should use this signal in decoding their I/O addresses and should not respond when this signal is asserted. When GPAEN is asserted, the GPDACKx signals are used to select the appropriate I/O device for the DMA transfer. GPAEN also asserts when a DMA cycle is occurring internally. GP Bus Address Latch Enable is driven at the beginning of a GP bus cycle with valid address. This signal can be used by external devices to latch the GP address for the current cycle. GP Bus Byte High Enable is driven active when data is to be transferred on the upper 8 bits of the GP data bus. General-Purpose Data Bus inputs data during memory and I/O read cycles, and outputs data during memory and I/O write cycles. GP Bus DMA Acknowledge can each be mapped to one of the seven available DMA channels. They are asserted active Low to acknowledge the corresponding DMA requests. [GPALE] PIO0 O [GPBHE] GPD15-GPD0 [GPDACK0] [GPDACK1] [GPDACK2] [GPDACK3] [GPDBUFOE] PIO1 -- PIO12 PIO11 PIO10 PIO9 PIO24 O B O O O O O GP Bus Data Bus Buffer Output Enable is used to control the output enable on an external transceiver that may be on the GP data bus. Using this transceiver is optional in the system design and is necessary only to alleviate loading or voltage issues. This pin is asserted for all external GP bus accesses. It is not asserted during accesses to the internal peripherals even if GP bus echo mode is enabled. Note that if the ROM is configured to use the GP data bus, then its bytes are not controlled by this buffer enable; they are controlled by the ROMBUFOE signal. [GPDRQ0] [GPDRQ1] [GPDRQ2] [GPDRQ3] [GPIOCS16] GPIORD PIO8 PIO7 PIO6 PIO5 PIO25 -- I I I I STI O GP Bus DMA Request can each be mapped to one of the seven available DMA channels. They are asserted active High to request DMA service. GP Bus I/O Chip-Select 16 is driven active early in the cycle by the targeted I/O device on the GP bus to request a 16-bit I/O transfer. GP Bus I/O Read indicates that the current cycle is a read of the currently addressed I/O device on the GP bus. When this signal is asserted, the selected I/O device can drive data onto the data bus. GP Bus I/O Write indicates that the current cycle is a write of the currently addressed I/O device on the GP bus. When this signal is asserted, the selected I/O device can latch data from the data bus. GPIOWR -- O 20 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY Table 2. Signal Descriptions (Continued) Signal [GPIRQ0] [GPIRQ1] [GPIRQ2] [GPIRQ3] [GPIRQ4] [GPIRQ5] [GPIRQ6] [GPIRQ7] [GPIRQ8] [GPIRQ9] [GPIRQ10] [GPMEMCS16] Multiplexed Signal PIO23 PIO22 PIO21 PIO20 PIO19 PIO18 PIO17 PIO16 PIO15 PIO14 PIO13 PIO26 Type I I I I I I I I I I I STI GP Bus Memory Chip-Select 16 is driven active early in the cycle by the targeted memory device on the GP bus to request a 16-bit memory transfer. GP Bus Memory Read indicates that the current GP bus cycle is a read of the selected memory device. When this signal is asserted, the selected memory device can drive data onto the data bus. GP Bus Memory Write indicates that the current GP bus cycle is a write of the selected memory device. When this signal is asserted, the selected memory device can latch data from the data bus. GP Bus Ready can be driven by open-drain devices. When pulled Low during a GP bus access, wait states are inserted in the current cycle. This pin has an internal weak pullup that should be supplemented by a stronger external pullup for faster rise time. GP Bus Reset, when asserted, re-initializes to reset state all devices connected to the GP bus. GP Bus Terminal Count is driven from the internal DMA controller to indicate that the transfer count for the currently active DMA channel has reached zero, and that the current DMA cycle is the last transfer. Clear To Send is driven back to the serial port to indicate that the external data carrier equipment (DCE) is ready to accept data. Data Carrier Detect is driven back to the serial port from a piece of DCE when it has detected a carrier signal from a communications target. Data Set Ready is used to indicate that the external DCE is ready to establish a communication link with the internal serial port controller. Data Terminal Ready indicates to the external DCE that the internal serial port controller is ready to communicate. Ring Indicate is used by an external modem to inform the serial port that a ring signal was detected. Request To Send indicates to the external DCE that the internal serial port controller is ready to send data. Serial Data In is used to receive the serial data from the external serial device or DCE into the internal serial port controller. Serial Data Out is used to transmit the serial data from the internal serial port controller to the external serial device or DCE. Description GP Bus Interrupt Request can each be mapped to one of the available interrupt channels or NMI. They are asserted when a peripheral requires interrupt service. Configuration registers allow inversion of these interrupt requests to recognize active low interrupt requests. These interrupt requests can be routed to generate NMI. [GPMEMRD] -- O [GPMEMWR] -- O [GPRDY] PIO2 STI GPRESET [GPTC] PIO4 -- O O Serial Ports CTS1 [CTS2] DCD1 [DCD2] DSR1 [DSR2] DTR2-DTR1 RIN1 [RIN2] RTS2-RTS1 SIN2-SIN1 SOUT2-SOUT1 PIO31 -- -- -- PIO29 -- -- PIO30 -- PIO28 -- -- I I I I I I O I I O I O ElanTMSC520 Microcontroller Data Sheet 21 PRELIMINARY Table 2. Signal Descriptions (Continued) Signal SSI_CLK Multiplexed Signal -- Type O Description SSI Clock is driven by the ELANSC520 microcontroller SSI port during active SSI transmit or receive transactions. The idle state of the clock and the assertion/sample edge are configurable. SSI Data Input receives incoming data from a peripheral device SSI port. Data is shifted in on the opposite SSI_CLK signal edge in which SSI_DO drives data. SSI_DO and SSI_DI can be tied together to interface to a three-pin SSI peripheral. SSI Data Output drives data to a peripheral device SSI port. Data is driven on the opposite SSI_CLK signal edge in which SSI_DI latches data. The DO signal is normally at high-impedance when no transmit transaction is active on the SSI port. 32.768-kHz Crystal Interface is used for connecting an external crystal or oscillator to the ELANSC520 microcontroller. This clock source is used to clock the real-time clock (RTC). In addition, internal PLLs generate clocks for the timers and UARTs based on this clock source. When an external oscillator is used, 32KXTAL1 should be grounded and the clock source driven on 32KXTAL2. 33MXTAL2- 33MXTAL1 -- Osc 33-MHz Crystal Interface is the main system clock for the chip. This clock source is used to derive the SDRAM, CPU, and PCI clocks. When an external oscillator is used, 33MXTAL1 should be unconnected and the clock source driven on 33MXTAL2. [CLKTEST] CLKTIMER O Test Clock Output is a shared pin that allows many of the internal clocks to be driven externally. CLKTEST can drive the internal clocks of the UARTs, PLL1, PLL2, the programmable interval timer (PIT), or the real-time clock (RTC) for testing or for driving an external device. Timer Clock Input is a shared clock pin that can be used to input a frequency to the programmable interval timer (PIT). Loop Filter Interface is used for connecting external loop filter components. Component values and circuit descriptions are contained in "Clock Generation and Control" on page 38. Programmable Reset can be programmed to reset the ELANSC520 microcontroller, but allow SDRAM refresh to continue during the reset. This allows the system to be reset without losing the information stored in SDRAM. On power-up, PRGRESET is disabled and must be programmed to be operational. When disabled, this pin has no effect on the ELANSC520 microcontroller. PWRGOOD -- STI Power Good is a reset signal that indicates to the ELANSC520 microcontroller that the VCC levels are within the normal operation range. It is used to reset the entire chip and must be held Low for one second after all VCC signals (except VCC_RTC) on the chip are High. This signal must be returned Low before the VCC signals degrade to put the RTC into the correct state for operation in RTC-only mode. SSI_DI -- STI SSI_DO -- OD Clocks and Reset 32KXTAL2- 32KXTAL1 -- Osc CLKTIMER LF_PLL1 [CLKTEST] -- I I PRGRESET -- STI 22 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY Table 2. Signal Descriptions (Continued) Signal JTAG JTAG_TCK JTAG_TDI -- -- I I Test Clock is the input clock for test access port. Test Data Input is the serial input stream for input data. This pin has a weak internal pullup resistor. It is sampled on the rising edge of JTAG_TCK. If not driven, this input is sampled High internally. Test Data Output is the serial output stream for result data. It is in the high-impedance state except when scanning is in progress. Test Mode Select is an input for controlling the test access port. This pin has a weak internal pullup resistor. If it is not driven, it is sampled High internally. JTAG Reset is the test access port (TAP) reset. This pin has a weak internal pulldown resistor. If not driven, this input is sampled Low internally and causes the TAP controller logic to remain in the reset state. Break Request/Trace Capture requests entry to AMDebug technology mode. The AMDebug technology serial/parallel interface can reconfigure this pin to turn instruction trace capture on or off. Command Acknowledge indicates command completion status. It is asserted High when the in-circuit emulator logic is ready to receive new commands from the host. It is driven Low when the in-circuit emulator core is executing a command from the host and remains Low until the command is completed. Stop/Transmit is asserted High on entry to AMDebug mode. During normal mode, this is set High when there is data to be transmitted to the host (during operating system/application communication). Trigger/Trace triggers events to a logic analyzer (optional, from Am5x86 CPU debug registers) or indicates trace on or off status. The AMDebug technology is used to enable and configure this pin. Code Fetch SDRAM, during SDRAM reads, provides code fetch status. When Low, this indicates that the current SDRAM read is a CPU code fetch demanded by the CPU, or a read prefetch initiated due to a demand code fetch by the CPU. When High during reads, this indicates that the SDRAM read is not a code fetch, and it could have been initiated by the CPU, PCI master, or the GP bus GP-DMA controller, either demand or prefetch. During SDRAM write cycles this pin provides an indication of the source of the data, either GP-DMA controller/PCI bus master or CPU. When High, this indicates that either a GP bus DMA initiator or an external PCI bus master contributed to the current SDRAM write cycle (the CPU may also have contributed). A Low indicates that the CPU is the only master that contributed to this write cycle. CF_ROM_GPCS [WBMSTR0] {CFG0} O{I} Code Fetch ROM/GPCS provides an indication that the CPU is performing a code fetch from ROM (on either the GP bus or SDRAM data bus), or from any GPCSx pin. When Low during a read cycle (as indicated by either GPMEMRD or ROMRD), the CPU is performing a code fetch from ROM or a GP bus chip select. At all other times (including writes), this signal is High. Data Strobe is a debug signal that is asserted to allow the external system to latch SDRAM data. This can be used to trace data on the SDRAM interface with an in-circuit emulator probe or logic analyzer. Multiplexed Signal Type Description JTAG_TDO JTAG_TMS -- -- O/TS I JTAG_TRST -- I AMDebug Interface BR/TC -- I CMDACK -- O STOP/TX -- O TRIG/TRACE -- O System Test CF_DRAM [WBMSTR2] {CFG2} O{I} DATASTRB [WBMSTR1] {CFG1} O{I} ElanTMSC520 Microcontroller Data Sheet 23 PRELIMINARY Table 2. Signal Descriptions (Continued) Signal [WBMSTR0] Multiplexed Signal CF_ROM_GPCS {CFG0} Type O{I} Description Write Buffer Master indicates which block(s) wrote to a rank in the write buffer (during SDRAM write cycles) and which block is reading from SDRAM (during SDRAM read cycles). WBMSTR0, when a logical 1, indicates that the internal GP bus DMA controller has contributed to the write buffer rank (write cycles) or is reading from SDRAM (read cycles). [WBMSTR1] DATASTRB {CFG1} CF_DRAM {CFG2} O{I} WBMSTR1, when a logical 1, indicates that the PCI master has contributed to the write buffer rank (write cycles) or is reading from SDRAM (read cycles). WBMSTR2, when a logical 1, it indicates that the CPU has contributed to the write buffer rank (write cycles) or is reading from SDRAM (read cycles). General-Purpose Chip Select signals are for the GP bus. They can be used for either memory or I/O accesses. These chip selects are asserted for Am5x86 CPU accesses to the corresponding regions set up in the Programmable Address Region (PAR) registers. [WBMSTR2] O{I} Chip Selects [GPCS0] [GPCS1] [GPCS2] [GPCS3] [GPCS4] [GPCS5] [GPCS6] [GPCS7] PIO27 ROMCS1 ROMCS2 PITGATE2 TMRIN1 TMRIN0 TMROUT1 TMROUT0 O O O O O O O O 24 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY Table 2. Signal Descriptions (Continued) Signal Multiplexed Signal [GPALE] [GPBHE] [GPRDY] [GPAEN] [GPTC] [GPDRQ3] [GPDRQ2] [GPDRQ1] [GPDRQ0] [GPDACK3] [GPDACK2] [GPDACK1] [GPDACK0] [GPIRQ10] [GPIRQ9] [GPIRQ8] [GPIRQ7] [GPIRQ6] [GPIRQ5] [GPIRQ4] [GPIRQ3] [GPIRQ2] [GPIRQ1] [GPIRQ0] [GPDBUFOE] [GPIOCS16] [GPMEMCS16] [GPCS0] [CTS2] [DSR2] [DCD2] [RIN2] [GPCS3] {CFG3} [GPCS5] [GPCS4] [GPCS7] [GPCS6] Type Description Programmable I/O (PIO) PIO0 PIO1 PIO2 PIO3 PIO4 PIO5 PIO6 PIO7 PIO8 PIO9 PIO10 PIO11 PIO12 PIO13 PIO14 PIO15 PIO16 PIO17 PIO18 PIO19 PIO20 PIO21 PIO22 PIO23 PIO24 PIO25 PIO26 PIO27 PIO28 PIO29 PIO30 PIO31 Timers PITGATE2 PITOUT2 TMRIN0 TMRIN1 TMROUT0 TMROUT1 I O{I} I I O O Programmable Interval Timer 2 Gate provides control for the PIT Channel 2. Programmable Interval Timer 2 Output is output from the PIT Channel 2. This signal is typically used as the PC speaker signal. Timer Inputs 0 and 1 can be programmed to be the control or clock for the general-purpose (GP) timers 0 and 1. Timer Outputs 0 and 1 are outputs from two of the GP timers. These outputs can be used as pulse-width modulation signals. B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B Programmable Input/Output signals can be programmed as inputs or outputs. When they are outputs, they can be driven High or Low by programming bits in registers. ElanTMSC520 Microcontroller Data Sheet 25 PRELIMINARY Table 2. Signal Descriptions (Continued) Signal Configuration {AMDEBUG_DIS} GPA23 I AMDebug Disable is an active High configuration signal latched at the assertion of Power Good (PWRGOOD). This pin has a built-in pulldown resistor. At Power Good assertion: Low = Normal operation, mode can be enabled by software. High = AMDebug mode is disabled and cannot be enabled by software. {CFG0} CF_ROM_GPCS [WBMSTR0] I Configuration Inputs 3-0 are latched into the chip when PWRGOOD is asserted. These signals are all shared with other features. These signals have built-in pulldown resistors. CFG0: Choose 8-, 16-, or 32-bit ROM/Flash interface for BOOTCS. {CFG1} DATASTRB [WBMSTR1] I CFG1: Choose 8-, 16-, or 32-bit ROM/Flash interface for BOOTCS. CFG1 0 0 1 {CFG2} CF_DRAM [WBMSTR2] I CFG0 0 1 x (don't care) BOOTCS Data Width 8-bit 16-bit 32-bit Multiplexed Signal Type Description CFG2: When Low when PWRGOOD is asserted, the ELANSC520 microcontroller uses the GP data bus for BOOTCS. When seen as High during PWRGOOD assertion, the BOOTCS access is across the SDRAM data bus. Default is Low (by a built-in pulldown resistor). CFG3 (Internal AMD test mode enable): For normal ELANSC520 microcontroller operation, do not pull High during reset. Enter AMDebug Mode is an active High configuration signal latched at the assertion of Power Good (PWRGOOD). This pin enables the AMDebug mode, which causes the processor to fetch and execute one instruction from the BOOTCS device, and then enter AMDebug mode where the CPU waits for debug commands to be delivered by the JTAG port. This pin has a built-in pulldown resistor. At PWRGOOD assertion: High = AMDebug mode enabled Low = Normal operation {CFG3} {DEBUG_ENTER} PITOUT2 GPA25 I I {INST_TRCE} GPA24 I Instruction Trace is an active High configuration signal latched at the assertion of Power Good (PWRGOOD). Enables trace record generation from Power Good assertion. This pin has a built-in pulldown resistor. At PWRGOOD assertion: High = Trace controller enabled to output trace records Low = Normal operation 26 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY Table 2. Signal Descriptions (Continued) Signal {RSTLD0} {RSTLD1} {RSTLD2} {RSTLD3} {RSTLD4} {RSTLD5} {RSTLD6} {RSTLD7} Power BBATSEN -- Analog Backup Battery Sense is a pin on which real-time clock (RTC) backup battery voltage is sampled each time PWRGOOD is asserted. If this pin samples below 2.0 V, the Valid RAM and Time (VRT) bit in RTC index 0Dh is cleared until read. After the read, the VRT bit is set until BBATSEN is sensed via a subsequent PWRGOOD assertion. BBATSEN also provides a power-on-reset signal for the RTC when an RTC backup battery is applied for the first time. Analog Power Supply for the analog circuits (PLLs). Power Supply for the ELANSC520 microcontroller core logic. Power Supply to the I/O pad ring. Power Supply for the real-time clock and 32-kHz oscillator. Digital Ground for the remaining ELANSC520 microcontroller core logic. Analog Ground for the analog circuits. Multiplexed Signal GPA15 GPA16 GPA17 GPA18 GPA19 GPA20 GPA21 GPA22 Type I I I I I I I I Description Reset Latched Inputs are shared signals that are latched into a register when PWRGOOD is asserted. They are used to input static information to software (i.e., board revision). These signals have builtin pulldown resistors. VCC_ANLG VCC_CORE VCC_I/O VCC_RTC GND GND_ANLG -- -- -- -- -- -- Power Power Power Power Power Power ElanTMSC520 Microcontroller Data Sheet 27 PRELIMINARY ARCHITECTURAL OVERVIEW The ELANSC520 microcontroller was designed to provide: s A balanced mix of high performance and low-cost s An industry-standard, 32-bit PCI bus is provided for interface mechanisms s A high-performance, industry-standard 32-bit PCI bus s Glueless interfacing to many 8- and 16-bit I/O pe- high bandwidth I/O peripherals such as local area network controllers, synchronous communications controllers, and disk storage controllers. s A simple 8/16-bit, 33-MHz general-purpose bus ripherals and an 8- and 16-bit bus with programmable timing s A cost-effective system architecture that meets a (GP bus) provides a glueless connection to lower bandwidth peripherals and NVRAM, SRAM, ROM, or custom ASICs; supports dynamic bus sizing and compatibility with many common ISA devices. These three buses listed above are provided in all operating modes of the ELANSC520 microcontroller. In addition to these three primary interfaces, the ELANSC520 microcontroller also contains internal oscillator circuitry and phase locked loop (PLL) circuitry, requiring only two simple crystals for virtually all system clock generation. Diagrams showing how the ELANSC520 microcontroller can be used in various system designs are included in "Applications" on page 33. wide range of performance criteria while retaining the lower cost of a 32-bit system s A high degree of leverage from present day hard- ware and software technologies Figure 1 on page 29 illustrates the integrated Am5x86 CPU, bus structure, and on-chip peripherals of the ELANSC520 microcontroller. Three primary interfaces are provided: s A high-performance, 66-MHz, 32-bit synchronous DRAM (SDRAM) interface of up to 256 Mbytes is used for Am5x86 CPU code execution, as well as buffer storage of external PCI bus masters and GP bus DMA initiators. A high-performance ROM/Flash interface can also be connected to the SDRAM interface. 28 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY CPU Address Bus SDRAM Controller CPU Bus Interface Address Decode Unit Read/Write Buffers ROM/Flash Controller Bus Interface Unit Am5x86C CPU CPU Data Bus AMDebugTM Technology and JTAG CPU Control/Status Bus GP-DMA Controller GP Bus Controller Control/Status CPU Request Address GP-DMA Request and Grant GP Bus Clock Generation External GP Bus Programmable Interrupt Controller Programmable Interval Timer Data CPU Bus Interface CPU Bus Arbiter Watchdog Timer FIFOs and FIFO Control Real-Time Clock CMOS RAM PCI Bus Arbiter PCI Master PCI Target General-Purpose Timers Software Timer 16550 UART 16550 UART PCI Bus PCI Requests and Grants Synchronous Serial Interface Programmable I/O Controls PC/AT Compatibility Logic ElanTMSC520 Microcontroller Figure 1. ElanTMSC520 Microcontroller Block Diagram ElanTMSC520 Microcontroller Data Sheet 29 PRELIMINARY Industry-Standard x86 Architecture The Am5x86 CPU in the ELANSC520 microcontroller utilizes the industry-standard x86 microprocessor instruction set that enables compatibility across a variety of performance levels from the 16-bit Am186TM processors to the high-end AMD AthlonTM processor. Software wr itten for the x86 architecture family is compatible with the ELANSC520 microcontroller. Other benefits of the Am5x86 CPU include: s Improved time-to-market and easy software migra- lator manufacturers. The parallel AMDebug port greatly simplifies the task of supporting high speed data exchange. Industry-Standard PCI Bus Interface The ELANSC520 microcontroller provides a 33-MHz, 32-bit PCI bus Revision 2.2-compliant host bridge interface, including integrated write-posting and readbuffering capabilities suitable for high-throughput applications. The PCI host bridge leverages standard peripherals and software. It also provides: s High throughput (132 Mbytes/s peak transfer rate) s Deep buffering and support for burst transactions tion s Existing availability of multiple operating systems that directly support the x86 architecture. Whether the application requires a real-time operating system (RTOS) or one of the popular Microsoft(R) operating systems, the ELANSC520 microcontroller provides consistent compatibility with many off-theshelf operating systems. s Multiple sources of field-proven development tools s Integrated floating point unit (FPU) (compliant with from PCI bus masters to SDRAM s Flexible arbitration mechanism s Support for up to five external PCI masters High-Performance SDRAM Controller The ELANSC520 microcontroller provides an integrated SDRAM controller that supports popular industry-standard synchronous DRAMs (SDRAM). s The SDRAM controller interfaces with SDRAM ANSI/IEEE 754 standard) s 16-KByte unified cache configurable for either write- back or write-through cache mode AMDebugTM Technology for Advanced Debugging The ELANSC520 microcontroller provides support for low-cost, full-featured, in-circuit emulation capability. This in-circuit emulation support was developed at AMD specifically to enable users to test and debug their software earlier in the design cycle. Utilizing this capability, the software can be more extensively exercised, and at full execution speeds. It also allows tracing during execution from the Am5x86 CPU's internal cache. AMDebug technology provides the product design team with two different communication paths on the ELANSC520 microcontroller, each of which is supported by powerful debug tools from third-party vendors in AMD's FusionE86SM program. s Serial AMDebug technology uses a serial connec- chips as well as with most standard DIMMs to enable use of standard off-the-shelf memory components. s The SDRAM controller supports programmable tim- ing options and provides the required external clock. s Up to four 32-bit banks of SDRAM are supported with a maximum capacity of 256 Mbytes. s An important reliability-enhancing Error Correction Code (ECC) feature is built into the SDRAM controller. The resultant increase in the memory content reliability enables the ELANSC520 microcontroller to be effectively utilized in applications that require more reliable operation, such as communications environments. s The SDRAM controller contains a write buffer and read ahead buffer subsystem that improves both write and read performance. s SDRAM refresh options allow the SDRAM contents tion based on an enhanced JTAG protocol and an inexpensive 12-pin connector that can be placed on each board design. This low-cost solution satisfies the requirement of a large number of software developers. s Parallel AMDebug technology uses a parallel debug to be maintained during reset. ROM/Flash Controller The ELANSC520 microcontroller provides an integrated ROM controller for glueless interfacing to ROM and Flash devices. The ELANSC520 microcontroller supports two types of interfaces to such devices--a simple interface via the GP bus (see "Easy-to-Use GP Bus Interface" on page 31) for 8- and 16-bit devices, and an interface to the SDRAM memory data bus for higher performance 8-, 16-, and 32-bit devices. port to exchange commands and data between the ELANSC520 microcontroller and the host. The higher pin count requires that the extra signal pins be provided on a special bond-out package of the ELANSC520 microcontroller, which is only made available to tool developers such as in-circuit emu- 30 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY The ROM/Flash controller: s Reduces system cost by gluelessly interfacing Clock Generation The ELANSC520 microcontroller offers user-configurable CPU core clock speed operation at 100 or 133 MHz for different power/performance points depending on the application. Not all ELANSC520 microcontroller devices support all CPU clock rates. The maximum supported clock rate for a device is indicated by the part number printed on the package. The clocking circuitry can be programmed to run the device at higher than the rated speeds. However, if an ELANSC520 microcontroller is programmed to run at a higher clock speed than that for which it is rated, then erroneous operation can result, and physical damage to the device may occur. The ELANSC520 microcontroller includes on-chip oscillators and PLLs, as well as most of the required PLL loop filter components. The ELANSC520 microcontroller requires two standard crystals, one for 32.768 kHz and one for 33 MHz. All the clocks required inside the ELANSC520 microcontroller are generated from these crystals. The ELANSC520 microcontroller also supplies the clocks for the SDRAM and PCI bus; however, external clock buffering may be required in some systems. static memory with up to three ROM/Flash chip selects s Supports execute-in-place (XIP) operating systems for applications that require executing out of ROM or Flash memory instead of DRAM s Supports high-performance page-mode devices Flexible Address-Mapping Hardware In addition to the memory management unit (MMU) within the Am5x86 CPU core, the ELANSC520 microcontroller provides 16 Programmable Address Region (PAR) registers that enable flexible placement of memory (SDRAM, ROM, Flash, SRAM, etc.) and peripherals into the two address spaces of the Am5x86 CPU (memory address space and I/O address space). The PAR hardware allows designers to flexibly configure both address spaces and place memory and/or external peripherals, as required by the application. The internal memory-mapped configuration registers space can also be remapped to accommodate system requirements. PAR registers also allow control of important attributes, such as cacheability, write protection, and code execution protection for memory resources. Easy-to-Use GP Bus Interface The ELANSC520 microcontroller includes a simple general-purpose bus (GP bus) that provides programmable bus timing and allows the connection of 8/16-bit peripheral devices and memory to the ELANSC520 microcontroller. The GP bus operates at 33 MHz, which offers good performance at a very low interface cost. The ELANSC520 microcontroller provides up to eight chip selects for external GP bus devices such as offthe-shelf I/O peripherals, custom ASICs, and SRAM or NVRAM. The GP bus interface supports programmable timing and dynamic bus width and cycle stretching to accommodate a wide variety of standard peripherals, such as UARTs, 10-Mbit LAN controller chips and serial communications controllers. Up to four external DMA channels provide fly-by DMA transfers between peripheral devices on the GP bus and system SDRAM. Internally, the GP bus is used to provide a complement of integrated peripherals, such as a DMA controller, programmable interrupt controller, timers, and UARTs, as described in "Integrated Peripherals" on page 31. These internal peripherals are designed to operate at the full clock rate of the GP bus. The internal peripherals can also be configured to operate in PC/AT-compatible configuration, but are generally not restricted to this configuration. The ELANSC520 microcontroller provides a way to view accesses to the internal peripherals on the external GP bus for debugging purposes. Note: The ELANSC520 microcontroller supports either a 33.000-MHz or 33.333-MHz crystal. In this document, the generic term "33 MHz" refers to the system clock derived from whichever 33-MHz crystal frequency is being used in the system. Integrated Peripherals The ELANSC520 microcontroller is a highly integrated single-chip CPU with a set of integrated peripherals that are a superset of common PC/AT peripherals, plus a set of memory-mapped peripherals that enhance its usability in various applications. s A programmable interrupt controller (PIC) that pro- vides the capability to prioritize 22 interrupt levels, up to 15 of these being external sources. The PIC can be programmed to operate in PC/AT-compatible mode, but also contains extended features, including support for more sources and flexible routing that allows any interrupt request to be steered to any PIC input. Interrupt requests can be programmed to generate either non-maskable interrupt (NMI) or maskable interrupt requests. s An integrated DMA controller is included for trans- ferring data between SDRAM and GP bus peripherals. The GP-DMA controller operates in single-cycle (fly-by) mode for more efficient transfers. The GPDMA controller can be programmed for PC/AT compatibility, but also contains enhanced features: - A double buffer-chaining mode provides a more efficient software interface - Extended address and transfer counts - Flexible routing of DMA channels ElanTMSC520 Microcontroller Data Sheet 31 PRELIMINARY s Three general-purpose 16-bit timers that provide JTAG Boundary Scan Test Interface The ELANSC520 microcontroller provides a JTAG test port that is compliant with IEEE 1149.1 for use during board testing. flexible cascading for extension to 32-bit operation. These timers provide the ability to configure down to the resolution of four clock periods where the clock period is the 33-MHz clock. Timer input and output pins provide the ability to interface with offchip hardware. s A standard PC/AT-compatible programmable inter- System Test and Debug Features To facilitate debugging, the ELANSC520 microcontroller provides observability of many portions of its internal operation, including: s A three-pin interface that can be used in either sys- val timer (PIT) that consists of three 16-bit timers. s A software timer that eases the task of keeping sys- tem time. It provides 1-ms resolution and can also be used for performance monitoring. s A watchdog timer to guard against runaway soft- ware. s A real-time clock (RTC) with battery backup capa- tem test mode or write buffer test mode, to aid in determining internal bus initiators of SDRAM cycles, and determining when SDRAM data is valid on the interface. An additional mode provides observability of integrated peripheral accesses. s A nonconcurrent arbitration mode to reduce debug bility. The RTC also provides 114 bytes of batterybacked RAM for storage of configuration parameters. s Two integrated 16550-compatible UARTs that pro- complexity when PCI bus masters and GP bus DMA initiators are also accessing SDRAM. s CPU cache control and dynamic core clock speed vide full handshaking capability with eight pins each. Enhancements enable the UARTs to operate at baud rates up to 1.152 Mbits/s. The UARTs can be configured to use the integrated GP bus DMA controller to transfer data between the serial ports and SDRAM. s A synchronous serial interface (SSI) that is compat- control under program control. s Ability to disable write posting and read prefetching in the SDRAM controller to simplify tracing of SDRAM cycles. s Notification of memory write protection and non-ex- ecutable memory region violations. ible with SCP, SPI, and Microwire slave devices. The SSI interface can be configured for either fullduplex or half-duplex operation using a 4-wire or 3-wire interface. s 32 programmable I/O pins are provided. These pins are multiplexed with other peripherals and interface functions. s The ELANSC520 microcontroller also provides PC/ AT-compatible functions for control of the a20 gate and the soft CPU reset (Por ts 0060h, 0064h, 0092h). 32 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY APPLICATIONS The f igu r es on th e fol lowi ng pag es sh ow th e ELANSC520 microcontroller as it might be used in several reference design applications in the data commun i c a t i o n s , i n fo r m a t i o n a p p l i a n c e s , a n d telecommunication markets. s Figure 2 on page 34 shows an ELANSC520 micros Figure 3 on page 35 shows an ELANSC520 micro- controller-based Smart Resident Gateway (SRG), which is a router for a home network between the wide area network (WAN) (the internet) and a local area network (LAN) (an intranet of computers and information appliances in the home). The SRG provides firewall protection of the LAN from unauthorized access through the internet. A common internet access medium is shared by all users on the LAN. A variety of connections are possible for both the WAN and the LAN. For example, the WAN connection can be a V.90 modem, cable modem, ISDN, ADSL, or Ethernet. The LAN connection can be: - HomePNA--Home Phoneline Networking Alliance, an alliance with a widely endorsed home networking specification; - Bluetooth--a computing and telecommunications industry specification that describes how computing devices can easily interconnect with each other and with home and business phones and computers using a short-range wireless connection); - Home RF--a standard competing with Bluetooth for the interconnection of computing devices in a LAN using radio frequency; - Ethernet--local area network technology; - power line--a LAN using the AC power distribution network in a home or business to interconnect devices. Digital information is transmitted on a high-frequency carrier signal on top of the AC power. controller-based "thin client," which is the modern replacement for the traditional terminal in a remote computing paradigm. Application programs run remotely on a server, and data is warehoused on centrally managed disks at the "server farm." An efficient communications protocol transmits keyboard and mouse commands upstream and transmits video BIOS calls downstream. The thin client renders and displays the graphics for the user. The thin client is typically connected to an Ethernet LAN, although a remote location can connect to a server via a WAN connection such as a modem. A minimum speed of 24 kbaud is required for the communication protocol, unless the application is graphics-intensive, in which case a faster connection is required. s Figure 4 on page 36 shows an ELANSC520 micro- controller-based digital set top box (DSTB), which is a consumer client device that uses a television set as the display. Common applications for the DSTB are internet access, e-mail, and streaming audio and video content. The minimal system includes a connection to the WAN via a modem, ADSL, or cable modem; an output to a TV; and an InfraRed (IR) link to a remote control or wireless keyboard. Expanded systems include DVD drives and MPEG2 decoders to deliver digital video content. A hard drive may be employed to store video data for future replay. Keyboard, mouse, printer, or a video camera are options that can be included. s Figure 5 on page 37 shows an ELANSC520 micro- controller-based telephone line concentrator located in the neighborhood that converts multiple analog subscriber loops into a high-speed digitally multiplexed line for connection to the central office switching network. ElanTMSC520 Microcontroller Data Sheet 33 PRELIMINARY RJ-11 RJ-11 RJ-45 WAN Interface ADSL, Cable Modem or V.90 RJ-45 or PCnetTM-Home LAN Interface Am79C978 or AD31-AD0 MD31-MD0 Control ElanTMSC520 Microcontroller GPD15-GPD0 Control 33-MHz Crystal Figure 2. ElanTMSC520 Microcontroller-Based Smart Residential Gateway Reference Design 34 ElanTMSC520 Microcontroller Data Sheet 32-kHz Crystal Flash or ROM MA12-MA0 SDRAM Bus SDRAM GP Bus Control PCI Bus GPA25-GPA0 PRELIMINARY VGA/LCD CRT/LCD Controller PS/2 Keyboard PS/2 Mouse Parallel Super I/O LAN Interface Am79C973/Am79C975 PCnetTM-Fast III RJ-45 AD31-AD0 Control Control PCI Bus MA12-MA0 SDRAM Bus SDRAM MD31-MD0 GP Bus GPD15-GPD0 GPA25-GPA0 Flash Memory ElanTMSC520 Microcontroller Control Control Figure 3. ElanTMSC520 Microcontroller-Based Thin Client Reference Design ElanTMSC520 Microcontroller Data Sheet 33-MHz Crystal 32-kHz Crystal Serial 35 36 SDRAM RJ-11 MA12-MA0 SDRAM Bus 33-MHz Crystal MD31-MD0 Control VGA NTSC/PAL WAN Interface ADSL, Cable Modem or V.90 32-kHz Crystal AD31-AD0 PCI Bus Control ElanTMSC520 Microcontroller Figure 4. PRELIMINARY DVD or HDD EIDE GP Bus PS/2 Keyboard PS/2 Mouse Super I/O Parallel IR Flash Memory Control Control ElanTMSC520 Microcontroller-Based Digital Set Top Box Reference Design ElanTMSC520 Microcontroller Data Sheet GPA1-GPA0 GPD15-GPD0 GPD15-GPD0 GPA25-GPA0 Control Figure 5. ISLIC Am79R241 SDRAM Quad ISLAC Am79Q2241 ISLIC Am79R241 ISLIC Am79R241 ISLIC Am79R241 SSI MD31-MD0 SDRAM Bus MA12-MA0 Control (6x to 10X) PCM Highway ISLIC Am79R241 ISLIC Am79R241 Quad ISLAC Am79Q2241 Control GP Bus ISLIC Am79R241 ISLIC Am79R241 ElanTMSC520 Microcontroller Analog Phone Lines 33-MHz Crystal PRELIMINARY ElanTMSC520 Microcontroller-Based Telephone Line Concentrator Reference Design ElanTMSC520 Microcontroller Data Sheet GPD15-GPD0 Flash Memory GPA25-GPA0 Control HDLC T1/E1 Interface T1 or E1 32-kHz Crystal 37 PRELIMINARY CLOCK GENERATION AND CONTROL The ELANSC520 microcontroller is designed to generate all of the internal and system clocks it requires. The ELANSC520 microcontroller includes on-chip oscillators and PLLs, as well as most of the required PLL loop filter components. The ELANSC520 microcontroller requires two standard crystals, one for 32.768 kHz and one for 33 MHz. All the clocks required inside the ELANSC520 microcontroller are generated from these crystals. Output clock pins are provided for selected clocks, providing up to 24 mA of sink or source current. The ELANSC520 microcontroller also supplies the clocks for SDRAM and PCI bus; however, external clock buffering may be required in some systems. Figure 6 shows a system block diagram of the ELANSC520 microcontroller's external clocks. Note: The ELANSC520 microcontroller supports either a 33.000-MHz or 33.333-MHz crystal. In this document, the generic term "33 MHz" refers to the system clock derived from whichever 33-MHz crystal frequency is being used in the system. VCC_ANLG 32KXTAL1 32.768-kHz Crystal C2 32KXTAL2 R1 33MXTAL1 33-MHz Crystal LF_PLL1 33MXTAL2 66 MHz Optional Clock Driver C1 66 MHz . . . SDRAM CLKMEMOUT CLKMEMIN CLKPCIIN CLKPCIOUT CLKTIMER/ [CLKTEST] ELANSC520 Microcontroller 33 MHz Programmable Optional Clock Driver 33 MHz Note: Dotted line ovals, , signify frequency groups. PCI Device PCI Device Figure 6. System Clock Distribution Block Diagram 38 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY Internal Clocks Figure 7 shows a block diagram of the ELANSC520 microcontroller's internal clocks. The clocks are generated from two local oscillators. The 32.768-kHz oscillator is used to drive PLL1 (1.47456-MHz PLL), which in turn drives PLL2 (36.864- MHz PLL). The 36.864-MHz clock is divided by 2 to produce the 18.432-MHz UART clock. It is divided by 31 to produce the 1.1892-MHz PIT clock. The 33-MHz oscillator produces the 33-MHz PCI and CPU clocks. The 33-MHz oscillator is also used to drive PLL3 (66-MHz PLL) to produce the SDRAM clock. 32.768-kHz RTC 32.768-kHz Crystal 32.768-kHz Oscillator 32.768-kHz SDRAM Refresh 36.864 MHz 1.47456 MHz PLL1 LF_PLL1 33-MHz Crystal PLL2 DIV 31 1.1892-MHz PIT DIV 2 18.432-MHz UART 33-MHz Oscillator 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz PLL3 66 MHz SDRAM CPU PCI GP Bus GP DMA ROM SSI Timers1 Notes: 1. Includes the programmable interval timer (PIT), general-purpose timers, watchdog timer, and the software timer. Figure 7. Clock Source Block Diagram ElanTMSC520 Microcontroller Data Sheet 39 PRELIMINARY Clock Specifications PLL period jitter specifications are summarized in Table 3. Jitter specifications are only guaranteed when analog supply noise restrictions are met. Table 4 shows PLL lock times and oscillator start-up times. Table 5 shows the oscillator input specifications. Loop filter components for the 1.47456-MHz PLL (PLL1) must be supplied externally. They are connected between the analog VCC (VCC_ANLG) and the ELANSC520 microcontroller pin, LF_PLL1. Specifications for VCC_ANLG are shown in Table 6. Figure 6 on page 38 shows the loop filter circuit composed of C1, C2, and R1. Component values are given in Table 7 on page 41. Figure 6 on page 38, an external clock driver may be necessary when the system presents a large capacitive load. Clock pads are designed to either source or sink 24 mA. The maximum amount of capacitive load that can be placed on a clock pad is determined by the required rise/fall times. Use the following equation to determine the maximum capacitive loading. C = I/(dV/dt) where I = current, dV = voltage change, and dt = time change. As an example, suppose that the system requires a rise/fall time of 1 ns, with a voltage swing of 2.5 V. Then, the maximum capacitive load is: CMAX = 24 mA/(2.5 V/1 ns) = 9.6 pF Clock Pin Loading The ELANSC520 microcontroller's clock driver pins are designed to source or sink 24 mA. As shown in Table 3. Clock Name PIT UART CPU SDRAM Clock Frequency 1.1892 MHz 18.432 MHz Clock Jitter Specifications Min 828.3 ns 53.44 ns -- 14.775 ns Nominal 840.9 ns 54.25 ns 250 ps 15.0 ns Max 853.5 ns 55.07 ns -- 15.225 ns 33.000 MHz or 33.333 MHz 66.000 MHz or 66.666 MHz Table 4. Clock Source 32.768-kHz Oscillator 33-MHz Oscillator PLL1 (1.47456 MHz) PLL2 (36.864 MHz) PLL3 (66 MHz) Clock Startup and Lock Times Min -- -- -- -- -- Typ -- -- -- -- -- Max 1s 10 ms 10 ms 100 ms 50 ms Table 5. Oscillator Input Specifications Parameter 32KXTAL2 Input Voltage Low 32KXTAL2 Input Voltage High 33MXTAL2 Input Voltage Low 33MXTAL2 Input Voltage High Min -0.3 V VCC_RTC - 0.8 V -0.3 V VCC_ANLG - 0.8 V Typ -- -- -- -- Max +0.8 V VCC_RTC + 0.3 V +0.8 V VCC_ANLG + 0.3 V Table 6. Parameter Peak-to-Peak Noise on VCC_ANLG VCC_ANLG Voltage Level VCC_ANLG Current Analog VCC (VCC_ANLG) Specifications Min -- 2.25 V 1.4 mA Typ -- 2.5 V 1.9 mA Max 75 mV 2.75 V 2.1 mA 40 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY Table 7. PLL1 Loop Filter Components Parameter C1 C2 R1 Min 0.009 mF 0.0009 mF 4.465 kW Typ 0.01 mF 0.001 mF 4.7 kW Max 0.011 mF 0.0011 mF 4.935 kW Selecting a Crystal The accuracy of the RTC depends on several factors relating to crystal selection and board design. A clock timing budget determines the clock accuracy. The designer should determine the timing budget before selecting a crystal. There are four major contributors to a clock timing budget. s Frequency Tolerance--This is the crystal calibration If you multiply Error by 106, the error in ppm is given. In the above equation, C1 is the crystal motional capacitance, and Co is the crystal static capacitance. CLxtal is the crystal load capacitance, and CLsystem is the system load capacitance. Once the complete timing error has been calculated by adding all of the errors together, compare it to the initial timing budget. Table 8 provides a convenient translation of ppm to seconds per month. frequency. It states how far off the actual crystal frequency is from the nominal frequency. For a typical 32.768-kHz crystal (watch crystal), the frequency tolerance is 20 parts per million (ppm). Frequency tolerance is specified at room temperature. s Frequency Table 8. Timing Error as It Translates to Clock Accuracy Timing Error (Parts per million) 10 20 30 40 50 Seconds/Month 25.9 51.8 77.8 103.7 129.6 Stability--This parameter is a measure of how much the cr ystal resonant frequency is influenced by operating temperature. For watch crystals, typical numbers are around -30 ppm over the temperature range. resonant frequency changes with time. Typical Aging numbers are 3 ppm per year. s Aging--This parameter is how much the crystal s Load Capacitance--The crystal is calibrated with a 32.768-kHz Crystal Selection The 32.768-kHz crystal oscillator is shown in Figure 8. The oscillator load capacitance is 5 pF. Table 9 provides specifications for selecting a proper 32.768-kHz crystal. The Ecliptek ECPSM29T is recommended. specific load capacitance. If the system load capacitance does not equal the cr ystal load capacitance, a timing error is introduced. The timing error is calculated by the following equation. Error = {[1 + C1/(CLxtal+Co)]1/2 - [1 +C1/ (CLsystem+Co)]1/2}/ [1 + C1/(CLxtal+Co)]1/2 AMP 10 pF 10 pF Internal External 32KXTAL1 32KXTAL2 32.768-kHz Crystal Figure 8. 32.768-kHz Crystal Circuit ElanTMSC520 Microcontroller Data Sheet 41 PRELIMINARY Table 9. 32.768-kHz Crystal Specifications Parameter Nominal Frequency Effective Series Resistance (ESR) Drive Level Load Capacitance (ELANSC520 microcontroller) Resonant Mode Crystal Cut Operating Mode Min -- -- 1 mW 4.5 pF -- -- -- Typ 32.768 kHz -- -- 5 pF -- -- -- Max -- 60000 W -- 5.5 pF -- -- -- Parallel BT Fundamental Comment Table 10. 33-MHz Crystal Specifications Parameter or Characteristic Nominal Frequency ESR Drive Level Load Capacitance (ELANSC520 microcontroller) Resonant Mode Crystal Cut Operating Mode Min 33.000 MHz -- 1 mW -- -- -- -- Typ -- -- -- 2.5 pF -- -- -- Max 33.333 MHz 40 W -- -- -- -- -- Parallel AT or BT Fundamental Comment 33-MHz Crystal Selection The same information related to the 32.768-kHz crystal selection applies to the 33-MHz crystal selection. The ELANSC520 microcontroller supports either a 33.000MHz or 33.333-MHz crystal. Specifications for the 33-MHz crystal are shown in Table 10. AMD recommends using a fundamental mode 33.333MHz crystal. If a third overtone crystal is used, the oscillator gain may not be large enough to produce a reliable clock. Third Overtone Crystal Component Selection For the third overtone crystal circuit implementation, refer to Figure 9 on page 43. Components C4 and L1 are selected by the user. C3 is a parasitic capacitor composed of board parasitics. Typical values for C3 range from 5 pF to 15 pF. C4 is required for DC isolation. A nominal value for C4 is 0.1 mF. L1 in conjunction with C3 and C2 form a resonant circuit. The value of L3 is selected so that the resonant frequency is between the fundamental frequency and the third overtone frequency. For a 33.333-MHz third overtone crystal, the fundamental frequency is 11.111 MHz. From this, a desirable resonant frequency is between 11.111 MHz and 33.333 MHz. A good target frequency is 22.222 MHz. L1 is selected from the basic equation: L1 = 1/[(2 1/4 Pi 1/4 frequency)2 1/4 (C2 + C3)] Assuming that the board parasitics are 15 pF, then: L1 = 1/[ (2 1/4 Pi 1/4 22.222 MHz)2 1/4 (7 pF + 15 pF)] = 2.3 mH 42 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY AMP C1 =7 pF C2 = 7 pF Internal External 33MXTAL1 C3 33MXTAL2 C4 = 0.1 mF L1 Figure 9. 33.333-MHz Third Overtone Crystal Implementation Running the ElanTMSC520 Microcontroller at 33.333 MHz The clock that is supplied to the PCI bus (CLKPCIOUT) is exactly the same as the frequency of the crystal. The ELANSC520 microcontroller simply buffers the 33-MHz crystal input and provides it to the CLKPCIOUT pin. Since crystals have inaccuracies, it is possible that these inaccuracies cause the period of CLKPCIOUT to become marginally less than 30 ns. It is up to the system designer to choose the accuracy of the crystal used with the ELANSC520 microcontroller. The 33.000-MHz frequency provides a better guard band than the 33.333-MHz crystal. In practice, most PCI devices can tolerate both frequencies, but it is important to be aware of the impact of choosing the crysta l o n t h is p ot e nt i a l v i o l at i o n of t h e P CI bu s specifications. The PCI bus specification requires that the minimum clock period be 30 ns. ElanTMSC520 Microcontroller Data Sheet 43 PRELIMINARY Bypassing Internal Oscillators The 32.768-kHz and the 33-MHz ELANSC520 microcontroller oscillators can be bypassed by connecting an external clock to the crystal pins. Refer to Figure 10 and Figure 11 for the suggested circuitry. R1 External 32.768-kHz Oscillator 2.5 V 10% typical 32KXTAL2 R2 100 k 32KXTAL1 ELANSC520 Microcontroller Note: R1 and R2 are required when the external oscillator voltage, VOSC, exceeds 2.5 V. The value of R1 depends on VOSC according to the formula R1 = 100 k (VOSC - 2.5) / 2.5, where 100 k is the fixed value of R2, and 2.5 is the typical voltage for 32KXTAL2 (10%). Figure 10. Bypassing the 32.768-kHz Oscillator External 33-MHz Oscillator 2.5-V 10% typical 33MXTAL2 No Connect 33MXTAL1 ELANSC520 Microcontroller Figure 11. Bypassing the 33-MHz Oscillator 44 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY Bandgap Voltage Generator VBG Amplifier 2.0 V + OneShot - RTC Reset BBATSEN PWRGOOD D FlipFlop Q Internal RTC Power-Down 32 kHz CK Figure 12. RTC Voltage Monitor Block Diagram RTC VOLTAGE MONITOR If an external backup battery is connected to the ELANSC520 microcontroller's VCC_RTC pin, the realtime clock (RTC) remains operational even if all the other power supplies are turned off. The ELANSC520 microcontroller's RTC voltage monitor is designed to signal the RTC core when the backup battery is not installed or is low. Additionally, the voltage monitor circuit signals the RTC core when the rest of the system is being powered down. Features of the voltage monitor include: s Bandgap voltage generator for precision reference tery voltage, BBATSEN. If BBATSEN drops below the 2-V reference, an RTC invalidate signal is generated to notify the user via the RTC_VRT bit (RTC index 0Dh[7]) that the RTC contents are no longer valid. There are three conditions that trigger an RTC invalidation. They are the following: s BBATSEN drops below 2 V (sampled when PWR- GOOD asserts)--During operation from the main power supply, the backup battery voltage might drop below the trip voltage (2 V). The RTC is not invalidated until a PWRGOOD assertion occurs. s Power is applied to VCC_RTC (the backup battery voltage s High-gain amplifier for adjusting bandgap voltage to "low battery" trip voltage s The RTC can be connected to the main power plane is plugged in)--When the backup battery is plugged in, the RTC is immediately invalidated. s No battery during power-up (sampled after PWR- if a backup battery is not needed in the system. Figure 12 shows a block diagram of the RTC voltage monitor. The voltage monitor circuit uses a delta Vbe voltage (voltage from base to emitter) source to generate a bandgap voltage of approximately 1.23 V. This voltage is the input to an amplifier whose gain is such that the output voltage is a 2-V reference. This reference signal is an input to a comparator, along with the backup bat- GOOD asserts)--If the system does not contain a backup battery and the BBATSEN line potential is below 2 V, the RTC is invalidated when PWRGOOD asserts. In addition to the backup battery monitor function, the voltage monitor also provides a power-down signal to the RTC. This signal is used to isolate the RTC core from the rest of the integrated peripherals. A timing diagram for this sequence is shown in Figure 27 on page 60. ElanTMSC520 Microcontroller Data Sheet 45 PRELIMINARY Table 11. RTC Voltage Monitor Component Specifications Component D1 D2 D1, D2 C1 C2 R1 Parameter Forward Voltage Drop Forward Voltage Drop Forward Current Capacitance Capacitance Resistance Min -- -- -- 5 pF 180 pF 900 Nominal 0.25 V Note 1 Max -- -- -- 20 pF 400 pF 1.1 kW 100 mA 10 pF 200 pF 1 kW Notes: 1. Diode should be selected so that the voltage into the RTC power pin (VCC_RTC) does not exceed 3.3 V. Backup Battery Considerations The behavior of the RTC when the primary power supply is turned off depends on whether or not an external backup battery is included in the system design. Using an External RTC Backup Battery An implementation using a backup battery is shown in Figure 13 on page 47. The primary power source for VCC_RTC is the main power plane (VCC). D1 should be chosen so that the forward voltage drop is small, less than 0.25 V. D1 also prevents the backup battery from powering up the VCC power plane when the main supply is turned off. The backup battery voltage must not exceed 3.3 V (affects the BBATSEN and VCC_RTC pins); higher voltages may damage the ELANSC520 microcontroller. The RC network composed of R1 and C2 provides a time delay for the internal circuit power-up sequence. Accuracy tolerances are 10% of nominal values given in Table 11. C1 is for high-frequency filtering purposes. Not Using an External RTC Backup Battery For the system that is not using a backup battery, Figure 14 on page 47 shows how the circuit should be designed. It uses the same RC that is needed by the battery system, but it is now connected to VCC_RTC. For this configuration, the RTC is invalidated after power-up, but is not invalidated by subsequent PWRGOOD assertions. s The RTC is invalidated after a power-up. In this case, power has been removed from the RTC, so it should be invalidated. s When a reset switch tied to PWRGOOD is pressed (V CC remains High), PWRGOOD reasserts with BBATSEN High, so the RTC is not invalidated. In this case, power did not go away, so the RTC contents are still good. VCC_ANLG is selected as the power plane for VCC_RTC because it is a well-filtered power plane that is well below the VCC_RTC maximum of 3.3 V. Component values for the resistor and capacitor are shown in Table 11. 46 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY D2 D1 10 VCC_RTC BATT (3.3 V max) C1 R1 VCC_RTC BBATSEN C2 ELANSC520 Microcontroller Figure 13. Circuit with Backup Battery VCC_ANLG C1 R1 VCC_RTC BBATSEN C2 ELANSC520 Microcontroller Figure 14. Circuit without Backup Battery ElanTMSC520 Microcontroller Data Sheet 47 PRELIMINARY ABSOLUTE MAXIMUM RATINGS1 Symbol -- VCC_CORE VCC_I/O VCC_RTC VCC_ANLG Parameter Storage temperature Core voltage I/O voltage 2 2,3 2 Minimum -65 -0.5 -0.5 -0.5 -0.5 Maximum +125 3.2 5.5 4.5 3.2 Unit C V V V V Real-time clock voltage Analog voltage2 Notes: 1. WARNING--the "Absolute Maximum Ratings" are stress ratings only. Stresses above those listed can cause permanent damage. Operation beyond the values specified in Operating Ranges at Commercial Temperatures is not recommended, and extended exposure beyond these operating range values can affect device reliability. 2. Referenced from GND. 3. All inputs are 5-V tolerant. OPERATING RANGES AT COMMERCIAL TEMPERATURES1 Symbol TCASE VCC_CORE VCC_I/O VCC_RTC VCC_ANLG Parameter Description Commercial case temperature operating in free air Core voltage I/O voltage 2 2,3 2 Minimum 0 +2.375 +3.0 +2.0 +2.25 Typical -- +2.5 +3.3 +2.5 +2.5 Maximum +85 +2.625 +3.6 +3.3 +2.75 Unit C V V V V Real-time clock voltage Analog voltage2 Notes: 1. Operating ranges define the temperature and voltage limits between which the functionality of the device is guaranteed. 2. Referenced from GND. 3. All inputs are 5-V tolerant. 48 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY VOLTAGE LEVELS FOR NON-PCI INTERFACE PINS1 Advance Information Symbol VIL VIH VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 Parameter Description Input Low voltage Input High voltage Output High voltage (IOH = -6 mA) Output Low voltage (IOL = 6 mA) Output High voltage (IOH = -12 mA) Output Low voltage (IOL = 12 mA) Output High voltage (IOH = -18 mA) Output Low voltage (IOL = 18 mA) Output High voltage (IOH = -24 mA) Output Low voltage (IOL = 24 mA) Min - 0.3 2.0 VCC_I/O - 0.45 -- VCC_I/O - 0.45 -- VCC_I/O - 0.45 -- VCC_I/O - 0.45 -- Max + 0.8 VCC_I/O + 1.7 -- 0.45 -- 0.45 -- 0.45 -- 0.45 Unit V V V V V V V V V V Notes: 1. The drive strengths of all the pins are listed in Table 20, "Pin List Summary," on page A-7. The pins with variable drive strengths can take on the characteristics of 12-, 18-, or 24-mA signals. VOLTAGE LEVELS FOR PCI INTERFACE PINS The voltage characteristics of the PCI interface input pins are specified in the PCI Local Bus Specification, Revision 2.2, section 4.2.1 5V Signaling Environment and section 4.2.2 3.3V Signaling Environment. The voltage characteristics of the PCI interface output pins are specified in the PCI Local Bus Specification, Revision 2.2, 4.2.2 3.3V Signaling Environment. ElanTMSC520 Microcontroller Data Sheet 49 PRELIMINARY DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES Advance Information Symbol ICC_CORE ICC_CORE ICC_I/O ICC_RTC ICC_ANLG ILI1 Parameter Description Current for VCC_CORE supply @ 133 MHz Current for VCC_CORE supply @ 100 MHz Current for VCC_ I/O supply @ 33-MHz Current for RTC-only mode Current for ANLG-only mode Input leakage current (0.1 V < VIN < VCC_I/O) (All pins except those with internal pullup or pulldown resistors) Input leakage current VIN = (VCC_I/O - 0.1 V) (All pins with internal pulldown resistors) Input leakage current VIN = 0.1 V (All pins with internal pullup resistors) Output leakage current 4,5 1 2,3 Notes Min -- -- -- -- 1.4 -- Typ 465 380 100 5 1.9 -- Max 660 540 120 -- 2.1 e20 Unit mA mA mA mA mA mA ILI2 ILI3 ILO 4, 5 -- -- -- -- -- -- 60 -60 15 mA mA mA 5 Notes: 1. Estimate based on 3.3-V operation. Current for the I/O supply is constant, independent of the CPU frequency. 2. Value determined by simulation will be updated once characterization is complete. 3. Current measured with power applied only to the VCC_RTC supplies. 4. VCC_I/O = 3.6 V. 5. Table 20, "Pin List Summary," on page A-7 shows which pins have internal pullups or pulldowns. 50 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY CAPACITANCE Non-PCI Interface Pin Capacitance Advance Information Symbol CIN C32KXTAL C33MXTAL COUT CIO Parameter Description Input capacitance 32KXTAL1, 33KXTAL2 pin capacitance 33MXTAL1, 33MXTAL2 pin capacitance Output capacitance I/O pin capacitance Test Conditions FC=1 MHz Min -- -- -- -- -- Max 10 20 15 10 10 Unit pF pF pF pF pF PCI Interface Pin Capacitance Pin capacitance values are specified in the PCI Local Bus Specification, Revision 2.2, section 4.2.2.1 DC Specifications, Table 4-3: DC Specifications for 3.3V Signaling. Derating Curves All programmable I/O pins can be driven to the maximum drive current at once. The derating curves on the following pages can be used to determine potential specified timing variations based on system capacitive loading. Table 20, "Pin List Summary," on page A-7 has a column named "Max Load (pF)." This column describes the specification load presented to the specific pin, when testing was performed, to generate the timing specification documented in the AC Characteristics section of this data sheet. If the capacitive load on GPA0 is 70 pF, then a typical rise time is 6.5 ns. From Figure 18, the same load gives a typical fall time of 7 ns. Crystal Capacitance The crystal specifications can be found in Table 9, "32.768-kHz Crystal Specifications" on page 42 and Table 10, "33-MHz Crystal Specifications" on page 42. ElanTMSC520 Microcontroller Data Sheet 51 PRELIMINARY 35 30 25 Worst Case 20 ns 15 Typical 10 5 0 0 20 40 60 pF 80 100 120 Figure 15. I/O Drive 6-mA Rise Time 35 30 Worst Case 25 20 ns Typical 15 10 5 0 pF Figure 16. I/O Drive 6-mA Fall Time 52 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY 18 16 14 12 Worst Case 10 ns 8 Typical 6 4 2 0 0 20 40 60 pF 80 100 120 Figure 17. I/O Drive 12-mA Rise Time 18 16 14 Worst Case 12 10 ns 8 Typical 6 4 2 0 0 20 40 60 pF 80 100 120 Figure 18. I/O Drive 12-mA Fall Time ElanTMSC520 Microcontroller Data Sheet 53 PRELIMINARY 9 8 7 6 Worst Case 5 ns 4 3 2 1 0 0 20 40 60 pF 80 100 120 Typical Figure 19. I/O Drive 24-mA Rise Time 9 8 7 Worst Case 6 5 ns 4 Typical 3 2 1 0 0 20 40 60 pF 80 100 120 Figure 20. I/O Drive 24-mA Fall Time 54 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY 7 6 5 4 ns 3 2 Best Case 1 0 0 10 20 30 pF 40 50 60 Typical Worst Case Figure 21. PCI Pads Rise Time with 1-ns Rise/Fall 4 3.5 3 2.5 ns 2 Typical 1.5 Best Case 1 0.5 0 0 10 20 30 pF Worst Case 40 50 60 Figure 22. PCI Pads Fall Time with 1-ns Rise/Fall ElanTMSC520 Microcontroller Data Sheet 55 PRELIMINARY POWER CHARACTERISTICS Dynamic ICC measurements are dependent upon chip activity, operating frequency, output buffer logic, and capacitive/resistive loading of the outputs. Actual power supply current is dependent on system design and may be greater or less than the typical ICC number present here. Maximum power is measured at maximum V CC at maximum case temperature. Typical power is measured at typical VCC at 55C. For power dissipation values, refer to Table 12 and Table 13. Table 12. Power Maximum power Typical power Device Power Dissipation1 133 MHz 2.0 1.4 Unit W W 1.7 1.2 100 MHz Notes: 1. Device power dissipation calculation assumes that 50% of the I/O power is consumed on chip. Table 13. Supply VCC_ANLG and VCC_RTC Power Dissipation Typical 2.5 1.9 4.75 2.5 5 12.5 Max 2.75 2.1 5.78 3.3 -- -- Unit V mA mW V mA mW VCC_ANLG voltage level VCC_ANLG current VCC_ANLG power VCC_RTC voltage level VCC_RTC current VCC_RTC power THERMAL CHARACTERISTICS 388-Pin PBGA Package The ELANSC520 microcontroller is specified for operation with case temperature ranges from 0C to +85C for VCC_CORE = 2.5 V 10% and VCC_I/O = 3.3 V 10%. Case temperature is measured at the top center of the package as shown in Figure 23. The various temperatures and thermal resistances can be determined using the equations in Figure 24 with information given in Table 15. Thermal, electrical, and mechanical characteristics of AMD qualified packages (including the 388 PBGA) can be found on AMD's website at www.amd.com. Click on the link Products, and then click on the document link Packages and Packing Methodologies. qJA TC q JC qCA qJA = qJC + qCA Figure 23. Thermal Resistance (C/Watt) 56 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY Table 14. Thermal Resistance (C/W) qJC and qJA for BGA Package with 6-Layer Board Board Type1 6-layer qJC 3.3 qJA vs. Airflow 0 16.6 200 14.7 400 13.6 600 12.9 800 12.5 Notes: 1. The board type is described in the JEDEC standards document entitled Thermal Test Chip Guideline (Wire Bond Type Chip) at www.jedec.org. On the home page click on the link Free Standards and Docs, and then click on the document link JESD51-4 under JEDEC PUBLICATIONS. Table 15. Maximum TA for Plastic BGA Package with 6-Layer Board1 with TCASE = 85C CPU Clock Rate 133 MHz 100 MHz Airflow (Linear Feet Per Minute) 0 67C 70C 200 70C 72C 400 71C 74C 600 72C 74C 800 73C 75C Notes: 1. The board type is described in the JEDEC standards document entitled Thermal Test Chip Guideline (Wire Bond Type Chip) at www.jedec.org. On the home page click on the link Free Standards and Docs, and then click on the document link JESD51-4 under JEDEC PUBLICATIONS. qJA = qJC + qCA P = ICC 1/4 VCC TJ = TC + (P 1/4 qJC) TJ = TA + (P where: 1/4 qJA) qJA = Thermal resistance from junction to ambient qJC = Thermal resistance from junction to case qCA = Thermal resistance from case to ambient TJ = Junction temperature TA = Ambient temperature TC = Case temperature P = Power in Watts ICC = Power supply current in mA Figure 24. Thermal Characteristics Equations ElanTMSC520 Microcontroller Data Sheet 57 PRELIMINARY SWITCHING CHARACTERISTICS AND WAVEFORMS The AC switching specifications provided in the AC characteristics tables that follow consist of output delays, input setup requirements, and input hold requirements. AC specifications measurement is defined by the figures that follow each timing table. All timings are referenced to 1.5 V unless otherwise specified. Output delays are specified with minimum and maximum limits, measured as shown. The minimum delay times are hold times provided to external circuitry. Input setup and hold times are specified as minimums, defining the smallest acceptable sampling window. Within the sampling window, a synchronous input signal must be stable for correct microcontroller operation. Key to Switching Waveforms WAVEFORMS INPUTS Must be Steady OUTPUTS Will be Steady May Change from H to L Will be Changing from H to L May Change from L to H Will be Changing from L to H Don't Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High-Impedance "Off" State AC SWITCHING TEST WAVEFORMS Non-PCI Bus Interface Pins VIH = VCC_I/O VCC_I/O 2 Test Points VCC_I/O 2 VIL= 0 Input Output Note: For AC testing, inputs are driven at 3 V for a logic 1 and 0 V for a logic 0. Figure 25. AC Switching Test Waveforms PCI Bus Interface Pins For AC timing for PCI bus interface pins, refer to the PCI Local Bus Specification, Revision 2.2, 4.2.3.3 Measurement and Test Conditions, Figure 4-7: Output Timing Measurement Conditions, and Figure 4-8: Input Timing Measurement Conditions. 58 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES In this section, the following timings and timing waveforms are shown: s Power-on reset (page 59) s Reset (page 61) s ROM (page 63) s PCI bus (page 65) s SDRAM (page 66) s SDRAM clock (page 68) s GP bus (page 69) s GP bus DMA read (page 71) s GP bus DMA write (page 72) s SSI (page 73) s JTAG (page 74) Power-On Reset Timing Advance Information Symbol t1 t2 t3 t4 Parameter Description VCC_RTC valid hold before all other VCCs are valid PWRGOOD valid hold from all VCC valid (except VCC_RTC) VCC_RTC valid to BBATSEN active CFGx, RSTLDx, DEBUG_ENTER, INST_TRCE, AMDEBUG_DIS setup to PWRGOOD active CFGx, RSTLDx, DEBUG_ENTER, INST_TRCE, AMDEBUG_DIS hold from PWRGOOD active GPRESET inactive from PWRGOOD active RST inactive from PWRGOOD active PWRGOOD inactive to all VCCs invalid (except VCC_RTC) 3 1 Notes Min 0 -- 100 5 Typ -- 1 -- -- Max -- -- -- -- Unit -- s ms ns 2 t5 5 -- -- ns t6 t7 t8 10 10 33 -- -- -- 11 11 -- ms ms ms Notes: 1. This parameter is dependent on the 32-kHz oscillator startup time, which is dependent on the characteristics of the crystal, leakage and capacitive coupling on the board, and ambient temperature. 2. This parameter ensures that the internal RTC valid status bit is cleared to indicate that the RTC time and CMOS contents are invalid. 3. This parameter must be met to ensure that the RTC date and time are not invalidated. ElanTMSC520 Microcontroller Data Sheet 59 PRELIMINARY VCC_RTC t1 All other VCCs t2 t4 t5 PWRGOOD CFGx, RSTLDx, DEBUG_ENTER, INST_TRCE, AMDEBUG_DIS t3 BBATSEN t6 GPRESET t7 RST Figure 26. Power-Up Timing Sequence PWRGOOD 2.5 V 2.0 V VCC1 t8 32 kHz Notes: 2. Applies to all VCCs except for VCC_RTC, which is left on for this mode. 3. These timings apply only when powering down the chip while leaving only the RTC powered. 4. Guarantees at least one rising edge on the 32-kHz signal after reset before 2 V is reached. Figure 27. PWRGOOD Timing for RTC Standalone Mode 60 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY Reset Timing with Power Applied Advance Information Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 Parameter Description PWRGOOD inactive pulse width CFGx, RSTLDx setup to PWRGOOD active CFGx, RSTLDx hold from PWRGOOD active PWRGOOD inactive to GPRESET, RST outputs active PWRGOOD active to GPRESET, RST outputs inactive PRGRESET active pulse width PRGRESET active to GPRESET, RST outputs active PRGRESET inactive to GPRESET, RST outputs inactive Reset outputs (GPRESET, RST) active pulse width for internally generated system reset 1 Notes Min 20 5 5 -- 10 40 90 10 10 Max -- -- -- 20 -- -- 1000 -- 11 Unit ns ns ns ns ms ns ns ms ms Notes: 1. Internal system reset sources include software system reset (SYS_RST bit), AMDebug interface system reset, and watchdog timer reset. t1 t2 t3 PWRGOOD CFGx, RSTLDx t4 GPRESET t4 RST t5 t5 Figure 28. External System Reset Timing with Power Applied ElanTMSC520 Microcontroller Data Sheet 61 PRELIMINARY t6 PRGRESET t7 GPRESET t7 RST t8 t8 Figure 29. PRGRESET Timing t9 GPRESET t9 RST Figure 30. Internal System Reset Timing 62 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY ROM Timing Advance Information Symbol t1 t2 t3 t4 t5 t6 t7 t8 Parameter Description1 GPA25-GPA4, chip select setup before ROMBUFOE, ROMRD, GPA3-GPA0 active GPA25-GPA4, chip select active pulse-width read access Read data valid required from GPA3-GPA0, ROMRD and ROMBUFOE, non-page-mode access Read data valid from GPA3-GPA0, page-mode access Read data hold from address, chip select, ROMRD, and ROMBUFOE GPA25-GPA0, chip select hold time from ROMBUFOE, ROMRD read access ROMBUFOE, ROMRD read recovery time GPA3-GPA0 valid, first access 2 2 Notes Min 10 (PFWS + 1) * 303 -- -- 0 0 25 ((PFWS + 1) * 303) - 5 ((PFWS + 1) * 303) - 5 ((PSWS + 1) * 303) - 5 25 Max -- -- ((PFWS + 1) * 303) - 20 ((PSWS + 1) * 303) - 20 -- -- -- -- Unit ns ns ns ns ns ns ns ns 2 4 t9 GPA3-GPA0 valid time, non-page-mode access 2 -- ns t10 t11 t12 t13 t14 t15 t16 GPA3-GPA0 valid time, page-mode access GPA25-GPA0, chip select setup to ROMBUFOE, FLASHWR active GPA25-GPA0 valid, chip select active pulse-width write access Write data valid setup to ROMBUFOE, FLASHWR GPA25-GPA0, chip select hold time from ROMBUFOE, FLASHWR write access Write data hold time from ROMBUFOE, FLASHWR write access ROMBUFOE, FLASHWR write recovery time 4 -- -- -- -- -- -- -- ns ns ns ns ns ns ns 2 (PFWS + 2) * 303 15 15 15 45 Notes: 1. Chip Select includes BOOTCS, ROMCS1, and ROMCS2. 2. PFWS represents the programmable first wait state timing parameter in the ROM controller register for the corresponding ROM chip select. 3. The value of 30 corresponds to the 33-MHz crystal frequency and assumes 33.333 MHz. 4. PSWS represents the programmable subsequent wait state timing parameter in the ROM controller register for the corresponding ROM chip select. ElanTMSC520 Microcontroller Data Sheet 63 PRELIMINARY t2 GPA25-GPA4, Chip Select t8 GPA3-GPA0 t1 ROMBUFOE t1 ROMRD t3 t3 DATA (In) t5 t5 t5 t3 t7 t7 t9 t6 Notes: 1. Chip select includes BOOTCS, ROMCS1, and ROMCS2. 2. Data includes GPD15-GPD0 or MD31-MD0. Figure 31. Non-Burst ROM Read Cycle Timing t2 GPA25-GPA4, Chip Select t8 GPA3-GPA0 t1 ROMBUFOE t1 ROMRD t4 t3 DATA (In) t5 t5 t5 t4 t7 t7 t10 t6 Notes: 1. Chip select includes BOOTCS, ROMCS1, and ROMCS2. 2. Data includes GPD15-GPD0 or MD31-MD0. Figure 32. Page-Mode ROM Read Cycle Timing 64 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY t12 GPA25-GPA0, Chip Select t11 ROMBUFOE t11 t13 FLASHWR t15 t16 t14 t16 DATA (Out) Notes: 1. Chip select includes BOOTCS, ROMCS1, and ROMCS2. 2. Data includes GPD15-GPD0 or MD31-MD0. Figure 33. Flash Write Cycle Timing PCI Bus Timing The characteristics of the PCI interface pins are specified in the PCI Local Bus Specification, Revision 2.2, section 4.2.1.1 DC Specifications, Table 4-1: DC Specifications for 5V Signaling, and section 4.2.2.1 DC Specifications, Table 4-3: DC Specifications for 3.3V Signaling. ElanTMSC520 Microcontroller Data Sheet 65 PRELIMINARY SDRAM Timing Parameter Name Parameter Description TRC TRAS TRCD TRP TDPL TCKH TCKL TCK TCS TCH TAC TDH THZ TLZ TT TDS TDH TAS TAH Refresh active to active command period TRC Active command to precharge command period TRAS Active command to column command same bank TRCD Precharge command to active command period TRP Write recovery or data-in to precharge lead time TDPL CK High pulse width TCKH CK Low pulse width TCKL CK period TCK Command setup TCS Command hold TCH Access time from CK TAC Data-in (read) hold time TDH CK to data-out high-impedance THZ CK to data-out low-impedance TLZ Transition time of CK, rise and fall TT Data-out (write) setup time TDS Data-out hold time TDH Address setup time TAS Address hold time TAH 2 Advance Information Notes Min 1351 751 301 301 301 7 7 151 5 2 12 2 15 0 1 3 2 5 2 Max -- 7500 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 Notes: 1. Corresponds to the 33-MHz crystal frequency and assumes 33.333 MHz with no guardband. 2. This access time is based on the clock period assuming minimal delay between the CLKMEMOUT output and the CLKMEMIN input. It does not take into account external delays for clock buffering/skew, clock loading/routing, and data loading/routing. The delays that the system designer must take into consideration are identified by the equation below: TAC + TSKEW + TCK_LD + TD_LD <= TCK where: TAC = Access time of SDRAM device (not impacted by board design) TSKEW = Delay between CLKMEMOUT to CLKMEMIN TCK_LD = Additional clock delay due to loading TD_LD = Data delay due to loading TCK = SDRAM memory clock = 15 ns (assumes 33.333 MHz crystal) 66 ElanTMSC520 Microcontroller Data Sheet CLKMEMIN t6 t7 t8 MA column bank t18 row t19 t5 t9 CMD1 write prechrg t10 t13 t14 MD4 data t16 data out t17 t113 data in t12 t4 t3 column bank row column t15 t2 ElanTMSC520 Microcontroller Data Sheet 67 PRELIMINARY active write prechrg 2 active read write precharge row active write precharge row active read Notes: 1. CMD applies to SRAS, SCAS, BA0, BA1, SWE, SCSx, and SDQM. 2. Prechrg is an abbreviation for precharge. 3. t11 is shown for CAS latency = 2. 4. MD includes all SDRAM data lines and all MECC lines. 5. Parameter t1 (TRC) is not shown. Figure 34. SDRAM Write and Read Timing PRELIMINARY SDRAM Clock Timing Symbol t1 t2 t3 t4 Parameter Description CLKMEMOUT period CLKMEMOUT High time CLKMEMOUT Low time CLKMEMIN delay rising from CLKMEMOUT rising Notes 1 1 1 Advance Information Min Max 14 -- 7 -- 7 -- -0.5 6 Unit ns ns ns ns Notes: 1. This parameter is based on a PLL, 2x multiplier of the frequency of the 33-MHz crystal. The value is affected by the chosen frequency of the crystal (33.000 MHz or 33.333 MHz). t1 t2 t4 CLKMEMOUT CLKMEMIN t3 Figure 35. SDRAM Clock Timing 68 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY GP Bus Timing1 Advance Information Symbol t1 t2 t2a t3 t4 t5 t6 t7 t11 t12 t13 t14 t15 Parameter Description Setup, GPA, GPBHE stable to command assertion, 8/16-bit I/O and memory access Setup, GPIOCS16, GPMEMCS16 asserted to programmed command deassertion Delay, GPIOCS16, GPMEMCS16 hold from programmed command deassertion Command pulse width, GPIOWR, GPMEMWR, GPIORD, GPIOWR, 8/16-bit cycles GPA, GPBHE hold from command deassertion Setup, GPRDY deasserted to programmed command deassertion GPRDY pulse width Command High (deassertion) time Setup, GPD to write command assertion Hold, GPD from write command deassertion Setup, GPD stable to read command deassertion Hold, GPD from read command deassertion Setup, GPA, GPBHE stable to GPALE falling edge 2,4 4 Notes 2 Min ((OFFS+1) * 303) - 5 45 0 ((PW + 1) * 303) - 5 25 45 303 85 ((OFFS+1) * 303) - 15 25 10 0 (OFFS + PW+2) * 303 - 10 ((PW + 1) * 303) - 5 ((OFFS+1) * 303) - 15 Max -- -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 6 t16 t17 t207 t217 t227 t27 t45 t46 GPALE pulse width Setup, GPAEN Low to GPIORD/GPIOWR assertion (echo mode) Setup, GPA, GPBHE stable to GPCS Hold, GPA, GPBHE stable from GPCS Pulse width, GPCS Hold, GPAEN to GPIORD/GPIOWR deassertion (echo mode) Setup, GPDBUFOE assertion to command assertion Hold, GPDBUFOE assertion from command assertion 4 -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns 2 8 (OFFS+1) * 303 - 5 (RCOV+1) * 303 - 5 ((PW + 1) * 303) - 5 25 ((OFFS+1) * 303) - 15 4 5 5 25 Notes: 1. If the GPCS7-GPCS0 signals are internally qualified with the command, the GPCS7-GPCS0 and command pads switch simultaneously. GPCSx may deassert prior to the deassertion of the command. 2. OFFS represents the programmable offset timing parameter for the corresponding pin. 3. The 30 corresponds to the 33-MHz crystal frequency and assumes 33.333 MHz. 4. PW represents the programmable pulse width parameter for the corresponding pin. 5. This can be increased based on the programmed chip-select offset and pulse width along with its recovery time. 6. This parameter must be met to ensure that a cycle is extended by GPRDY. 7. This parameter assumes that the GPCS7-GPCS0 signals are not internally qualified with the command. 8. RCOV represents the programmable recovery time for the chip selects. ElanTMSC520 Microcontroller Data Sheet 69 PRELIMINARY GPA25-GPA0, GPBHE t20 GPCS7-GPCS0 GPALE GPIOWR/GPMEMWR GPIORD/GPMEMRD t2 GPIOCS16/GPMEMCS16 t5 t t6 t11 t12 t13 t45 GPDBUFOE GPAEN t17 t46 t27 t45 t17 t14 t46 t27 t2a t15 t16 t1 t3 t4 t4 t7 t21 t20 t22 t15 t16 t21 t22 t1 t2 t3 GPRDY GPD15-GPD0 (Write) GPD15-GPD0 (Read) t5 t6 Figure 36. GP Bus Non-DMA Cycle Timing 70 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY GP Bus DMA Read Cycle Timing Advance Information Symbol TCLK t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 Parameter Description GP-DMA clock cycle GPDRQ asserted to GPDACK assertion GPDACK asserted to GPAEN and GPDBUFOE assertion GPD setup time for GPIOWR, GPMEMWR for non-compressed and non-extended write mode GPDACK asserted to GPIOWR, GPMEMWR assertion GPIOWR, GPMEMWR pulse width GPDACK asserted to GPTC assertion GPTC pulse width GPAEN and GPDBUFOE deasserted from command deasserted GPDRQ deasserted from GPDACK assertion GPDACK deasserted from command deasserted GPD hold from GPIOWR, GPMEMWR GPD setup time for GPIOWR, GPMEMWR for compressed or extended write mode Min 58 2 1 20 3.5 1 3.5 1.5 1 0 1 0.5 0.5 Max 244 -- -- -- -- -- -- -- -- -- -- -- -- Unit ns TCLK TCLK ns TCLK TCLK TCLK TCLK TCLK ns TCLK TCLK TCLK t9 GPDRQ t1 GPDACK t2 GPAEN GPDBUFOE GPD15-GPD0 t12 t3 t4 GPIOWR, GPMEMWR t6 GPTC t7 t5 t11 t8 t10 Figure 37. GP-DMA Read Cycle Timing ElanTMSC520 Microcontroller Data Sheet 71 PRELIMINARY GP Bus DMA Write Cycle Timing Advance Information Symbol TCLK t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 Parameter Description GP-DMA clock cycle GPDRQ to GPDACK assertion GPDACK asserted to GPAEN and GPDBUFOE assertion GPIORD, GPMEMRD asserted to GPD valid GPDACK asserted to GPIORD, GPMEMRD assertion GPIORD, GPMEMRD pulse width GPDACK asserted to GPTC assertion GPTC pulse width GPAEN and GPDBUFOE deasserted from command deasserted GPDRQ deasserted from GPDACK assertion GPDACK deasserted from command deasserted GPIORD, GPMEMRD deasserted to GPD invalid Min 58 2 1 -- 2.5 1.5 3.5 1.5 1 0 1 0 Max 244 -- -- 0.5 -- -- -- -- -- -- -- -- Unit ns TCLK TCLK TCLK TCLK TCLK TCLK TCLK TCLK ns TCLK ns t9 GPDRQ t1 GPDACK t2 GPAEN GPDBUFOE t3 GPD15-GPD0 t4 GPIORD, GPMEMRD t6 GPTC t7 t5 t11 t8 t10 Figure 38. GP-DMA Write Cycle Timing 72 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY SSI Timing Advance Information Symbol t1 t2 t3 t4 t5 t6 t7 t8 Parameter Description SSI_CLK period SSI_CLK High time SSI_CLK Low time SSI_DI setup time to sample edge SSI_DI hold time from sample edge SSI_DO hold time from assert edge SSI_DO setup to sample edge SSI_DO high impedance from sample edge of last bit 2 2 2 2,3 2,3 Notes 1 Min 110 55 55 3 3 0 (0.5 TCLK) - 5 0.5 TCLK Max -- -- -- -- -- -- -- (0.5 TCLK) + 5 Unit ns ns ns ns ns ns ns ns Notes: 1. The clock period for the SSI interface is programmable as a divisor of the 33-MHz crystal input. Rates provided are binary multiples from divide by 4 (~110 ns) to divide by 512 (~15526 ns). The actual period is affected by the frequency of the crystal (33.000 MHz or 33.333 MHz). 2. The sample/assert clock edge for the SSI interface is programmable. 3. TCLK refers to the programmed period for the SSI_CLK pin. t1 t2 t7 SSI_CLK t4 SSI_DI t6 SSI_DO t6 t8 t5 t3 Notes: Asserted on rising edge, sampled on falling edge. Figure 39. SSI Timing ElanTMSC520 Microcontroller Data Sheet 73 PRELIMINARY JTAG Timing Advance Information Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 Parameter Description JTAG_TRST active pulse width JTAG_TCK period JTAG_TCK High time JTAG_TCK Low time JTAG_TMS, JTAG_TDI setup time JTAG_TMS, JTAG_TDI hold time JTAG_TDO delay Input pin setup time Input pin hold time Output pin delay Min 20 40 15 15 5 10 -- 15 15 -- Max -- -- -- -- -- -- 10 -- -- 15 Unit ns ns ns ns ns ns ns ns ns ns t1 JTAG_TRST t2 t3 JTAG_TCK t5 JTAG_TMS t5 JTAG_TDI t7 JTAG_TDO t8 Input Pin t10 Output Pin t9 t6 t6 t4 Figure 40. JTAG Boundary Scan Timing 74 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY APPENDIX A PIN TABLES This appendix contains pin tables for the ELANSC520 microcontroller. Several different tables are included with the following characteristics: s Multiplexed signal tradeoffs--Table 16 on For pin tables showing pins sorted by pin number and signal name, respectively, see "Pin Designations (Pin Number)" on page 11 and "Pin Designations (Pin Name)" on page 13. For signal descriptions, see Table 2, "Signal Descriptions" on page 17. In all tables the brackets, [ ], indicate alternate, multiplexed functions, and braces, { }, indicate reset configuration pins (pinstraps). The line over a pin name indicates an active Low signal. The word pin refers to the physical wire; the word signal refers to the electrical signal that flows through it. page A-2. s Programmable I/O pins ordered by PIO pin number and multiplexed signal name, respectively, including a column showing pin configurations following system reset--Table 17 on page A-4 and Table 18 on page A-5. s Pin summary showing signal name and alternate function, pin number, I/O type, termination, reset state, output drive, and maximum load--Table 20 on page A-7. ElanTMSC520 Microcontroller Data Sheet A-1 PRELIMINARY Table 16. Signal You Want ROM/Flash Control ROMCS1 ROMCS2 GP Bus GPAEN GPALE GPBHE GPCS0 GPCS1 GPCS2 GPCS3 GPCS4 GPCS5 GPCS6 GPCS7 GPDACK0 GPDACK1 GPDACK2 GPDACK3 GPDBUFOE GPDRQ0 GPDRQ1 GPDRQ2 GPDRQ3 GPIOCS16 GPIRQ0 GPIRQ1 GPIRQ2 GPIRQ3 GPIRQ4 GPIRQ5 GPIRQ6 GPIRQ7 GPIRQ8 GPIRQ9 GPIRQ10 GPMEMCS16 GPRDY GPTC Serial Ports CTS2 DCD2 DSR2 RIN2 PIO28 PIO30 PIO29 PIO31 AF4 AE3 AF3 AD3 PIO3 PIO0 PIO1 PIO27 ROMCS1 ROMCS2 PITGATE2 TMRIN1 TMRIN0 TMROUT1 TMROUT0 PIO12 PIO11 PIO10 PIO9 PIO24 PIO8 PIO7 PIO6 PIO5 PIO25 PIO23 PIO22 PIO21 PIO20 PIO19 PIO18 PIO17 PIO16 PIO15 PIO14 PIO13 PIO26 PIO2 PIO4 AE11 AE12 AF12 AE4 B24 C23 AC21 AA24 AC20 AC23 AD23 AC8 AC9 AD9 AE9 AD5 AF9 AF10 AE10 AD10 AC4 AE5 AF5 AF6 AE6 AD6 AD7 AE7 AF7 AF8 AE8 AD8 AD4 AF11 AD11 GPCS1 GPCS2 B24 C23 Multiplexed Signal Trade-Offs Signal You Give Up Pin # A-2 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY Table 16. Clocks CLKTEST CLKTIMER Timers PITGATE2 TMRIN0 TMRIN1 TMROUT0 TMROUT1 System Test CF_DRAM CF_ROM_GPCS DATASTRB WBMSTR0 WBMSTR1 WBMSTR2 WBMSTR2 WBMSTR0 WBMSTR1 CF_ROM_GPCS DATASTRB CF_DRAM W24 AD20 AC24 AD20 AC24 W24 GPCS3 GPCS5 GPCS4 GPCS7 GPCS6 AC21 AC20 AA24 AD23 AC23 CLKTIMER CLKTEST A7 A7 Multiplexed Signal Trade-Offs (Continued) Signal You Give Up Pin # Signal You Want Configuration Pins (Pinstraps)--See "Configuration" on page 26. Programmable I/O PIO0 PIO1 PIO2 PIO3 PIO4 PIO5 PIO6 PIO7 PIO8 PIO9 PIO10 PIO11 PIO12 PIO13 PIO14 PIO15 PIO16 PIO17 PIO18 PIO19 PIO20 PIO21 PIO22 PIO23 PIO24 PIO25 PIO26 PIO27 GPALE GPBHE GPRDY GPAEN GPTC GPDRQ3 GPDRQ2 GPDRQ1 GPDRQ0 GPDACK3 GPDACK2 GPDACK1 GPDACK0 GPIRQ10 GPIRQ9 GPIRQ8 GPIRQ7 GPIRQ6 GPIRQ5 GPIRQ4 GPIRQ3 GPIRQ2 GPIRQ1 GPIRQ0 GPDBUFOE GPIOCS16 GPMEMCS16 GPCS0 AE12 AF12 AF11 AE11 AD11 AD10 AE10 AF10 AF9 AE9 AD9 AC9 AC8 AD8 AE8 AF8 AF7 AE7 AD7 AD6 AE6 AF6 AF5 AE5 AD5 AC4 AD4 AE4 ElanTMSC520 Microcontroller Data Sheet A-3 PRELIMINARY Table 17. PIO (Default Function) PIO0 PIO1 PIO2 PIO3 PIO4 PIO5 PIO6 PIO7 PIO8 PIO9 PIO10 PIO11 PIO12 PIO13 PIO14 PIO15 PIO16 PIO17 PIO18 PIO19 PIO20 PIO21 PIO22 PIO23 PIO24 PIO25 PIO26 PIO27 PIO28 PIO29 PIO30 PIO31 Pin # AE12 AF12 AF11 AE11 AD11 AD10 AE10 AF10 AF9 AE9 AD9 AC9 AC8 AD8 AE8 AF8 AF7 AE7 AD7 AD6 AE6 AF6 AF5 AE5 AD5 AC4 AD4 AE4 AF4 AF3 AE3 AD3 PIOs Sorted by PIO Number Multiplexed Signal GPALE GPBHE GPRDY GPAEN GPTC GPDRQ3 GPDRQ2 GPDRQ1 GPDRQ0 GPDACK3 GPDACK2 GPDACK1 GPDACK0 GPIRQ10 GPIRQ9 GPIRQ8 GPIRQ7 GPIRQ6 GPIRQ5 GPIRQ4 GPIRQ3 GPIRQ2 GPIRQ1 GPIRQ0 GPDBUFOE GPIOCS16 GPMEMCS16 GPCS0 CTS2 DSR2 DCD2 RIN2 Pin Configuration Following System Reset Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pulldown Input with pulldown Input with pulldown Input with pulldown Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup A-4 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY Table 18. PIOs Sorted by Signal Name Multiplexed Signal CTS2 DCD2 DSR2 GPAEN GPALE GPBHE GPCS0 GPDACK0 GPDACK1 GPDACK2 GPDACK3 GPDBUFOE GPDRQ0 GPDRQ1 GPDRQ2 GPDRQ3 GPIOCS16 GPIRQ0 GPIRQ1 GPIRQ10 GPIRQ2 GPIRQ3 GPIRQ4 GPIRQ5 GPIRQ6 GPIRQ7 GPIRQ8 GPIRQ9 GPMEMCS16 GPRDY GPTC RIN2 PIO (Default Function) PIO28 PIO30 PIO29 PIO3 PIO0 PIO1 PIO27 PIO12 PIO11 PIO10 PIO9 PIO24 PIO8 PIO7 PIO6 PIO5 PIO25 PIO23 PIO22 PIO13 PIO21 PIO20 PIO19 PIO18 PIO17 PIO16 PIO15 PIO14 PIO26 PIO2 PIO4 PIO31 Pin Configuration Pin # Following System Reset Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pulldown Input with pulldown Input with pulldown Input with pulldown Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup AF4 AE3 AF3 AE11 AE12 AF12 AE4 AC8 AC9 AD9 AE9 AD5 AF9 AF10 AE10 AD10 AC4 AE5 AF5 AD8 AF6 AE6 AD6 AD7 AE7 AF7 AF8 AE8 AD4 AF11 AD11 AD3 ElanTMSC520 Microcontroller Data Sheet A-5 PRELIMINARY Pin List Summary Table Column Definitions The following paragraphs describe the individual columns of information in Table 20, "Pin List Summary," on page A-7. The pins are grouped alphabetically by function. Table 19. Type Pin List Summary Table Abbreviations Definition None or not applicable. Brackets signify a programmable alternate state. Reset configuration pin. These are the configuration pins latched during reset. Used in the Reset State column to indicate signals active during reset. Pin is an analog input. Bidirectional. Driven High (a logical 1). Pin is an input. Input or open-drain output. Driven Low (a logical 0). Used in the Reset State column to indicate a signal latched on reset. Not applicable. Pin is an active output. Open-drain output. Oscillator. Built-in pulldown resistor (~100-150 kW). Power pins. Built-in pullup resistor (~100-150 kW). Pin is a Schmitt trigger input. Sustained three-state (PCI drive). Three-state output. -- [] {} Active Analog B H I IOD L Latched NA O OD Osc PD Power PU STI STS TS Column #1--Signal Name, [Alternate Function], {Pinstrap} This column denotes the primary and alternate functions of the pins. Brackets, [ ], are used to indicate the alternate, multiplexed function of a pin. Braces, { }, are used to indicate the functionality of a pin only during a processor reset. These signals are called pinstraps. For pinstraps, see "Configuration" on page 26. Column #2--Pin # The pin number column identifies the pin number of the individual I/O signal on the package. Column #3--Type Definitions of the abbreviations in the Type column are shown in Table 19. Column #4--Termination The Termination column specifies the presence of pullups or pulldowns on the pins. Column #5--Reset State Definitions of the abbreviations in the Reset State column are shown in Table 19. Column #6--Output Drive The Output Drive column shows the output amperage. Column #7--Max Load (pF) The Max Load column designates the capacitive load at which the I/O timing for that pin is guaranteed. Column #8--Note The Note column shows footnote numbers. A-6 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY Table 20. Signal Name [Alternate Function] {Pinstrap} SDRAM BA0 BA1 CLKMEMIN CLKMEMOUT MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 T25 U25 A4 B19 L25 L26 M26 M25 N25 N26 P26 P25 R25 R26 T26 U26 V26 B7 A8 B9 A10 B11 A12 B13 A14 B15 A16 B17 A18 B20 A21 A22 B23 B8 A9 B10 A11 B12 A13 B14 A15 O O I O O O O O O O O O O O O O O B B B B B B B B B B B B B B B B B B B B B B B B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- H H I Active H H H H H H H H H H H H H I I I I I I I I I I I I I I I I I I I I I I I I 12/18/24 mA 12/18/24 mA -- 24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 50 pF 50 pF -- 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF Pin # Type Pin List Summary Reset State Output Drive Max Load (pF) Termination ElanTMSC520 Microcontroller Data Sheet A-7 PRELIMINARY Table 20. Pin List Summary (Continued) Signal Name [Alternate Function] {Pinstrap} MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 MECC0 MECC1 MECC2 MECC3 MECC4 MECC5 MECC6 SCASA SCASB SCS0 SCS1 SCS2 SCS3 SDQM0 SDQM1 SDQM2 SDQM3 SRASA SRASB SWEA SWEB ROM/Flash Control BOOTCS FLASHWR ROMBUFOE ROMCS1 [GPCS1] ROMCS2 [GPCS2] ROMRD PCI Bus AD0 AD1 AD2 AD3 AC2 AC1 AB1 AB2 STS-B STS-B STS-B STS-B -- -- -- -- L L L L -- -- -- -- -- -- -- -- AB25 AB24 AA25 B24 C23 AB23 O O O O [O] O [O] O -- -- -- -- -- -- H H H H H H 12 mA 24 mA 12 mA 12 mA 12 mA 24 mA 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF Pin # B16 A17 B18 A19 A20 B21 A23 A24 C25 D26 W26 Y25 C26 D25 Y26 F25 F26 V25 W25 J25 J26 G25 H26 G26 H25 K25 K26 E26 E25 Type B B B B B B B B B B B B B B B O O O O O O O O O O O O O O Termination -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reset State I I I I I I I I I I I I I I I H H H H H H H H H H H H H H Output Drive 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18 mA 12/18 mA 12/18 mA 12/18 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA 12/18/24 mA Max Load (pF) 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF A-8 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY Table 20. Pin List Summary (Continued) Signal Name [Alternate Function] {Pinstrap} AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 CBE0 CBE1 CBE2 CBE3 CLKPCIIN CLKPCIOUT DEVSEL FRAME GNT0 GNT1 GNT2 GNT3 GNT4 INTA Pin # AA2 AA1 Y1 Y2 W1 V1 V2 U2 U1 T1 T2 R2 K2 J2 J1 H1 H2 G2 G1 F1 E2 E1 D1 D2 B2 B1 A1 A2 W2 R1 K1 F2 G3 A6 M1 L1 M3 N4 P3 T3 U4 K3 Type STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B I O STS-B STS-B O O O O O I Termination -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reset State L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L I Active TS TS TS TS TS TS TS I Output Drive -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max Load (pF) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ElanTMSC520 Microcontroller Data Sheet A-9 PRELIMINARY Table 20. Pin List Summary (Continued) Signal Name [Alternate Function] {Pinstrap} INTB INTC INTD IRDY PAR PERR REQ0 REQ1 REQ2 REQ3 REQ4 RST SERR STOP TRDY GP Bus GPA0 GPA1 GPA2 GPA3 GPA4 GPA5 GPA6 GPA7 GPA8 GPA9 GPA10 GPA11 GPA12 GPA13 GPA14 GPA15 {RSTLD0} GPA16 {RSTLD1} GPA17 {RSTLD2} GPA18 {RSTLD3} GPA19 {RSTLD4} GPA20 {RSTLD5} J24 G4 K24 J23 L24 H24 C1 F23 M24 C2 M23 N23 N24 P24 R24 C24 D24 E24 B22 C21 C14 O O O O O O O O O O O O O O O O {I} O {I} O {I} O {I} O {I} O {I} -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PD PD PD PD PD PD H H H H H H H H H H H H H H H Latched Latched Latched Latched Latched Latched 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF Pin # J3 H3 H4 L2 P1 N2 L3 N3 P4 R3 U3 A5 P2 N1 M2 Type I I I STS-B STS-B STS-B I I I I I O STS-I STS-B STS-B Termination -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reset State I I I TS L TS I I I I I L TS TS TS Output Drive -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max Load (pF) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- A-10 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY Table 20. Pin List Summary (Continued) Signal Name [Alternate Function] {Pinstrap} GPA21 {RSTLD6} GPA22 {RSTLD7} GPA23 {AMDEBUG_DIS} GPA24 {INST_TRCE} GPA25 {DEBUG_ENTER} GPD0 GPD1 GPD2 GPD3 GPD4 GPD5 GPD6 GPD7 GPD8 GPD9 GPD10 GPD11 GPD12 GPD13 GPD14 GPD15 GPIORD GPIOWR GPMEMRD GPMEMWR GPRESET PIO0 [GPALE] PIO1 [GPBHE] PIO2 [GPRDY] PIO3 [GPAEN] PIO4 [GPTC] PIO5 [GPDRQ3] PIO6 [GPDRQ2] Pin # C19 F3 D3 D4 C3 C4 B5 C7 C8 C9 D9 D10 C10 C11 C12 C13 D13 D14 C15 C17 D17 G24 C16 F24 C18 AC22 AE12 AF12 AF11 AE11 AD11 AD10 AE10 Type O {I} O {I} O {I} O {I} O {I} B B B B B B B B B B B B B B B B O O O O O B [O] B [O] B [STI] B [O] B [O] B [I] B [I] Termination PD PD PD PD PD PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU -- -- -- -- -- PU PU PU PU PU PD PD Reset State Latched Latched Latched Latched Latched I I I I I I I I I I I I I I I I H H H H H I I I I I I I Output Drive 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 6 mA 6 mA 6 mA 6 mA 6 mA 6 mA 6 mA 6 mA Max Load (pF) 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 30 pF 30 pF 30 pF 30 pF 30 pF 30 pF 30 pF ElanTMSC520 Microcontroller Data Sheet A-11 PRELIMINARY Table 20. Pin List Summary (Continued) Signal Name [Alternate Function] {Pinstrap} PIO7 [GPDRQ1] PIO8 [GPDRQ0] PIO9 [GPDACK3] PIO10 [GPDACK2] PIO11 [GPDACK1] PIO12 [GPDACK0] PIO13 [GPIRQ10] PIO14 [GPIRQ9] PIO15 [GPIRQ8] PIO16 [GPIRQ7] PIO17 [GPIRQ6] PIO18 [GPIRQ5] PIO19 [GPIRQ4] PIO20 [GPIRQ3] PIO21 [GPIRQ2] PIO22 [GPIRQ1] PIO23 [GPIRQ0] PIO24 [GPDBUFOE] PIO25 [GPIOCS16] PIO26 [GPMEMCS16] PIO27 [GPCS0] Serial Ports CTS1 DCD1 DSR1 DTR1 DTR2 V3 V4 Y3 W3 AE23 I I I O O PU PU PU -- -- I I I H H -- -- -- 6 mA 6 mA -- -- -- 30 pF 30 pF Pin # AF10 AF9 AE9 AD9 AC9 AC8 AD8 AE8 AF8 AF7 AE7 AD7 AD6 AE6 AF6 AF5 AE5 AD5 AC4 AD4 AE4 Type B [I] B [I] B [O] B [O] B [O] B [O] B [I] B [I] B [I] B [I] B [I] B [I] B [I] B [I] B [I] B [I] B [I] B [O] B [STI] B [STI] B [O] Termination PD PD PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU Reset State I I I I I I I I I I I I I I I I I I I I I Output Drive 6 mA 6 mA 6 mA 6 mA 6 mA 6 mA 6 mA 6 mA 6 mA 6 mA 6 mA 6 mA 6 mA 6 mA 6 mA 6 mA 6 mA 6 mA 6 mA 6 mA 6 mA Max Load (pF) 30 pF 30 pF 30 pF 30 pF 30 pF 30 pF 30 pF 30 pF 30 pF 30 pF 30 pF 30 pF 30 pF 30 pF 30 pF 30 pF 30 pF 30 pF 30 pF 30 pF 30 pF A-12 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY Table 20. Pin List Summary (Continued) Signal Name [Alternate Function] {Pinstrap} PIO28 [CTS2] PIO29 [DSR2] PIO30 [DCD2] PIO31 [RIN2] RIN1 RTS1 RTS2 SIN1 SIN2 SOUT1 SOUT2 SSI_CLK SSI_DI SSI_DO Clocks and Reset 32KXTAL1 32KXTAL2 33MXTAL1 33MXTAL2 CLKTIMER [CLKTEST] LF_PLL1 PRGRESET PWRGOOD JTAG JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST AMDebug Interface BR/TC CMDACK STOP/TX TRIG/TRACE System Test CF_DRAM [WBMSTR2] {CFG2} W24 O [O] {I} PD Latched 6 mA 30 pF AD24 U24 AF17 AC13 I O O O PD -- -- -- I L L L -- 6 mA 6 mA 6 mA -- 30 pF 30 pF 30 pF AD21 AF21 AF22 AE21 AE22 I I O/TS I I PU PU PU PU PD I I TS I I -- -- 6 mA -- -- -- -- 30 pF -- -- AF26 AE26 AB26 AC26 A7 AF24 D20 C20 Osc Osc Osc Osc I [O] Osc STI STI -- -- -- -- PU -- -- -- Active Active Active Active I Active I I -- -- -- -- 18 mA -- -- -- -- -- -- -- 50 pF -- -- -- Pin # AF4 AF3 AE3 AD3 AA3 W4 AD22 AE2 V24 AF2 U23 AD19 AE19 AF19 Type B [I] B [I] B [I] B [I] I O O I I O O O STI OD Termination PU PU PU PU PU -- -- PU PU -- -- -- PU -- Reset State I I I I I H H I I H H H I L Output Drive 6 mA 6 mA 6 mA 6 mA -- 6 mA 6 mA -- -- 6 mA 6 mA 6 mA -- 6 mA Max Load (pF) 30 pF 30 pF 30 pF 30 pF -- 30 pF 30 pF -- -- 30 pF 30 pF 30 pF -- 30 pF ElanTMSC520 Microcontroller Data Sheet A-13 PRELIMINARY Table 20. Pin List Summary (Continued) Signal Name [Alternate Function] {Pinstrap} CF_ROM_GPCS [WBMSTR0] {CFG0} DATASTRB [WBMSTR1] {CFG1} Timers PITGATE2 [GPCS3] PITOUT2 {CFG3} TMRIN0 [GPCS5] TMRIN1 [GPCS4] TMROUT0 [GPCS7] TMROUT1 [GPCS6] Power and Ground BBATSEN GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND B25 L11 L12 L13 L14 L15 L16 M11 M12 M13 M14 M15 M16 N11 N12 N13 N14 N15 N16 P11 P12 P13 P14 P15 P16 Analog Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Latched -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- AC21 Y24 AC20 AA24 AD23 AC23 I [O] O {I} I [O] I [O] O [O] O [O] PU PD PU PU -- -- I Latched I I H H 6 mA 6 mA 6 mA 6 mA 6 mA 6 mA 30 pF 30 pF 30 pF 30 pF 30 pF 30 pF Pin # AD20 Type O [O] {I} O [O] {I} Termination PD Reset State Latched Output Drive 6 mA Max Load (pF) 30 pF AC24 PD Latched 6 mA 30 pF A-14 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY Table 20. Pin List Summary (Continued) Signal Name [Alternate Function] {Pinstrap} GND GND GND GND GND GND GND GND GND GND GND GND GND_ANLG VCC_ANLG VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O Pin # R11 R12 R13 R14 R15 R16 T11 T12 T13 T14 T15 T16 A25 B26 AC14 AC15 AC5 AC6 AC7 D11 D12 D18 D19 E4 F4 G23 H23 P23 R23 R4 T4 AA23 AA4 AC10 AC11 AC18 AC19 D15 D16 D21 D22 D5 Type Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Termination -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reset State -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Output Drive -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max Load (pF) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ElanTMSC520 Microcontroller Data Sheet A-15 PRELIMINARY Table 20. Pin List Summary (Continued) Signal Name [Alternate Function] {Pinstrap} VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_RTC No Connects NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC 1 Pin # D6 D7 D8 J4 K23 K4 L23 L4 M4 V23 W23 Y23 Y4 A26 A3 AA26 AB3 AB4 AC12 AC16 AC17 AC25 AC3 AD1 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD2 AD25 AD26 AE1 AE13 AE14 AE15 AE16 AE17 AE18 Type Power Power Power Power Power Power Power Power Power Power Power Power Power Power -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Termination -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reset State -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Output Drive -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max Load (pF) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- A-16 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY Table 20. Pin List Summary (Continued) Signal Name [Alternate Function] {Pinstrap} NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Pin # AE20 AE24 AE25 AF1 AF13 AF14 AF15 AF16 AF18 AF20 AF23 AF25 B3 B4 B6 C22 C5 C6 D23 E23 E3 T23 T24 Type -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Termination -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reset State -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Output Drive -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max Load (pF) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Notes: 1. The NCs are true "no connects" and should be left disconnected. ElanTMSC520 Microcontroller Data Sheet A-17 PRELIMINARY A-18 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY APPENDIX B PHYSICAL DIMENSIONS 388-Pin Plastic BGA (PBGA) Package Top View 35.00 BSC 29.90 30.10 28.00 BSC A 3X 0.50 R. A1 CORNER A1 CORNER I.D. ENCAPSULATION 35.00 BSC 17.0 X 14.0 MIN FLAT AREA 4.00 X 45 4X 4X .20 TOP SIDE (DIE SIDE) B 0.50 0.70 0.51 0.61 30 TYP 0.15 C 0.15 C C 2.20 2.46 SIDE VIEW 0.15 C A SEATING PLANE DETAIL A SCALE:NONE ElanTMSC520 Microcontroller Data Sheet B-1 PRELIMINARY Bottom View 31.75 BSC (DATUM A) .30 C A B .10 C A1 CORNER A1 CORNER I.D. 0.60 388X 0.90 0.635 BSC 31.75 BSC (DATUM B) 0.635 BSC BOTTOM VIEW 1.27 BSC ALL ROWS AND COLUMNS 16-038-BGA388-2 ET118 10.26.98 lv B-2 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY Circuit Board Layout Considerations There are two basic ways to set up a BGA ball pad, solder-mask defined and solder-pad defined. s Solder-mask defined is when the solder mask opening is smaller than the copper pad, so the solder surface is defined by the solder mask rather than the copper pad. s Solder-pad defined is when the copper pad is board is pad-defined, then a problem can occur where there is more surface area on the board making contact than on the part itself. When the part heats and cools, a different amount of stress is placed on the chip than on the board (because there is more surface area soldered on the board), and the chip can warp. The pad definition on the board should match the chip. The ELANSC520 microcontroller is solder-mask defined, so the circuit board design should be soldermask defined with a solder-mask opening of 0.60 mm over a 0.80-mm pad as shown in Figure 41. smaller than the solder mask, so the solder surface is defined by the copper pad. A problem can occur when you mix these two methods. For example, if the chip is solder-pad defined and the 0.80 mm Copper Pad Exposed Copper Solder Mask Covered Copper 0.60 mm Solder Mask Opening Top View of BGA Pad Solder Mask Copper Pad Printed Circuit Board Side View of BGA Pad Figure 41. BGA Ball Pad Layout ElanTMSC520 Microcontroller Data Sheet B-3 PRELIMINARY B-4 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY APPENDIX C CUSTOMER SUPPORT AMD-K6TME Microprocessor Am5x86 Microprocessor Am486(R)DX Microprocessor Am386(R)SX/DX Microprocessors ElanSC300 Microcontroller Am186CC Communications Controller Am186CH HDLC Microcontroller Am186TMCU USB Microcontroller ElanSC410 Microcontroller AMD-K6TM-2E Microprocessor ELANSC520 Microcontroller ElanSC400 Microcontroller ElanTMSC310 Microcontroller Am186EM and Am188TMEM Microcontrollers Am186EMLV & Am188EMLV Microcontrollers Am186ES and Am188ES Microcontrollers Am186ESLV & Am188ESLV Microcontrollers Am186ER and Am188ER Microcontrollers Am186ED Microcontroller Am186EDLV Microcontroller 80C186 and 80C188 Microcontrollers 80L186 and 80L188 Microcontrollers -- Microprocessors -- 16- and 32-bit microcontrollers -- 16-bit microcontrollers E86TM Family of Embedded Microprocessors and Microcontrollers Table 21. Related AMD Products--E86TM Family Devices Device1 80C186/80C188 80L186/80L188 Am186TMEM/Am188TMEM Am186EMLV/Am188EMLV Am186ES/Am188ES Am186ESLV/Am188ESLV Am186ED Am186EDLV Am186ER/Am188ER Am186CC Am186CH Am186CU ElanSC300 ElanSC310 ElanSC400 ElanSC410 ELANSC520 Am386(R)DX Am386(R)SX Am486(R)DX Amx586(R) AMD-K6TME AMD-K6TM-2E Description 16-bit microcontroller Low-voltage, 16-bit microcontroller High-performance, 16-bit embedded microcontroller High-performance, 16-bit embedded microcontroller High-performance, 16-bit embedded microcontroller High-performance, 16-bit embedded microcontroller High-performance, 80C186- and 80C188-compatible, 16-bit embedded microcontroller with 8- or 16-bit external data bus High-performance, 80C186- and 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8- or 16-bit external data bus High-performance, low-voltage, 16-bit embedded microcontroller with 32 Kbyte of internal RAM High-performance, 16-bit embedded communications controller High-performance, 16-bit embedded HDLC microcontroller High-performance, 16-bit embedded USB microcontroller High-performance, highly integrated, low-voltage, 32-bit embedded microcontroller High-performance, single-chip, 32-bit embedded PC/AT-compatible microcontroller High-performance, single-chip, low-power, PC/AT-compatible microcontroller High-performance, single-chip, PC/AT-compatible microcontroller High-performance, single-chip, 32-bit embedded microcontroller High-performance, 32-bit embedded microprocessor with 32-bit external data bus High-performance, 32-bit embedded microprocessor with 16-bit external data bus High-performance, 32-bit embedded microprocessor with 32-bit external data bus High-performance, 32-bit embedded microprocessor with 32-bit external data bus High-performance, 32-bit embedded microprocessor with 64-bit external data bus High-performance, 32-bit embedded microprocessor with 64-bit external data bus and 3DNow!TM technology Notes: 1. 186 = 16-bit microcontroller and 80C186-compatible (except where noted otherwise); 188 = 16-bit microcontroller with 8-bit external data bus and 80C188-compatible (except where noted otherwise); LV = low voltage ElanTMSC520 Microcontroller Data Sheet C-1 PRELIMINARY Related Documents The following documents contain additional information that will be useful in designing an embedded application based on the ELANSC520 microcontroller. s ElanTMSC520 Microcontroller Register Set Manual, s 80486 System Architecture, Mindshare, Inc., Read- ing, MA: Addison-Wesley, 1995, ISBN 0-20140994-1 s The Indispensable PC Hardware Book, Hans-Peter order #22005, fully describes all the registers required to program the microcontroller. s ElanTMSC520 Microcontroller User's Manual, order Messmer, Wokingham, England: Addison-Wesley, 1995, ISBN 0-201-87697-3. Customer Development Platform The ELANSC520 microcontroller customer development platform (CDP) is provided as a test and development platform to illustrate the capabilities of the ELANSC520 microcontroller using the PCI bus and an on-board 10/100 Mbit/s Ethernet connection. In addition, the CDP serves as a platform for embedded product development using the ELANSC520 microcontroller, Am79C972 Ethernet controller, and the PCI bus. The ELANSC520 microcontroller CDP enables developers to benchmark their embedded, network-ready applications, understand the functionality of the microcontroller, and to know how to wire an ELANSC520 microcontroller system using off-the-shelf components. The CDP board also demonstrates how the embedded PCI bus controller works well with other PCI-ready peripherals. #22004, provides a functional description of the microcontroller for both hardware and software designers. s The Am486(R) Microprocessor Software User's Man- ual, order #18497, includes the complete instruction set for the integrated Am5x86 CPU. Other information of interest: s Am5x86(R) Microprocessor Family Data Sheet, order #19751 s Am486(R) DX/DX2 Microprocessor Hardware Refer- ence Manual, order #17965 s E86 Family Products and Development Tools CD, order #21058, provides a single-source multimedia tool for customer evaluation of AMD products, as well as FusionE86 partner tools and technologies that support the E86TM family. Technical documentation is included on the CD in PDF format. To order literature, contact the nearest AMD sales office or call the literature center at one of the numbers listed on the back cover of this manual. In addition, all these documents are available in PDF form on the AMD web site. To access the AMD home page, go to www.amd.com. Then follow the Embedded Processor link for information about E86 microcontrollers. Third-Party Development Support Products The FusionE86 Program of Partnerships for Application Solutions provides the customer with an array of products designed to meet critical time-to-market needs. Products and solutions available from the AMD FusionE86 partners include protocol stacks, emulators, hardware and software debuggers, board-level products, and software development tools, among others. In addition, mature development tools and applications for the x86 platform are widely available in the general marketplace. Additional Information The following non-AMD documents and sources provide additional information that may be of interest to ELANSC520 microcontroller users: s PCI Local Bus Specification, December 18, 1998, PCI Special Interest Group, 800-433-5177 (US), 503-693-6232 (International), www.pcisig.com. s IEEE Std 1149.1-1990 Standard Test Access Port and Boundar y-Scan Architecture, (order #SH16626-NYF), Institute of Electrical and Electronic Engineers, Inc., 800-678-4333, www.ieee.org. s PCI System Architecture, Mindshare, Inc., Reading, MA: Addison-Wesley, 1995, ISBN 0-201-40993-3. s ISA System Architecture, Mindshare, Inc., Reading, MA: Addison-Wesley, 1995, ISBN 0-201-40996-8. C-2 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY Customer Service The AMD customer service network includes U.S. offices, international offices, and a customer training center. Expert technical assistance is available from the AMD worldwide staff of field application engineers and factory support staff to answer E86 and Comm86 family hardware and software development questions. Hotline and World Wide Web Support For answers to technical questions, AMD provides e-mail support as well as a toll-free number for direct access to our corporate applications hotline. The AMD World Wide Web home page provides the latest product information, including technical information and data on upcoming product releases. In addition, EPD CodeKit software on the Web site provides tested source code example applications. Corporate Applications Hotline (800) 222-9323 44-(0) 1276-803-299 Toll-free for U.S. and Canada U.K. and Europe hotline World Wide Web Home Page To access the AMD home page go to: www.amd.com. Then follow the Embedded Processors link for information about E86 family and Comm86TM products. Questions, requests, and input concerning AMD's WWW pages can be sent via e-mail to web.feedback@amd.com. Documentation and Literature Free information such as data books, user's manuals, data sheets, application notes, the E86TM Family Products and Development Tools CD, order #21058, and other literature is available with a simple phone call. Internationally, contact your local AMD sales office for product literature, or go to www.amd.com/support/literature.html. Additional contact information is listed on the back of this data sheet. Literature Ordering (800) 222-9323 Toll-free for U.S. and Canada Additional contact information is listed on the back of this datasheet. For technical support questions on all E86 and Comm86 products, send e-mail to epd.support@amd.com. ElanTMSC520 Microcontroller Data Sheet C-3 PRELIMINARY C-4 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY INDEX A a20 gate, 32 address mapping, 31 AMDebug technology description, 30 parallel, 30 pin summary, A-13 serial, 30 signal descriptions, 23 applications description, 33 digital set top box, 36 Smart Residential Gateway, 34 thin client, 35 architecture overview, 28 x86 instruction set, 30 B block diagram, 29 bootstraps See configuration. C capacitance crystal, 51 derating curves, 51 non-PCI interface, 51 PCI interface, 51 chip select GP bus signal description, 24 circuit board layout, B-3 clock 32.768-kHz crystal selection, 41 33.333-MHz crystal speed, 43 33-MHz crystal selection, 42 backup battery, 46 circuit diagrams, 46 block diagram of clock source, 39 bypassing internal oscillators, 44 circuit with backup battery, 47 circuit without backup battery, 47 control, 38 crystal selection, 41 crystal speeds, 38 generation and control, 38 internal, 39 multiplexed signal trade-offs, A-3 not using backup battery, 46 overview, 31 pin loading, 40 pin summary, A-13 real-time clock (RTC) voltage monitor, 45 RTC voltage monitor block diagram, 45 RTC voltage monitor specifications, 46 SDRAM clock timing, 68 signal descriptions, 22 specifications, 40 system clock block diagram, 38 configuration multiplexed signal trade-offs, A-3 signal descriptions, 26 CPU x86 instruction set, 30 crystal 32.768-kHz crystal circuit, 41 32.768-kHz crystal selection, 41 33.333-MHz crystal speed, 43 33-MHz crystal selection, 42 3rd overtone crystal circuit implementation, 42 capacitance, 51 crystal speeds, 38 selecting, 41 customer support customer development platform, C-2 documentation and literature, C-3 hotline and web, C-3 literature ordering, C-3 ordering the microcontroller, 2 related AMD products/devices, C-1 related documents/information, C-2 third-party development support products, C-2 web home page, C-3 D DC characteristics, 50 operating ranges, 48 voltage for non-PCI interface pins, 49, 51 debugging See also AMDebug technology. features and system test, 32 ElanTMSC520 Microcontroller Data Sheet Index-1 PRELIMINARY JTAG boundary scan test interface, 32 JTAG signal descriptions, 23 derating curves, 51 DMA GP bus DMA read cycle, 71 GP bus DMA write cycle, 72 integrated controller, 31 documentation See customer support. DRAM See SDRAM. G GP bus chip-select signal descriptions, 24 description, 31 DMA read cycle, 71 DMA write cycle, 72 multiplexed signal trade-offs, A-2 pin summary, A-10 signal descriptions, 19 timing, 69 ground pin summary, A-14 E ElanTMSC520 microcontroller application examples, 33 architectural overview, 28 block diagram, 29 capacitance, 51 circuit board layout, B-3 DC characteristics, 50 distinctive characteristics, 1 documentation, C-2 general description, 1 logic diagram by default pin function, 7 logic diagram by interface, 6 maximum ratings, 48 operating ranges, 48 ordering information, 2 PBGA package, B-1 peripherals (overview), 31 physical dimensions, B-1 pin connection diagram, 8 pin designations, 10 pin tables (Appendix A), A-1 power characteristics, 56 programmable address region (PAR) registers, 31 related AMD E86 family devices, C-1 switching characteristics and waveforms, 58 thermal characteristics, 56 voltage levels, 48-49 H hotline and world wide web support, C-3 I I/O programmable I/O (PIO) signal descriptions, 25 interrupts programmable interrupt controller (PIC), 31 J JTAG boundary scan test interface, 32 pin summary, A-13 signal descriptions, 23 timing, 74 L literature See customer support. logic diagram by default pin function, 7 by interface, 6 F Flash addressing mapping, 31 controller description, 30 multiplexed signal trade-offs, A-2 pin summary, A-8 signal descriptions, 18 write cycles, 65 maximum ratings, 48 multiplexed functions signal trade-offs, A-2 M N no connect (NC) pin summary, A-16 Index-2 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY O operating ranges, 48 ordering information, 2 sorted by pin number, A-4 sorted by signal name, A-5 R P package PBGA physical dimensions, B-1 PAR programmable address region registers, 31 PBGA package physical dimensions, B-1 thermal characteristics, 56 PCI bus AC timing, 58 capacitance, 51 description, 30 pin summary, A-8 signal descriptions, 18 switching test waveforms, 58 timing, 65 voltage, 49 peripherals integrated, description of, 31 physical dimensions, B-1 PIC (programmable interrupt controller), 31 pins See also signals. clock pin loading, 40 pin and signal tables, 10 pin connection diagram, 8 pin designations, 10 pin designations by pin name, 13 pin designations sorted by pin number, 11 pin tables (Appendix A), A-1 Multiplexed Signal Trade-Offs table, A-2 Pin List Summary table, A-7 PIOs Sorted by PIO Number table, A-4 PIOs Sorted by Signal Name table, A-5 PIO See programmable I/O (PIO). power characteristics, 56 pin summary, A-14 power dissipation, 56 signal descriptions, 27 supply current, 56 voltage levels, 48 power-on reset timing, 59 programmable I/O (PIO) multiplexed signal trade-offs, A-3 signal descriptions, 25 real-time clock (RTC) backup battery, 46 circuit with backup battery, 47 circuit without backup battery, 47 not using backup battery, 46 voltage monitor, 45 voltage monitor block diagram, 45 voltage monitor specifications, 46 reset pin summary, A-13 power-on reset timing, 59 signal descriptions, 22 soft CPU reset, 32 timing with power applied, 61 ROM address mapping, 31 controller description, 30 multiplexed signal trade-offs, A-2 pin summary, A-8 signal descriptions, 18 timing, 63 RTC See real-time clock (RTC). S SDRAM address mapping, 31 clock timing, 68 controller description, 30 error correction code (ECC), 30 pin summary, A-7 signal descriptions, 17 timing, 66 serial ports multiplexed signal trade-offs, A-2 pin summary, A-12 signal descriptions, 21 signals See also pins. multiplexed signal trade-offs table, A-2 signal description table, 17 signal descriptions, 16 software timer, 32 SSI See synchronous serial interface (SSI). switching characteristics and waveforms GP bus, 69 JTAG, 74 non-PCI bus interface pins, 58 ElanTMSC520 Microcontroller Data Sheet Index-3 PRELIMINARY over commercial/industrial operating ranges, 59 PCI bus, 65 PCI bus interface pins, 58 power-on reset, 59 reset with power applied, 61 ROM, 63 SDRAM, 66 SSI, 73 synchronous serial interface (SSI) description, 32 timing, 73 system test multiplexed signal trade-offs, A-3 pin summary, A-13 signal descriptions, 23 W watchdog timer, 32 www home page, C-3 support, C-3 T technical support See customer support. testing JTAG boundary scan test interface, 32 system test and debug features, 32 system test multiplexed signal trade-offs, A-3 system test pin summary, A-13 system test signal descriptions, 23 thermal characteristics, 56 equations, 57 timers description, 32 multiplexed signal trade-offs, A-3 pin summary, A-14 signal descriptions, 25 timing See switching characteristics and waveforms. U UARTs description, 32 V voltage for non-PCI interface pins, 49 for PCI interface pins, 49 maximum ratings, 48 operating ranges, 48 Index-4 ElanTMSC520 Microcontroller Data Sheet PRELIMINARY Trademarks AMD, the AMD logo, and combinations thereof, AMD Athlon, Elan, AMDebug, PCnet, E86, Am186, Am188 and Comm86 are trademarks; Am5x86, Am386, Am486 and AMD-K6 are registered trademarks and FusionE86 is a servicemark of Advanced Micro Devices, Inc. Microsoft and Windows are registered trademarks of Microsoft Corporation. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Disclaimer The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD's Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD's product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice. (c)2001 Advanced Micro Devices, Inc. All rights reserved. ElanTMSC520 Microcontroller Data Sheet |
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