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M48Z2M1 M48Z2M1Y
16 Mbit (2Mb x 8) ZEROPOWER(R) SRAM
FEATURES SUMMARY s INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERIES
s
Figure 1. Packages
CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 10 YEARS OF DATA RETENTION IN THE ABSENCE OF POWER AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION WRITE PROTECT VOLTAGES (VPFD = Power-fail Deselect Voltage): - M48Z2M1: 4.5V VPFD 4.75V - M48Z2M1Y: 4.2V VPFD 4.5V BATTERIES ARE INTERNALLY ISOLATED UNTIL POWER IS APPLIED PIN and FUNCTION COMPATIBLE WITH JEDEC STANDARD 2Mb x 8 SRAMs
36 1
s
s
s
PLDIP36 (PL) Module
s
s
May 2002
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M48Z2M1, M48Z2M1Y
TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Logic Diagram (Figure 2.) . . . . . . . Signal Names (Table 1.) . . . . . . . . DIP Connections (Figure 3.) . . . . . Block Diagram (Figure 4.) . . . . . . . ....... ....... ....... ....... ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... .....3 .....3 .....3 .....4
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Absolute Maximum Ratings (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operating and AC Measurement Conditions (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 AC Testing Load Circuit (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Capacitance (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DC Characteristics (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Operating Modes (Table 6.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 READ Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Address Controlled, READ Mode AC Waveforms (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chip Enable or Output Enable Controlled, READ Mode AC Waveforms (Figure 7.). . . . . . . . . . . . . 7 READ Mode AC Characteristics (Table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 WRITE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 WRITE Enable Controlled, WRITE Mode AC Waveforms (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . 9 Chip Enable Controlled, WRITE Mode AC Waveforms (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . 9 WRITE Mode AC Characteristics (Table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power Down/Up Mode AC Waveforms (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power Down/Up AC Characteristics (Table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power Down/Up Trip Points DC Characteristics (Table 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VCC Noise And Negative Going Transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Supply Voltage Protection (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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M48Z2M1, M48Z2M1Y
SUMMARY DESCRIPTION The M48Z2M1/Y ZEROPOWER(R) RAM is a nonvolatile 16,777,216-bit, Static RAM organized as 2,097,152 words by 8 bits. The device combines two internal lithium batteries, CMOS SRAMs and a control circuit in a plastic 36-pin DIP, long Module.
The ZEROPOWER RAM replaces industry standard SRAMs. It provides the nonvolatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed.
Figure 2. Logic Diagram
VCC
Table 1. Signal Names
A0-A20 DQ0-DQ7 Address Inputs Data Inputs / Outputs Chip Enable Output Enable WRITE Enable Supply Voltage Ground Not Connected Internally
21 A0-A20 M48Z2M1 M48Z2M1Y
8 DQ0-DQ7
E G W VCC VSS NC
W E G
VSS
AI02048
Figure 3. DIP Connections
NC A20 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 36 1 35 2 34 3 33 4 32 5 31 6 30 7 29 8 M48Z2M1 9 M48Z2M1Y 28 27 10 26 11 25 12 24 13 23 14 22 15 21 16 20 17 19 18
AI02049
VCC A19 NC A15 A17 W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
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M48Z2M1, M48Z2M1Y
Figure 4. Block Diagram
VCC
A0-A20
POWER E VOLTAGE SENSE AND SWITCHING CIRCUITRY
2048K x 8 SRAM ARRAY
DQ0-DQ7
E W G
INTERNAL BATTERIES
VSS
AI02050
MAXIMUM RATING Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 2. Absolute Maximum Ratings
Symbol TA TSTG TBIAS TSLD(1) VIO VCC IO PD Parameter Ambient Operating Temperature Storage Temperature (VCC Off) Temperature Under Bias Lead Solder Temperature for 10 seconds Input or Output Voltages Supply Voltage Output Current Power Dissipation
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Value 0 to 70 -40 to 85 -40 to 85 260 -0.3 to 7 -0.3 to 7 20 1
Unit C C C C V V mA W
Note: 1. Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds).
CAUTION: Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up mode.
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M48Z2M1, M48Z2M1Y
DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Table 3. Operating and AC Measurement Conditions
Parameter Supply Voltage (VCC) Ambient Operating Temperature (TA) Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages
Note: Output Hi-Z is defined as the point where data is no longer driven.
M48Z2M1 4.75 to 5.5 0 to 70 100 5 0 to 3 1.5
M48Z2M1Y 4.5 to 5.5 0 to 70 100 5 0 to 3 1.5
Unit V C pF ns V V
Figure 5. AC Testing Load Circuit
5V
1.9k DEVICE UNDER TEST 1k
OUT
CL = 100pF or 5pF
CL includes JIG capacitance
AI01030
Table 4. Capacitance
Symbol CIN CIO(3) Input Capacitance Input / Output Capacitance Parameter(1,2) Min Max 40 40 Unit pF pF
Note: 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested. 2. Outputs deselected. 3. At 25C.
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M48Z2M1, M48Z2M1Y
Table 5. DC Characteristics
Symbol ILI(2) ILO(2) ICC ICC1 ICC2 VIL VIH VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 2.1mA IOH = -1mA 2.4 Test Condition(1) 0V VIN VCC 0V VOUT VCC E = VIL, Outputs open E = VIH E VCC - 0.2V -0.3 2.2 Min Max 4 4 140 10 8 0.8 VCC + 0.3 0.4 Unit A A mA mA mA V V V V
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. Outputs deselected.
OPERATION MODES The M48Z2M1/Y has its own Power-fail Detect Circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of Table 6. Operating Modes
Mode Deselect WRITE READ READ Deselect Deselect VSO to VPFD (min)(1) VSO(1) 4.75 to 5.5V or 4.5 to 5.5V VCC E VIH VIL VIL VIL X X G X X VIL VIH X X
data security in the midst of unpredictable system operations brought on by low VCC. As VCC falls below approximately 3V, the control circuitry connects the batteries which sustain data until valid power returns.
W X VIL VIH VIH X X
DQ0-DQ7 High Z DIN DOUT High Z High Z High Z
Power Standby Active Active Active CMOS Standby Battery Back-up Mode
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. 1. See Table 10, page 12 for details.
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M48Z2M1, M48Z2M1Y
READ Mode The M48Z2M1/Y is in the READ Mode whenever W (WRITE Enable) is high and E (Chip Enable) is low. The device architecture allows ripple-through access of data from eight of 16,777,216 locations in the static storage array. Thus, the unique address specified by the 21 Address Inputs defines which one of the 2,097,152 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is stable, providing that the E (Chip Enable) and G (Output Enable) access times are also satisfied. If the E and G ac-
cess times are not met, valid data will be available after the later of Chip Enable Access time (tELQV) or Output Enable Access Time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain low, output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access.
Figure 6. Address Controlled, READ Mode AC Waveforms
A0-A20 tAVAV tAVQV DQ0-DQ7 DATA VALID
AI02051
tAXQX
Note: Chip Enable (E) and Output Enable (G) = Low, WRITE Enable (W) = High.
Figure 7. Chip Enable or Output Enable Controlled, READ Mode AC Waveforms
tAVAV A0-A20 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7 DATA OUT
AI02052
VALID tAXQX tEHQZ
tGHQZ
Note: WRITE Enable (W) = High.
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M48Z2M1, M48Z2M1Y
Table 7. READ Mode AC Characteristics
M48Z2M1/Y Symbol Parameter
(1)
-70 Min Max
Unit
tAVAV tAVQV(2) tAXQX(2) tEHQZ(3) tELQV(2) tELQX(3) tGHQZ(3) tGLQV(2) tGLQX(3)
READ Cycle Time Address Valid to Output Valid Address Transition to Output Transition Chip Enable High to Output Hi-Z Chip Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition
70 70 5 30 70 5 25 35 5
ns ns ns ns ns ns ns ns ns
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. CL = 100pF or 50pF (see Figure 5, page 5). 3. CL = 5pF (see Figure 5, page 5).
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M48Z2M1, M48Z2M1Y
WRITE Mode The M48Z2M1/Y is in the WRITE Mode whenever W and E are active. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for minimum of tEHAX from E or tWHAX from W prior to the initiation
of another READ or WRITE cycle. Data-in must be valid tDVEH or tDVWH prior to the end of WRITE and remain valid for tEHDX or tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls.
Figure 8. WRITE Enable Controlled, WRITE Mode AC Waveforms
tAVAV A0-A20 VALID tAVWH tAVEL E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI02053
tWHAX
tWHQX
Note: Output Enable (G) = High.
Figure 9. Chip Enable Controlled, WRITE Mode AC Waveforms
tAVAV A0-A20 VALID tAVEH tAVEL E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI02054
tELEH
tEHAX
Note: Output Enable (G) = High.
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M48Z2M1, M48Z2M1Y
Table 8. WRITE Mode AC Characteristics
M48Z2M1/Y Symbol Parameter
(1)
-70 Min Max
Unit
tAVAV tAVEH tAVEL tAVWH tAVWL tDVEH tDVWH tEHAX tEHDX tELEH tWHAX tWHDX tWHQX(2,3) tWLQZ(2,3) tWLWH
WRITE Cycle Time Address Valid to Chip Enable High Address Valid to Chip Enable Low Address Valid to WRITE Enable High Address Valid to WRITE Enable Low Input Valid to Chip Enable High Input Valid to WRITE Enable High Chip Enable High to Address Transition Chip Enable High to Input Transition Chip Enable Low to Chip Enable High WRITE Enable High to Address Transition WRITE Enable High to Input Transition WRITE Enable High to Output Transition WRITE Enable Low to Output Hi-Z WRITE Enable Pulse Width
70 65 0 65 0 30 30 15 10 55 5 0 5 25 55
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. CL = 5pF (see Figure 5, page 5). 3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
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M48Z2M1, M48Z2M1Y
Data Retention Mode With valid VCC applied, the M48Z2M1/Y operates as a conventional BYTEWIDETM static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself tWP after VCC falls below VPFD. All outputs become high impedance, and all inputs are treated as "Don't care." If power fail detection occurs during a valid access, the memory cycle continues to completion. If the memory cycle fails to terminate within the time tWP, write protection takes place. When VCC drops below VSO, the control circuit switches power to the internal energy source which preserves data. Figure 10. Power Down/Up Mode AC Waveforms
VCC VPFD (max) VPFD (min) VSO tF tFB tWP E
RECOGNIZED
The internal coin cells will maintain data in the M48Z2M1/Y after the initial application of VCC for an accumulated period of at least 10 years when VCC is less than VSO. As system power returns and VCC rises above VSO, the batteries are disconnected, and the power supply is switched to external VCC. Write protection continues for tER after VCC reaches VPFD to allow for processor stabilization. After tER, normal RAM operation can resume. For more information on Battery Storage life refer to the Application Note AN1012.
tDR tRB
tR
tER DON'T CARE
RECOGNIZED
HIGH-Z OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI01031
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M48Z2M1, M48Z2M1Y
Table 9. Power Down/Up AC Characteristics
Symbol tER tF(2) tFB(3) tR tWP E Recovery Time VPFD (max) to VPFD (min) VCC Fall Time VPFD (min) to VSO VCC Fall Time VPFD (min) to VPFD (max) VCC Rise Time Write Protect Time from VCC = VPFD Parameter(1) Min 40 300 10 0 40 150 Max 120 s s s s Unit
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200s after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 10. Power Down/Up Trip Points DC Characteristics
Symbol VPFD VSO tDR(3) Parameter(1,2) M48Z2M1 Power-fail Deselect Voltage M48Z2M1Y Battery Back-up Switchover Voltage Expected Data Retention Time 10 4.2 4.3 3.0 4.5 V V YEARS Min 4.5 Typ 4.6 Max 4.75 Unit V
Note: 1. All voltages referenced to VSS. 2. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 3. At 25C
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M48Z2M1, M48Z2M1Y
VCC Noise And Negative Going Transients ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1F (as shown in Figure 11) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to connect a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Figure 11. Supply Voltage Protection
VCC VCC
0.1F
DEVICE
VSS
AI02169
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M48Z2M1, M48Z2M1Y
PART NUMBERING Table 11. Ordering Information Scheme
Example: M48Z 2M1 -70 PL 1
Device Type M48Z
Supply Voltage and Write Protect Voltage 2M1 = VCC = 4.75 to 5.5V; VPFD = 4.5 to 4.75V 2M1Y = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V
Speed -70 = 70ns (M48Z2M1/Y)
Package PL = PLDIP36
Temperature Range 1 = 0 to 70C 9(1) = Extended Temperature
Shipping Method blank = Tubes
Note: 1. Contact Sales Offices for availability of Extended Temperature.
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest you.
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M48Z2M1, M48Z2M1Y
PACKAGE MECHANICAL INFORMATION Figure 12. PLDIP36 - 36-pin Plastic DIP Long Module, Package Outline
A
A1 S B e3 D e1
L eA
C
N
E
1 PMDIP
Note: Drawing is not to scale.
Table 12. PLDIP36 - 36-pin Plastic DIP Long Module, Package Mechanical Data
mm Symb Typ A A1 B C D E e1 e3 eA L S N Min 9.27 0.38 0.43 0.20 52.58 18.03 2.30 38.86 14.99 3.05 4.45 36 0.59 0.33 53.34 18.80 2.81 47.50 16.00 3.81 5.33 Max 9.52 Typ Min 0.3650 0.0150 0.0169 0.0079 2.0701 0.7098 0.0906 1.5300 0.5902 0.1201 0.1752 36 0.0232 0.0130 2.1000 0.7402 0.1106 1.8701 0.6299 0.1500 0.2098 Max 0.3748 inches
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M48Z2M1, M48Z2M1Y
REVISION HISTORY Table 13. Document Revision History
Date July 1999 August 2000 03/20/02 05/29/02 First Issue From Preliminary Data to Data Sheet Reformatted; Temperature information added to tables (Table 4, 5, 7, 8, 9, 10) Modified "VCC Noise and Negative Going Transients" text Revision Details
16/17
M48Z2M1, M48Z2M1Y
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. (c) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. www.st.com
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