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Dual Bootstrapped, 12 V MOSFET Driver with Output Disable ADP3110A
FEATURES
All-in-one synchronous buck driver Bootstrapped high-side drive One PWM signal generates both drives Anticross conduction protection circuitry OD for disabling the driver outputs Meets CPU VR requirement when used with Analog Devices Flex-ModeTM 1 controller
GENERAL DESCRIPTION
The ADP3110A is a dual, high voltage MOSFET driver optimized for driving two N-channel MOSFETs, the two switches in a nonisolated synchronous buck power converter. Each driver is capable of driving a 3000 pF load with a 25 ns propagation delay and a 30 ns transition time. One of the drivers can be bootstrapped and is designed to handle the high voltage slew rate associated with floating high-side gate drivers. The ADP3110A includes overlapping drive protection to prevent shoot-through current in the external MOSFETs. The OD pin shuts off both the high-side and the low-side MOSFETs to prevent rapid output capacitor discharge during system shutdown. The ADP3110A is specified over the commercial temperature range of 0C to 85C and is available in an 8-lead SOIC_N or an 8-lead LFCSP_VD package.
1
APPLICATIONS
Multiphase desktop CPU supplies Single-supply synchronous buck converters
Flex-ModeTM is protected by U.S. Patent 6683441; other patents pending.
FUNCTIONAL BLOCK DIAGRAM
12V
VCC
4
D1 BST
1
ADP3110A
LATCH R1 R2 Q S DELAY
CBST2 CBST1 DRVH RG
IN 2
8
Q1 TO INDUCTOR
RBST SW
7
CMP
VCC 6 DRVL
5
CMP 1V CONTROL LOGIC
Q2
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
05832-001
OD 3
DELAY
PGND
6
ADP3110A TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 4 ESD Caution.................................................................................. 4 Pin Configuration and Function Descriptions............................. 5 Timing Characteristics..................................................................... 6 Typical Performance Characteristics ............................................. 7 Theory of Operation .........................................................................9 Low-Side Driver ............................................................................9 High-Side Driver ...........................................................................9 Overlap Protection Circuit...........................................................9 Application Information................................................................ 10 Supply Capacitor Selection ....................................................... 10 Bootstrap Circuit........................................................................ 10 MOSFET Selection..................................................................... 10 PC Board Layout Considerations............................................. 11 Outline Dimensions ....................................................................... 13 Ordering Guide .......................................................................... 13
REVISION HISTORY
3/06--Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADP3110A SPECIFICATIONS
VCC = 12 V, BST = 4 V to 26 V, TA = 25C, unless otherwise noted. 1 Table 1.
Parameter DIGITAL INPUTS (PWM, OD) Input Voltage High 2 Input Voltage Low2 Input Current2 Hysteresis2 HIGH-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Output Resistance, Unbiased Transition Times Propagation Delay Times Symbol Conditions Min 2.0 -1 90 BST to SW = 12 V BST to SW = 12 V BST to SW = 0 V BST to SW = 12 V, CLOAD = 3 nF, see Figure 4 BST to SW = 12 V, CLOAD = 3 nF, see Figure 4 BST to SW = 12 V, CLOAD = 3 nF, see Figure 4 BST to SW = 12 V, CLOAD = 3 nF, see Figure 4 See Figure 3 See Figure 3 SW to PGND 0.8 +1 250 2.6 1.4 10 40 30 45 25 20 40 10 2.5 1.4 10 40 20 15 30 20 110 110 95 4.15 BST = 12 V, IN = 0 V VCC rising 2 1.5 350 190 190 150 13.2 5 3.0 3.4 1.8 50 30 35 40 35 3.4 1.8 55 45 65 35 35 55 Typ Max Unit V V A mV k ns ns ns ns ns ns k k ns ns ns ns ns ns ns ns V mA V mV
trDRVH tfDRVH tpdhDRVH tpdlDRVH
t pdl
OD
tpdh
OD
SW Pull-Down Resistance LOW-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Output Resistance, Unbiased Transition Times Propagation Delay Times
trDRVL tfDRVL tpdhDRVL tpdlDRVL
t pdl
OD OD
VCC = PGND CLOAD = 3 nF, see Figure 4 CLOAD = 3 nF, see Figure 4 CLOAD = 3 nF, see Figure 4 CLOAD = 3 nF, see Figure 4 See Figure 3 See Figure 3 SW = 5 V SW = PGND
tpdh
Timeout Delay SUPPLY Supply Voltage Range2 Supply Current2 UVLO Voltage2 Hysteresis2
1 2
VCC ISYS
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods. Specifications apply over the full operating temperature range TA = 0C to 85C.
Rev. 0 | Page 3 of 16
ADP3110A ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter VCC BST DC <200 ns BST to SW SW DC <200 ns DRVH DC <200 ns DRVL DC <200 ns IN, OD JA, SOIC_N 2-Layer Board 4-Layer Board Operating Ambient Temperature Range Junction Temperature Range Storage Temperature Range Lead Temperature Soldering (10 sec) Vapor Phase (60 sec) Infrared (15 sec) Rating -0.3 V to +15 V -0.3 V to VCC + 15 V -0.3 V to +35 V -0.3 V to +15 V -5 V to +15 V -10 V to +25 V SW - 0.3 V to BST + 0.3 V SW - 2 V to BST + 0.3 V -0.3 V to VCC + 0.3 V -2 V to VCC + 0.3 V -0.3 V to 6.5 V 123C/W 90C/W 0C to 85C 0C to 150C -65C to +150C 300C 215C 260C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Unless otherwise specified, all voltages are referenced to PGND.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 4 of 16
ADP3110A PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BST 1 IN 2 OD 3 VCC 4
8
DRVH SW DRVL
05832-002
ADP3110A
TOP VIEW (Not to Scale)
7 6 5
PGND
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 Mnemonic BST IN OD VCC DRVL PGND SW Description Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this bootstrapped voltage for the high-side MOSFET while it is switching. Logic Level PWM Input. This pin has primary control of the driver outputs. In normal operation, pulling this pin low turns on the low-side driver; pulling it high turns on the high-side driver. Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low. Input Supply. This pin should be bypassed to PGND with ~1 F ceramic capacitor. Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET. Power Ground. Connect this pin closely to the source of the lower MOSFET. Switch Node Connection. This pin is connected to the buck-switching node, close to the upper MOSFET source. It is the floating return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent the lower MOSFET from turning on until the voltage is below ~1 V. Buck Drive. Output drive for the upper (buck) MOSFET.
8
DRVH
Rev. 0 | Page 5 of 16
ADP3110A TIMING CHARACTERISTICS
Timing is referenced to the 90% and 10% points, unless otherwise noted.
OD
tpdlOD
tpdhOD
90% 10%
05832-003
DRVH OR DRVL
Figure 3. Output Disable Timing Diagram
IN
tpdlDRVL
DRVL
tfDRVL
tpdlDRVH
trDRVL
tpdhDRVH
trDRVH
tfDRVH
DRVH-SW
VTH
VTH
tpdhDRVL
SW 1V
05832-004
Figure 4. Timing Diagram
Rev. 0 | Page 6 of 16
ADP3110A TYPICAL PERFORMANCE CHARACTERISTICS
24
IN
VCC = 12V CLOAD = 3nF 22
DRVH
FALL TIME (ns)
20
DRVL
18 DRVL
DRVH
16
05832-017
0
25
50
75
100
125
JUNCTION TEMPERATURE (C)
Figure 5. DRVH Rise and DRVL Fall Times CLOAD = 6 nF for DRVL, CLOAD = 2 nF for DRVH
40 35
IN
Figure 8. DRVH and DRVL Fall Times vs. Temperature
TA = 25C VCC = 12V
DRVH
30
RISE TIME (ns)
DRVL
25 20 15 10
DRVL
05832-016
DRVH
2.5
3.0
3.5
4.0
4.5
5.0
LOAD CAPACITANCE (nF)
Figure 6. DRVH Fall and DRVL Rise Times CLOAD = 6 nF for DRVL, CLOAD = 2 nF for DRVH
35 VCC = 12V CLOAD = 3nF
Figure 9. DRVH and DRVL Rise Times vs. Load Capacitance
35 VCC = 12V TA = 25C 30 DRVH
30 RISE TIME (ns)
DRVH
FALL TIME (ns)
25
25
20
DRVL
DRVL 20
15
10
05832-015
0
25
50
75
100
125
2.5
3.0
3.5
4.0
4.5
5.0
JUNCTION TEMPERATURE (C)
LOAD CAPACITANCE (nF)
Figure 7. DRVH and DRVL Rise Times vs. Temperature
Figure 10. DRVH and DRVL Fall Times vs. Load Capacitance
Rev. 0 | Page 7 of 16
05832-012
15
5 2.0
05832-013
5 2.0
05832-014
14
ADP3110A
60 TA= 25C VCC = 12V CLOAD = 3nF
DRVL OUTPUT VOLTAGE (V)
12 11 10 9 8 7 6 5 4 3 2 1
05832-011
TA = 25C CLOAD = 3nF
SUPPLY CURRENT (mA)
45
30
15
0
200
400
600
800
1000
1200
1400
0
1
2
3
4
5
6 VCC (V)
7
8
9
10
11
12
FREQUENCY (kHz)
Figure 11. Supply Current vs. Frequency
13 VCC = 12V CLOAD = 3nF fIN = 250kHz SUPPLY CURRENT (mA) 12
Figure 13. DRVL Output Voltage vs. Supply Voltage
11
10
0
25
50
75
100
125
JUNCTION TEMPERATURE (C)
Figure 12. Supply Current vs. Temperature
05832-010
9
Rev. 0 | Page 8 of 16
05832-009
0
0
ADP3110A THEORY OF OPERATION
The ADP3110A is a dual MOSFET driver optimized for driving two N-channel MOSFETs in a synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high-side and the low-side MOSFETs. Each driver is capable of driving a 3 nF load at speeds up to 500 kHz. A functional block diagram of the ADP3110A is shown in Figure 1. pulling the gate down to the voltage at the SW pin. When the low-side MOSFET, Q2, turns on, the SW pin is pulled to ground. This allows the bootstrap capacitor to charge up to VCC again. The high-side driver is in phase with the PWM input. When the driver is disabled, the high-side gate is held low.
LOW-SIDE DRIVER
The low-side driver is designed to drive a ground referenced N-channel MOSFET. The bias to the low-side driver is internally connected to the VCC supply and PGND. When the ADP3110A is enabled, the driver output is 180 out of phase with the PWM input. When the ADP3110A is disabled, the low-side gate is held low.
OVERLAP PROTECTION CIRCUIT
The overlap protection circuit prevents both of the main power switches, Q1 and Q2, from being on at the same time. This prevents shoot-through currents from flowing through both power switches and the associated losses that can occur during their on/off transitions. The overlap protection circuit accomplishes this by adaptively controlling the delay from the Q1 turn-off to the Q2 turn-on, and by internally setting the delay from the Q2 turn-off to the Q1 turn-on. To prevent the overlap of the gate drives during the Q1 turn-off and the Q2 turn-on, the overlap circuit monitors the voltage at the SW pin. When the PWM input signal goes low, Q1 begins to turn off (after propagation delay). Before Q2 can turn on, the overlap protection circuit makes sure that SW has first gone high and then waits for the voltage at the SW pin to fall from VIN to 1 V. Once the voltage on the SW pin falls to 1 V, Q2 begins turn-on. If the SW pin has not gone high first, the Q2 turn-on is delayed by a fixed 150 ns. By waiting for the voltage on the SW pin to reach 1 V or for the fixed delay time, the overlap protection circuit ensures that Q1 is off before Q2 turns on, regardless of variations in temperature, supply voltage, input pulse width, gate charge, and drive current. If SW does not go below 1 V after 190 ns, DRVL turns on. This can occur if the current flowing in the output inductor is negative and flows through the high-side MOSFET body diode.
HIGH-SIDE DRIVER
The high-side driver is designed to drive a floating N-channel MOSFET. The bias voltage for the high-side driver is developed by an external bootstrap supply circuit that is connected between the BST and SW pins. The bootstrap circuit comprises Diode D1 and Bootstrap Capacitor CBST1. CBST2 and RBST are included to reduce the highside gate drive voltage and limit the switch node slew rate (referred to as a Boot-SnapTM circuit, see the Application Information section for more details). When the ADP3110A is starting up, the SW pin is at ground; therefore, the bootstrap capacitor charges up to VCC through D1. When the PWM input goes high, the high-side driver begins to turn on the high-side MOSFET, Q1, by pulling charge out of CBST1 and CBST2. As Q1 turns on, the SW pin rises up to VIN and forces the BST pin to VIN + VC(BST). This holds Q1 on because enough gate-to-source voltage is provided. To complete the cycle, Q1 is switched off by
Rev. 0 | Page 9 of 16
ADP3110A APPLICATION INFORMATION
SUPPLY CAPACITOR SELECTION
For the supply input (VCC) of the ADP3110A, a local bypass capacitor is recommended to reduce the noise and to supply some of the peak currents that are drawn. Use a 4.7 F, low ESR capacitor. Multilayer ceramic chip (MLCC) capacitors provide the best combination of low ESR and small size. Keep the ceramic capacitor as close as possible to the ADP3110A. A small signal diode can be used for the bootstrap diode due to the ample gate drive voltage supplied by VCC. The bootstrap diode must have a minimum 15 V rating to withstand the maximum supply voltage. The average forward current can be estimated by
I F ( AVG ) = QGATE x f MAX
(5)
BOOTSTRAP CIRCUIT
The bootstrap circuit uses a charge storage capacitor (CBST1) and a diode, as shown in Figure 1. These components can be selected after the high-side MOSFET is chosen. The bootstrap capacitor must have a voltage rating that can handle twice the maximum supply voltage. A minimum 50 V rating is recommended. The capacitor values are determined using the following equations:
C BST 1 + C BST 2 Q = 10 x GATE VGATE
where fMAX is the maximum switching frequency of the controller. The peak surge current rating should be calculated by
I F ( PEAK ) = V CC - V D R BST
(6)
MOSFET SELECTION
When interfacing the ADP3110A to external MOSFETs, the designer should consider ways to make a robust design that minimizes stresses on both the driver and the MOSFETs. These stresses include exceeding the short time duration voltage ratings on the driver pins as well as the external MOSFET. It is also highly recommended to use the Boot-Snap circuit to improve the interaction of the driver with the characteristics of the MOSFETs. If a simple bootstrap arrangement is used, make sure to include a proper snubber network on the SW node.
(1) (2)
C BST 1 VGATE = C BST 1 + C BST 2 VCC - V D
where: QGATE is the total gate charge of the high-side MOSFET at VGATE. VGATE is the desired gate drive voltage (usually in the range of 5 V to 10 V, 7 V being typical). VD is the voltage drop across D1. Rearranging Equation 1 and Equation 2 to solve for CBST1 yields
C BST 1 = 10 x QGATE VCC - V D
High-Side (Control) MOSFETs
The high-side MOSFET is usually selected to be high speed to minimize switching losses (see the ADP3186 or ADP3188 data sheets for Flex-Mode controller details). This usually implies a low gate resistance and low input capacitance/charge device. Yet, a significant source lead inductance can also exist that depends mainly on the MOSFET package; it is best to contact the MOSFET vendor for this information. The ADP3110A DRVH output impedance and the input resistance of the MOSFETs determine the rate of charge delivery to the internal capacitance of the gate. This determines the speed at which the MOSFETs turn on and off. However, because of potentially large currents flowing in the MOSFETs at the on and off times (this current is usually larger at turn-off due to ramping up of the output current in the output inductor), the source lead inductance generates a significant voltage when the high-side MOSFETs switch off. This creates a significant drainsource voltage spike across the internal die of the MOSFETs and can lead to a catastrophic avalanche. The mechanisms involved in this avalanche condition are referenced in literature from the MOSFET suppliers.
(3)
CBST2 can then be found by rearranging Equation 1
C BST 2 = 10 x QGATE - C BST 1 VGATE
(4)
For example, an NTD60N02 has a total gate charge of about 12 nC at VGATE = 7 V. Using VCC = 12 V and VD = 1 V, then CBST1 = 12 nF and CBST2 = 6.8 nF. Good quality ceramic capacitors should be used. RBST is used to limit slew rate and minimize ringing at the switch node. It also provides peak current limiting through D1. An RBST value of 1.5 to 2.2 is a good choice. The resistor needs to handle at least 250 mW due to the peak currents that flow through it.
Rev. 0 | Page 10 of 16
ADP3110A
The MOSFET vendor should provide a rating for the maximum voltage slew rate at drain current around which this can be designed. When this rating is obtained, determine the expected maximum current in the MOSFET by
I MAX = I DC ( per phase) + (VCC - VOUT )x D MAX f MAX x LOUT
(7)
to go below one sixth of VCC; then, a delay is added. Due to the Miller capacitance and internal delays of the low-side MOSFET gate, ensure the Miller-to-input capacitance ratio is low enough, and the low-side MOSFET internal delays are not so large as to allow accidental turn on of the low-side MOSFET when the high-side MOSFET turns on. Contact Sales for an updated list of recommended low-side MOSFETs.
where: DMAX is determined for the VR controller that is used with the driver. This current is divided roughly equally between MOSFETs if more than one is used (assume a worst-case mismatch of 30% for design margin). LOUT is the output inductor value. When producing the design, there is no exact method for calculating the dV/dt due to the parasitic effects in the external MOSFETs as well as the PCB. However, it can be measured to determine if it is safe. If it appears the dV/dt is too fast, an optional gate resistor can be added between DRVH and the high-side MOSFETs. This resistor slows down the dV/dt, but it also increases the switching losses in the high-side MOSFETs. The ADP3110A is optimally designed with an internal drive impedance that works with most MOSFETs to switch them efficiently, yet minimizes dV/dt. However, some high speed MOSFETs can require this external gate resistor, depending on the currents being switched in the MOSFET.
PC BOARD LAYOUT CONSIDERATIONS
Use the following general guidelines when designing printed circuit boards: * * * * * Trace out the high current paths and use short, wide (>20 mil) traces to make these connections. Minimize trace inductance between the DRVH and DRVL outputs and the MOSFET gates. Connect the PGND pin of the ADP3110A as closely as possible to the source of the lower MOSFET. Locate the VCC bypass capacitor as closely as possible to the VCC and PGND pins. Use vias to other layers, when possible, to maximize thermal conduction away from the IC.
Low-Side (Synchronous) MOSFETs
The low-side MOSFETs are usually selected to have a low on resistance to minimize conduction losses. This usually implies a large input gate capacitance and gate charge. The first concern is to ensure the power delivery from the ADP3110A DRVL does not exceed the thermal rating of the driver (see the ADP3186, ADP3188, or ADP3189 data sheets for Flex-Mode controller details). The next concern for the low-side MOSFETs is to prevent them from inadvertently being switched on when the high-side MOSFET turns on. This occurs due to the drain gate (Miller capacitance, also specified as Crss capacitance) of the MOSFET. When the drain of the low-side MOSFET is switched to VCC by the high-side turning on (at a rate dV/dt), the internal gate of the low-side MOSFET is pulled up by an amount roughly equal to VCC x (Crss/Ciss). It is important to make sure this does not put the MOSFET into conduction. Another consideration is the nonoverlap circuitry of the ADP3110A that attempts to minimize the nonoverlap period. During the state of the high-side turning off to low-side turning on, the SW pin and the conditions of SW prior to switching are monitored to adequately prevent overlap. However, during the low-side turn-off to high-side turn-on, the SW pin does not contain information for determining the proper switching time, so the state of the DRVL pin is monitored
The circuit in Figure 15 shows how four drivers can be combined with the ADP3181 to form a total power conversion solution for generating VCC(CORE) for an Intel(R) CPU that is VRD 10.x compliant. Figure 14 shows an example of the typical land patterns based on the guidelines given previously. For more detailed layout guidelines for a complete CPU voltage regulator subsystem, refer to the Layout and Component Placement section in the ADP3181 data sheet.
CBST1
CBST2 D1
RBST
CVCC
Figure 14. External Component Placement Example
Rev. 0 | Page 11 of 16
05832-005
ADP3110A
VIN 12V C7 4.7F
L1 370nH 18A R3 2.2 C8 12nF
2700F/16V/3.3A x 2 SANYO MV-WX SERIES
VIN RTN D2 1N4148
1 2 3
+ C1
+ C2
U2 C6 ADP3110A 6.8nF
BST IN SW 7 PGND 6 DRVL 5 C24 Q3 NTD110N02 Q4 NTD110N02 + C31 OD VCC DRVH 8 Q1 NTD60N02 560F/4V x 8 L2 320nH/1.4m SANYO SEPC SERIES 5m EACH +
VCC (CORE) 0.8375V - 1.6V 95A TDC, 119A PK VCC (CORE) RTN
C5 4.7F R4 2.2 C11 4.7F C12 12nF
4
D1 1N4148
1 2 3
D3 1N4148 BST IN SW 7 PGND 6 DRVL 5 Q8 NTD110N02 OD VCC DRVH 8 Q5 NTD60N02
U3 C10 ADP3110A 6.8nF
10F x 18 MLCC IN SOCKET
L3 320nH/1.4m
R1 10 C9 4.7F R5 2.2 C16 12nF
4
C3 100F
+
Q7 NTD110N02
C4 1F
R2 357k, 1%
1 2 3 4 5 6 7 8 9 10 11 12 13 14
U1 ADP3181
VCC 28 PWM1 27 PWM2 26
1 2
VID4 VID3 VID2 VID1 PWM3 25 PWM4 24 SW1 23 SW2 22 SW3 21 SW4 20 GND 19 CSCOMP 18 CSSUM 17 CSREF 16 C22 1nF CCS1 560pF CCS2 1.5nF RCS1 RCS2 35.7k 84.5k RPH4 158k, 1% RPH2 RPH3 158k, RPH1 1% 158k, 158k, 1% 1% RSW41 RSW31 RSW21 C13 4.7F
4
D4 1N4148 BST IN OD VCC
U4 C14 ADP3110A 6.8nF
DRVH 8 SW 7 PGND 6 DRVL 5
C15 4.7F Q9 NTD60N02
Figure 15. VRD 10.x Compliant Power Supply Circuit
VID0 CPUID FBRTN FB COMP PWRGD EN DELAY RT RAMPADJ ILIMIT 15 RSW11
3
Rev. 0 | Page 12 of 16
R6 2.2 C20 12nF
FROM CPU
L4 320nH/1.4m
CB
C21 1
470pF
1nF
POWER GOOD
ENABLE
CA RA RB 1.21k 470pF 12.1k
CFB 22pF
Q11 NTD110N02
Q12 NTD110N02
CLDY 39nF
RLDY 470k
D5 1N4148
1 2 3
U5 C18 ADP3110A 6.8nF
BST IN OD
4
C19 4.7F
DRVH 8 SW 7 PGND 6 VCC DRVL 5
RT 137k, 1%
Q13 NTD60N02
L5 320nH/1.4m RTH1 100k, 5% NTC
C23 1nF
RLIM 150k, 1%
C17 4.7F
Q15 NTD110N02
Q16 NTD110N02
05832-006
1FOR A
DESCRIPTION OF OPTIONAL COMPONENTS, SEE THE ADP3181 THEORY OF OPERATION SECTION.
ADP3110A OUTLINE DIMENSIONS
5.00 (0.1968) 4.80 (0.1890)
8 5
4.00 (0.1574) 3.80 (0.1497) 1
6.20 (0.2440)
4 5.80 (0.2284)
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040)
1.75 (0.0688) 1.35 (0.0532)
0.50 (0.0196) x 45 0.25 (0.0099)
0.51 (0.0201) COPLANARITY SEATING 0.31 (0.0122) 0.10 PLANE
8 0.25 (0.0098) 0 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 16. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches)
0.50 0.40 0.30
3.00 BSC SQ
0.60 MAX
PIN 1 INDICATOR
8
1
PIN 1 INDICATOR
TOP VIEW
2.75 BSC SQ
0.50 BSC
1.50 REF
5 4
1.89 1.74 1.59
0.90 MAX 0.85 NOM
12 MAX
0.70 MAX 0.65 TYP 0.05 MAX 0.01 NOM 0.30 0.23 0.18 0.20 REF
1.60 1.45 1.30
SEATING PLANE
Figure 17. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD} 3 mm x 3 mm Body, Very Thin, Dual Lead (CP-8-2) Dimensions shown in millimeters
ORDERING GUIDE
Model ADP3110AKRZ 1 ADP3110AKRZ-RL1 ADP3110AJCPZ-RL1
1
Temperature Range 0C to 85C 0C to 85C 0C to 85C
Package Description 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N], Reel 8-Lead Lead Frame Chip Scale Package [LFCSP_VD], Reel
Package Option R-8 R-8 CP-8-2
Ordering Quantity 98 2,500 5,000
Branding
L3E
Z = Pb-free part.
Rev. 0 | Page 13 of 16
ADP3110A NOTES
Rev. 0 | Page 14 of 16
ADP3110A NOTES
Rev. 0 | Page 15 of 16
ADP3110A NOTES
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05832-0-3/06(0)
Rev. 0 | Page 16 of 16

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