Part Number Hot Search : 
64265 GP30A 1498N 23000 ST6252C 2SW470M 475M0 1200W
Product Description
Full Text Search
 

To Download AT88SC0104C Datasheet File

  If you can't view the Datasheet, Please click here to try to view without PDF Reader .  
 
 


  Datasheet File OCR Text:
 Features
* One of a Family of Devices with User Memories from 1 Kbit to 256-Kbit * 1-Kbit (128-byte) EEPROM User Memory
- Four 32 byte (256 bit) Zones - Self-timed Write Cycle - Single Byte or 16-byte Page Write Mode - Programmable Access Rights for Each Zone 2-Kbit Configuration Zone - 37-byte OTP Area for User-defined Codes - 160-byte Area for User-defined Keys and Passwords High Security Features - 64-bit Patented Dynamic Symetric Mutual Authentication Protocol - Encrypted Checksum - Stream Encryption - Four Key Sets for Authentication and Encryption - Eight Sets of Two 24-bit Passwords - Anti-tearing Function - Voltage and Frequency Monitor Smart Card Features - ISO 7816 Class A (5V) or Class B (3V) Operation - ISO 7816-3 Asynchronous T = 0 Protocol (Gemplus(R) Patent) - Multiple Zones, Key Sets and Passwords for Multi-application Use - Synchronous 2-wire Serial Interface for Faster Device Initialization - Programmable 8-byte Answer-To-Reset Register - ISO 7816-2 Compliant Modules Embedded Application Features - Low Voltage Operation: 2.7V to 5.5V - Secure Nonvolatile Storage for Sensitive System or User Information - 2-wire Serial Interface - 1.5 MHz Compatibility for Fast Operation - Standard 8-lead Plastic Packages - Same Pinout as 2-wire Serial EEPROM's High Reliability - Endurance: 100,000 Cycles - Data Retention: 10 years - ESD Protection: 4,000V min
* *
CryptoMemory 1 Kbit AT88SC0104C
*
Summary
*
*
Table 1. Pin Configuration
Pad VCC GND SCL/CLK SDA/IO RST Description Supply Voltage Ground Serial Clock Input Serial Data Input/Output Reset Input ISO Module Contact C1 C5 C3 C7 C2 Standard Package Pin 8 4 6 5 NC
Smart Card Module
VCC=C1 RST=C2 SCL/CLK=C3 NC=C4 C5=GND C6=NC C7=SDA/IO C8=NC
8-lead SOIC, PDIP
NC NC NC GND
8-lead SAP
VCC NC SCL SDA VCC NC SCL SDA
1 2 3 4
8 7 6 5
8 7 6 5
1 2 3 4
NC NC NC GND
Bottom view
Rev. 2021GS-SMEM-7/06
Note: This is a summary document. A complete document is available under NDA. For more information, please contact your local Atmel sales office.
1
Description
The AT88SC0104C member of the CryptoMemory(R) family is a high-performance secure memory providing 1 Kbit of user memory with advanced security and cryptographic features built in. The user memory is divided into four 32-byte zones, each of which may be individually set with different security access rights or combined together to provide space for 1 to 4 data files. The AT88SC0104C provides high security, low cost, and ease of implementation without the need for a microprocessor operating system. The embedded cryptographic engine provides for dynamic, symmetric-mutual authentication between the device and host, as well as performing stream encryption for all data and passwords exchanged between the device and host. Up to four unique key sets may be used for these operations. The AT88SC0104C offers the ability to communicate with virtually any smart card reader using the asynchronous T = 0 protocol (Gemplus Patent) defined in ISO 7816-3. Through dynamic, symmetric-mutual authentication, data encryption, and the use of encrypted checksums, the AT88SC0104C provides a secure place for storage of sensitive information within a system. With its tamper detection circuits, this information remains safe even under attack. A 2-wire serial interface running at 1.5 MHz is used for fast and efficient communications with up to 15 devices that may be individually addressed. The AT88SC0104C is available in industry standard 8-lead packages with the same familiar pinout as 2-wire serial EEPROMs. Figure 1. Block Diagram
Smart Card Applications
Embedded Applications
VCC GND
Power Management
Authentication, Encryption and Certification Unit
Random Generator
Synchronous Interface SCL/CLK SDA/IO RST Asynchronous ISO Interface Reset Block
Data Transfer Password Verification Answer to Reset
EEPROM
Pin Descriptions
Supply Voltage (VCC) Clock (SCL/CLK) The VCC input is a 2.7V to 5.5V positive voltage supplied by the host. In the asynchronous T = 0 protocol, the SCL/CLK input is used to provide the device with a carrier frequency f. The nominal length of one bit emitted on I/O is defined as an "elementary time unit" (ETU) and is equal to 372/f. When the synchronous protocol is used, the SCL/CLK input is used to positive edge clock data into the device and negative edge clock data out of the device. The AT88SC0104C provides an ISO 7816-3 compliant asynchronous answer to reset sequence. When the reset sequence is activated, the device will output the data pro-
Reset (RST)
2
AT88SC0104C
2021GS-SMEM-7/06
AT88SC0104C
grammed into the 64-bit answer-to-reset register. An internal pull-up on the RST input pad allows the device to be used in synchronous mode without bonding RST. The AT88SC0104C does not support the synchronous answer-to-reset sequence. Serial Data (SDA/IO) The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wired with any number of other open drain or open collector devices. An external pull-up resistor should be connected between SDA and V CC . The value of this resistor and the system capacitance loading the SDA bus will determine the rise time of SDA. This rise time will determine the maximum frequency during read operations. Low value pull-up resistors will allow higher frequency operations while drawing higher average power supply current. SDA/IO information applies to both asynchronous and synchronous protocols. When the synchronous protocol is used, the SCL/CLK input is used to positive edge clock data into the device and negative edge clock data out of the device. Table 2. DC Characteristics
Applicable over recommended operating range from VCC = +2.7 to 5.5V, TAC = -40oC to +85oC (unless otherwise noted) Symbol VCC ICC ICC ICC ICC ISB VIL VIL VIL VIH VIH VIH IIL IIL IIL IIH IIH IIH VOH VOL IOH Note: Parameter Supply Voltage Supply Current (VCC = 5.5V) Supply Current (VCC = 5.5V) Supply Current (VCC = 5.5V) Supply Current (VCC = 5.5V) Standby Current (VCC = 5.5V) SDA/IO Input Low Threshold(1) SCL/CLK Input Low Threshold(1) RST Input Low Threshold
(1) (1) (1)
Test Condition
Min 2.7
Typ
Max 5.5 5 5 5 5 100
Units V mA mA mA mA uA V V V V V V uA uA uA uA uA uA V V uA
Async READ at 3.57MHz Async WRITE at 3.57MHz Synch READ at 1MHz Synch WRITE at 1MHz VIN = VCC or GND 0 0 0 VCC x 0.7 VCC x 0.7 VCC x 0.7 0 < VIL < VCC x 0.15 0 < VIL < VCC x 0.15 0 < VIL < VCC x 0.15 VCC x 0.7 < VIH < VCC VCC x 0.7 < VIH < VCC VCC x 0.7 < VIH < VCC 20K ohm external pull-up IOL = 1mA VCC x 0.7 0
VCC x 0.2 VCC x 0.2 VCC x 0.2 VCC VCC VCC 15 15 50 20 100 150 VCC VCC x 0.15 20
SDA/IO Input High Threshold
(1)
SCL/CLK Input High Threshold RST Input High Threshold SDA/IO Input Low Current SCL/CLK Input Low Current RST Input Low Current SDA/IO Input High Current SCL/CLK Input High Current RST Input High Current SDA/IO Output High Voltage SDA/IO Output Low Voltage
SDA/IO Output High Current VOH 1. VIIL min and VIH max are reference only and are not tested.
3
2021GS-SMEM-7/06
Table 3. AC Characteristics
Applicable over recommended operating range from VCC = +2.7 to 5.5V, TAC = -40oC to +85oC, CL = 30pF (unless otherwise noted) Symbol fCLK fCLK fCLK tR tF tR tF tAA tHD.STA tSU.STA tHD.DAT tSU.DAT tSU.STO tDH tWR Parameter Async Clock Frequency (VCC Range: +4.5 - 5.5V) Async Clock Frequency (VCC Range: +2.7 - 3.3V) Synch Clock Frequency Clock Duty cycle Rise Time - I/O, RST Fall Time - I/O, RST Rise Time - CLK Fall Time - CLK Clock Low to Data Out Valid Start Hold Time Start Set-up Time Data In Hold Time Data In Set-up Time Stop Set-up Time Data Out Hold Time Write Cycle Time 200 200 10 100 200 20 9 Min 1 1 0 40 Max 5 4 1 60 1 1 9% x period 9% x period 35 Units MHz MHz MHz % uS uS uS uS nS nS nS nS nS nS nS mS
Device Operation For Synchronous Protocols
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 4 on page 5). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 5 on page 6). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 5 on page 6). ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle. MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2wire part can be reset by following these steps: 1. Clock up to 9 cycles. 2. Look for SDA high in each cycle while SCL is high. 3. Create a start condition.
4
AT88SC0104C
2021GS-SMEM-7/06
AT88SC0104C
Figure 2. Bus Timing for 2 wire communications SCL: Serial Clock, SDA: Serial Data I/O
Figure 3. Write Cycle Timing: SCL: Serial Clock, SDA: Serial Data I/O
SCL
SDA
8th BIT WORDn
ACK
twr STOP CONDITION
Note:
(1)
START CONDITION
The write cycle time twr is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
Figure 4. Data Validity
5
2021GS-SMEM-7/06
Figure 5. Start and Stop Definition
Figure 6. Output Acknowledge
Device Architecture
User Zones
The EEPROM user memory is divided into 4 zones of 256 bits each. Multiple zones allow for different types of data or files to be stored in different zones. Access to the user zones is allowed only after security requirements have been met. These security requirements are defined by the user during the personalization of the device in the configuration zone. If the same security requirements are selected for multiple zones, then these zones may effectively be accessed as one larger zone. Table 4. User Zones
ZONE $0 $1 $2 $3 $4 $5 $6 $7 $000 32 bytes User 0 - $018 -
6
AT88SC0104C
2021GS-SMEM-7/06
AT88SC0104C
Table 4. User Zones
ZONE $0 $1 $2 $3 $4 $5 $6 $7 $000 32 bytes User 1 - $018 $000 32 bytes User 2 - $018 $000 32 bytes User 3 - $018 - - -
Control Logic
Access to the user zones occurs only through the control logic built into the device. This logic is configurable through access registers, key registers and keys programmed into the configuration zone during device personalization. Also implemented in the control logic is a cryptographic engine for performing the various higher-level security functions of the device. The configuration zone consists of 2048 bits of EEPROM memory used for storing passwords, keys and codes and defining security levels to be used for each user zone. Access rights to the configuration zone are defined in the control logic and may not be altered by the user. Table 5. Configuration Zone
Component Answer to Reset Fab Code Memory Test Zone Card Manufacturers Code Lot History Code Device Configuration Register Identification Number Access Registers Password/Key Registers Issuer Code Authentication Attempts Counters Cryptograms Session Encryption Keys $50 $18 Address $00
Configuration Zone
7
2021GS-SMEM-7/06
Table 5. Configuration Zone
Secret Seeds Password Attempts Counters Write Passwords Read Passwords Reserved $B0
Security Fuses
There are three fuses on the device that must be blown during the device personalization process. Each fuse locks certain portions of the configuration zone as OTP memory. Fuses are designed for the module manufacturer, card manufacturer and card issuer and should be blown in sequence, although all programming of the device and blowing of the fuses may be performed at one final step. The AT88SC0104C supports two different communication protocols. * * Smart Card Applications: The asynchronous T = 0 protocol defined by ISO 7816-3 is used for compatibility with the industry's standard smart card readers. Embedded Applications: A 2-wire serial interface is used for fast and efficient communication with logic or controllers.
Protocol Selection
The power-up sequence determines which of the two communication protocols will be used.
Asynchronous T = 0 Protocol
This power-up sequence complies with ISO 7816-3 for a cold reset in smart card applications. * * * * VCC goes high; RST, I/O-SDA and CLK-SCL are low. Set I/O-SDA in receive mode. Provide a clock signal to CLK-SCL. RST goes high after 400 clock cycles.
The device will respond with a 64-bit ATR code, including historical bytes to indicate the memory density within the CryptoMemory family. Once the asynchronous mode has been selected, it is not possible to switch to the synchronous mode without powering off the device. Figure 7. Asynchronous T = 0 Protocol (Gemplus Patent)
Vcc I/O-SDA RST CLK-SCL ATR
8
AT88SC0104C
2021GS-SMEM-7/06
AT88SC0104C
Synchronous 2-wire Serial Interface
The synchronous mode is the default after powering up VCC due to the internal pull-up on RST. For embedded applications using CryptoMemory in standard plastic packages, this is the only communication protocol. * * Power-up VCC, RST goes high also. After stable VCC, CLK-SCL and I/O-SDA may be driven.
Figure 8. Synchronous 2-wire Protocol
Vcc I/O-SDA RST CLK-SCL
Note:
1
2
3
4
5
Five clock pulses must be sent before the first command is issued.
Communication Security Modes
Communications between the device and host operate in three basic modes. Standard mode is the default mode for the device after power-up. Authentication mode is activated by a successful authentication sequence. Encryption mode is activated by a successful encryption activation following a successful authentication.
Table 6. Communication Security Modes(1)
Mode Standard Authentication Encryption Note: Configuration Data Clear Clear Clear User Data Clear Clear Encrypted Passwords Clear Encrypted Encrypted Data Integrity Check MDC(1) MAC(1) MAC(1)
1. Configuration data include viewable areas of the Configuration Zone except the passwords: MDC: Modification Detection Code. MAC: Message Authentication Code.
Security Options
Anti-tearing
In the event of a power loss during a write cycle, the integrity of the device's stored data may be recovered. This function is optional: the host may choose to activate the antitearing function, depending on application requirements. When anti-tearing is active, write commands take longer to execute, since more write cycles are required to complete them, and data are limited to eight bytes. Data are written first to a buffer zone in EEPROM instead of the intended destination address, but with the same access conditions. The data are then written in the required location. If this second write cycle is interrupted due to a power loss, the device will automatically recover the data from the system buffer zone at the next power-up. In 2-wire mode, the host is required to perform ACK polling for up to 8 ms after write commands when anti-tearing is active. At power-up, the host is required to perform ACK polling, in some cases for up to 2 ms, in the event that the device needs to carry out the data recovery process.
9
2021GS-SMEM-7/06
Write Lock
If a user zone is configured in the write lock mode, the lowest address byte of an 8-byte page constitutes a write access byte for the bytes of that page. Example: The write lock byte at $080 controls the bytes from $080 to $087.
$080 11011001
$081 xxxx xxxx locked
$082 xxxx xxxx locked
$083 xxxx xxxx
$084 xxxx xxxx
$085 xxxx xxxx locked
$086 xxxx xxxx
$087 xxxx xxxx
@ $80
The write lock byte may also be locked by writing its least significant (rightmost) bit to "0". Moreover, when write lock mode is activated, the write lock byte can only be programmed -- that is, bits written to "0" cannot return to "1". In the write lock configuration, only one byte can be written at a time. Even if several bytes are received, only the first byte will be taken into account by the device.
Password Verification
Passwords may be used to protect read and/or write access of any user zone. When a valid password is presented, it is memorized and active until power is turned off, unless a new password is presented or RST becomes active. There are eight password sets that may be used to protect any user zone. Only one password is active at a time, but write passwords give read access also. The access to a user zone may be protected by an authentication protocol. Any one of four keys may be selected to use with a user zone. The authentication success is memorized and active as long as the chip is powered, unless a new authentication is initialized or RST becomes active. If the new authentication request is not validated, the card loses its previous authentication and it should be presented again. Only the last request is memorized.
Note: Password and authentication may be presented at any time and in any order. If the trials limit has been reached (after four consecutive incorrect attempts), the password verification or authentication process will not be taken into account.
Authentication Protocol
Figure 9. Password and Authentication Operations
VERIFY RPW DATA Checksum (CS)
VERIFY CS
VERIFY CS Write DATA
CS
10
AT88SC0104C
2021GS-SMEM-7/06
AT88SC0104C
Checksum
The AT88SC0104C implements a data validity check function in the form of a checksum, which may function in standard, authentication or encryption modes. In the standard mode, the checksum is implemented as a Modification Detection Code (MDC), in which the host may read an MDC from the device in order to verify that the data sent was received correctly. In the authentication and encryption modes, the checksum becomes more powerful since it provides a bidirectional data integrity check and data origin authentication capability in the form of a Message Authentication Code (MAC). Only the host/device that carried out a valid authentication is capable of computing a valid MAC. While operating in the authentication or encryption modes, the use of a MAC is required. For an ingoing command, if the device calculates a MAC different from the MAC transmitted by the host, not only is the command abandoned but the mode is also reset. A new authentication and/or encryption activation will be required to reactivate the MAC.
Encryption
The data exchanged between the device and the host during read, write and verify password commands may be encrypted to ensure data confidentiality. The issuer may choose to require encryption for a user zone by settings made in the configuration zone. Any one of four keys may be selected for use with a user zone. In this case, activation of the encryption mode is required in order to read/write data in the zone and only encrypted data will be transmitted. Even if not required, the host may elect to activate encryption provided the proper keys are known.
Supervisor Mode Modify Forbidden
Enabling this feature allows the holder of one specific password to gain full access to all eight password sets, including the ability to change passwords. No write access is allowed in a user zone protected with this feature at any time. The user zone must be written during device personalization prior to blowing the security fuses. For a user zone protected by this feature, data within the zone may be changed from a "1" to a "0", but never from a "0" to a "1". To enable the security features of CryptoMemory, the device must first be personalized to set up several registers and load in the appropriate passwords and keys. This is accomplished through programming the configuration zone of CryptoMemory using simple write and read commands. To gain access to the configuration zone, the secure code must first be successfully presented. For the AT88SC0104C device, the secure code is $DD 42 97. After writing and verifying data in the configuration zone, the security fuses must be blown to lock this information in the device. For additional information on personalizing CryptoMemory, please see the application notes Programming CryptoMemory for Embedded Applications and Initializing CryptoMemory for Smart Card Applications (at www.Atmel.com).
Program Only
Initial Device Programming
11
2021GS-SMEM-7/06
Ordering Information
Ordering Code AT88SC0104C-MJ AT88SC0104C-MP AT88SC0104C-PI AT88SC0104C-SI AT88SC0104C-Y4I AT88SC0104C-PU AT88SC0104C-SU AT88SC0104C-Y4U AT88SC0104C-WI Package M2 - J Module M2 - P Module 8P3 8S1 8Y4 8P3 8S1 8Y4 7 mil wafer Voltage Range 2.7V-5.5V Temperature Range Commercial (0C-70C)
2.7V-5.5V
Industrial (-40C-85C)
2.7V-5.5V 2.7V-5.5V
Lead-free/Halogen-free/Industrial (-40C-85C) Industrial (-40C-85C)
Package Type(1) M2 - J Module M2 - P Module 8P3 8S1 8Y4 Note:
Description M2 ISO 7816 Smart Card Module M2 ISO 7816 Smart Card Module with Atmel(R) Logo 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8-lead, 6.00 mm x 4.90 mm Body, SOIC Array Package (SAP)
1. Formal drawings may be obtained from an Atmel sales office.
12
AT88SC0104C
2021GS-SMEM-7/06
AT88SC0104C
Packaging Information
Ordering Code: MJ
Module Size: M2 Dimension*: 12.6 x 11.4 [mm] Glob Top: Round - 8.5 [mm] Thickness: 0.58 [mm] Pitch: 14.25 mm
Ordering Code: MP
Module Size: M2 Dimension*: 12.6 x 11.4 [mm] Glob Top: Square - 8.8 x 8.8 [mm] Thickness: 0.58 [mm] Pitch: 14.25 mm
*Note: The module dimensions listed refer to the dimensions of the exposed metal contact area. The actual dimensions of the module after excise or punching from the carrier tape are generally 0.4 mm greater in both directions (i.e., a punched M2 module will yield 13.0 x 11.8 mm).
13
2021GS-SMEM-7/06
Ordering Code: SI, SU 8-lead SOIC
C
1
E
E1
N
L
Top View End View
e B A
SYMBOL COMMON DIMENSIONS (Unit of Measure = mm) MIN 1.35 0.10 0.31 0.17 4.80 3.81 5.79 NOM - - - - - - - 1.27 BSC 0.40 0 - - 1.27 8 MAX 1.75 0.25 0.51 0.25 5.00 3.99 6.20 NOTE
A1
A A1 b C
D
D E1 E
Side View
e L
Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. 8S1 REV. B
R
14
AT88SC0104C
2021GS-SMEM-7/06
AT88SC0104C
Ordering Code: PI, PU 8-lead PDIP
1
E E1
N
Top View
c eA
End View
D e D1 A2 A
SYMBOL
COMMON DIMENSIONS (Unit of Measure = inches) MIN NOM MAX NOTE
A A2 b b2 b3 c D 0.115 0.014 0.045 0.030 0.008 0.355 0.005 0.300 0.240 0.310 0.250 0.100 BSC 0.300 BSC 0.115 0.130 0.130 0.018 0.060 0.039 0.010 0.365
0.210 0.195 0.022 0.070 0.045 0.014 0.400
2
5 6 6
3 3
b2 b3
4 PLCS
L
D1 E E1 e eA L
b
0.325 0.280
4 3
Side View
4 0.150 2
Notes:
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. 8P3 REV. B
R
15
2021GS-SMEM-7/06
Ordering Code: Y4I, Y4U 8-lead SAP
PIN 1 INDEX AREA
A
PIN 1 ID
D E1
D1
L
E
A1 b e1 A
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 D E D1 E1 b e e1 L 0.50 MIN - 0.00 5.80 4.70 2.85 2.85 0.35 NOM - - 6.00 4.90 3.00 3.00 0.40 1.27 TYP 3.81 REF 0.60 0.70 MAX 0.90 0.05 6.20 5.10 3.15 3.15 0.45 NOTE
e
5/24/04 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80817 TITLE 8Y4, 8-lead (6.00 x 4.90 mm Body) SOIC Array Package (SAP) Y4 DRAWING NO. 8Y4 REV. A
R
16
AT88SC0104C
2021GS-SMEM-7/06
Atmel Corporation
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
Atmel Operations
Memory
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314
RF/Automotive
Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759
Regional Headquarters
Europe
Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500
Microcontrollers
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60
Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom
Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80
Asia
Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369
ASIC/ASSP/Smart Cards
Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743
Japan
9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Literature Requests
www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
(c) 2006 Atmel Corporation. All rights reserved. Atmel(R), logo and combinations thereof, Everywhere You Are (R), CryptoMemory (R) and others, are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.
Printed on recycled paper.
2021GS-SMEM-7/06


▲Up To Search▲   

 
Price & Availability of AT88SC0104C

All Rights Reserved © IC-ON-LINE 2003 - 2022  

[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy]
Mirror Sites :  [www.datasheet.hk]   [www.maxim4u.com]  [www.ic-on-line.cn] [www.ic-on-line.com] [www.ic-on-line.net] [www.alldatasheet.com.cn] [www.gdcy.com]  [www.gdcy.net]


 . . . . .
  We use cookies to deliver the best possible web experience and assist with our advertising efforts. By continuing to use this site, you consent to the use of cookies. For more information on cookies, please take a look at our Privacy Policy. X