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| MIC5162 Micrel, Inc. MIC5162 Dual Regulator Controller For High-Speed Bus Termination General Description The MIC5162 is a dual regulator controller designed for highspeed bus termination. It offers a simple, low-cost JEDEC compliant solution for terminating high-speed, low-voltage digital buses (i.e. DDR, SCSI, GTL, SSTL, HSTL, LV-TTL, Rambus, LV-PECL, LV-ECL, etc). The MIC5162 controls two external N-Channel MOSFETs to form two separate regulators. It operates by switching between either the high-side MOSFET or the low-side MOSFET depending on whether the current is being sourced to the load or sinked by the regulator. Designed to provide a universal solution for bus termination regardless of input voltage, output voltage, or load current, the desired MIC5162 output voltage can be programmed by externally forcing the reference voltage. The MIC5162 operates from an input of 1.35V to 6V, with a second bias supply input required for operation. It is available in the tiny MSOP-10 package with operating junction temperature range of -40C to +125C. Features * JEDEC Compliant Bus Termination for SCSI, GTL, SSTL, HSTL, LV-TTL, Rambus, LV-PECL, LV-ECL, etc. * DDR memory termination * Tracking programmable output * Requires minimal external components * Wide bandwidth * Input voltage range: 1.35V to 6V * Logic controlled enable input * Tiny MSOP-10 package * Available -40C < TJ < +125C Applications * * * * Desktop computers Notebook computers Communication systems Video cards Ordering Information Part Number Standard Pb-Free MIC5162BMM MIC5162YMM Junction Temp Range -40C to +125C Package 10-Pin MSOP Typical Application Load Transient VIN=2.5V to 1.5V VDDQ = 1.35V to 6.0V MIC5162BMM SUD50N02-06 120pF VTT = 1/2 VDDQ COUT = 330F Sink 3A SOURCE (2A/div) 0A Source 3A VDDQ VREF VCC VCC = 5.0V EN EN COMP 220pF FB LD GND HD 3k Typical SSTL-2 Application VTT - VREF (50mV/div) TIME (200s/div) Micrel, Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel + 1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com February 2005 1 M9999-092004 MIC5162 Micrel, Inc. Pin Configuration VCC 1 EN 2 VDDQ 3 VREF 4 GND 5 10 N/C 9 HD 8 LD 7 COMP 6 FB 10-Lead MSOP Pin Description Pin Number Pin Name VCC EN VDDQ VREF GND FB Comp LD HD N/C Pin Function Bias Supply Input. Apply 5V to this input for internal bias to the controller. Enable (Input): CMOS compatible input. Logic high = enable, logic low = shutdown. Input supply voltage. Reference output equal to half of VDDQ. Ground. Feedback input to the to the internal error amplifier. Compensation (Output): Connect a capacitor to feedback pin for compensation of the internal control loop. Low-side drive: Connects to the Gate of the external low side MOSFET. High-side drive: Connects to the Gate of the external high side MOSFET. Not internally connected. 1 2 3 4 5 6 7 8 9 10 M9999-092004 2 February 2005 MIC5162 Micrel, Inc. Absolute Maximum Ratings (Note 1) Supply Voltage (VCC) ...................................................... 7V Supply Voltage (VDDQ) .................................................... 7V Enable Input Voltage (VEN) ............................................. 7V Junction Temperature Range ............ -40C < TJ < +125C Operating Ratings (Note 2) Supply Voltage (VCC) ............................................ 3V to 6V Supply Voltage (VDDQ) ....................................... 1.35V - 6V Enable Input Voltage (VEN) .................................. 0V to VIN Electrical Characteristics TA = 25C with VDDQ = 2.5V; VCC = 5V; VEN = VCC; bold values indicate -40C Note 1. Note 2. Note 3. Note 4. Condition Min -1% -5 -10 -5 -10 Typ 0.5VDDQ 0.4 0.6 120 15 10 8 Max 1% 5 -10 5 10 140 200 20 25 35 15 30 Units V mV mV A mA A s VEN = 1.2V (controller ON) No Load No Load VEN = 0.2V (controller OFF) VCC, = 5V external bias; VEN = VIN 1.2 0.3 40 0.01 5.5 V V mV A A High Side MOSFET Fully ON High Side MOSFET Fully OFF Low Side MOSFET Fully ON Low Side MOSFET Fully OFF 4.8 4.97 0.03 0.2 V V V 0.2 V 4.8 4.97 0.03 Exceeding the absolute maximum ratings may damage the device. The VTT voltage accuracy is measured as a delta voltage from the reference output (VTT - VREF). Shutdown current is measured only on the VCC pin. The VDDQ pin will always draw a minimum amount of current when voltage is applied. Start-up time is defined as the amount of time from VEN = VCC to HSD = 90% of VCC. February 2005 3 M9999-092004 MIC5162 Micrel, Inc. Test Circuit VDDQ = 1.8V or 2.5V MIC5162BMM VDDQ VCC VCC = 5.0V EN 220F 10F 470pF EN LD 120pF HD SUD50N02-06 VTT COUT = 3 x 560F COMP VREF FB GND 10k Figure 1. Test Circuit M9999-092004 4 February 2005 MIC5162 Micrel, Inc. Typical Characteristics [VTT-VREF] vs. Output Current [VTT-VREF] vs. Temperature [VTT-VREF] vs. Temperature 5 4 3 [VTT-V REF] (mV) 10 8 6 [VTT-V REF] (mV) 10 8 6 [VTT-V REF] (mV) 2 1 0 -1 -2 -3 -4 -5 -3 4 2 0 -2 -4 -6 -8 SINK 3A -10 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) 4 2 0 -2 -4 -6 -8 SOURCE 3A -10 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) -2 -1 0 1 2 OUTPUT CURRENT (A) 3 1.2625 VREF vs. Temperature SOURCE CURRENT (mA) 18 16 14 12 10 8 6 4 2 0 0 VCC Current vs. Input Voltage SOURCE CURRENT (mA) 20 18 16 14 12 10 8 6 4 VCC Current vs. Temperature 1.2600 VDDQ = 2.5V 1.2575 VREF (V) 1.2550 1.2525 1.2500 1.2475 1.2450 1.2425 1.2400 1.2375 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) 1 2 3 4 5 INPUT VOLTAGE (V) 6 2 V = 5V CC 0 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) February 2005 5 M9999-092004 MIC5162 Micrel, Inc. Functional Diagram VDDQ VCC R1 A VREF HD -A R2 Shutdown EN LD GND FB COMP Block Diagram M9999-092004 6 February 2005 MIC5162 Micrel, Inc. VDDQ The VDDQ pin on the MIC5162 provides the source current through the high side N-Channel and the reference voltage to the device. The MIC5162 can operate at VDDQ voltages as low as 1.35V. Due to the possibility of large transient currents being sourced from this line, significant bypass capacitance will aid in performance by improving the source impedance at higher frequencies. Since the reference is simply VDDQ/2, perturbations on the VDDQ will also appear at half the amplitude on the reference. For this reason, low ESR capacitors such as ceramics or Oscons are recommended on VDDQ. VTT VTT is the actual termination point. VTT is regulated to VREF. Due to high speed signaling, the load current seen by VTT is constantly changing. To maintain adequate large signal transient response, large Oscons ceramics are recommended on VTT. The proper combination and placement of the Oscon and ceramic capacitors is important to reduce both ESR and ESL such that high-current high-speed transients do not exceed the dynamic voltage tolerance requirement of VTT. The larger Oscon capacitors provide bulk charge storage while the smaller ceramic capacitors provide current during the fast edges of the bus transition. Using several smaller ceramic capacitors distributed near the termination resistors is typically important to reduce the effects of PCB trace inductance. VREF Two resistors dividing down the VDDQ voltage provide VREF (Figure 3). The resistors are valued at around 17k. A minimum capacitor value of 120pF from VREF to ground is required to remove high frequency signals reflected from the source. Large capacitance values (>1500pF) should be avoided. Values greater than 1500pF slow down VREF and detract from the reference voltage's ability to track VDDQ during high speed load transients. Applications Information High performance memory requires high speed signaling. This increase in speed requires special attention to maintain signal integrity. Bus termination provides a means to increase signaling speed while maintaining good signal integrity. An example of bus termination is the Series Stub Termination Logic or SSTL. Figure 1 is an example of an SSTL 2 single ended series parallel terminated output. SSTL 2 is a JEDEC signaling standard operating off of a 2.5V supply. It consists of a series resistor (RS) and a terminating resistor (RT). Values of RS will range between 10 to 30 with a typical of 22, while RT will range from 22 to 28 with a typical value of 25. VREF must maintain 1/2 VDD with a 1% tolerance, while VTT will dynamically sink and source current to maintain a termination voltage of 40mV from the VREF line under all conditions. This method of bus termination reduces common mode noise, settling time, voltage swings, EMI/RFI and improves slew rates. VDDQ VTT MEMORY RT RS VREF Figure 1. The MIC5162 is a high performance linear controller, utilizing scalable N-Channel MOSFETs to provide JEDEC compliant bus termination. Termination is achieved by dividing down the VDDQ voltage by half, providing the reference (VREF) voltage. An internal error amplifier compares the termination voltage (VTT) and VREF, controlling 2 external N-Channel MOSFETs to sink and/or source current to maintain a termination voltage (VTT) equal to VREF. The N-Channels receive their enhancement voltage from a separate VCC pin on the device. Although the general discussion is focused on SSTL, the MIC5162 is also capable of providing bus terminations for SCSI, GTL, HSTL, LV-TTL, Rambus, LV-PECL and other systems. Vishay SUD50N02-06 MIC5162BMM 100F Oscon 1F Ceramic 120pF VDDQ VCC LD VREF COMP GND FB 220pF 3k HD Vishay SUD50N02-06 330F Oscon Figure 2. February 2005 7 M9999-092004 MIC5162 VDDQ VREF 120pF GND Micrel, Inc. tance. Although a 10F ceramic capacitor will suffice for most applications, input capacitance may need to be increased in cases where the termination circuit is greater than 1" away from the bulk capacitance. Output Capacitance Large, low ESR capacitors are recommended for the output (VTT) of the MIC5162. Although low ESR capacitors are not required for stability, they are recommended to reduce the effects of high-speed current transients on VTT. The change in voltage during the transient condition will be the effect of the peak current multiplied by the output capacitor's ESR. For that reason, Oscon type capacitors are excellent for this application. They have extremely low ESR and large capacitance-to-size ratio. Ceramic capacitors are also well suited to termination due to their low ESR. These capacitors should have a dielectric rating of X5R or X7R. Y5V and Z5U type capacitors are not recommended, due to their poor performance at high frequencies and over temperature. The minimum recommended capacitance for a 3 amp peak circuit is 100F. Output capacitance can be increased to achieve greater transient performance. MOSFET Selection The MIC5162 utilizes external N-Channel MOSFETs to sink and source current. MOSFET selection will settle to two main categories: size and gate threshold (VGS). MOSFET Power Requirements One of the most important factors is to determine the amount of power the MOSFET is going to be required to dissipate. Power dissipation in an SSTL circuit will be identical for both the high side and low side MOSFETs. Since the supply voltage is divided by half to supply VTT, both MOSFETs have the same voltage dropped across them. They are also required to be able to sink and source the same amount of current (for either all 0's or all 1's). This equates to each side being able to dissipate the same amount of power. Power dissipation calculation for the high-side driver is as follows: PD = (VDDQ - VTT ) x I _ SOURCE Figure 3. VREF can also be manipulated for different applications. A separate voltage source can be used to externally set the reference point, bypassing the divider network. Also, external resistors can be added from VREF to ground or VREF to VDDQ to shift the reference point up or down. VCC VCC supplies the internal circuitry of the MIC5162 and provides the drive voltage to enhance the external N-Channel MOSFETs. A small 1F capacitor is recommended for bypassing the VCC pin. The minimum VCC voltage should be a gate-source voltage above VTT without exceeding 6V. For example, on an SSTL compliant terminator, VDDQ equals 2.5V and VTT equals 1.25V. If the N-Channel MOSFET selected requires a gate source voltage of 2.5V, VCC should be a minimum of 3.75V. Feedback and Compensation The feedback provides the path for the error amplifier to regulate VTT. An external resistor must be placed between the feedback and VTT. This allows the error amplifier to be correctly externally compensated. For most applications, a 3k resistor is recommended. The COMP pin on the MIC5162 is the output of the internal error amplifier. By placing a capacitor between the COMP pin and the feedback pin, this coupled with the feedback resistor places an external pole on the error amplifier. With a 3k feedback resistor, a minimum 220pF capacitor is recommended for a 3A peak termination circuit. Increases in load, multiple N-Channel MOSFETs and/or increase in output capacitance may require feedback and/or compensation capacitor values to be increased to maintain stability. Feedback resistor values should not exceed 100k and compensation capacitors should not be less than 40pF. Enable The MIC5162 features an active high enable input. In the off mode state, leakage currents are reduced to microamperes. The enable input has thresholds compatible with TTL/CMOS for simple logic interfacing. The enable pin can be tied directly to VDDQ or VCC for functionality. Do not float the enable pin. Floating this pin causes the enable to be in an indeterminate state. Input Capacitance Although the MIC5162 does not require an input capacitor for stability, using one greatly improves device performance. Due to the high-speed nature of the MIC5162, low ESR capacitors such as Oscon and ceramics are recommended for bypassing the input. The recommended value of capacitance will depend greatly on the proximity to the bulk capaciM9999-092004 8 Where I_source is the average source current. Power dissipation for the low-side MOSFET is as follows; PD = VTT x I _ SINK Where I_sink is the average sink current. In a typical 3 amp peak SSTL_2 circuit, power considerations for MOSFET selection would occur as follows. PD = (VDDQ - VTT ) x I _ SOURCE PD = (2.5V - 1.25V) x 1.6A PD = 2W This typical SSTL_2 application would require both high-side and low-side N-Channel MOSFETs to be able to handle 2 Watts each. In applications where there is excessive power dissipation, multiple N-Channel MOSFETs may be placed in parallel. These MOSFETs will share current, distributing power dissipation across each device. February 2005 MIC5162 The maximum MOSFET die (junction) temperature limits maximum power dissipation. The ability of the device to dissipate heat away from the junction is specified by the junction-to-ambient (JA) thermal resistance. This is the sum of junction-to-case (JC) thermal resistance, case-to-sink (CA) thermal resistance and sink-to-ambient (SA) thermal resistance; Micrel, Inc. MOSFET Gate Threshold N-Channel MOSFETs require an enhancement voltage greater than its source voltage. Typical N-Channel MOSFETs have a gate-source threshold (VGS) of 1.8V and higher. Since the source of the high side N-Channel is connected to VTT, the MIC5162 VCC pin requires a voltage equal to or greater than the VGS voltage. For example, our SSTL_2 termination circuit has a VTT voltage of 1.25V. For an NChannel that has a VGS rating of 2.5V, the VCC voltage can be as low as 3.75V. With an N-Channel that has a 4.5V VGS, the minimum VCC required is 5.75V. Although these NChannels are driven below their full enhancement threshold, it is recommended that the VCC voltage has enough margin to be able to fully enhance the MOSFETs for large signal transient response. In addition, low gate thresholds MOSFETs are recommended to reduce the VCC requirements. JA = JC + CS + SA In our example of a 3A peak SSTL_2 termination circuit, we have selected a D-pack N-Channel MOSFET that has a maximum junction temperature of 150C. The device has a junction-to-case thermal resistance of 1.5C/Watt. Our application has a maximum ambient temperature of 60C. The required junction-to-ambient thermal resistance can be calculated as follows; JA = TJ - TA PD Where TJ is the maximum junction temperature, TA is the maximum ambient temperature and PD is the power dissipation. In our example; JA = JA = JA TJ - TA PD 150C - 60C 2W = 45C/W This shows that our total thermal resistance must be better than 45C/W. Since the total thermal resistance is a combination of all the individual thermal resistances, the amount of heat sink required can be calculated as follows; SA = JA - (JC + CA ) In our example; SA = 45C/W - (1.5C/W + 0.5C/W ) SA = 43C/W In most cases, case-to-sink thermal resistance can be assumed to be about 0.5C/W. The SSTL termination circuit for our example, using 2 D-pack N-Channel MOSFETs (one high side and one on the low side) will require at least a 43C/W heat sink per MOSFET. This may be accomplished with an external heat sink or even just the copper area that the MOSFET is soldered to. In some cases, airflow may also be required to reduce thermal resistance. February 2005 9 M9999-092004 MIC5162 Micrel, Inc. SUB75N03-07 VDDQ = 1.8V SUB75N03-07 VDDQ VCC 5V EN 150F/10V Oscon 1F 10V 120pF VCC HSD VTT = 0.9V@+/-7A EN MIC5162BMM SUB75N03-07 VREF LSD Comp 220pF FB 3.01K SUB75N03-07 680F/4V Oscon GND GND Figure 4. DDR2 Termination MIC5162 DDR2 40 30 VTT - VREF (mV) 20 10 0 -10 -20 -30 -40 -7 -5 -3 -1 1 3 CURRENT (A) 5 7 OUTPUT CURRENT (5A/div) VTT AC COUPLED (20mV/div) TIME (200s/div) VTT AC COUPLED (20mV/div) OUTPUT CURRENT (5A/div) -7A Load Transient 7A Load Transient TIME (200s/div) M9999-092004 10 February 2005 MIC5162 Micrel, Inc. Package Information 3.15 (0.122) 2.85 (0.114) 4.90 BSC (0.193) DIMENSIONS: MM (INCH) 3.10 (0.122) 2.90 (0.114) 1.10 (0.043) 0.94 (0.037) 0.26 (0.010) 0.10 (0.004) 0.30 (0.012) 0.15 (0.006) 0.50 BSC (0.020) 0.15 (0.006) 0.05 (0.002) 6 MAX 0 MIN 0.70 (0.028) 0.40 (0.016) 10-Pin SOP (M) MICREL INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com This information furnished by Micrel in this data sheet is believed to be accurate and reliable. However no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2003 Micrel Incorporated February 2005 11 M9999-092004 |
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