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Rev 0; 4/06
Dual, 64-Position Nonvolatile Digital Potentiometer with Buffered Outputs
General Description
The DS3908 contains two nonvolatile digital potentiometers with programmable-gain amplifiers buffering the wiper outputs. The potentiometer position and amplifier gain are controlled through an I2C*-compatible serial bus. The DS3908 operates in both 3.3V and 5V systems and features a write-protect pin that locks the position of the potentiometers and gain registers. Up to eight DS3908s can be placed on a single I2C bus.
Features
o Two 64-Position Linear Taper Potentiometers o Integral Wiper Buffering Amplifiers with Selectable Gains of 1V/V, 2V/V, or 4V/V o 100k Potentiometer End-to-End Resistance o Low Potentiometer Temperature Coefficient o Nonvolatile Wiper and Gain Storage o I2C-Compatible Interface o Write-Protect Pin Prevents Accidental Field Reprogramming o 3V to 5.5V Supply Voltage Range o -40C to +85C Operating Temperature Range o 14-Pin TDFN Package
DS3908
Applications
Pin-Diode Biasing Power-Supply Calibration Cell Phones and PDAs Portable Electronics
PART DS3908N+
Ordering Information
TEMP RANGE -40C to +85C PIN-PACKAGE 14 TDFN
+Denotes lead-free package.
Typical Operating Circuit
TOP VIEW
VCC POT0 H0 PGA0 V0 L0 I2C INTERFACE POT1 PGA1 H1 VOLTAGE REFERENCE NV ADJUSTABLE REFERENCE VOLTAGE
Pin Configuration
SDA SCL A0 A1 A2
1 2 3 4
14 VCC 13 H1 12 V1 11 L1
+
DS3908
SDA SCL A0 A1 A2 WP
DS3908
5 6 7
10 H0 9 8 V0 L0
V1 L1
NV ADJUSTABLE REFERENCE VOLTAGE
WP GND
TDFN (3mm x 3mm)
I2C is a trademark of Philips Corp. Purchase of I2C components from Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
______________________________________________ Maxim Integrated Products
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Dual, 64-Position Nonvolatile Digital Potentiometer with Buffered Outputs DS3908
ABSOLUTE MAXIMUM RATINGS
Voltage on VCC, SDA, and SCL Relative to GND .....-0.5V to +6.0V Voltage on A0, A1, A2, L0, L1, H0, H1, and WP Relative to GND................-0.5V to (VCC + 0.5V) (not to exceed +6.0V) Operating Temperature Range ...........................-40C to +85C Programming Temperature Range .........................0C to +70C Storage Temperature Range .............................-55C to +125C Soldering Temperature ............Refer to J-STD-020 Specification
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = -40C to +85C.)
PARAMETER Supply Voltage Input Logic 1 (SCL, SDA, A0, A1, A2, WP) Input Logic 0 (SCL, SDA, A0, A1, A2, WP) Potentiometer Voltage (L0, L1, H0, H1) SYMBOL VCC VIH VIL VCC = +3.0V to +5.5V (Note 1) CONDITIONS MIN +3.0 0.7 x VCC -0.3 -0.3 TYP MAX +5.5 VCC + 0.3 0.3 x VCC VCC + 0.3V UNITS V V V V
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +5.5V, TA = -40C to +85C.)
PARAMETER Input Leakage Standby Supply Current Low-Level Output Voltage (SDA) I/O Capacitance WP Internal Pullup Resistance SYMBOL IL ISTBY VOL1 VOL2 CI/O RWP 40 65 VCC = 5.5V (Note 2) 3mA sink current 6mA sink current 0 0 CONDITIONS MIN -1 TYP MAX +1 2 0.4 0.6 10 100 UNITS A mA V pF k
ANALOG POTENTIOMETER CHARACTERISTICS
(VCC = +3.0V to +5.5V, TA = -40C to +85C.)
PARAMETER End-to-End Resistance Absolute Linearity Relative Linearity End-to-End Temperature Coefficient INL DNL SYMBOL +25C (Notes 3, 4) (Notes 4, 5) CONDITIONS MIN 79 -0.6 -0.25 50 TYP 100 MAX 121 +0.6 +0.25 UNITS k LSB LSB ppm/C
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Dual, 64-Position Nonvolatile Digital Potentiometer with Buffered Outputs
PROGRAMMABLE-GAIN AMPLIFIER CHARACTERISTICS
(VCC = +3.0V to +5.5V, TA = -40C to +85C.)
PARAMETER Common-Mode Input Voltage Gain Output Voltage Range Power-Supply Rejection Ratio Output Source Current Output Sink Current Unity-Gain Frequency Amplifier Capacitive Loading Input Offset Voltage Load Regulation Output-Voltage Slew Rate SYMBOL CMVIN RL 2k, G = 1V/V G VOUT PSRR IOUT:SOURCE IOUT:SINK fT CL VOS -1mA < IOUT < 1mA RL = 10k, CL = 10pF 270 -9 800 VOUT = 0V, Hx = Lx = 1V VOUT = 1V, Hx = Lx = 0V Gain = 1V/V, position 3Fh 15 3.5 100 +9 2200 840 RL 2k, G = 2V/V RL 2k, G = 4V/V RL = 2k, -1mA < IOUT < 1mA CONDITIONS MIN 0 0.975 1.925 3.850 0.3 60 90 -15 1 2 4 TYP MAX VCC - 1.5 1.025 2.05 4.10 VCC - 0.3 V dB mA mA MHz pF mV V/mA V/ms V/V UNITS V
DS3908
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +5.5V, TA = -40C to +85C.) (See Figure 2.)
PARAMETER SCL Clock Frequency Bus Free Time between STOP and START Conditions Hold Time (Repeated) START Condition Low Period of SCL High Period of SCL Data Hold Time Data Setup Time Start Setup Time SDA and SCL Rise Time SDA and SCL Fall Time STOP Setup Time SDA and SCL Capacitance EEPROM Write Time Startup Time SYMBOL fSCL tBUF tHD:STA tLOW tHIGH tHD:DAT tSU:DAT tSU:STA tR tF tSU:STO CB tW tST (Note 7) (Note 8) VCC = 3.0V 10 (Note 7) (Note 7) (Note 6) 1.3 0.6 1.3 0.6 0 100 0.6 20 + 0.1CB 20 + 0.1CB 0.6 400 17 40 300 300 0.9 CONDITIONS MIN TYP MAX 400 UNITS kHz s s s s s ns s ns ns s pF ms s
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Dual, 64-Position Nonvolatile Digital Potentiometer with Buffered Outputs DS3908
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +3.0V to +5.5V.)
PARAMETER EEPROM Write Cycles SYMBOL CONDITIONS At +70C MIN 50,000 MAX UNITS
Note 1: Note 2:
Note 3: Note 4: Note 5: Note 6: Note 7: Note 8:
All voltages are referenced to ground. ISTBY specified assuming control pins are connected as follows: WP must be disconnected or connected high. H terminal connected to VCC, L terminal connected to GND, potentiometer position 1Dh, PGA is at 2V/V, A0 to A2 connected to VCC, SDA and SCL connected to VCC, with no load. Absolute linearity is used to measure expected wiper voltage as determined by wiper position in a voltage-divider configuration. This specification only refers to the potentiometers, and does not include the gain and offset error due to the PGA. Relative linearity is used to determine the change of wiper voltage between two adjacent wiper positions in a voltagedivider configuration. I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I2C standard-mode timing. CB--total capacitance of one bus line in picofarads, timing referenced to 0.9 x VCC and 0.1 x VCC. EEPROM write begins after a stop condition occurs.
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
STANDBY SUPPLY CURRENT vs. SUPPLY VOLTAGE
DS3908 toc01
STANDBY SUPPLY CURRENT vs. TEMPERATURE
1.8 1.6 1.4 ISTBY (mA) ISTBY (mA) 1.2 1.0 0.8 0.6 0.4 0.2 0 1.15200 1.15000 -40 -15 10 35 60 85 1 3.3V 5.5V 4.0V
DS3908 toc02
STANDBY SUPPLY CURRENT vs. SCL FREQUENCY
1.16200 1.16000 1.15800 1.15600 1.15400
DS3908 toc03
2.0 1.8 1.6 1.4 ISTBY (mA) 1.2 1.0 0.8 0.6 0.4 0.2 0 3.0 3.5 4.0 VCC 4.5 5.0 Hx = VCC, Lx = GND A0 TO A2 = VCC SDA, SCL = VCC POT AT 1Dh GAIN = 2V/V NO LOAD -40C +85C +25C
2.0
1.16400
5.5
100
10,000
1,000,000
TEMPERATURE (C)
SCL FREQUENCY (Hz)
OUTPUT VOLTAGE vs. POT SETTING
DS3908 toc04
VOL vs. IOUT:SINK
DS3908 toc05
VCC - VOH vs. IOUT:SOURCE
DS3908 toc06
1.10000 1.00000 OUTPUT VOLTAGE AT Vx (mA) 1.90000 1.80000 1.70000 1.60000 1.50000 1.40000 1.30000 0 10 20 30 40 50 60 POT SETTING (DEC) GAIN = 1V/V Hx = 1V Lx = 0.3V
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10
1 VCC - VOH (V)
1
VOL (V)
0.1 +85C +25C 0.01
0.1 +85C +25C 0.01
0.001 0.001
-40C 0.01 0.1 1 10 100
-40C 0.001 0.001 0.01 0.1 1 10 100
IOUT:SINK (mA)
IOUT:SOURCE (mA)
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Dual, 64-Position Nonvolatile Digital Potentiometer with Buffered Outputs
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
NORMALIZED POT END-END RESISTANCE vs. TEMPERATURE
DS3908 toc07
DS3908
POT INL vs. SETTING
DS3908 toc08
POT DNL vs. SETTING
0.20 0.15 0.10 POT DNL (LSB) 0.05 0 -0.05 -0.10 -0.15 -0.20 -1.25 GAIN = 1V/V
DS3908 toc09
NORMALIZED POT END-END RESISTANCE (/)
1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -40 -15 10 35 60 VCC = 5V
0.25 0.20 0.15 0.10 POT INL (LSB) 0.05 0 -0.05 -0.10 -0.15 -0.20 -1.25 GAIN = 1V/V
0.25
85
0
10
20
30
40
50
60
0
10
20
30
40
50
60
TEMPERATURE (C)
POT0 SETTING (DEC)
POT0 SETTING (DEC)
TYPICAL PGA OFFSET vs. COMMON-MODE INPUT VOLTAGE
DS3908 toc10
TYPICAL PGA OFFSET vs. TEMPERATURE
0.2 TYPICAL PGA OFFSET (mV) 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 CMVIN = 2.0V CMVIN = 3.5V
DS3908 toc11
0.6 0.5 0.4 TYPICAL PGA OFFSET (mV) 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 GAIN = 1V/V DATA OFFSET TO SHOW 0 AT 2V CMVIN 0.3 0.7 1.1 1.5 1.9 2.3 2.7 3.1 +25C -40C +85C
0.25 CMVIN = 0.3V
3.5
-40
-15
10
35
60
85
COMMON-MODE INPUT VOLTAGE (V)
TEMPERATURE (C)
Pin Description
TDFN PIN 1 2 3, 4, 5 6 7 8, 11 9, 12 10, 13 14 NAME SDA SCL A0, A1, A2 WP GND L0, L1 V0, V1 H0, H1 VCC I2C Serial Data. Input/output for I2C data. I2C Serial Clock. Input for I2C clock. Address-Select Inputs. Determines I2C address. Device address is 1010A2A1A0. (See the I2C Slave Address and Address Pins section for more details.) Write-Protect Input. Must be grounded to write to the registers. An internal pullup will lock the register values if this pin is not connected. Ground Terminal Potentiometer Low Terminals. Voltages on these pins should remain between GND and VCC. Amplifier Outputs Potentiometer High Terminals. Voltages on these pins should remain between GND and VCC. Supply Voltage Terminal FUNCTION
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Dual, 64-Position Nonvolatile Digital Potentiometer with Buffered Outputs DS3908
Functional Diagram
DS3908
EEPROM VCC VCC F8h POT0 REGISTER PGA0 SDA SCL A0 A1 A2 FAh VCC RWP WP GND FBh G1 G0 1x, 2x, 4x GAIN POT0/1 REGISTER 1x, 2x, 4x GAIN I2C INTERFACE POT1 REGISTER PGA1 V1 L1 F9h POT1 POT0 H0 V0 L0 H1
Detailed Description
The DS3908 contains two nonvolatile digital potentiometers with programmable-gain amplifiers buffering the wiper outputs. The potentiometers have 63 equally weighted (lineartaper) resistive elements, for a total of 64 taps. The resistive elements are built using a low-temperaturedrift material, and have a typical 100k end-to-end resistance. This produces an output that is highly linear, with the highest and lowest taps connected to high (Hx) and low (Lx) terminals, respectively. The potentiometers are independently controlled using an I2Ccompatible interface. Three address pins allow one of eight slave addresses to be selected. The eight slave addresses allow the DS3908 address to be customized for applications with multiple I2C devices, and allow up to eight DS3908s to be placed on the same I2C bus. The potentiometer positions are saved in EEPROM, and are recalled during each power-up to provide nonvolatile position settings. Once the settings are written, the write-protect pin prevents accidental writes to the potentiometers. The write-protection function is ideal for
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analog factory calibration because it prevents errant transactions on the I2C bus from corrupting the settings of the device. The WP pin contains an internal pullup resistor that must be pulled low to write to the device. The programmable-gain amplifiers can be independently set to one of three different gains--1V/V, 2V/V, or 4V/V. The amplifiers' common-mode input range is from ground to 1.5V below VCC, and the output is rail-to-rail and capable of driving 1mA loads, 300mV from each supply rail. The outputs are stable driving 100pF loads for applications that require output filtering. The addition of the amplifier to buffer the potentiometer wiper offers distinct advantages over standard digital potentiometers. The buffer provides a high-impedance load for the potentiometer and a low-impedance voltage output. This improves the linearity of the output voltage for systems that load the potentiometer by eliminating the changes in current through both the potentiometer and the wiper impedance. It also allows voltage gain from the potentiometer input to the output. Because the amplifiers are integrated into the DS3908, this is done without increasing the footprint of the design or the complexity of the PC board.
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Dual, 64-Position Nonvolatile Digital Potentiometer with Buffered Outputs
I2C Slave Address and Address Pins The DS3908's I2C slave address is determined by the state of the A0, A1, and A2 address pins as shown in the pin configuration (see Figure 1). Address pins connected to GND result in a `0' in the corresponding bit position in the slave address. Conversely, address pins connected to VCC result in a `1' in the corresponding bit positions. I2C communication is described in detail in the I2C Serial Interface Description section. Potentiometer Control
The potentiometers of the DS3908 have 64 taps with 63 resistive elements separating them. Thus, the most and least significant wiper positions connect the amplifier to the voltages at the high and low terminals of the potentiometer, respectively. The potentiometers of the DS3908 are controlled by communicating with the following registers:
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0, A1, AND A2.
DS3908
MSB 1 0 1 0 A2 A1 A0
LSB R/W
SLAVE ADDRESS*
READ/WRITE BIT
Figure 1. DS3908 Slave Address Byte
Table 1. Potentiometer Registers
ADDRESS F8h F9h FAh POTENTIOMETER Pot 0 Pot 1 Pot 0 and Pot 1 I2C FUNCTIONS Read/Write Read/Write Write Only NUMBER OF POSITIONS* 64 (00h to 3Fh) 64 (00h to 3Fh) 64 (00h to 3Fh) DEFAULTS 1Fh 1Fh --
*The two most significant bits of each potentiometer position register are ignored. Writing values greater than 3Fh to any of the potentiometer registers will result in a valid 6-bit position, without regard to the value of the most significant two bits. Example: Register values C2h, 82h, 42h, and 02h are all potentiometer position 2.
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Dual, 64-Position Nonvolatile Digital Potentiometer with Buffered Outputs
When writing to the DS3908, the potentiometer will adjust to the new setting once it has acknowledged the new data that is being written, and the EEPROM (used to make the setting nonvolatile) will be written following the stop condition at the end of the write command. To change the setting without changing the EEPROM, terminate the write with a repeated start condition before the next stop condition occurs. Using a repeated start
DS3908
condition prevents the 20ms (maximum) delay required for the EEPROM write cycle to finish.
Programmable Amplifier Control
The gain of both DS3908 amplifiers is controlled by writing to register address FBh. The most significant nibble of the FBh address controls the PGA1 gain, and the least significant nibble controls the PGA0 gain. The format of each nibble is shown in the tables below:
Table 2. Programmable Amplifier Register
ADDRESS FBh R* bit7 G12 REGISTER FORMAT (BINARY) PGA1 G11 G10 R* G02 PGA0 G01 G00 bit0
Default value = 11h. *Reserved for future use, write to zeros.
Table 3. Programmable Amplifier Gain Codes
Gx2Gx1Gx0 00X 01X 1XX AMPLIFIER GAIN (V/V) 1 2 4
X = Don't care.
Writes to this register are similar to writes to the potentiometer register. A stop condition must follow the write to ensure that the EEPROM is modified. A repeated start condition before a stop condition following a write operation will prevent the settings from being stored in EEPROM. (See the I 2 C Communication section for more details.)
Write Protection
The write-protect pin has an internal pullup resistor. To adjust the potentiometers' position, this pin must be grounded. This pin can be left floating or connected to VCC to write protect the EEPROM memory. All registers can be read when the device is write protected.
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Dual, 64-Position Nonvolatile Digital Potentiometer with Buffered Outputs
I2C Serial Interface Description
I2C Definitions The following terminology is commonly used to describe I2C data transfers: Master Device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses, and start and stop conditions. Slave Devices: Slave devices send and receive data at the master's request. Bus Idle or not Busy: Time between stop and start conditions when both SDA and SCL are inactive and in their logic-high states. When the bus is idle it often initiates a low-power mode for slave devices. Start Condition: A start condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a start condition. See the timing diagram for applicable timing. Stop Condition: A stop condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a stop condition. See the timing diagram for applicable timing.
Repeated Start Condition: The master can use a repeated start condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. Repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated start condition is issued identically to a normal start condition. See the timing diagram for applicable timing. Bit Write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the setup and hold-time requirements (see Figure 2). Data is shifted into the device during the rising edge of the SCL. Bit Read: At the end of a write operation, the master must release the SDA bus line for the proper amount of setup time (see Figure 2) before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses including when it is reading bits from the slave. Acknowledgement (ACK and NACK): An Acknowledgement (ACK) or Not Acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a zero during the 9th bit. A device performs a NACK by transmitting a one during the 9th bit. Timing (Figure 2) for the ACK and NACK is identical to all other bit writes. An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or as an indication that the device is not receiving data. Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. The 8 bits transmitted by the master are done according to the bit write definition and the acknowledgement is read using the bit read definition.
DS3908
SDA
tBUF tLOW tR tF
tHD:STA
tSP
SCL tHD:STA STOP START tHD:DAT NOTE: TIMING IS REFERENCE TO VIL(MAX) AND VIH(MIN). tHIGH tSU:DAT REPEATED START tSU:STA tSU:STO
Figure 2. I2C Timing Diagram _____________________________________________________________________ 9
Dual, 64-Position Nonvolatile Digital Potentiometer with Buffered Outputs
Byte Read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition above, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to terminated communication so the slave will return control of SDA to the master. Slave Address Byte: Each slave on the I 2 C bus responds to a slave address byte sent immediately following a start condition. The slave address byte contains the slave address in the most significant 7 bits and the R/W bit in the least significant bit. The DS3908's slave address is determined by the state of the A0, A1, and A2 address pins as shown in Figure 1. Address pins connected to GND result in a `0' in the corresponding bit position in the slave address. Conversely, address pins connected to VCC result in a `1' in the corresponding bit positions. When the R/W bit is 0 (such as in A0h), the master is indicating it will write data to the slave. If R/W = 1, (A1h in this case), the master is indicating it wants to read from the slave. If an incorrect slave address is written, the DS3908 will assume the master is communicating with another I2C device and ignore the communication until the next start condition is sent. Memory Address: During an I2C write operation to the DS3908, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte transmitted during a write operation following the slave address byte.
DS3908
condition prevents the 20ms (maximum) delay required for the EEPROM write cycle to finish. If the master continues to write data to the DS3908, without generating a stop condition, then the same register will be overwritten. Acknowledge Polling: Any time an EEPROM byte is written, the DS3908 requires the EEPROM write time (tW) after the stop condition to write the contents of the byte to EEPROM. During the EEPROM write time, the device will not acknowledge its slave address because it is busy. It is possible to take advantage of this phenomenon by repeatedly addressing the DS3908, which allows communication to continue as soon as the DS3908 is ready. The alternative to acknowledge polling is to wait for a maximum period of tW to elapse before attempting to access the device. EEPROM Write Cycles: The DS3908's EEPROM write cycles are specified in the Nonvolatile Memory Characteristics table. The specification shown is at the worst-case temperature. It is capable of handling many additional writes at room temperature. Reading a Single Byte from a Slave: Unlike the write operation that uses the specified memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address pointer. To read a single byte from the slave, the master generates a start condition, writes the slave address byte with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a stop condition. Manipulating the Address Pointer for Reads: A dummy write cycle can be used to force the address pointer to a particular value. To do this, the master generates a start condition, writes the slave address byte (R/W = 0), writes the memory address where it desires to read, generates a repeated start condition, writes the slave address byte (R/W = 1), reads data with ACK or NACK as applicable, and generates a stop condition. See Figure 3 for a read example using the repeated start condition to specify the memory location.
I2C Communication Writing a Single Byte to a Slave: The master must generate a start condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data, and generate a stop condition. The master must read the slave's acknowledgement during all byte write operations. When writing to the DS3908, the potentiometer will adjust to the new setting once it has acknowledged the new data that is being written, and the EEPROM (used to make the setting nonvolatile) will be written following the stop condition at the end of the write command. To change the setting without changing the EEPROM, terminate the write with a repeated start condition before the next stop condition occurs. Using a repeated start
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Applications Information
Power-Supply Decoupling
To achieve the best results when using the DS3908, decouple the power supply with a 0.01F or 0.1F capacitor. Use a high-quality, ceramic, surface-mount capacitor if possible. Surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate highfrequency response for decoupling applications.
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Dual, 64-Position Nonvolatile Digital Potentiometer with Buffered Outputs
Total Error
The total error in a reading from the DS3908 can be calculated using the following formula: PotVoltage = (PotCode / 63) x (VH - VL) + VL ErrorPOT = (INLERR / 63) x (VH - VL) ErrorOFFSET = Gain x VOFF ErrorGAIN = PotVoltage x GainERR Total Output Error = ErrorPOT + ErrorOFFSET + ErrorGAIN where: PotCode = Potentiometer Setting (dec) GainERR = Amplifier Gain Deviation from Desired (V/V) VOFF = PGA Input Voltage Offset Voltage (V) INLERR = Potentiometer Integral Non-Linearity (LSB) For example, the worst-case error for VH = 2V, VL = 0.5V, PGA Gain = 2V/V, PotCode = 31d (1Fh), is given by: PotVoltage = 31 / 63 x (2.0V - 0.5V) + 0.5V = 1.238V ErrorPOT = (0.6 / 63) x (2.0V - 0.5V) = 0.014V ErrorOFFSET = 2.0V/V x 9mV = 0.018V ErrorGAIN = PotVoltage x GainERR = 0.0929V Total Output Error = ErrorPOT + ErrorOFFSET + ErrorGAIN = 0.014V + 0.018V + 0.0929V = 0.125V
DS3908
TYPICAL I2C WRITE TRANSACTION MSB START 1 0 1 0 A2 A1 A0 LSB R/W SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK STOP
SLAVE ADDRESS*
READ/ WRITE
REGISTER/MEMORY ADDRESS
DATA
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0, A1, AND A2. EXAMPLE I2C TRANSACTIONS (WHEN A0, A1, AND A2 ARE CONNECTED TO GND) A0h A) SINGLE BYTE NONVOLATILE WRITE -WRITE POTENTIOMETER 1 TO 00h A) SINGLE BYTE VOLATILE WRITE -WRITE POTENTIOMETER 1 TO 00h B) SINGLE BYTE READ -READ POTENTIOMETER 0 F9h SLAVE 0 0 0 0 0 0 0 0 ACK SLAVE ACK STOP
START 1 0 1 0 0 0 0 0 SLAVE 1 1 1 1 1 0 0 1 ACK A0h F9h
SLAVE SLAVE START 1 0 1 0 0 0 0 0 11111 001 ACK ACK A0h START 1 0 1 0 0 0 0 0 F8h SLAVE SLAVE 111 11000 ACK ACK
00000000
SLAVE ACK
REPEATED START
STOP
REPEATED START
A1h 1 0 1 0 0 0 0 1 SLAVE ACK
DATA POT 0 MASTER NACK STOP
Figure 3. I2C Communication Examples
Chip Topology
TRANSISTOR COUNT: 9950
Package Information
For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 (c) 2006 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.
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