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HANBit
HMD4M32M2VE
16Mbyte(4Mx32) DRAM SIMM EDO MODE, 4K Refresh, 3.3V Part No. HMD4M32M2VE, HMD4M32M2VEG
GENERAL DESCRIPTION
The HMD4M32M2VE is a 4M x 32 bit dynamic RAM high-density memory module. The module consists of two CMOS 4M x 16 bit DRAMs in 50-pin TSOP packages mounted on a 72-pin. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a single In-line memory module with edge connections and is intended for mounting in to 72-pin edge connector sockets. All module components may be powered from a single 3.3V DC power supply. All inputs and outputs are LVTTL-compatible.
FEATURES
w Part Identification HMD4M32M2VE----Lead finish Solder HMD4M32M2VEG- Lead finish Gold w Access times : 50, 60ns w High-density 16MByte design w 4K Cycles/64ms Ref, Gold w Single +3.3V 0.3V power supply wJEDEC standard pinout w EDO Mode operation w LVTTL compatible inputs and outputs w FR4-PCB design
PIN SYMBOL
PIN ASSIGNMENT
PIN SYMBOL PIN SYMBOL PIN SYMBOL
1 2 3 4 5 6 7 8 9 10
VSS DQ0 DQ16 DQ1 DQ17 DQ2 DQ18 DQ3 DQ19 VCC NC A0 A1 A2 A3 A4 A5 A6
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
A10 DQ4 DQ20 DQ5 DQ21 DQ6 DQ22 DQ7 DQ23 A7 A11 VCC A8 A9 NC NC NC NC
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
NC NC VSS /CAS0 /CAS2 /CAS3 /CAS1 /RAS0 NC NC /W NC DQ8 DQ24 DQ9 DQ25 DQ10 DQ26
55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
DQ11 DQ27 DQ12 DQ28 VCC DQ29 DQ13 DQ30 DQ14 DQ31 DQ15 NC PD1 PD2 PD3 PD4 NC VSS
OPTIONS
w Timing 50ns access 60ns access w Packages 72-pin SIMM
MARKING
11 12 13
-5 -6 M
14 15 16 17 18
PERFORMANCE RANGE
Speed 5 6 tRAC 50ns 60ns tCAC 13ns 15ns tRC 84ns 104ns
PIN NAMES
Pin Name A0-A11 DQ0-DQ31 /W Function Address Input(4K Ref) Data In/Out Read/Write Input Pin Name /RAS0 /CAS0 - /CAS3 PD1 - PD4 Function Row Address Strobe Column Address Strobe Presence Detect Pin Name Vss NC Vcc Function Ground No Connection Power(+3.3V)
URL:www.hbe.co.kr REV.1.0 (August.2002)
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FUNCTIONAL BLOCK DIAGRAM U0
/RAS
/RAS0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
HMD4M32M2VE
DQ0-DQ7
/CAS0
/LCAS
/CAS1
/UCAS
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 A0-A11 DQ15
/OE
DQ8-DQ15
/W
U2
/RAS
/CAS2
/LCAS
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DQ16-DQ23
/CAS3
/UCAS
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
/OE
DQ24-DQ31
/W
A0-A11
/W A0-A11
Vcc Vss
0.1uF or Capacitor for each DRAM 0.22uF Toall DRAMs
URL:www.hbe.co.kr REV.1.0 (August.2002)
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ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature SYMBOL VIN ,OUT Vcc PD TSTG
HMD4M32M2VE
RATING -0.5V to 6.5V -0.5V to 4.6V 2W -55oC to 150oC
Short Circuit Output Current IOS 50mA w Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
( Voltage reference to VSS, TA=0 to 70 o C ) PARAMETER Supply Voltage Ground Input High Voltage Input Low Voltage SYMBOL Vcc Vss VIH VIL MIN 3.0 0 2.0 -0.3 TYP. 3.3 0 MAX 3.6 0 +5.5 0.8 UNIT V V V V
DC AND OPERATING CHARACTERISTICS
SYMBOL ICC1 -6 ICC2 -5 ICC3 -6 -5 ICC4 -6 ICC5 -5 ICC6 -6 Il(L) IO(L) VOH VOL ICC1 : Operating Current * (/RAS , /CAS , Address cycling @t RC=min.) ICC2 : Standby Current ( /RAS=/CAS=VIH )
URL:www.hbe.co.kr REV.1.0 (August.2002)
SPEED -5
MIN -10 -10 2.4 -
MAX 220 200 4 220 200 220 200 600 220 200 10 10 0.4
UNITS mA mA mA mA mA mA mA mA mA mA A A V V
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ICC3 : /RAS Only Refresh Current * (/CAS=V IH, /RAS, Address cycling @tRC=min ) ICC4 : Fast Page Mode Current * (/RAS=VIL, /CAS, Address cycling @tPC=min ) ICC5 : Standby Current (/RAS=/CAS=Vcc-0.2V ) ICC6 : /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t RC=min )
HMD4M32M2VE
* NOTE: ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address cad be changed maximum once while /RAS=VIL. In ICC4, address can be changed maximum once within one page mode cycle.
o
CAPACITANCE
( TA=25 C, Vcc = 3.3V, f = 1Mz )
DESCRIPTION Input Capacitance (A0-A11) Input Capacitance (/W) Input Capacitance (/RAS0, /RAS1) Input Capacitance (/CAS0-/CAS3) Input/Output Capacitance (DQ0-31)
SYMBOL CIN1 C IN2 CIN3 CIN4 CDQ1
o
MIN -
MAX 10 14 14 14 14
UNITS pF pF pF pF pF
AC CHARACTERISTICS
( 0 C TA 70oC , Vcc = 3.3V10%, See notes 1,2.) -5 -6 MAX MIN 104 50 13 25 3 1 30 50 13 38 8 20 15 5 0 10 0 10K 37 25 10K 50 3 1 40 60 15 45 10 20 15 5 0 10 0 10K 45 30 10K 50 60 15 30 MAX UNIT
STANDARD OPERATION
SYMBOL
MIN 84
Random read or write cycle time Access time from /RAS Access time from /CAS Access time from column address /CAS to output in Low-Z Transition time (rise and fall) /RAS precharge time /RAS pulse width /RAS hold time /CAS hold time /CAS pulse width /RAS to /CAS delay time /RAS to column address delay time /CAS to /RAS precharge time Row address set-up time Row address hold time Column address set-up time
URL:www.hbe.co.kr REV.1.0 (August.2002)
tRC tRAC tCAC tAA tCLZ tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Column address hold time Column Address to /RAS lead time Read command set-up time Read command hold referenced to /CAS Read command hold referenced to /RAS Write command hold time Write command pulse width Write command to /RAS lead time Write command to /CAS lead time Data-in set-up time Data-in hold time Refresh period Write command set-up time /CAS setup time (C-B-R refresh) /CAS hold time (C-B-R refresh) /RAS precharge to /CAS hold time Access time from /CAS precharge Fast page mode cycle time /CAS precharge time (Fast page) /RAS pulse width (Fast page ) /W to /RAS precharge time (C-B-R refresh) /W to /RAS hold time (C-B-R refresh) tCAH tRAL tRCS tRCH tRRH tWCH tWP tRWL tCWL tDS tDH tREF tWCS tCSR tCHR tRPC tCPA tPC tCP tRASP tWRP tWRH 28 8 50 10 10 0 5 10 5 8 25 0 0 0 10 10 10 8 0 8
HMD4M32M2VE
10 30 0 0 0 10 10 10 10 0 10 64 0 5 10 5 35 35 10 100K 60 10 10 100K 40 64 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES 1.An initial pause of 200s is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles before proper device operation is achieved. 2.VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3.Measured with a load equivalent to 1TTL loads and 100pF 4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by t CAC. 5.Assumes that tRCD tRCD(max) 6. tAR, tWCR, tDHR are referenced to tRAD(max) 7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V OH or VOL. 8. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameter. They are included in the data sheet as electrical characteristic only. If tWCS tWCS(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 9. Either tRCH or tRRH must be satisfied for a read cycle. 10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in readwrite cycles. 11. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit. then access time is controlled by tAA.
URL:www.hbe.co.kr REV.1.0 (August.2002)
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TIMING DIAGRAM
HMD4M32M2VE
Please refer to attached timing diagram chart (I)
PACKAGING INFORMATION
SIMM Design
107.95 mm 101.19 mm 3.38 mm R1.57 mm 3.18 0.51
19.00 10.16 mm 6.35 mm 2.00 6.35 6.35 mm 95.25 mm R1.571.0 mm
5.08 MAX
0.25 mm MAX
2.54 mm MIN
1.27
Gold : 1.0410 mm
1.270.08 mm
ORDERING INFORMATION
Part Number Density Org. Package Refresh Cycle 4,096 Cycles 64ms Ref. 4,096 Cycles 64ms Ref. Vcc SPEED
HMD4M32M2VEG-5 HMD4M32M2VEG-6
16MByte 16MByte
4MX 32bit 4MX 32bit
72 Pin-SIMM 72 Pin-SIMM
3.3V 3.3V
50ns 60ns
URL:www.hbe.co.kr REV.1.0 (August.2002)
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