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IS61NVVP25672 IS61NVVP51236
256K x 72 and 512K x 36, 18Mb PIPELINE 'NO WAIT' STATE BUS SRAM
FEATURES
* 100 percent bus utilization * No wait cycles between Read and Write * Internal self-timed write cycle * Individual Byte Write Control * Single R/W (Read/Write) control pin * Clock controlled, registered address, data and control * Interleaved or linear burst sequence control using MODE input * Power Down mode * Common data inputs and data outputs * CKE pin to enable clock and suspend operation * JEDEC 119-ball PBGA (x36) and 209-ball (x72) PBGA packages * Single +1.8V ( 5%) power supply * JTAG Boundary Scan * Industrial temperature available
ISSI
ADVANCE INFORMATION JULY 2002 DESCRIPTION
(R)
The 16 Meg 'NVVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for network and communications customers. They are organized as 256K words by 72 bits, 512K words by 36 bits and are fabricated with ISSI's advanced CMOS technology. Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal device will hold their previous values. All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW. Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW. Separate byte enables allow individual bytes to be written. A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected.
FAST ACCESS TIME
Symbol tKQ tKC Parameter Clock Access Time Cycle Time Frequency -250 2.6 4 250 -200 3.2 5 200 Units ns ns MHz
Copyright (c) 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
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ADVANCED INFORMATION Rev. 00A 07/17/02
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IS61NVVP25672 IS61NVVP51236
BLOCK DIAGRAM
ISSI
(R)
A [0:17] or A [0:18]
ADDRESS REGISTER
A2-A17 or A2-A18 256Kx72; 512Kx36 MEMORY ARRAY MODE A0-A1 BURST ADDRESS COUNTER
A'0-A'1
K
DATA-IN REGISTER
CLK CKE
CONTROL LOGIC K
WRITE ADDRESS REGISTER
WRITE ADDRESS REGISTER
K
DATA-IN REGISTER
CE CE2 CE2 ADV WE BWY X OE ZZ DQa0-DQd7 or DQa0-DQb8 DQPa-DQPd 72 or 36 CONTROL REGISTER
}
CONTROL LOGIC
K
OUTPUT REGISTER BUFFER
(X=a,b,c,d or a,b)
2
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ADVANCED INFORMATION Rev. 00A 07/17/02
IS61NVVP25672 IS61NVVP51236
PIN CONFIGURATION -- 256K X 72, 209-Ball PBGA (TOP VIEW)
1 A B C D E F G H J K L M N P R T U V W DQg DQg DQg DQg DQPg DQc DQc DQc DQc NC DQh DQh DQh DQh DQPd DQd DQd DQd DQd 2 DQg DQg DQg DQg DQPc DQc DQc DQc DQc NC DQh DQh DQh DQh DQPh DQd DQd DQd DQd 3 A BWc BWh GND VCCQ GND VCCQ GND VCCQ CLK VCCQ GND VCCQ GND VCCQ GND NC A TMS 4 CE2 BWg BWd NC VCCQ GND VCCQ GND VCCQ NC VCCQ GND VCCQ GND VCCQ NC A A TDI 5 A NC NC NC VCC GND VCC GND VCC GND VCC GND VCC GND VCC NC NC A A 6 ADV WE CE OE VCC NC NC NC NC CKE NC NC NC ZZ VCC MODE A A1 A0 7 A A NC NC VCC GND VCC GND VCC GND VCC GND VCC GND VCC NC NC A A 8 CE2 BWb BWe NC VCCQ GND VCCQ GND VCCQ NC VCCQ GND VCCQ GND VCCQ NC A A TDO 9 A BWf BWa GND VCCQ GND VCCQ GND VCCQ NC VCCQ GND VCCQ GND VCCQ GND NC A TCK
ISSI
10 DQb DQb DQb DQb DQPf DQf DQf DQf DQf NC DQa DQa DQa DQa DQPa DQe DQe DQe DQe 11 DQb DQb DQb DQb DQPb DQf DQf DQf DQf NC DQa DQa DQa DQa DQPe DQe DQe DQe DQe
(R)
11 x 19 Ball BGA--14 x 22 mm2 Body--1 mm Ball Pitch
PIN DESCRIPTIONS
A A0, A1 Synchronous Address Inputs Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Burst Address Advance Synchronous Byte Write Enable Synchronous Clock Clock Enable Synchronous Data Input/Output Parity Data Input/Output GND MODE OE TCK, TDI TDO, TMS VCC VCCQ WE ZZ Ground Burst Sequence Mode Selection Output Enable JTAG Boundary Scan Pins +1.8V Power Supply Isolated Output Buffer Supply: 1.8V Write Enable Snooze Enable
ADV BWa-BWh CLK CKE DQa-DQh DQPa-DQPh
CE, CE2, CE2 Synchronous Chip Enable
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ADVANCED INFORMATION Rev. 00A 07/17/02
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IS61NVVP25672 IS61NVVP51236
PIN CONFIGURATION
119-pin PBGA (Top View)
ISSI
3 4 5 6 7
(R)
1 A VCCQ B NC C NC D DQc E DQc F VCCQ G DQc H DQc J VCCQ K DQd L DQd M VCCQ N DQd P DQd R NC T NC U VCCQ
2
A CE2 A DQPc DQc DQc DQc DQc VCC DQd DQd DQd DQd DQPd A NC TMS
A A A GND GND GND BWc GND NC GND BWd GND GND GND MODE A TDI
A ADV VCC NC CE OE A WE VCC CLK NC CKE A1 A0 VCC A TCK
A A A GND GND GND BWb GND NC GND BWa GND GND GND NC A TDO
A CE2 A DQPb DQb DQb DQb DQb VCC DQa DQa DQa DQa DQPa A NC NC
VCCQ NC NC DQb DQb VCCQ DQb DQb VCCQ DQa DQa VCCQ DQa DQa NC ZZ VCCQ
512K x 36
PIN DESCRIPTIONS
A A0, A1 Synchronous Address Inputs Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Burst Address Advance Synchronous Byte Write Enable Synchronous Clock Clock Enable Synchronous Data Input/Output Parity Data Input/Output Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
ADVANCED INFORMATION Rev. 00A 07/17/02
GND MODE OE TCK, TDI TDO, TMS VCC VCCQ WE ZZ
Ground Burst Sequence Mode Selection Output Enable JTAG Boundary Scan Pins 1.8V Power Supply Isolated Output Buffer Supply: 1.8V Write Enable Snooze Enable
ADV BWa-BWh CLK CKE DQa-DQd DQPa-DQPd 4
CE, CE2, CE2 Synchronous Chip Enable
IS61NVVP25672 IS61NVVP51236
STATE DIAGRAM
READ BEGIN READ WRITE DS READ DS WRITE BEGIN WRITE
ISSI
(R)
READ
WRITE
READ
BURST DS
DESELECT BURST
BURST
WRITE
DS BURST READ WRITE
DS BURST WRITE
BURST
BURST
READ
SYNCHRONOUS TRUTH TABLE(1)
Operation Not Selected Continue Not Selected Not Selected Not Selected Begin Burst Read Continue Burst Read NOP/Dummy Read Dummy Read Begin Burst Write Continue Burst Write NOP/Write Abort Write Abort Ignore Clock Address Used N/A N/A N/A N/A External Address Next Address External Address Next Address External Address Next Address N/A Next Address Current Address CS1 CS X H X X L X L X L X L X X CS2 X X L X H X H X H X H X X CS2 CS X X X H L X L X L X L X X ADV H L L L L H L H L H L H X WE X X X X H X H X L X L X X BWx BW X X X X X X X X L L H H X OE X X X X L L H H X X X X X CKE L L L L L L L L L L L L H CLK

Notes: 1. "X" means don't care. 2. The rising edge of clock is symbolized by 3. A continue deselect cycle can only be entered if a deselect cycle is executed first. 4. WE = L means Write operation in Write Truth Table. WE = H means Read operation in Write Truth Table. 5. Operation finally depends on status of asynchronous pins (ZZ and OE).
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ADVANCED INFORMATION Rev. 00A 07/17/02
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IS61NVVP25672 IS61NVVP51236
ASYNCHRONOUS TRUTH TABLE(1)
Operation Sleep Mode Read Write Deselected ZZ H L L L L OE X L H X X I/O STATUS High-Z DQ High-Z Din, High-Z High-Z
ISSI
(R)
Notes: 1. X means "Don't Care". 2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time. 4. Deselected means power Sleep Mode where stand-by current depends on cycle time.
WRITE TRUTH TABLE (x36)
Operation READ WRITE BYTE a WRITE BYTE b WRITE BYTE c WRITE BYTE d WRITE ALL BYTEs WRITE ABORT/NOP WE H L L L L L L BWa BW X L H H H L H BWb BW X H L H H L H BWc BW X H H L H L H BWd BW X H H H L L H
Notes: 1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
6
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ADVANCED INFORMATION Rev. 00A 07/17/02
IS61NVVP25672 IS61NVVP51236
WRITE TRUTH TABLE (x72)
Operation READ WRITE BYTE a WRITE BYTE b WRITE BYTE c WRITE BYTE d WRITE BYTE e WRITE BYTE f WRITE BYTE g WRITE BYTE h WRITE ALL BYTEs WRITE ABORT/NOP WE H L L L L L L L L L L BWa BW X L H H H H H H H L H BWb BW X H L H H H H H H L H BWc BW X H H L H H H H H L H BWd BW X H H H L H H H H L H BWe BW X H H H H L H H H L H BWf BW X H H H H H L H H L H
ISSI
BWg BW X H H H H H H L H L H X H H H H H H H L L H
(R)
BWh BW
Notes: 1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
INTERLEAVED BURST ADDRESS TABLE (MODE = VCC)
External Address A1 A0 00 01 10 11 1st Burst Address A1 A0 01 00 11 10 2nd Burst Address A1 A0 10 11 00 01 3rd Burst Address A1 A0 11 10 01 00
LINEAR BURST ADDRESS TABLE (MODE = GND)
0,0
A1', A0' = 1,1
0,1
1,0
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ADVANCED INFORMATION Rev. 00A 07/17/02
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IS61NVVP25672 IS61NVVP51236
ABSOLUTE MAXIMUM RATINGS(1)
Symbol TOPR TSTG PD IOUT VIN, VOUT VIN Parameter Operating Temperature Com Ind Value -0 to +70 -40 to +85 -65 to +150 1.6 100 -0.5 to VCCQ + 0.3 -0.5 to VCCQ + 0.3 Unit C C W mA V V
ISSI
(R)
Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to GND for I/O Pins Voltage Relative to GND for for Address and Control Inputs
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
OPERATING RANGE
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 1.8V 5% 1.8V 5% VCCQ 1.8V 5% 1.8V 5%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
1.8V Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current GND VIN VCC
(1)
Test Conditions IOH = -4.0 mA IOL = 4.0 mA
Min. VCCQ -0.4 -- 1.1 -0.3 -5 -10
Max. -- 0.4 VCC + 0.3 0.6 5 10
Unit V V V V A A
GND VOUT VCCQ, OE = VI
8
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ADVANCED INFORMATION Rev. 00A 07/17/02
IS61NVVP25672 IS61NVVP51236
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-250 MAX x36 450 500 -200 MAX x36 400 450
ISSI
Test Conditions Device Selected, Com. OE = VIH, ZZ VIL, IND. All Inputs 0.2V OR VCC - 0.2V, Cycle Time tKC min. Device Deselected, COM. VCC = Max., Ind. All Inputs 0.2V OR VCC - 0.2V, ZZ VIL, f = Max. Device Deselected, Com. VCC = Max., Ind. VIN GND + 0.2V or VCC - 0.2V f=0 x72 500 550 x72 450 500
(R)
Symbol Parameter ICC AC Operating Supply Current
Unit mA
ISB
Standby Current TTL Input
225 --
250 --
175 200
200 230
mA
ISBI
Standby Current CMOS Input
150 --
150 --
150 200
150 200
mA
Note: 1. MODE pin has an internal pullup and should be tied to Vcc or GND. It exhibits 30 A maximum leakage current when tied to GND + 0.2V or Vcc - 0.2V.
CAPACITANCE(1,2)
Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF
Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, Vcc = 3.3V.
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IS61NVVP25672 IS61NVVP51236
1.8V I/O AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0.4V to 1.4V 2V/ ns 0.9V See Figures 1 and 2
ISSI
(R)
1.8V I/O OUTPUT LOAD EQUIVALENT
317
ZO = 50 OUTPUT 50
+1.8V
OUTPUT 351 5 pF Including jig and scope
0.9V
Figure 1
Figure 2
10
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IS61NVVP25672 IS61NVVP51236
READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol fmax tKC tKH tKL tKQ tKQX
(2) (2,3)
ISSI
-250 Min. Max. -- 4.0 1.7 1.7 -- 0.8 0.8 -- -- 0 -- 1.0 1.0 1.0 1.0 1.0 1.0 0.5 0.5 0.5 0.5 0.5 0.5 -- -- 250 -- -- -- 2.6 -- -- 2.6 2.6 -- 2.6 -- -- -- -- -- -- -- -- -- -- -- -- 2 2 -200 Min. Max. -- 5 2 2 -- 1.5 1 -- -- 0 -- 1.2 1.2 1.2 1.2 1.2 1.2 0.5 0.5 0.5 0.5 0.5 0.5 -- -- 200 -- -- -- 3.0 -- -- 3.0 3.0 -- 3.0 -- -- -- -- -- -- -- -- -- -- -- -- 2 2 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cyc cyc
(R)
Parameter Clock Frequency Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Read/Write Setup Time Chip Enable Setup Time Clock Enable Setup Time Address Advance Setup Time Data Setup Time Address Hold Time Clock EnableHold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time Data Hold Time ZZ High to Power Down ZZ Low to Power Down
tKQLZ tOEQ tOELZ tAS tWS tCES tSE
tKQHZ(2,3)
(2,3) (2,3)
tOEHZ
tADVS tDS tAH tHE tWH tCEH tADVH tDH tPDS tPUS
Notes: 1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with load in Figure 2.
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IS61NVVP25672 IS61NVVP51236
SLEEP MODE ELECTRICAL CHARACTERISTICS
Symbol ISB2 tPDS tPUS tZZI tRZZI Parameter Current during SLEEP MODE ZZ active to input ignored ZZ inactive to input sampled ZZ active to SLEEP current ZZ inactive to exit SLEEP current Conditions ZZ Vih ZZ Vih ZZ Vil ZZ Vih ZZ Vil 2 2 2 0 Min. Max. 150
ISSI
Unit mA cycle cycle cycle ns
(R)
SLEEP MODE TIMING
K
tPDS ZZ setup cycle tPUS ZZ recovery cycle
ZZ
tZZI
Isupply
ISB2 tRZZI
All Inputs (except ZZ)
Deselect or Read Only
Deselect or Read Only Normal operation cycle
Outputs (Q)
High-Z Don't Care
12
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IS61NVVP25672 IS61NVVP51236
READ CYCLE TIMING
tKH tKL
Clock
ISSI
(R)
tADVS tADVH
ADV
tKC
tAS tAH
Address A1 A2 A3
tWS tWH
WE
tSE tHE
CKE
tCES tCEH
CE
OE
tOEQ tOEHZ
Data Out
Q1-1
tOEHZ
tDS
Q2-1
tKQ tKQHZ
Q2-2 Q2-3 Q2-4 Q3-1 Q3-2 Q3-3 Q3-4
NOTES: WE = H and BWX = H CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
Don't Care Undefined
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IS61NVVP25672 IS61NVVP51236
WRITE CYCLE TIMING
ISSI
tKH tKL
(R)
Clock
tKC
ADV
Address
A1
A2
A3
WE
tSE tHE
CKE
CE
OE
tDS
Data In
D1-1 D2-1 D2-2 D2-3 D2-4 D3-1 D3-2
tDH
D3-3 D3-4
tOEHZ
Data Out
Q0-3 Q0-4
NOTES: WE = L and BWX = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
Don't Care Undefined
14
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IS61NVVP25672 IS61NVVP51236
SINGLE READ/WRITE CYCLE TIMING
ISSI
tKH tKL
(R)
Clock
tSE tHE tKC
CKE
Address
A1
A2
A3
A4
A5
A6
A7
A8
A9
WRITE
CS
ADV
OE
tOEQ tOELZ
Data Out
Q1
tDS tDH
Q3
Q4
Q6
Q7
Data In
D2
NOTES: WRITE = L means WE = L and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L and CS2 = L
D5
Don't Care Undefined
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IS61NVVP25672 IS61NVVP51236
CKE OPERATION TIMING
tKH tKL
ISSI
(R)
Clock
tSE tHE tKC
CKE
Address
A1
A2
A3
A4
A5
A6
WRITE
CS
ADV
OE
tKQ tKQLZ tKQHZ
Data Out
Q1
tDS tDH
Q3
Q4
Data In
NOTES: WRITE = L means WE = L and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L and CS2 = L
D2
Don't Care Undefined
16
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IS61NVVP25672 IS61NVVP51236
CS OPERATION TIMING
tKH tKL
ISSI
(R)
Clock
tSE tHE tKC
CKE
Address
A1
A2
A3
A4
A5
WRITE
CS
ADV
OE
tOEQ tOELZ tKQHZ tKQ tKQLZ
Data Out
Q1
Q2
tDS tDH
Q4
Data In
D3
NOTES: WRITE = L means WE = L and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L and CS2 = L
D5
Don't Care Undefined
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17
IS61NVVP25672 IS61NVVP51236
IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG)
The IS61NVVP51236 and IS61NVVP25672 have a serial boundary scan Test Access Port (TAP) in the PBGA package only. This port operates in accordance with IEEE Standard 1149.1-1900, but does not include all functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because they place added delay in the critical speed path of the SRAM. The TAP controller operates in a manner that does not conflict with the performance of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 1.8V I/O logic levels.
ISSI
TEST MODE SELECT (TMS)
(R)
TEST ACCESS PORT (TAP) - TEST CLOCK
The test clock is only used with the TAP controller. All inputs are captured on the rising edge of TCK and outputs are driven from the falling edge of TCK.
The TMS input is used to send commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left disconnected if the TAP is not used. The pin is internally pulled up, resulting in a logic HIGH level.
TEST DATA-IN (TDI)
The TDI pin is used to serially input information to the registers and can be connected to the input of any register. The register between TDI and TDO is chosen by the instruction loaded into the TAP instruction register. For information on instruction register loading, see the TAP Controller State Diagram. TDI is internally pulled up and can be disconnected if the TAP is unused in an application. TDI is connected to the Most Significant Bit (MSB) on any register.
DISABLING THE JTAG FEATURE
The SRAM can operate without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (GND) to prevent clocking of the device. TDI and TMS are internally pulled up and may be disconnected. They may alternately be connected to VCC through a pull-up resistor. TDO should be left disconnected. On power-up, the device will start in a reset state which will not interfere with the device operation.
TAP CONTROLLER BLOCK DIAGRAM
0 Bypass Register
2 TDI Selection Circuitry
1
0 Selection Circuitry TDO
Instruction Register
31 30 29
...
2
1
0
Identification Register
x
.....
Boundary Scan Register*
2
1
0
TCK TMS
TAP CONTROLLER
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IS61NVVP25672 IS61NVVP51236
TEST DATA OUT (TDO)
The TDO output pin is used to serially clock data-out from the registers. The output is active depending on the current state of the TAP state machine (see TAP Controller State Diagram). The output changes on the falling edge of TCK and TDO is connected to the Least Significant Bit (LSB) of any register.
ISSI
Boundary Scan Register
(R)
is set LOW (GND) when the BYPASS instruction is executed. The boundary scan register is connected to all input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The x36 configuration has a 84-bit-long register and the x72 configuration has a 123-bit-long register. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.
PERFORMING A TAP RESET
A Reset is performed by forcing TMS HIGH (VCC) for five rising edges of TCK. RESET may be performed while the SRAM is operating and does not affect its operation. At power-up, the TAP is internally reset to ensure that TDO comes up in a high-Z state.
TAP REGISTERS
Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK and output on the TDO pin on the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins. (See TAP Controller Block Diagram) At power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as previously described. When the TAP controller is in the CaptureIR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board level serial test path.
Scan Register Sizes
Register Name Instruction Bypass ID Boundary Scan Bit Size (x36) 3 1 32 84 Bit Size (x72) 3 1 32 123
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded to the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has vendor code and other information described in the Identification Register Definitions table.
Bypass Register
To save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register
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IS61NVVP25672 IS61NVVP51236
IDENTIFICATION (ID) REGISTER
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from
ISSI
(R)
a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID REGISTER CONTENTS
Die Revision Code I/O Configuration ISSI Technology JEDEC Vendor ID Code
Presence Register
Not Used
Bit # x72 x36
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 XXXX00000000000011 0000011010101 XXXX00 00 00 000 00 010 00 0001 1 010 10 1
0 1 1
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IS61NVVP25672 IS61NVVP51236
TAP INSTRUCTION SET
Eight instructions are possible with the three-bit instruction register and all combinations are listed in the Instruction Code table. Three instructions are listed as RESERVED and should not be used and the other five instructions are described below. The TAP controller used in this SRAM is not fully compliant with the 1149.1 convention because some mandatory instructions are not fully implemented. The TAP controller cannot be used to load address, data or control signals and cannot preload the Input or Output buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; instead it performs a capture of the Inputs and Output ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted from the instruction register through the TDI and TDO pins. To execute an instruction once it is shifted in, the TAP controller must be moved into the Update-IR state.
ISSI
SAMPLE/PRELOAD
(R)
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. Because EXTEST is not implemented in the TAP controller, this device is not 1149.1 standard compliant. The TAP controller recognizes an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is a difference between the instructions, unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state.
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the TAP controller is not fully 1149.1 compliant. When the SAMPLE/PRELOAD instruction is loaded to the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. It is important to realize that the TAP controller clock operates at a frequency up to 10 MHz, while the SRAM clock runs more than an order of magnitude faster. Because of the clock frequency differences, it is possible that during the Capture-DR state, an input or output will under-go a transition. The TAP may attempt a signal capture while in transition (metastable state). The device will not be harmed, but there is no guarantee of the value that will be captured or repeatable results. To guarantee that the boundary scan register will capture the correct signal value, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). To insure that the SRAM clock input is captured correctly, designs need a way to stop (or slow) the clock during a SAMPLE/ PRELOAD instruction. If this is not an issue, it is possible to capture all other signals and simply ignore the value of the CLK and CLK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Note that since the PRELOAD part of the command is not implemented, putting the TAP into the Update to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command.
BYPASS
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state.
RESERVED
These instructions are not implemented but are reserved for future use. Do not use these instructions.
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IS61NVVP25672 IS61NVVP51236
JTAG TAP INSTRUCTION SET SUMMARY
Instruction EXTEST(1) IDCODE(1,2) SAMPLE-Z RFU(1) SAMPLE/PRELOAD(1) Private RFU Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in Test-Logic-Reset state.
(1) (1) (1) (1)
ISSI
Description Places the Boundary Scan Register between TDI and TDO. When EXTEST is selected, data will be driven out of the DQ pad. Preloads ID Register and places it between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all Data and Clock output drivers to High-Z.
(R)
Code 000 001 010 011 100 101 110 111
Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Private instruction. Do not use this instruction; Reserved for Future Use. Places Bypass Register between TDI and TDO.
BYPASS
TAP ELECTRICAL CHARACTERISTICS Over the Operating Range(1,2)
Symbol VOH1 VOH2 VOL1 VOL2 VIH VIL IX Parameter Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current IOLT = 2mA GND V I VDDQ Test Conditions IOH = -100 A IOH = -8 mA IOL = 100 A IOL = 8 mA Min. Vcc -0.1 Vcc -0.4 -- -- 1.2 -0.3 -10 Max. -- -- 0.1 0.4 VCC +0.3 0.6 10 Units V V V V V V A
Notes: 1. All Voltage referenced to Ground. 2. Overshoot: VIH (AC) VDD +1.5V for t tTCYC/2, Undershoot:VIL (AC) 0.5V for t tTCYC/2, Power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms.
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IS61NVVP25672 IS61NVVP51236
TAP AC ELECTRICAL CHARACTERISTICS(1) (OVER OPERATING RANGE)
Symbol Parameter tTCYC fTF tTH tTL tTMSS tTDIS tCS tTMSH tTDIH tCH tTDOV tTDOX Notes:
7. tCS and tCHrefer to the set-up and hold time requirements of latching data from the boundary scan register. 8. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
ISSI
Min. 100 -- 40 40 10 10 10 10 10 10 -- 0 Max. -- 10 -- -- -- -- -- -- -- -- 20 -- Unit ns
(R)
TCK Clock cycle time TCK Clock frequency TCK Clock HIGH TCK Clock LOW TMS setup to TCK Clock Rise TDI setup to TCK Clock Rise Capture setup to TCK Rise TMS hold after TCK Clock Rise TDI Hold after Clock Rise Capture hold after Clock Rise TCK LOW to TDO valid TCK LOW to TDO invalid
MHz ns ns ns ns ns ns ns ns ns ns
TAP CONTROLLER STATE DIAGRAM
Test Logic Reset 1 0 Run Test/Idle 0 1 1 Select DR 0 Capture DR 0 Shift DR 1 Exit1 DR 0 1 Select IR 0 1 Capture IR 0 Shift IR 1 Exit1 IR 0 Pause IR 1 0 Exit2 IR 1 1
0 1
0 1
Pause DR 0 1 0 1 Exit2 DR 1 Update DR 0
0
1
Update IR 0
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ADVANCED INFORMATION Rev. 00A 07/17/02
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IS61NVVP25672 IS61NVVP51236
TAP AC TEST CONDITIONS
Input pulse levels Input rise and fall times Input timing reference levels Output reference levels Test load termination supply voltage 0.2 to 1.6V 1ns 0.9V 0.9V 0.9V
ISSI
(R)
TAP OUTPUT LOAD EQUIVALENT
50 0.9V
TDO Z0 = 50 20 pF GND
TAP TIMING
1 tTHTH TCK tMVTH tTHMX TMS tDVTH tTHDX TDI tTLOV TDO tTLOX DON'T CARE UNDEFINED 2 tTLTH tTHTL 3 4 5 6
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IS61NVVP25672 IS61NVVP51236
ISSI
X36 Ball Location
W6 V7 V8 U8 V9 U6 U5 W7 U7 T6 M6 J6 K6 D6 C7 C8 C9 B8 B9 B6 A6 B7 A8 A9 F6 A3 A4 A5 A7 B5 18 19 20 21 22 23 24 25 26 27 28 29 W ADV A CE2 A NC A CE2 A A A Bc 16 17 Ba Bb
(R)
BOUNDARY SCAN ORDER ASSIGNMENTS (by Exit Sequence) PH =Place Holder
X72 Sequence
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Pkg. Ball
A0 A A A A A PH
(1)
Sequence
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Pkg. Ball
A0 A A A A A PH(1) A PH(1) Mode NC(2) NC(2) CKE OE PH(1)
Ball Location
A PH
(1)
Mode NC
(2)
NC(2) CKE OE PH
(1)
Be Ba Bb Bf W ADV A CE2 A NC(2) A CE2 A A
30 31 32 33 34 35 36
Bc Bg Bh Bd PH
(1)
B3 B4 C3 C4 C5 C6 G6
30 31 32 33
Bd PH(1) CE NC
CE NC
(2)
Notes:
1.Input of PH register connected to VSS 2. NC = Don't care
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IS61NVVP25672 IS61NVVP51236
BOUNDARY SCAN ORDER ASSIGNMENTS (by Exit Sequence) Continued:
X72 Sequence
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73
ISSI
X36 Ball Location
H6 K3 L6 N6 P6 V3 U4 V4 V5 W5 V6 W2 W1 V2 V1 U2 U1 T2 T1 R1 R2 P2 P1 N2 N1 M2 M1 L2 L1 K2 K1 J2 J1 H2 H1 G2 G1 54 55 56 57 58 59 60 61 NC(2) NC(2) DQc DQc DQc DQc DQc DQc
(R)
Pkg. Ball
NC
(2)
Sequence
34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
Pkg. Ball
NC
(2)
Ball Location
CK NC(2) NC(2) ZZ A A A A A A DQd DQd DQd DQd DQd DQd DQd DQd DQPd DQPh DQh DQh DQh DQh DQh DQh DQh DQh NC
(2)
CK NC(2) NC(2) ZZ A A A A A A1 DQd DQd DQd DQd DQd DQd DQd DQd DQPd
NC(2) DQc DQc DQc DQc DQc DQc
Notes:
1.Input of PH register connected to VSS 2. NC = Don't care
26
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IS61NVVP25672 IS61NVVP51236
BOUNDARY SCAN ORDER ASSIGNMENTS (by Exit Sequence) Continued:
X72 Sequence
74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110
ISSI
X36 Ball Location
F2 F1 E2 E1 D2 D1 C2 C1 B2 B1 A2 A1 A10 A11 B10 B11 C10 C11 D10 D11 E11 E10 F10 F11 G10 G11 H10 H11 J10 J11 K11 K10 L10 L11 M10 M11 N10 74 75 76 77 78 79 80 NC(2) NC(2) DQa DQa DQa DQa DQa 65 66 67 68 69 70 71 72 73 DQb DQb DQb DQb DQb DQb DQb DQb DQPb
(R)
Pkg. Ball
DQc DQc DQPc DQPg DQg DQg DQg DQg DQg DQg DQg DQg DQb DQb DQb DQb DQb DQb DQb DQb DQPb DQPf DQf DQf DQf DQf DQf DQf DQf DQf NC
(2)
Sequence
62 63 64
Pkg. Ball
DQc DQc DQPc
Ball Location
NC(2) DQa DQa DQa DQa DQa
Notes:
1.Input of PH register connected to VSS 2. NC = Don't care
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ADVANCED INFORMATION Rev. 00A 07/17/02
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IS61NVVP25672 IS61NVVP51236
BOUNDARY SCAN ORDER ASSIGNMENTS (by Exit Sequence) Continued:
X72 Sequence
111 112 113 114 115 116 117 118 119 120 121 122 123
ISSI
X36 Ball Location
N11 P10 P11 R10 R11 T10 T11 U10 U11 V10 V11 W10 W11
(R)
Pkg. Ball
DQa DQa DQa8 DQPa9 DQPe DQe DQe DQe DQe DQe DQe DQe DQe
Sequence
81 82 83 84
Pkg. Ball
DQa DQa DQa8 DQPa9
Ball Location
Notes:
1.Input of PH register connected to VSS 2. NC = Don't care
28
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ADVANCED INFORMATION Rev. 00A 07/17/02
IS61NVVP25672 IS61NVVP51236
ORDERING INFORMATION Commercial Range: 0C to +70C
Frequency 256Kx72 250 200 512Kx36 250 200 IS61NVVP51236-250B IS61NVVP51236-200B PBGA PBGA IS61NVVP25672-250B IS61NVVP25672-200B PBGA PBGA Order Part Number Package
ISSI
Industrial Range: -40C to +85C
Frequency 256Kx72 250 200 512Kx36 250 200 IS61NVVP51236-250BI IS61NVVP51236-200BI PBGA PBGA IS61NVVP25672-250BI IS61NVVP25672-200BI PBGA PBGA Order Part Number Package
(R)
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