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| IPDH4N03LA G IPSH4N03LA G OptiMOS(R)2 Power-Transistor Features * Ideal for high-frequency dc/dc converters * Qualified according to JEDEC1) for target applications * N-channel, logic level * Excellent gate charge x R DS(on) product (FOM) * Superior thermal resistance * 175 C operating temperature * Pb-free lead plating; RoHS compliant Product Summary V DS R DS(on),max (SMD Version) ID 25 4.2 90 V m A Type IPDH4N03LA G IPSH4N03LA G Package Ordering Code Marking P-TO252-3-11 Q67042-S4250 H4N03LA P-TO251-3-11 Q67042-S4254 H4N03LA Maximum ratings, at T j=25 C, unless otherwise specified Parameter Continuous drain current Symbol Conditions ID T C=25 C2) T C=100 C Pulsed drain current Avalanche energy, single pulse Reverse diode dv /dt Gate source voltage4) Power dissipation Operating and storage temperature IEC climatic category; DIN IEC 68-1 I D,pulse E AS dv /dt V GS P tot T j, T stg T C=25 C T C=25 C3) I D=90 A, R GS=25 I D=90 A, V DS=20 V, di /dt =200 A/s, T j,max=175 C Value 90 77 360 150 6 20 94 -55 ... 175 55/175/56 mJ kV/s V W C Unit A Rev. 0.92 - target data sheet page 1 2004-10-27 IPDH4N03LA G Parameter Symbol Conditions min. Thermal characteristics Thermal resistance, junction - case SMD version, device on PCB R thJC R thJA minimal footprint 6 cm2 cooling area5) Electrical characteristics, at T j=25 C, unless otherwise specified Static characteristics Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current V (BR)DSS V GS=0 V, I D=1 mA V GS(th) I DSS V DS=V GS, I D=40 A V DS=25 V, V GS=0 V, T j=25 C V DS=25 V, V GS=0 V, T j=125 C Gate-source leakage current Drain-source on-state resistance I GSS R DS(on) V GS=20 V, V DS=0 V V GS=4.5 V, I D=50 A V GS=4.5 V, I D=50 A, SMD version V GS=10 V, I D=60 A V GS=10 V, I D=60 A, SMD version Gate resistance Transconductance RG g fs |V DS|>2|I D|R DS(on)max, I D=60 A 25 1.2 1.6 0.1 Values typ. IPSH4N03LA G Unit max. 1.6 75 50 K/W 2 1 V A 45 10 10 6.1 5.9 3.7 3.5 1.3 90 100 100 7.6 7.4 4.4 4.2 S nA m 1) J-STD20 and JESD22 Current is limited by bondwire; with an R thJC=1.6 K/W the chip is able to carry 109 A. See figure 3 T j,max=150 C and duty cycle D <0.25 for V GS<-5 V 1) 3) 4) 5) 2 Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm (one layer, 70 m thick) copper area for drain connection. PCB is vertical in still air. Rev. 0.92 - target data sheet page 2 2004-10-27 IPDH4N03LA G Parameter Symbol Conditions min. Dynamic characteristics Input capacitance Output capacitance Reverse transfer capacitance Turn-on delay time Rise time Turn-off delay time Fall time Gate Charge Characteristics 6) Gate to source charge Gate charge at threshold Gate to drain charge Switching charge Gate charge total Gate plateau voltage Gate charge total, sync. FET Output charge Reverse Diode Diode continous forward current Diode pulse current Diode forward voltage IS I S,pulse V SD T C=25 C V GS=0 V, I F=78 A, T j=25 C V R=15 V, I F=I S, di F/dt =400 A/s 0.93 Q gs Q g(th) Q gd Q sw Qg V plateau Q g(sync) Q oss V DS=0.1 V, V GS=0 to 5 V V DD=15 V, V GS=0 V V DD=15 V, I D=45 A, V GS=0 to 5 V 8 3.9 5.6 10 19 3.4 17 20 C iss C oss Crss t d(on) tr t d(off) tf V DD=15 V, V GS=10 V, I D=25 A, R G=2.7 V GS=0 V, V DS=15 V, f =1 MHz 2400 920 110 9 7 29 4.6 Values typ. IPSH4N03LA G Unit max. 3200 1200 160 14 11 44 7 pF ns 11 5.1 8 14 26 23 27 nC V nC 78 360 1.2 A V Reverse recovery charge Q rr - - 15 nC 6) See figure 16 for gate charge parameter definition Rev. 0.92 - target data sheet page 3 2004-10-27 Rev. 0.92 - target data sheet page 4 2004-10-27 IPDH4N03LA G 1 Power dissipation P tot=f(T C) 2 Drain current I D=f(T C); V GS10 V IPSH4N03LA G 120 100 100 80 80 60 P tot [W] 60 I D [A] 40 20 0 0 50 100 150 200 0 50 100 150 200 40 20 0 T C [C] T C [C] 3 Safe operating area I D=f(V DS); T C=25 C; D =0 parameter: t p 1000 4 Max. transient thermal impedance Z thJC=f(t p) parameter: D =t p/T 10 limited by on-state resistance 10 s 100 s 1 s 100 1 0.5 I D [A] DC 1 ms Z thJC [K/W] 0.2 0.1 0.05 10 10 ms 0.1 0.02 0.01 single pulse 1 0.1 1 10 100 0.01 10-6 10-5 10-4 10-3 10-2 10-1 100 V DS [V] t p [s] Rev. 0.92 - target data sheet page 5 2004-10-27 IPDH4N03LA G 5 Typ. output characteristics I D=f(V DS); T j=25 C parameter: V GS 100 4.5 V 4V IPSH4N03LA G 6 Typ. drain-source on resistance R DS(on)=f(I D); T j=25 C parameter: V GS 16 3V 3.2 V 3.4 V 3.7 V 90 80 10 V 4V 14 12 70 3.7 V 50 40 30 20 3V 3.4 V R DS(on) [m] 60 10 I D [A] 8 4.5 V 6 3.2 V 4 10 V 10 0 0 1 2 2 2.8 V 0 3 0 20 40 60 80 100 V DS [V] I D [A] 7 Typ. transfer characteristics I D=f(V GS); |V DS|>2|I D|R DS(on)max parameter: T j 100 8 Typ. forward transconductance g fs=f(I D); T j=25 C 140 120 80 100 60 g fs [S] 40 20 175 C 25 C I D [A] 80 60 40 20 0 0 1 2 3 4 5 0 0 20 40 60 80 100 V GS [V] I D [A] Rev. 0.92 - target data sheet page 6 2004-10-27 IPDH4N03LA G 9 Drain-source on-state resistance R DS(on)=f(T j); I D=60 A; V GS=10 V 10 Typ. gate threshold voltage V GS(th)=f(T j); V GS=V DS parameter: I D 8 2.5 IPSH4N03LA G 7 2 6 400 A R DS(on) [m] 5 98 % V GS(th) [V] 1.5 40 A 4 typ 3 1 2 0.5 1 0 -60 -20 20 60 100 140 180 0 -60 -20 20 60 100 140 180 T j [C] T j [C] 11 Typ. capacitances C =f(V DS); V GS=0 V; f =1 MHz 12 Forward characteristics of reverse diode I F=f(V SD) parameter: T j 104 1000 25 C, 98% Ciss 103 Coss 100 175 C 25 C 175 C, 98% C [pF] Crss 102 I F [A] 10 101 0 10 20 30 1 0.0 0.5 1.0 1.5 2.0 V DS [V] V SD [V] Rev. 0.92 - target data sheet page 7 2004-10-27 IPDH4N03LA G 13 Avalanche characteristics I AS=f(t AV); R GS=25 parameter: Tj(start) 100 25 C 150 C 100 C IPSH4N03LA G 14 Typ. gate charge V GS=f(Q gate); I D=45 A pulsed parameter: V DD 12 15 V 10 5V 20 V 8 10 V GS [V] 1 10 100 1000 I AV [A] 6 4 2 1 0 0 10 20 30 40 t AV [s] Q gate [nC] 15 Drain-source breakdown voltage V BR(DSS)=f(T j); I D=1 mA 16 Gate charge waveforms 29 V GS 28 27 26 Qg V BR(DSS) [V] 25 24 23 22 21 20 -60 -20 20 60 100 140 180 V g s(th) Q g(th) Q gs Q sw Q gd Q g ate T j [C] Rev. 0.92 - target data sheet page 8 2004-10-27 IPDH4N03LA G Package Outline P-TO252-3-11: Outline IPSH4N03LA G Footprint: Packaging: Dimensions in mm Rev. 0.92 - target data sheet page 9 2004-10-27 |
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