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Memory Module Specifications
KVR533D2S8F4/512I 512MB 64M x 72-Bit PC2-4200 CL4 ECC 240-Pin FBDIMM
Description:
This document describes ValueRAM's 512MB (64M x 72-bit) PC2-4200 CL4 SDRAM (Synchronous DRAM) "fully buffered" ECC "single rank" Intel Certified memory module. This module is based on nine 64M x 8-bit 533MHz DDR2 FBGA components. The module also includes an AMB device (Advanced Memory Buffer). The electrical and mechanical specifications are as follows:
Feature:
* * * * * * * * * * * * * FBDIMM Module: 240-pin JEDEC Standard: R/C A Memory Organization: 1 rank of x8 devices DDR2 DRAM Interface: SSTL_18 DDR2 Speed Grade: 533 Mbps CAS Latency: 4-4-4 Module Bandwidth: 4.2 GB/s DRAM: VDD = VDDQ = 1.8V AMB: VCC = VCCFBD = 1.5V EEPROM: VDDSPD = 3.3V (typical) Heat Spreader: Full DIMM Heat Spreader (FDHS) PCB Height: 30.35mm, double-side RoHS Compliant
VALUERAM0502-001.A00
08/28/06
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DDR2 240-pin FBDIMM Pinout:
Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Front Side
VDD VDD VDD VSS VDD VDD VDD VSS VCC VCC VSS VCC VCC VSS VTT VID1 RESET VSS RFU** RFU** VSS PN0 PN0 VSS PN1 PN1 VSS PN2 PN2 VSS
Pin #
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136
Back Side
VDD VDD VDD VSS VDD VDD VDD VSS VCC VCC VSS VCC VCC VSS VTT VID0
Pin #
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Front Side
PN3 PN3 VSS PN4 PN4 VSS PN5 PN5 VSS PN13 PN13 VSS VSS RFU* RFU* VSS VSS PN12 PN12 VSS PN6 PN6 VSS PN7 PN7 VSS PN8 PN8 VSS PN9
Pin #
151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180
Back Side
SN3 SN3 VSS SN4 SN4 VSS SN5 SN5 VSS SN13 SN13 VSS VSS RFU* RFU* VSS VSS SN12 SN12 VSS SN6 SN6 VSS SN7 SN7 VSS SN8 SN8 VSS SN9
Pin #
61 62 63 64 65 66 67 68
Front Side
PN9 VSS PN10 PN10 VSS PN11 PN11 VSS
Pin #
181 182 183 184 185 186 187 188 KEY
Back Side
SN9 VSS SN10 SN10 VSS SN11 SN11 VSS
Pin #
91 92 93 94 95 96 97 98 99
Front Side
PS9 VSS PS5 PS5 VSS PS6 PS6 VSS PS7 PS7 VSS PS8 PS8 VSS RFU** RFU** VSS VDD VDD VSS VDD VDD VDD VSS VDD VDD VTT SA2 SDA SCL
Pin #
211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240
Back Side
SS9 VSS SS5 SS5 VSS SS6 SS6 VSS SS7 SS7 VSS SS8 SS8 VSS RFU** RFU** VSS SCK SCK VSS VDD VDD VDD VSS VDD VDD VTT VDDSPD SA0 SA1
69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
VSS PS0 PS0 VSS PS1 PS1 VSS PS2 PS2 VSS PS3 PS3 VSS PS4 PS4 VSS VSS RFU* RFU* VSS VSS PS9
189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210
VSS SS0 SS0 VSS SS1 SS1 VSS SS2 SS2 VSS SS3 SS3 VSS SS4 SS4 VSS VSS RFU* RFU* VSS VSS SS9
100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
137 DNU/M_Test 138 139 140 141 142 143 144 145 146 147 148 149 150 VSS RFU** RFU** VSS SN0 SN0 VSS SN1 SN1 VSS SN2 SN2 VSS
RFU = Reserved Future Use. * These pin positions are reserved for forwarded clocks to be used in future module implementations ** These pin positions are reserved for future architecture flexibility 1) The following signals are CRC bits and thus appear out of the normal sequence: PN12/PN12, SN12/SN12, PN13/PN13, SN13/SN13, PS9/PS9, SS9/SS9
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DIMM Connector Pin Description:
Pin Name SCK SCK PN[13:0] PN[13:0] PS[9:0] PS[9:0] SN[13:0] SN[13:0] SS[9:0] SS[9:0] SCL SDA SA[2:0] VID[1:0] RESET RFU VCC VDD VTT VDDSPD VSS Pin Description System Clock Input, positive line1 System Clock Input, negative line1 Primary Northbound Data, positive lines Primary Northbound Data, negative lines Primary Southbound Data, positive lines Primary Southbound Data, negative lines Secondary Northbound Data, positive lines Secondary Northbound Data, negative lines Secondary Southbound Data, positive lines Secondary Southbound Data, negative lines Serial Presence Detect (SPD) Clock Input SPD Data Input / Output SPD Address Inputs, also used to select the DIMM number in the AMB Voltage ID: These pins must be unconnected for DDR2-based Fully Buffered DIMMs VID[0] is VDD value: OPEN = 1.8 V, GND = 1.5 V; VID[1] is V CC value: OPEN = 1.5 V, GND = 1.2 V AMB reset signal Reserved for Future Use
2
Count 1 1 14 14 10 10 14 14 10 10 1 1 3 2 1 16 8 24 4 1 80
AMB Core Power and AMB Channel Interface Power (1.5 Volt) DRAM Power and AMB DRAM I/O Power (1.8 Volt) DRAM Address/Command/Clock Termination Power (V DD/2) SPD Power Ground The DNU/M_Test pin provides an exter nal connection on R/Cs A-D for testing the margin of Vref which is produced by a voltage divider on the module. It is not intended to be used in normal system operation and must not be connected (DNU) in a system. This test pin may have other features on future card designs and if it does, will be included in this specification at that time. 1 Total
DNU/M_Test
1
240
1. System Clock Signals SCK and SCK switch at one half the DRAM CK/CK frequency 2. Eight pins reserved for forwarded clocks, eight pins reserved for future architecture flexibility
Absolute Maximum Ratings
Symbol VIN, VOUT VCC VDD VTT TSTG TCASE Parameter Voltage on any pin relative to V Voltage V DD pin relative to Vss Voltage on V TT pin relative to V SS Storage temperature DDR2 SDRAM device operat ing temperature (Ambient) AMB device operating temperature (Ambient)
SS
MIN -0.3 -0.3 -0.5 -0.5 -55 0 0
MAX 1.75 1.75 2.3 2.3 100 95 (1) 110
Units V V V V C C C
Voltage on V CC pin relative to V SS
Note: (1) Above 85C DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 s.
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Functional Block Diagram:
S0 DQS0 DQS0 DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQS1 DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQS2 DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQS3 DQS12 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DM/ NU/ RDQS RDQS CS DQS DQS DM/ NU/ RDQS RDQS CS DQS DQS DM/ NU/ RDQS RDQS CS DQS DQS DM/ NU/ RDQS RDQS CS DQS DQS
DQS4 DQS4 DQS13 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DQS5 DQS14 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DQS6 DQS15 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DQS7 DQS16 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS8 DQS8 DQS17 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
DM/ NU/ RDQS RDQS CS DQS DQS DM/ NU/ RDQS RDQS CS DQS DQS DM/ NU/ RDQS RDQS CS DQS DQS DM/ NU/ RDQS RDQS CS DQS DQS DM/ NU/ RDQS RDQS CS DQS DQS
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D0
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D4
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D1
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D5
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D2
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D6
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D3
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D7
PN0-PN13 PN0-PN13 PS0-PS9 PS0-PS9
SN0-SN13 SN0-SN13 SS0-SS9 SS0-SS9
A M B
SCL SDA SA1-SA2 SA0 RESET SCK/SCK
S0 -> CS (all SDRAMs) CKE0 -> CKE (all SDRAMs) ODT -> ODT (all SDRAMs) BA0-BA2 (all SDRAMs) A0-A15 (all SDRAMs) RAS (all SDRAMs) CAS (all SDRAMs) WE (all SDRAMs) CK/CK (all SDRAMs)
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D8
VTT VCC
22
Terminators AMB SPD, AMB D0-D8, AMB D0-D8 D0-D8,SPD,AMB
825 All address/command/control/clock
VTT
VDDSPD VDD
trol/clock
Notes: 1. DQ-to-I/O wiring may be changed within a byte. 2. There are two physical copies of each address/command/con-
Serial PD SCL WP A0 A1 A2 SA0 SA1 SA2 SDA
VREF VSS
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Architecture:
Advanced Memory Buffer Pin Description:
Pin Name Pin Description Count
FB-DIMM Channel Signals
SCK SCK PN[13:0] PN[13:0] PS[9:0] PS[9:0] SN[13:0] SN[13:0] SS[9:0] SS[9:0] FBDRES System Clock Input, positive line System Clock Input, negative line Primary Northbound Data, positive lines Primary Northbound Data, negative lines Primary Southbound Data, positive lines Primary Southbound Data, negative lines Secondary Northbound Data, positive lines Secondary Northbound Data, negative lines Secondary Southbound Data, positive lines Secondary Southbound Data, negative lines To an external precision calibration resistor connected to Vcc
99
1 1 14 14 10 10 14 14 10 10 1
DDR2 Interface Signals
DQS[8:0] DQS[8:0] DQS[17:9]/DM[8:0] DQS[17:9] DQ[63:0] CB[7:0] A[15:0]A, A[15:0]B BA[2:0]A, BA[2:0]B RASA, RASB CASA, CASB WEA, WEB ODTA, ODTB CS[1:0]A, CS[1:0]B CLK[3:0] CLK[3:0] DDRC_C14 DDRC_B18 DDRC_C18 DDRC_B12 DDRC_C12 Data Strobes, positive lines Data Strobes, negative lines Data Strobes (x4 DRAM only), positive lines. These signals are driven low to x8 DRAM on writes. Data Strobes (x4 DRAM only), negative lines Data Checkbits Addresses. A10 is part of the pre-charge command Bank Addresses Part of command, with CAS, WE, and CS[1:0]. Part of command, with RAS, WE, and CS[1:0]. Part of command, with RAS, CAS, and CS[1:0]. On-die Termination Enable Chip Select (one per rank)
175
9 9 9 9 64 8 32 6 2 2 2 2 4 4
CKE[1:0]A, CKE[1:0]B Clock Enable (one per rank)
CLK[1:0] used on 9 and 18 device DIMMs, CLK[3:0] used on 36 device DIMMs. CLK[3:2] should be out4 put disabled when not in use. Negative lines for CLK[3:0] DDR Compensation: Common return pin for DDRC_B18 and DDRC_C18. DDR Compensation: Resistor connected to common return pin DDRC_C14 DDR Compensation: Resistor connected to common return pin DDRC_C14 DDR Compensation: Resistor connected to VSS DDR Compensation: Resistor connected to VDD 4 1 1 1 1 1
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Advanced Memory Buffer Pin Description: SPD Bus Interface Signals
SCL SDA SA[2:0] Serial Presence Detect (SPD) Clock Input SPD Data Input / Output SPD Address Inputs, also used to select the DIMM number in the AMB
5
1 1 3
Miscellaneous Signals
PLLTSTO VCCAPLL VSSAPLL TEST_pin# TESTLO_pin# BFUNC RESET NC RFU PLL Clock Observability Output Analog VCC for the PLL. Tied with low pass filter to VCC. Analog VSS for the PLL. Tied to ground on the AMB die. Do not tie to ground on the DIMM. Leave floating on the DIMM Tie to ground on the DIMM AMB reset signal No connect. Many NC are connected to VDD on the DIMM, to lower the impedance of the VDD power islands. Reserved for Future Use
2
163
1 1 1 6 5 1 1 129 18
Tie to ground to set functionality as buffer on DIMM.
Power/Ground Signals
VCC VCCFBD VDD VDDSPD VSS AMB Core Power (1.5 Volt) AMB Channel I/O Power (1.5 Volt) AMB DRAM I/O Power (1.8 Volt) SPD Power (3.3 Volt) Ground
213
24 8 24 1 156
Total
655
1. System Clock Signals SCK and SCK switch at one half the DRAM CK/CK frequency. 2. TESTLO_AB20 and TESTLO_AC20 should be configured for debug purposes on prototype DIMMs: each pin should have a zero ohm resistor pulldown to ground, and an unpopulated resistor pullup to VCC. These resistors can be replaced on production DIMMs with a direct connection to ground.
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Package Dimensions:
TECHNOLOGY
FBGA DDR2 SDRAM
FBGA DDR2 SDRAM
Advanced Memory Buffer
AMB
FBGA DDR2 SDRAM
FBGA DDR2 SDRAM
(Units = millimeters)
0.346 (8.8) MAX with heat sink
Units: inches (millimeters)
45x 0.0071(0.18) 0.047 (1.19) 0.042 (1.06) 0.042 (1.06)
0.054 (1.37) 0.046 (1.17)
Detail A
VALUERAM0502-001.A00
TECHNOLOGY
FBGA DDR2 SDRAM
FBGA DDR2 SDRAM
FBGA DDR2 SDRAM
FBGA DDR2 SDRAM
FBGA DDR2 SDRAM
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