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M36W0R5020T0 M36W0R5020B0
32 Mbit (2Mb x16, Multiple Bank, Burst) Flash Memory and 4 Mbit SRAM, 1.8V Supply Multi-Chip Package
FEATURES SUMMARY
MULTI-CHIP PACKAGE - 1 die of 32 Mbit (2Mb x 16) Flash Memory - 1 die of 4 Mbit (256Kb x16) SRAM SUPPLY VOLTAGE - VDDF = VDDQ = VDDS = 1.7 to 1.95V LOW POWER CONSUMPTION ELECTRONIC SIGNATURE - Manufacturer Code: 20h - Device Code (Top Flash Configuration): 8814h - Device Code (Bottom Flash Configuration): 8815h PACKAGE - Compliant with Lead-Free Soldering Processes - Lead-Free Versions FLASH MEMORY PROGRAMMING TIME - 8s by Word typical for Fast Factory Program - Double/Quadruple Word Program option - Enhanced Factory Program options MEMORY BLOCKS - Multiple Bank Memory Array: 4 Mbit Banks - Parameter Blocks (Top or Bottom location) SYNCHRONOUS / ASYNCHRONOUS READ - Synchronous Burst Read mode: 66MHz - Asynchronous/ Synchronous Page Read mode - Random Access: 70ns DUAL OPERATIONS - Program Erase in one Bank while Read in others - No delay between Read and Write operations
Figure 1. Package
FBGA
Stacked TFBGA88 (ZAQ)
BLOCK LOCKING - All blocks locked at Power-up - Any combination of blocks can be locked - WPF for Block Lock-Down SECURITY - 128-bit user programmable OTP cells - 64-bit unique device number COMMON FLASH INTERFACE (CFI) 100,000 PROGRAM/ERASE CYCLES per BLOCK SRAM ACCESS TIME: 70ns LOW VDDS DATA RETENTION: 1.0V POWER DOWN FEATURES USING TWO CHIP ENABLE INPUTS
December 2004
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M36W0R5020T0, M36W0R5020B0
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Chip Enable (EF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Output Enable (GF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Write Enable (WF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Write Protect (WPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Reset (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Latch Enable (LF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Clock (KF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Wait (WAITF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SRAM Chip Enable inputs (E1S, E2S). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SRAM Write Enable (WS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SRAM Output Enable (GS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SRAM Upper Byte Enable (UBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SRAM Lower Byte Enable (LBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VDDF Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VDDS Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VDDQ Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VPPF Program Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VSS Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2. Main Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 FLASH MEMORY COMPONENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SRAM COMPONENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5. SRAM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SRAM OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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M36W0R5020T0, M36W0R5020B0
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Standby/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 4. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 6. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 7. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 5. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 6. Flash Memory DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 7. Flash Memory DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 8. SRAM DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8. SRAM Read Mode AC Waveforms, Address Controlled with UBS = LBS = VIL . . . . . . . 16 Figure 9. SRAM Read AC Waveforms, GS Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 10.SRAM Standby AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 9. SRAM Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 11.SRAM Write AC Waveforms, E1S or E2S Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 12.SRAM Write AC Waveforms, WS Controlled, GS High during Write . . . . . . . . . . . . . . . . 19 Figure 13.SRAM Write AC Waveforms, WS Controlled with GS Low . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 14.SRAM Write AC Waveform, UBS and LBS Controlled GS Low . . . . . . . . . . . . . . . . . . . . 20 Table 10. SRAM Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 15.SRAM Low VDDS Data Retention AC Waveforms, E1S or UBS / LBS Controlled . . . . . . 22 Figure 16.SRAM Low VDDS Data Retention AC Waveforms, E2S Controlled . . . . . . . . . . . . . . . . . 22 Table 11. SRAM Low VDDS Data Retention Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 17. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Outline . . 23 Table 12. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Mechanical Data . . 23 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 13. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 14. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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M36W0R5020T0, M36W0R5020B0
SUMMARY DESCRIPTION
The M36W0R5020T0 and M36W0R5020B0 combine two memory devices in a Multi-Chip Package: a 32-Mbit, Multiple Bank Flash memory, the M58WR032FT/B and a 4-Mbit SRAM. Recommended operating conditions do not allow more than one memory to be active at the same time. The memory is offered in a Stacked TFBGA88 (8 x 10mm, 8x10 ball array, 0.8mm pitch) package. In addition to the standard version, the package is also available in Lead-free version, in compliance with JEDEC Std J-STD-020B, the ST ECOPACK 7191395 Specification, and the RoHS (Restriction of Hazardous Substances) directive. All packages are compliant with Lead-free soldering processes. The memory supplied with all the bits erased (set to `1'). Figure 2. Logic Diagram
VDDQ VDDF 21 A0-A20 DQ0-DQ15 EF GF WF RPF WPF LF KF E1S GS WS E2S UBS LBS M36W0R5020T M36W0R5020B WAITF VPPF VDDS 16
Table 1. Signal Names
A0-A20 (1) DQ0-DQ15 VDDF VDDQ VPPF VSS VDDS NC DU Flash Memory LF EF GF WF RPF WPF KF WAITF SRAM E1S, E2S GS WS UBS LBS Chip Enable input Output Enable input Write Enable input Upper Byte Enable input Lower Byte Enable input Latch Enable input Chip Enable input Output Enable input Write Enable input Reset input Write Protect input Burst Clock Wait Data in Burst Mode Address Inputs Common Data Input/Output Flash Memory Power Supply Common Flash and SRAM Power Supply for I/O Buffers Common Flash Optional Supply Voltage for Fast Program and Erase Ground SRAM Power Supply Not Connected Internally Do Not Use as Internally Connected
Note: 1. A20-A18 are address inputs for the Flash memory component only.
VSS
AI08754b
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M36W0R5020T0, M36W0R5020B0
Figure 3. TFBGA Connections (Top view through package)
1
2
3
4
5
6
7
8
A
DU
DU
DU
DU
B
A4
A18
A19
VSS
VDDF
NC
NC
A11
C
A5
LBS
NC
VSS
E2S
KF
NC
A12
D
A3
A17
NC
VPPF
WS
NC
A9
A13
E
A2
A7
NC
WPF
LF
A20
A10
A15
F
A1
A6
UBS
RPF
WF
A8
A14
A16
G
A0
DQ8
DQ2
DQ10
DQ5
DQ13
WAITF
NC
H
GS
DQ0
DQ1
DQ3
DQ12
DQ14
DQ7
NC
J
E1S
GF
DQ9
DQ11
DQ4
DQ6
DQ15
VDDQ
K
EF
NC
NC
VDDS
NC
NC
VDDQ
NC
L
VSS
VSS
VDDQ
VDDF
VSS
VSS
VSS
VSS
M
DU
DU
DU
DU
AI08755
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M36W0R5020T0, M36W0R5020B0
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram and Table 1., Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A20). Addresses A0-A17 are common inputs for the Flash memory and SRAM components. The other lines (A18-A20) are inputs for the Flash memory component only. The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. The Flash memory is accessed through the Chip Enable signal (EF) and through the Write Enable (WF) signal, while the SRAM is accessed through two Chip Enable signals (E1S and E2S) and the Write Enable signal (WS). Data Input/Output (DQ0-DQ15). The Data I/O output the data stored at the selected address during a Bus Read operation or input a command or the data to be programmed during a Write Bus operation. Flash Chip Enable (EF). The Chip Enable input activates the Flash memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is Low, VIL, and Reset is High, VIH, the device is in active mode. When Chip Enable is at VIH the Flash memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. It is not allowed to set EF at VIL, E1S at VIL and E2S at VIH at the same time. Flash Output Enable (GF). The Output Enable pin controls data outputs during Flash memory Bus Read operations. Flash Write Enable (WF). The Write Enable input controls the Bus Write operation of the Flash memory's Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first. Flash Write Protect (WPF). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is Low, VIL, Lock-Down is enabled and the protection status of the Locked-Down blocks cannot be changed. When Write Protect is at High, VIH, Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (Refer to Lock Status Table in M58WR032FT/B datasheet). Flash Reset (RPF). The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in Reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current IDD2. Refer to Table 6., Flash Memory DC Characteristics - Currents, for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting Reset mode the device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to VRPH (refer to Table 7., Flash Memory DC Characteristics - Voltages). Flash Latch Enable (LF). Latch Enable latches the address bits on its rising edge. The address latch is transparent when Latch Enable is Low, VIL, and it is inhibited when Latch Enable is High, VIH. Latch Enable can be kept Low (also at board level) when the Latch Enable function is not required or supported. Flash Clock (KF). The Clock input synchronizes the Flash memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, according to the configuration settings) when Latch Enable is at VIL. Clock is don't care during Asynchronous Read and in write operations. Flash Wait (WAITF). WAIT is a Flash memory output signal used during Synchronous Read to indicate whether the data on the output bus are valid. This output is high impedance when the Flash memory Chip Enable is at VIH or Reset is at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance. The WAITF signal is not gated by Output Enable. SRAM Chip Enable inputs (E1S, E2S). The Chip Enable inputs activate the SRAM memory control logic, input buffers and decoders. E1S at VIH with E2S at VIH deselects the memory, reducing the power consumption to the standby level, whereas E2S at VIL deselects the memory and reduces the power consumption to the Power-down level, regardless of the level of E1S. E1S and E2S can also be used to control writing to the SRAM memory array, while WS remains at VIL. It is not allowed to set EF at VIL, E1S at VIL and E2S at VIH at the same time. SRAM Write Enable (WS). The Write Enable input controls writing to the SRAM memory array. WS is active low. SRAM Output Enable (GS). The Output Enable gates the outputs through the data buffers during a Read operation of the SRAM memory. GS is active low. SRAM Upper Byte Enable (UBS). The Upper Byte Enable input enables the upper byte for SRAM (DQ8-DQ15). UBS is active low.
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M36W0R5020T0, M36W0R5020B0
SRAM Lower Byte Enable (LBS). The Lower Byte Enable input enables the lower byte for SRAM (DQ0-DQ7). LBS is active low. VDDF Supply Voltage. VDDF provides the power supply to the internal core of the Flash memory component. It is the main power supply for all Flash memory operations (Read, Program and Erase). VDDS Supply Voltage. VDDS provides the power supply to the internal core of the SRAM device. It is the main power supply for all SRAM operations. VDDQ Supply Voltage. VDDQ provides the power supply for the Flash memory and SRAM I/O pins. This allows all Outputs to be powered independently of the Flash memory and SRAM core power supplies: VDDF and VDDS, respectively. VPPF Program Supply Voltage. VPPF is a Flash memory power supply pin. The Supply Voltage VDDF and the Program Supply Voltage VPP can be applied in any order. The pin can also be used as a control input for the Flash memory. The two functions are selected by the voltage range applied to the pin. If VPPF is kept in a low voltage range (0V to VDDQ) VPPF is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection against program or erase, while VPPF > VPP1 enables these functions (see Tables 6 and 7, DC Characteristics for the relevant values). VPPF is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. If VPPF is in the range of VPPH it acts as a power supply pin. In this condition VPPF must be stable until the Program/Erase algorithm is completed. VSS Ground. VSS is the common ground reference for all voltage measurements in the Flash memory (core and I/O Buffers) and SRAM components. Note: Each Flash memory device in a system should have its supply voltage (VDDF) and the program supply voltage VPPF decoupled with a 0.1F ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 7., AC Measurement Load Circuit. The PCB track widths should be sufficient to carry the required VPPF program and erase currents.
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M36W0R5020T0, M36W0R5020B0
FUNCTIONAL DESCRIPTION
The Flash memory and SRAM components have separate power supplies but share the same grounds. They are distinguished by three Chip Enable inputs: EF for the Flash memory and E1S and E2S for the SRAM. Recommended operating conditions do not allow more than one device to be active at a time. The Figure 4. Functional Block Diagram most common example is simultaneous read operations on the Flash memory and SRAM components which would result in a data bus contention. Therefore it is recommended to put the other devices in the high impedance state when reading the selected device.
VDDF
VPPF
VDDQ
A18-A20
EF GF WF LF KF RPF A0-A17 WPF
32 Mbit Flash Memory
WAITF
DQ0-DQ15
VDDS
E1S GS WS E2S UBS LBS 4Mbit SRAM
VSS
AI08756b
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M36W0R5020T0, M36W0R5020B0
Table 2. Main Operating modes
Operation Flash Read Flash Write Flash Address Latch Flash Output Disable Flash Standby Flash Reset SRAM Read Flash Memory must be disabled SRAM Write Output Disable Any Flash mode is allowed. SRAM Standby X
Note: 1. 2. 3. 4.
EF VIL VIL VIL VIL VIH X
GF
VIL VIH X VIH X X
WF
VIH VIL VIH VIH X X
LF VIL(2) VIL(2) VIL X X X
RPF VIH VIH VIH VIH VIH VIL
WAITF(4)
E1S
E2S
GS
WS
UBS LBS
DQ15-DQ0 Flash Data Out
SRAM must be disabled
Flash Data In Flash Data Out or Hi-Z (3) Flash Hi-Z
Hi-Z Hi-Z VIL VIL VIL VIH
Any SRAM mode is allowed
Flash Hi-Z Flash Hi-Z
VIH VIH VIH X VIL
VIL X VIH X X
VIH VIL VIH X X
VIL VIL VIL X X
VIL VIL VIL X X
SRAM data out SRAM data in SRAM Hi-Z SRAM Hi-Z SRAM Hi-Z
X = Don't care. LF can be tied to VIH if the valid address has been previously latched. Depends on GF. WAIT signal polarity is configured using the Set Configuration Register command. Refer to M58WR032FT/B datasheet for details.
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M36W0R5020T0, M36W0R5020B0
FLASH MEMORY COMPONENT
The M36W0R5020T0 and M36W0R5020B0 contain a 32 Mbit Flash memory. For detailed information on how to use it, see the M58WR032FT/B datasheet which is available from your local STMicroelectronics distributor.
SRAM COMPONENT
The M36W0R5020T0 and M36W0R5020B0 contain a 4 Mbit SRAM. See Figure 5., SRAM Block Diagram in conjunction with the SRAM OPERAFigure 5. SRAM Block Diagram
DATA IN DRIVERS
TIONS section, Table 2., Main Operating modes and the SRAM AC Waveforms and Characteristics for details.
ROW DECODER
A0-A10
256K x16 RAM Array 2048 x 2048
SENSE AMPS
DQ0-DQ7 DQ8-DQ15
COLUMN DECODER
A11-A17
UBS WS GS LBS
E2S E1S
E2S POWER-DOWN CIRCUIT UBS LBS
AI08706b
E1S
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M36W0R5020T0, M36W0R5020B0
SRAM OPERATIONS
There are five standard operations that control the device. These are Read, Write, Standby/Powerdown, Data Retention and Output Disable. Read. Read operations are used to output the contents of the SRAM Array. The device is in Byte Read mode whenever Write Enable, WS, is at VIH, Output Enable, GS, is at VIL, Chip Enable, E1S, is at VIL, Chip Enable, E2S, is at VIH, and UBS or LBS is at VIL. The device is in Word Read mode whenever Write Enable, WS, is at VIH, Output Enable, GS, is at VIL, Byte Enable inputs UBS and LBS are both at VIL and the two Chip Enable inputs, E1S, and E2S are Don't Care. The Read and Standby AC Waveforms are shown in Figures 9 and 10, respectively and the parameters are given in Table 9., SRAM Read AC Characteristics. Write. Write operations are used to write data to the SRAM. The device is in Write mode whenever WS, E1S and UBS and/or LBS are at VIL, and E2S is at VIH. All these signals must be asserted to initiate a Write cycle. The data is latched on the falling edge of E1S, the rising edge of E2S, the falling edge of WS, or the falling edge of UBS and/or LBS, whichever occurs last. The Write cycle will terminate on the rising edge of E1S, the rising edge of WS, the rising edge of UBS and/or LBS, or the falling edge of E2S, whichever occurs first. The timings are referenced to the signal that terminates the Write cycle. The outputs are disabled during Write cycles (whenever E1S, at VIL, E2S at VIH, and WS at VIL). The Write AC Waveforms are shown in Figures 11, 12, 13 and 14, while Table 10. gives the Write AC Characteristics. Standby/Power-Down. The device automatically enters the Standby/Power-Down mode when DQ0-DQ15 are not toggling, reducing the power consumption to the Standby level, ISB. The device is also in Standby/Power-Down mode whenever E1S is at VIH, E2S is at VIL or both UBS and LBS are at VIH. The outputs then become high impedance. The Standby AC Waveforms are shown in Figure 10. See Table 9., SRAM Read AC Characteristics, for timings. Data Retention. The data retention mode is entered tCDR after de-asserting E1S, E2S or UBS and LBS. The data retention performance as VDD goes down to VDR is described in Table 11., Figures 15 and 16, SRAM Low VDDS Data Retention AC Waveforms, E1S or UBS / LBS Controlled and SRAM Low VDDS Data Retention AC Waveforms, E2S Controlled, respectively. Output Disable. The device is in the Output Disable mode whenever GS, is at VIH. In this mode, DQ0-DQ15 are high impedance.
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M36W0R5020T0, M36W0R5020B0
MAXIMUM RATING
Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 3. Absolute Maximum Ratings
Value Symbol TA TBIAS TSTG TLEAD VIO VDDF VDDQ VDDS VPPF IO tVPPFH Parameter Min Ambient Operating Temperature Temperature Under Bias Storage Temperature Lead Temperature During Soldering Input or Output Voltage Flash Memory Core Supply Voltage Input/Output Supply Voltage SRAM Supply Voltage Flash Memory Program Voltage Output Short Circuit Current Time for VPPF at VPPFH -0.5 -0.2 -0.2 -0.2 -0.2 -40 -40 -65 Max 85 125 155
(1)
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Unit C C C C V V V V V mA hours
VDDQ+0.6 2.45 2.45 2.4 14 100 100
Note: 1. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK (R) 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
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M36W0R5020T0, M36W0R5020B0
DC AND AC PARAMETERS
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 4., Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters.
Table 4. Operating and AC Measurement Conditions
Flash Memory Parameter Min VDDF Supply Voltage VDDS Supply Voltage VDDQ Supply Voltage 1.7 - 1.7 11.4 -0.4 -40 30 16.7 5 0 to VDDQ VDDQ/2 0 to VDDS VDDS/2 Max 1.95 - 1.95 12.6 VDDQ +0.4 85 Min - 1.7 - - - -40 30 16.7 1 Max - 1.95 - - - 85 V V V V V C pF k ns V V SRAM Unit
VPPF Supply Voltage (Factory environment) VPPF Supply Voltage (Application environment)
Ambient Operating Temperature Load Capacitance (CL) Output Circuit Resistors (R1, R2) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages
Figure 6. AC Measurement I/O Waveform
Figure 7. AC Measurement Load Circuit
VDDQ
VDDQ VDDQ/2 0V
VDDF
VDDQ R1 DEVICE UNDER TEST
AI06161
0.1F 0.1F
CL
R2
CL includes JIG capacitance
AI08364B
Table 5. Device Capacitance
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 12 15 Unit pF pF
Note: Sampled only, not 100% tested.
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M36W0R5020T0, M36W0R5020B0
Table 6. Flash Memory DC Characteristics - Currents
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Supply Current Asynchronous Read (f=6MHz) Test Condition 0V VIN VDDQ 0V VOUT VDDQ EF = VIL, GF = VIH 4 Word Supply Current Synchronous Read (f=54MHz) IDD1 8 Word 16 Word Continuous 4 Word Supply Current Synchronous Read (f=66MHz) 8 Word 16 Word Continuous IDD2 IDD3 IDD4 Supply Current (Reset) Supply Current (Standby) Supply Current (Automatic Standby) Supply Current (Program) IDD5 (1) Supply Current (Erase) RPF = VSS 0.2V EF = VDDF 0.2V EF = VIL, GF = VIH VPPF = VPPH VPPF = VDDF VPPF = VPPH VPPF = VDDF Program/Erase in one Bank, Asynchronous Read in another Bank Program/Erase in one Bank, Synchronous Read in another Bank EF = VDDF 0.2V VPPF = VPPH VPPF = VDDF VPPF = VPPH VPPF = VDDF VPPF VDDF VPPF VDDF 3 7 10 12 13 8 11 14 16 10 10 10 8 10 8 10 13 Min Typ Max 1 1 6 16 18 22 25 17 20 25 30 50 50 50 15 20 15 20 26 Unit A A mA mA mA mA mA mA mA mA mA A A A mA mA mA mA mA
Supply Current IDD6 (1,2) (Dual Operations)
23
45
mA
IDD7(1)
Supply Current Program/ Erase Suspended (Standby) VPPF Supply Current (Program)
10 2 0.2 2 0.2 0.2 0.2
50 5 5 5 5 5 5
A mA A mA A A A
IPP1(1) VPPF Supply Current (Erase) IPP2 IPP3(1) VPPF Supply Current (Read) VPPF Supply Current (Standby)
Note: 1. Sampled only, not 100% tested. 2. VDDF Dual Operation current is the sum of read and program or erase currents.
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M36W0R5020T0, M36W0R5020B0
Table 7. Flash Memory DC Characteristics - Voltages
Symbol VIL VIH VOL VOH VPP1 VPPH VPPLK VLKO VRPH Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VPPF Program Voltage-Logic VPPF Program Voltage Factory Program or Erase Lockout VDDF Lock Voltage RPF pin Extended High Voltage 1 3.3 IOL = 100A IOH = -100A Program, Erase Program, Erase VDDQ -0.1 1.1 11.4 1.8 12 3.3 12.6 0.4 Test Condition Min -0.5 VDDQ -0.4 Typ Max 0.4 VDDQ + 0.4 0.1 Unit V V V V V V V V V
Table 8. SRAM DC Characteristics
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Test Condition 0V VIN VDD 0V VOUT VDDS, Output disabled E1S VDDS - 0.2V or E2S 0.2V VIN VDDS - 0.2V or VIN 0.2V f = fmax (Address and Data inputs only) f = 0 (GS, WS, UBS and LBS) E1S VDDS - 0.2V or E2S 0.2V VIN VDDS - 0.2V or VIN 0.2V f = 0, VDD(max) f = fmax = 1/tAVAV, CMOS levels VDDS = VDDS(max) IOUT = 0 mA, f = 1MHz, CMOS levels VIL VIH VOL VOH Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 0.1mA, VDSD = 1.65V IOH = -0.1mA, VDDS = 1.65V 1.4 -0.2 1.4 Min Max 1 1 Unit A A
10
A
IDDS
VDD Standby Current
10
A
6 3 0.4 VDDS+0.2 0.2
mA mA V V V V
IDD
Supply Current
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M36W0R5020T0, M36W0R5020B0
Figure 8. SRAM Read Mode AC Waveforms, Address Controlled with UBS = LBS = VIL
tAVAV A0-A17 tAVQV tAVQX DQ0-DQ15 DATA VALID DATA VALID
AI09881
VALID
Note: E1S = Low, E2S = High, GS = Low, WS = High.
Figure 9. SRAM Read AC Waveforms, GS Controlled
tE1LE1H tE2HE2L A0-A17 tE1LQV tE2HQV E1S tE1LQX tE2HQX E2S tGLQV GS tGLQX LBS, UBS tBLQX DQ0-DQ15 DATA VALID tBHQZ tGHQZ tE2LQZ VALID tE1HQZ
AI09882
Note: 1. UBS, LBS means both UBS and LBS. 2. Write Enable (WS) = High. Address Valid prior to or at the same time as E1S and UBS, LBS go Low and E2S goes High.
Figure 10. SRAM Standby AC Waveforms
E1S
E2S IDD IDDS tPU 50%
AI08192
tPD
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M36W0R5020T0, M36W0R5020B0
Table 9. SRAM Read AC Characteristics
Symbol Alt Parameter M36W0R5020T0, M36W0R5020B0 Min tAVAV tE1LE1H tE2HE2L tAVQV tAVQX tBHQZ(2) tBLQV tBLQX(2) tE1HQZ tE2LQZ tE1LQV tE2HQV tE1LQX tE2HQX tGHQZ tGLQV tGLQX tPD(1) tPU(1) tRC tAA tOHA tHZBE tDBE tLZBE tHZCE tACE tLZCE tHZOE tDOE tLZOE Read Cycle Time Address Valid to Output Valid Address Transition to Output Transition Byte Enable High to Data Hi-Z Byte Enable Low to Data Valid Byte Enable Low to Data Transition Chip Enable 1 High or Chip Enable 2 Low to Data Hi-Z Chip Enable 1 Low or Chip Enable 2 High to Data Valid Chip Enable 1 Low or Chip Enable 2 High to Data Transition Output Enable High to Data Hi-Z Output Enable Low to Data Valid Output Enable Low to Data Transition Chip Enable 1 High or Chip Enable 2 Low to Power Down Chip Enable 1 Low or Chip Enable 2 High to Power Up 0 5 70 10 25 35 5 25 70 10 25 70 70 70 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Sampled only. Not 100% tested. 2. Whatever the temperature and voltage, tE1HDZ and tE2LDZ are less than tE1LDX and tE2HDX; tBHDZ is less than tBLDX and, tGHDZ is less than tGHDX.
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M36W0R5020T0, M36W0R5020B0
Figure 11. SRAM Write AC Waveforms, E1S or E2S Controlled
tAVAV A0-A17 VALID tAVE1H tAVE2L tAVE1L E1S tE1LE1H tE1HAX
E2S tAVE2H tE2HE2L tWLE1H tWLE2L WS tBLE1H tBLE2L UBS, LBS tE2LAX
GS tGHDZ DQ0-DQ15 tDVE1H tDVE2L tE1HDX tE2LDX
Note 2
INPUT VALID
AI09883
Note: 1. 2. 3. 4.
WS, E1S, E2S and UBS,LBS must be asserted to initiate a write cycle. The I/O pins are in output mode and input signals should not be applied. If E1S, E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance. UBS, LBS means both UBS and LBS.
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M36W0R5020T0, M36W0R5020B0
Figure 12. SRAM Write AC Waveforms, WS Controlled, GS High during Write
tAVAV A0-A17 VALID tAVWH tE1LWH E1S tWHAX
E2S tE2HWH tAVWL WS tBLWH UBS, LBS tWLWH
GS tGHDX DQ0-DQ15 tDVWH tWHDX
Note 2
INPUT VALID
AI09884
Note: 1. 2. 3. 4.
WS, E1S, E2S and UBS,LBS must be asserted to initiate a write cycle. The I/O pins are in output mode and input signals should not be applied. If E1S, E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance. UBS, LBS means both UBS and LBS.
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M36W0R5020T0, M36W0R5020B0
Figure 13. SRAM Write AC Waveforms, WS Controlled with GS Low
tAVAV A0-A17 VALID tAVWH tE1LWH tE2HWH E1S tWHAX
E2S tBLWH UBS, LBS tAVWL WS tWHDX tWLDZ DQ0-DQ15 Note 1 tDVWH INPUT VALID
AI09885
tWLWH
tWHDZ
Note: 1. During this period, the I/O pins are in output mode and input signals should not be applied. 2. If E1S, E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance. 3. UBS, LBS means both UBS and LBS.
Figure 14. SRAM Write AC Waveform, UBS and LBS Controlled GS Low
tAVAV A0-A17 VALID tAVBH tE1LBH tE2HBH E1S
E2S tAVBL UBS, LBS tWLBH WS tDVBH DQ0-DQ15 Note 2 INPUT VALID tBHDX tBLBH tBHAX
AI09886
Note: 1. If E1S, E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance. 2. The I/O pins are in output mode and input signals should not be applied. 3. UBS, LBS means both UBS and LBS.
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M36W0R5020T0, M36W0R5020B0
Table 10. SRAM Write AC Characteristics
M36W0R5020T0, M36W0R5020B0 Symbol tAVAV tAVE1L, tAVE2H, tAVWL tAVBL tAVWH tAVE1H tAVE2L tAVBH tBLWH tBLE1H tBLE2L tBLBH tDVE1H, tDVE2L, tDVWH tDVBH tE1HAX, tE2LAX, tWHAX tBHAX tE1HDX, tE2LDX, tWHDX tBHDX tE1LE1H, tE2HE2L, tE1LWH tE2HWH tE1LBH, tE2HBH tGHDZ tWHDZ(1) tWLDZ(1) tWLWH tWLE1H tWLE2L tWLBH Alt tWC Write Cycle Time Parameter Min 70 Max ns Unit
tSA
Address Valid to Beginning of Write
0
ns
tAW
Address Valid to Write Enable High
60
ns
tBW
UBS, LBS Valid to End of Write
60
ns
tSD
Input Valid to End of Write
30
ns
tHA
End of Write to Address Change
0
ns
tHD
Data Transition to End of Write
0
ns
tSCE
Chip Enable 1 Low or Chip Enable 2 High to End of Write
60
ns
tHZOE tLZWE tHZWE
Output Enable High to Output Hi-Z Write Enable High to Input Transition Write Enable Low to Output Hi-Z 10
25
ns ns
25
ns
tPWE
Write Enable Pulse Width
50
ns
Note: 1. Whatever the temperature and voltage, tWLDZ is less than tWHDX.
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M36W0R5020T0, M36W0R5020B0
Figure 15. SRAM Low VDDS Data Retention AC Waveforms, E1S or UBS / LBS Controlled
DATA RETENTION MODE VDDS VDDS (min) tCDR E1S or UBS, LBS
AI08197B
VDR tR
VDDS (min)
Figure 16. SRAM Low VDDS Data Retention AC Waveforms, E2S Controlled
DATA RETENTION MODE VDDS VDDS (min) tCDR E2S
AI08198B
VDR tR
VDDS (min)
Table 11. SRAM Low VDDS Data Retention Characteristic
Symbol IDDDR Parameter Supply Current (Data Retention) Supply Voltage (Data Retention) Chip Disable to Power Down Operation Recovery Time Test Condition VDDS = 1.0V, E1S VDDS - 0.2V or E2S 0.2V, VIN VDDS - 0.2V or VIN 0.2V 1.0 0 70 Min Max 8 Unit A
VDR tCDR tR
1.95
V ns ns
Note: 1. Sampled only. Not 100% tested.
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M36W0R5020T0, M36W0R5020B0
PACKAGE MECHANICAL
Figure 17. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Outline
D D1
e SE E E2 E1 b BALL "A1"
ddd FE FE1 A A1 FD SD A2
BGA-Z42
Note: Drawing is not to scale.
Table 12. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Mechanical Data
millimeters Symbol Typ A A1 A2 b D D1 ddd E E1 E2 e FD FE FE1 SD SE 10.000 7.200 8.800 0.800 1.200 1.400 0.600 0.400 0.400 - - 9.900 0.850 0.350 8.000 5.600 0.100 10.100 0.3937 0.2835 0.3465 0.0315 0.0472 0.0551 0.0236 0.0157 0.0157 - - 0.3898 0.300 7.900 0.400 8.100 0.200 0.0335 0.0138 0.3150 0.2205 0.0039 0.3976 0.0118 0.3110 0.0157 0.3189 Min Max 1.200 0.0079 Typ Min Max 0.0472 inches
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M36W0R5020T0, M36W0R5020B0
PART NUMBERING
Table 13. Ordering Information Scheme
Example: Device Type M36 = Multi-Chip Package (Flash + RAM) Flash 1 Architecture W = Multiple Bank, Burst mode Flash 2 Architecture 0 = none present Operating Voltage R = VDDF = VDDQ =VDDP = 1.7 to 1.95V Flash 1 Density 5 = 32 Mbit Flash 2 Density 0 = none present RAM 1 Density 2 = 4 Mbit RAM 0 Density 0 = none present Parameter Blocks Location T = Top Boot Block Flash B = Bottom Boot Block Flash Product Version 0 = 0.13m Flash technology, 70ns; 0.15m RAM, 70ns speed Package ZAQ = Stacked TFBGA88 8 x 10mm - 8x10 active ball array, 0.8mm pitch Option Blank = Standard Packing T = Tape & Reel Packing E = Lead-free and RoHS Package, Standard Packing F = Lead-free and RoHS Package, Tape & Reel Packing M36 W0 R 5 0 2 0 T 0 ZAQ T
Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
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M36W0R5020T0, M36W0R5020B0
REVISION HISTORY
Table 14. Document Revision History
Date 27-Aug-2003 Version 1.0 First Issue M36W0R5030T0 and M36W0R5030B0 part numbers and 8 Mbit SRAM option removed. 0.15m Flash memory technology replaced by the 0.13m technology. Package specifications updated. E and F Lead-free Package options added to Table 13., Ordering Information Scheme. Document status promoted to full Datasheet. Flash memory and PSRAM data updated. TFBGA88 package fully compliant with the ST ECOPACK specification. Revision Details
06-May-2004
2.0
17-Dec-2004
3.0
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M36W0R5020T0, M36W0R5020B0
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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