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Freescale Semiconductor Technical Data
MC100ES60T22 Rev 2, 2/2005
3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Translator
The MC100ES60T22 is a low skew dual LVTTL/LVCMOS to differential LVPECL translator. The low voltage PECL levels, small package, and dual gate design are ideal for clock translation applications. Features * * * * * 280 ps typical propagation delay 100 ps max output-to-output skew LVPECL operating range: VCC = 3.135 V to 3.8 V 8-lead SOIC and 8-lead TSSOP packages Ambient temperature range -40C to +85C
MC100ES60T22
D SUFFIX 8-LEAD SOIC PACKAGE CASE 751-06
DT SUFFIX 8-LEAD TSSOP PACKAGE CASE 1640-01
Q0
1
8
VCC
ORDERING INFORMATION
Device MC100ES60T22D Package SOIC-8 SOIC-8 TSSOP-8 TSSOP-8
Q0
2 LVPECL LVTTL/LVCMOS
7
D0
MC100ES60T22DR2 MC100ES60T22DT MC100ES60T22DTR2
Q1
3
6
D1 Pin D0, D1 Qn, Qn
PIN DESCRIPTION
Function LVTTL/LVCMOS Inputs LVPECL Differential Outputs Positive Supply Negative Supply
Q1
4
5
GND
VCC GND
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
(c) Freescale Semiconductor, Inc., 2005. All rights reserved.
Table 1. General Specifications
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection JA Thermal Resistance (Junction-to-Ambient) Human Body Model Machine Model 0 LFPM, 8 SOIC 500 LFPM, 8 SOIC 0 LFPM, 8 TSSOP 500 LFPM, 8 TSSOP Value 75 k 75 k > 2000 V > 200 V 190C/W 130C/W 185C/W 140C/W
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Table 2. Absolute Maximum Ratings(1)
Symbol VSUPPLY VIN Iout TA TSTG Rating Power Supply Voltage Input Voltage Output Current Operating Temperature Range Storage Temperature Range Conditions Difference between VCC & VEE VCC - VEE 3.6 V Continuous Surge Rating 3.9 VCC + 0.3 VEE - 0.3 50 100 -40 to +85 -65 to +150 Units V V V mA mA C C
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.
Table 3. DC Characteristics (VCC = 3.135 V to 3.8 V; VEE = 0 V)
-40C Symbol VOH
(1)
0C to 85C Max VCC - 800 VCC - 1250 Min VCC - 1200 VCC - 2000 Typ VCC - 970 VCC - 1680 Max VCC - 750 VCC - 1300 Unit mV mV
Characteristic Output HIGH Voltage Output LOW Voltage
Min VCC - 1150 VCC - 1950
Typ VCC - 1020 VCC - 1620
VOL(1)
1. Outputs are terminated through a 50 resistor to VCC - 2 volts.
Table 4. LVTTL / LVCMOS Input DC Characteristics (VCC = 3.135 V to 3.8 V)
-40C Symbol IIN VIK VIH VIL Characteristic Input Current Input Clamp Voltage Input HIGH Voltage Input LOW Voltage Condition VIN = VCC IIN = -18 mA 2.0 Min Typ Max 150 -1.2 VCC+0.3 0.8 2.0 Min 0C to 85C Typ Max 150 -1.2 VCC+0.3 0.8 Unit A V V V
MC100ES60T22 2 Advanced Clock Drivers Devices Freescale Semiconductor
Table 5. AC Characteristics (VCC = 3.134 V to 3.8 V; VEE = 0 V)
-40C Symbol fmax tPLH, tPHL tSKEW Characteristic Maximum Toggle Frequency Propagation Delay Skew part-to-part RMS (1) 350 50 750 400 100 260 Min Typ Max 1 400 300 1 350 50 750 400 100 280 Min 25C Typ Max 1 400 300 1 350 50 750 400 100 280 Min 85C Typ Max 1 450 350 1 Unit GHz ps ps ps mV ps
tJITTER Cycle-to-Cycle Jitter VoutPP Output Peak-to-Peak Voltage tr / tf
Output Rise/Fall Times (20% - 80%)
Q Driver Device Qb 50 50
D Receiver Device Db
V TT
Figure 2. Typical Termination for Output Driver and Device Evaluation
MC100ES60T22 Advanced Clock Drivers Devices Freescale Semiconductor 3
PACKAGE DIMENSIONS
A
8
D
5
C
E
1 4
H
0.25
M
B
M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS ARE IN MILLIMETER. 3. DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0 7
h B C e A
SEATING PLANE
X 45
L 0.10 A1 B 0.25
M
CB
S
A
S
DIM A A1 B C D E e H h L
SOIC-8 D SUFFIX 8-LEAD SOIC PACKAGE CASE 751-06 ISSUE T
MC100ES60T22 4 Advanced Clock Drivers Devices Freescale Semiconductor
PACKAGE DIMENSIONS
2X
3 3.00 1.95 1.5 A
2
0.20 C
8
1
D 0.60
0.60 2.45 3 3.00 1.5 4.90 B
2X
B
H
0.20 C D 0.25 C 8
SEE VIEW C
VIEW A-A 0.65 0.325
8X 8
0.38 0.25 0.33 0.25 0.18 0.13 0.23 0.13
B
0.38 0.25 0.13
M
C A-B D 0.48 MAX DETAIL "B"
DAMBAR PROTRUSION
BASE METAL
TOP VIEW A
DETAIL "B"
SECTION B-B
SEE NOTE 6
0.95 0.75
8X
1.10 MAX 0.15 0.05 A SIDE VIEW
0.10 C
SEATING PLANE
C
4X
15 5
0.07 MIN
0.25
GAUGE PLANE SEATING PLANE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS ARE IN MILLIMETERS. 3. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT DATUM H, MOLD FLASH OR PROTRUSIONS, SHALL NOT EXCEED 0.15mm PER SIDE. 4. DIMENSION IS THE LENGTH OF TERMINAL FOR SOLDERING TO A SUBSTRATE. 5. THE LEAD WIDTH DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE LEAD FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.14mm SEE DETAIL "B" AND SECTION B-B. 6. SECTION B-B TO BE DETERMINED AT 0.10 TO 0.25mm FROM THE LEAD TIP. 7. THIS PART IS COMPLIANT WITH JEDEC REGISTRATION MO-187 AA. 8. DATUMS A AND B TO BE DETERMINED DATUM PLANE H.
6 0
0.70 0.40
4
4X
15 5
C
(0.95) VIEW C
TSSOP-8 DT SUFFIX 8-LEAD TSSOP PACKAGE CASE 1640-01 ISSUE O
MC100ES60T22 Advanced Clock Drivers Devices Freescale Semiconductor 5
NOTES
MC100ES60T22 6 Advanced Clock Drivers Devices Freescale Semiconductor
NOTES
MC100ES60T22 Advanced Clock Drivers Devices Freescale Semiconductor 7
NOTES
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MC100ES60T22 Rev. 2 2/2005

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