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X T 0RWKHUERDUG &ORFN *HQHUDWRU ,& )6 January 2000 1.0 * * * * * Features (R) 2.0 Description Generates clocks required for Intel i820 based desktop and workstation systems, including: Four enabled 2.5V 133/100MHz CPU Front Side Bus (FSB) clocks Two 2.5V CPU/2 clocks for synchronous memory Seven enabled 3.3V PCI bus clocks and one free-running PCI clock Four enabled 3.3V 66MHz AGP clocks Three 2.5V 16.67MHz APIC bus clocks Two 3.3V 14.318MHz REF clocks One 3.3V 48MHz USB clock The FS6261-01 is a CMOS clock generator IC designed for high-speed motherboard applications. Two different frequencies can be selected for the CPU clocks via two SEL pins. Glitch-free stop clock control of the CPU, AGP (66MHz) and PCI clocks is provided. A low current power-down mode is available for mobile applications. Separate clock buffers provide for a 2.5V voltage range on the CPU_0:3, CPU/2_0:1 and APIC_0:2 clocks. Figure 2: Pin Configuration VSS_R REF_0 REF_1 VDD_R XIN XOUT VSS_P PCI_F PCI_1 VDD_P PCI_2 PCI_3 VSS_P PCI_4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDD_A APIC_2 APIC_1 APIC_0 VSS_A VDD_C2 CPU/2_1 CPU/2_0 VSS_C2 VDD_C CPU_3 CPU_2 VSS_C VDD_C CPU_1 CPU_0 VSS_C VDD VSS PCI_STOP# CPU_STOP# PWR_DWN# SS_EN# SEL_1 SEL_0 VDD_48 CK48 VSS_48 CPU clock cycle - cycle jitter < 150ps p-p Non-linear spread-spectrum modulation (-0.5% at 31.5kHz) Supports test mode and tristate output control Separate CPU-enable, PCI-enable and power-down inputs with glitch-free stop clock controls on all clocks for clock control and power management (2.5V outputs) FS6261-01 Figure 1: Block Diagram XIN XOUT Crystal Oscillator VDD_R PCI_5 VDD_P PCI_6 PCI_7 VSS_P VSS_66 CK66_0 VDD_C2 REF_0:1 SEL_0:1 SS_EN# SEL_133/100# VSS_R PLL /2 CPU/2_0:1 VSS_C2 VDD_A CK66_1 VDD_66 VSS_66 CK66_2 CK66_3 VDD_66 SEL133/100# delay PWR_DWN# /6 or /8 APIC_0:2 VSS_A VDD_C CPU_0:3 VSS_C (2.5V outputs) 56-pin SSOP CPU_STOP# VDD_66 delay /11/2 or /2 Table 1: CPU/PCI Frequency Selection SEL_133/100# 0 0 0 0 1 1 1 1 SEL_1 0 0 1 1 0 0 1 1 SEL_0 0 1 0 1 0 1 0 1 CPU (MHz) tristate (reserved) 100 100 XIN/2 (reserved) 133 133 PCI (MHz) tristate (reserved) 33.33 33.33 XIN/6 (reserved) 33.33 33.33 CK66_0:3 VSS_66 VDD_P delay PCI_STOP# /3 or /4 PCI_F PCI_1:7 VSS_P VDD_48 PLL /3 or /4 CK48 VSS_48 FS6261-01 Intel and Pentium are registered trademarks of Intel Corporation. Spread spectrum modulation is licensed under US Patent No. 5488627, Lexmark International, Inc. American Microsystems, Inc. reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. ,62 1.31.00 )6 0RWKHUERDUG &ORFN *HQHUDWRU ,& X T January 2000 Table 2: Pin Descriptions Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active-low pin PIN 53, 54, 55 30 21, 22, 25, 26 41, 42, 45, 46 49, 50 36 9, 11, 12, 14, 15, 17, 18 8 37 35 2, 3 32, 33 28 34 39 31 23, 27 56 43, 47 51 10, 16 4 38 29 20, 24 52 40, 44 48 7, 13, 19 1 5 6 TYPE DO DO DO DO DO DIU DO DO DIU DIU DO DI U NAME APIC_0:2 CK48 CK66_0:3 CPU_0:3 CPU/2_0:1 CPU_STOP# PCI_1:7 PCI_F PCI_STOP# PWR_DWN# REF_0:1 SEL_0:1 SEL_133/100# SS_EN# VDD VDD_48 VDD_66 VDD_A VDD_C VDD_C2 VDD_P VDD_R VSS VSS_48 VSS_66 VSS_A VSS_C VSS_C2 VSS_P VSS_R XIN XOUT DESCRIPTION Three low-skew (<250ps @ 1.25V) 2.5V 16.67MHz clock outputs for APIC bus timing. APIC clocks are synchronous with CPU clocks but lag the CPU clocks by 1.5 to 4ns. One 3.3V 48MHz clock output for Universal Serial Bus (USB) timing Four 3.3V 66MHz AGP clock outputs. CK66 clocks are synchronous with CPU clocks but lag the CPU clocks by 0 to 1.5ns. Four low-skew 2.5V 133/100MHz CPU clock outputs for host frequencies Two low-skew 2.5V clock outputs at half the CPU clock frequencies (66/50MHz) CPU_0:3 and CK66_0:3 clock output enable. Asynchronous, active-low disable stops all CPU and CK66 clocks in the low state. Seven 3.3V PCI clock outputs. PCI clocks are synchronous with CPU clocks but lag the CK66 clocks by 1.5 to 4ns. One free-running 3.3V PCI clock output PCI_1:7 clock output enable. Asynchronous, active-low disable stops all PCI clocks in the low state. Asynchronous active-low power-down signal shuts down oscillator, all PLLs, puts all clocks in low state. Clock re-enable latency of 3ms. Two buffered outputs of the 14.318MHz reference clock Two frequency select inputs (see Table 4) Selects 133MHz or 100MHz CPU frequency (pull-up/pull-down must be provided externally) Spread spectrum enable. Active-low enable turns on the spread spectrum feature; a logic-high turns off the spread spectrum modulation. 3.3V 10% Power supply for 3.3V CK48 clock output Power supply for 3.3V CK66_0:3 clock outputs Power supply for 2.5V APIC_0:2 clock outputs Power supply for 2.5V CPU_0:3 clock outputs Power supply for 2.5V CPU/2_0:1 clock outputs Power supply for 3.3V PCI_1:7 and PCI_F clock outputs Power supply for 3.3V REF_0:1 clock outputs Ground Ground for CK48 clock outputs Ground for CK66_0:3 clock outputs Ground for APIC_0:2 clock outputs Ground for CPU_0:3 clock outputs Ground for CPU/2_0:1 clock outputs Ground for PCI_1:7 and PCI_F clock outputs Ground for REF_0:1 clock outputs 14.318MHz crystal oscillator input. XIN can be driven by an external frequency source. 14.318MHz crystal oscillator output DI DIU P P P P P P P P P P P P P P P P AI AO ,62 1.31.00 2 X T 0RWKHUERDUG &ORFN *HQHUDWRU ,& )6 January 2000 Table 3: Actual Clock Frequencies Note: Spread spectrum disabled CLOCK APIC_0:2 CPU_0:3 CPU/2_0:1 PCI_1:7, PCI_F CK66_0:3 CK48 (1) TARGET (MHz) 16.67 (with CPU = 133.3) 16.67 (with CPU = 100.0) 133.33 100.00 66.67 50.00 33.33 (with CPU = 133.3) 33.33 (with CPU = 100.0) 66.67 (with CPU = 133.3) 66.67 (with CPU = 100.0) 48 ACTUAL (MHz) 16.6634 16.6661 133.3072 99.9963 66.6536 49.9982 33.3268 33.3321 66.6536 66.6642 48.0080 DEVIATION (ppm) -195.92 -36.657 -195.92 -36.657 -195.92 -36.657 -195.92 -36.657 -195.92 -36.657 +167 (1) 48MHz USB clock is required to be 167ppm off from 48.000MHz to conform to USB requirements. 3.0 Programming Information Table 4: Function/Clock Enable Configuration CONTROL INPUTS SEL_ 133/100# 0 0 0 0 1 1 1 1 X SEL_1 0 0 1 1 0 0 1 1 X SEL_0:1 and SEL_133/100# 0 or SEL_0:1 01 SEL_0 0 1 0 1 0 1 0 1 X PWR_ DWN# 1 1 1 1 1 1 1 1 0 1 1 1 1 CPU_ STOP# X 1 1 1 1 1 1 1 X 0 0 1 1 PCI_ STOP# X 1 1 1 1 1 1 1 X 0 1 0 1 REF_0:1 CPU_0:3 tristate 14.318 14.318 XIN 14.318 14.318 low 14.318 14.318 14.318 14.318 tristate 100 100 XIN/2 133.33 133.33 low low low running running CLOCK OUTPUTS (MHz) CPU/2_ 0:1 tristate 50 50 XIN/4 66.67 66.67 low running running running running PCI_F tristate 33.33 33.33 XIN/8 33.33 33.33 low 33.33 33.33 33.33 33.33 PCI_1:7 tristate 33.33 33.33 XIN/8 33.33 33.33 low low 33.33 low 33.33 APIC_ 0:2 tristate 16.67 16.67 XIN/16 16.67 16.67 low 16.67 16.67 16.67 16.67 CK48 tristate tristate 48 XIN/2 tristate 48 low 48 48 48 48 CK66_ 0:3 tristate 66.67 66.67 XIN/4 66.67 66.67 low low low 66.67 66.67 (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) ,62 1.31.00 3 )6 0RWKHUERDUG &ORFN *HQHUDWRU ,& X T January 2000 3.1 SEL_1, SEL_0 These two input pins can either tristate the output drivers, select the Test Mode frequency, or choose the CPU frequencies. Both the SEL_1 and SEL_0 pins have pull-ups that default the CPU output frequency to either 100MHz or 133MHz, depending on the state of the SEL_133/100# pin. These pins should be fixed at a logic state before power-up occurs. Powering down occurs in less than two PCI clocks from the falling edge of PWR_DWN# to when all clock outputs are forced low. The REF and CK48 clocks are brought low as soon as possible. 4.2 Clock Enable Latency Clock enable latency is defined in the number of rising edges of free-running PCI clocks between when the enable signal becomes active (a rising edge) to when the first valid clock is driven from the device. 3.2 SEL_133/100# 4.2.1 CPU_STOP# The CPU_STOP# pin is an active-low LVTTL input pin that disables the CPU_0:3 and CK66_0:3 clocks for low power operation. CPU_STOP# can be asserted asynchronously, and the stop clock control is glitch-free, in that the CPU clock must complete a full cycle before the clock is stopped low. One rising edge of the PCI_F clock is allowed before the CPU and CK66 clocks are enabled or disabled. 4.2.2 PCI_STOP# The PCI_STOP# pin is an active-low LVTTL input pin that disables the PCI_1:7 clocks for low power operation, except for the PCI_F clock. The PCI_F is a free-running clock, and will continue to run even if all other PCI clocks have stopped. PCI_STOP# can be asserted asynchronously, and the stop-clock control is glitch-free, in that the PCI clock must complete a full cycle before the clock is stopped low. Only one rising edge of the PCI_F clock is allowed after the PCI_STOP# signal is enabled/disabled. This pin is an active-low LVTTL input that switches between a 133MHz or a 100MHz system (CPU) clock. A pull-up or pull-down must be provided externally and this pin should be fixed at a logic state before power-up occurs. 4.0 Clock Latency All clock outputs are stopped in the low state, and are started so that the first high pulse is a full pulse width. All clocks complete a full period on transitions between running (enabled) and stopped (disabled) to ensure glitchfree stop clock control. All enabled clocks will continue to run while disabled clocks are stopped. The clock enable signals are assumed to be asynchronous inputs relative to clock outputs. Enable signals are synchronized to their respective clocks by this device. The CPU and PCI clocks will transition between running and stopped according to Table 5. 4.1 Power-Up Latency Table 5: Latency Table SIGNAL SIGNAL STATE 0 1 0 1 0 1 disabled enabled disabled enabled Power OFF Power ON PCI CLOCK ENABLE LATENCY 1 1 1 1 2 (max.) 3ms Power-up latency is defined as the time from the moment when PWR_DWN# goes inactive (a rising edge) to when the first valid clocks are driven from the device. Upon release of PWR_DWN#, external circuitry should allow a minimum of 3ms for the PLLs to lock before enabling any clocks. CPU_STOP# 4.1.1 PWR_DWN# The PWR_DWN# signal is an asynchronous, active-low LVTTL input that puts the device in a low power inactive state without removing power from the device. All internal clocks are turned off, and all clock outputs are held low. PCI_STOP# PWR_DWN# ,62 1.31.00 4 X T 0RWKHUERDUG &ORFN *HQHUDWRU ,& )6 January 2000 Figure 2: CPU_STOP# Timing CPU_ STOP# PCI_F CPU (133MHz) CPU (100MHz) Figure 3: PCI_STOP# Timing PCI_ STOP# PCI_F PCI_1:7 Figure 4: PWR_DWN# Timing PWR_ DWN# PCI_F PCI_1:7 CPU (133MHz) CPU (100MHz) VCO Crystal Oscillator Shaded regions in the Crystal Oscillator and VCO waveforms indicate that the clock is valid and the Crystal Oscillator and VCO are active. ,62 1.31.00 5 )6 0RWKHUERDUG &ORFN *HQHUDWRU ,& X T January 2000 5.0 Spread Spectrum Modulation 5.2 Modulation Frequency To limit peak EMI emissions, high-speed motherboard designs now require the reduction of the peak harmonic energy contained in the system bus frequencies. A reduction in the peak energy of a specific frequency can be accomplished by spreading the energy over a limited range of frequencies through a technique known as spread spectrum clocking. In this technique, a generated clock frequency is dithered in a tightly controlled sweep near the clock frequency using a predetermined modulation profile and period. The frequency of modulation, noted as fm, describes how fast the center frequency sweeps between fnom, and (1-) fnom,. Typical modulation frequencies must be greater than 30kHz (above the audio band) but small enough to not upset system timing. Since a tracking PLL cannot instantaneously update the output clock to match a modulated input clock, any accumulation of the difference in phase between the modulated input clock and a tracking PLL output clock is called tracking skew. The resulting phase error will decrease the timing margins in any successive circuitry. Figure 5: Spectral Energy Distribution spreadspectrum clock E 5.3 Modulation Profile (1-)fnom non-spread clock fnom The amount of EMI reduction is directly related to three parameters: the modulation percentage, the frequency of the modulation, and the modulation profile. The modulation profile determines the shape of the spectral energy distribution by defining the time that the clock spends at a specific frequency. The longer a clock remains at a specific frequency, the larger the energy concentration at that frequency. A sinusoidal modulation spends a large portion of time between fnom, and (1-) fnom, resulting in large energy peaks at the edges of the spectral energy distribution. A linear modulation, such as a triangle profile, improves the spectral distribution but also exhibits energy peaking at the edges. A non-linear modulation profile, known as the "Hershey Kiss" profile offers the best distribution of spectral energy. 5.1 Modulation Percentage Figure 6: Modulation Profiles fnom fnom The modulation percentage , is typically 0.5% of the center frequency (denoted here as fnom). The modulation percentage determines the range of frequencies the spectral energy is distributed over. For a 100MHz clock frequency, a 0.5% modulation sweeps the clock frequency between 99.5MHz and 100.5MHz. If the sweep is symmetrical around the center frequency, the technique is known as center-spread modulation. However, a circuit that is designed for a 100MHz reference may not have enough timing margin to support a clock greater then 100MHz. The clock frequency can instead be modulated between fnom, and (1-) fnom,; the technique is known as down-spread modulation. For a of -0.5%, the clock will sweep between 99.5MHz and 100MHz. A small degradation in circuit performance may be noticed, as the clock frequency now averages 99.75MHz. time time (1-)fnom 1/fm (1-)fnom 1/fm The type of modulation profile used will also impact tracking skew. The maximum frequency change occurs at the profile limits where the modulation changes the slew rate polarity. To track the sudden reversal in clock frequency, the downstream PLL must have a large loop bandwidth. ,62 1.31.00 6 X T 0RWKHUERDUG &ORFN *HQHUDWRU ,& )6 January 2000 Compared to the profile limits the modulation slew rate is relatively slow between the limits, allowing the downstream PLL a chance to reduce the tracking skew. The ability of the downstream PLL to catch up is determined by the loop transfer function phase angle. Spread spectrum clocking can be shown to have a negligible effect on cycle-to-cycle jitter performance. Any increase in jitter is less than 1ps when <1% and fm<50kHz. Careful design of downstream PLLs can ensure that tracking skew is minimized. To have less than 100ps of tracking skew, a downstream PLL should have a loop bandwidth greater than 1MHz, and a phase angle less than 0.1. Figure 7 shows the tracking skew of a downstream PLL with a loop bandwidth of 1.5MHz and a phase angle of 0.26 following a non-linear profile-modulated 100MHz input clock with a =-0.5% and an fm=31.2kHz. Figure 7: PLL Tracking Skew PLL Tracking Skew 100 80 60 40 Skew [ps] 20 0 20 40 60 80 100 Time [us] 5.4 Spread Spectrum Enable The active-low LVTTL SS_EN# input pin enables spread spectrum modulation of the CPU and PCI clocks. When SS_EN# is a logic-high, the spread spectrum modulation of these clocks is disabled. If SS_EN# is a logic-low, spread spectrum modulation is enabled. A pull-up on this pin disables spread spectrum modulation by default. Figure 8: Actual Modulation Profile 100 99.9 Frequency (MHz) 99.8 99.7 99.6 99.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 1/fm (s) ,62 1.31.00 7 )6 0RWKHUERDUG &ORFN *HQHUDWRU ,& X T January 2000 6.0 Electrical Specifications Table 6: Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance, functionality, and reliability. PARAMETER Supply Voltage (VSS = ground) Input Voltage, dc Output Voltage, dc Input Clamp Current, dc (VI < 0 or VI > VDD) Output Clamp Current, dc (VI < 0 or VI > VDD) Storage Temperature Range (non-condensing) Ambient Temperature Range, Under Bias Junction Temperature Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection (MIL-STD 883E, method 3015.7) SYMBOL VDD VI VO IIK IOK TS TA TJ MIN. VSS-0.5 VSS-0.5 VSS-0.5 -50 -50 -65 -55 MAX. 7 VDD+0.5 VDD+0.5 50 50 150 125 125 260 2 UNITS V V V mA mA C C C C kV CAUTION: ELECTROSTATIC SENSITIVE DEVICE Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge. Table 7: Operating Conditions PARAMETER SYMBOL CONDITIONS/DESCRIPTION Core (VDD) @ 3.3V 5% Supply Voltage VDD Clock Buffers (VDD_P, VDD_R, VDD_66, VDD_48) @ 3.3V 5% Clock Buffers (VDD_A, VDD_C, VDD_C2) @ 2.5V 5% Operating Temperature Range Crystal Resonator Frequency Crystal Resonator Load Capacitance TA fXTAL CXL XIN, XOUT pins APIC_0:2 CPU_0:3 CPU/2_0:3 Load Capacitance CL PCI_F, PCI_1:7 CK48 CK66_0:3 REF_0:1 MIN. 3.135 3.135 2.375 0 14.316 13.5 10 10 10 10 10 10 10 14.318 18 TYP. 3.3 3.3 2.5 MAX. 3.465 3.465 2.625 70 14.32 22.5 20 20 20 30 20 30 20 pF C MHz pF V UNITS ,62 1.31.00 8 X T 0RWKHUERDUG &ORFN *HQHUDWRU ,& )6 January 2000 Table 8: DC Electrical Specifications Unless otherwise stated, all power supplies = 3.3V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 from typical. Negative currents indicate current flows out of the device. PARAMETER Overall SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS fCPU = 133MHz; SEL_0:1 = 11 VDD_A = VDD_C = VDD_C2 = 3.465V 120 88 mA 120 86 12 A 8 Supply Current, Dynamic, with Loaded Outputs IDD fCPU = 133MHz; SEL_0:1 = 11 VDD_A = VDD_C = VDD_C2 = 2.625V fCPU = 100MHz; SEL_0:1 = 11 VDD_A = VDD_C = VDD_C2 = 3.465V fCPU = 100MHz; SEL_0:1 = 11 VDD_A = VDD_C = VDD_C2 = 2.625V PWR_DWN# low VDD_A = VDD_C = VDD_C2 = 3.465V PWR_DWN# low VDD_A = VDD_C = VDD_C2 = 2.625V Supply Current, Static IDDs Digital Inputs (CPU_STOP#, PCI_STOP#, PWR_DWN#, SEL_0:1, SS_EN#) High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current (pull-up) Digital Inputs (SEL_133/100#) High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Crystal Oscillator Feedback (XIN) Threshold Bias Voltage High-Level Input Current Low-Level Input Current Crystal Loading Capacitance * Input Loading Capacitance * Crystal Oscillator Drive (XOUT) High Level Output Source Current Low Level Output Sink Current IOH IOL VI = 3.3V, VO = 0V VI = 0V, VO = 3.3V -8.0 8.7 mA mA VTH IIH IIL CL(xtal) CL(XIN) VIH = 3.3V VIL = 0V As seen by an external crystal connected to XIN and XOUT As seen by an external clock driver on XOUT; XIN unconnected VIH VIL IIH IIL VIL = 0.4V 2.0 VSS-0.3 -2 -0.8 VDD+0.3 0.8 5 V V A A VIH VIL II 2.0 VSS-0.3 -5 VDD+0.3 0.8 +5 V V A 1.5 32 -32 13.5 18 36 22.5 V A A pF pF ,62 1.31.00 9 )6 0RWKHUERDUG &ORFN *HQHUDWRU ,& X T January 2000 Table 8: DC Electrical Specifications, continued Unless otherwise stated, all power supplies = 3.3V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 from typical. Negative currents indicate current flows out of the device. PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS CPU_0:3, CPU/2_0:1, APIC_0:2 Clock Outputs (2.5V Type 1 Clock Buffer) IOH min High Level Output Source Current IOH max IOL min Low Level Output Sink Current IOL max Output Impedance Tristate Output Current Short Circuit Output Source Current Short Circuit Output Sink Current zOL zOH IOZ ISCH ISCL VO = 0V; shorted for 30s, max. VO = 2.5V; shorted for 30s, max. VDD_C, VDD_C2, VDD_A = 2.375V, VO = 1.0V VDD_C, VDD_C2, VDD_A = 2.625V, VO = 2.375V VDD_C, VDD_C2, VDD_A = 2.375V, VO = 1.2V VDD_C, VDD_C2, VDD_A = 2.625V, VO = 0.3V -27 -27 27 mA 30 13.5 13.5 -10 -56 58 23 25 45 45 10 A mA mA mA Measured at 1.25V, output driving low Measured at 1.25V, output driving high REF_0:1, CK48 Clock Outputs (3.3V Type 3 Clock Buffer) High-Level Output Source Current Low-Level Output Sink Current Output Impedance Tristate Output Current Short Circuit Output Source Current Short Circuit Output Sink Current IOH min IOH max IOL min IOL max zOL zOH IOZ IOSH IOSL VO = 0V; shorted for 30s, max. VO = 3.3V; shorted for 30s, max. VDD_R, VDD_48 = 3.135V, VO = 1.0V VDD_R, VDD_48 = 3.465V, VO = 3.135V VDD_R, VDD_48 = 3.135V, VO = 1.95V VDD_R, VDD_48 = 3.465V, VO = 0.4V -29 -23 29 27 20 20 -10 -41 40 45 46 60 60 10 mA mA A mA mA Measured at 1.65V, output driving low Measured at 1.65V, output driving high PCI_1:7, PCI_F, CK66_0:1 Clock Outputs (3.3V Type 5 Clock Buffer) High Level Output Source Current Low Level Output Sink Current Output Impedance Tristate Output Current Short Circuit Output Source Current Short Circuit Output Sink Current IOH min IOH max IOL min IOL max zOL zOH IOZ IOSH IOSL VO = 0V; shorted for 30s, max. VO = 3.3V; shorted for 30s, max. VDD_P, VDD_66 = 3.135V, VO = 1.0V VDD_P, VDD_66 = 3.465V, VO = 3.135V VDD_P, VDD_66 = 3.135V, VO = 1.95V VDD_P, VDD_66 = 3.465V, VO = 0.4V -33 -33 30 38 12 12 -10 -51 62 29 37 55 55 10 mA mA A mA mA Measured at 1.65V, output driving low Measured at 1.65V, output driving high ,62 1.31.00 10 X T 0RWKHUERDUG &ORFN *HQHUDWRU ,& )6 January 2000 Table 9: AC Timing Specifications Unless otherwise stated, all power supplies = 3.3V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 from typical. Negative currents indicate current flows out of the device. Spread spectrum modulation is disabled except for Rise/Fall time measurements. PARAMETER Overall Spread Spectrum Modulation Frequency * Spread Spectrum Modulation Index* SYMBOL CONDITIONS/DESCRIPTION MIN. 133MHz TYP. MAX. MIN. 100MHz TYP. MAX. UNITS fm m SS_EN# low SS_EN# low CPU @ 1.25V, CL=20pF to CK66 @ 1.5V, CL=30pF (rising edges) 31.5 -0.5 0 1.5 1.5 1.0 1.0 0.3 2.9 2.3 1.5 4.0 4.0 10 10 3.0 0 1.5 1.5 1.0 1.0 0.4 3.1 3.3 31.5 -0.5 1.5 4.0 4.0 10 10 3.0 kHz % Clock Offset tpd CK66 @ 1.5V, CL=30pF to PCI @ 1.5V, CL=30pF (rising edges) CPU @ 1.25V, CL=20pF to APIC @ 1.25V, CL=20pF (rising edges) ns Tristate Enable Delay * Tristate Disable Delay * Clock Stabilization (on power-up) * tDZL, tDZH tDZL, tDZH tSTB SEL_0:1 and SEL_133/100#=0 SEL_0:1 and SEL_133/100#=0 via PWR_DWN# ns ns ms APIC_0:2 Clock Output (2.5V Type 1 Clock Buffer) Duty Cycle * Clock Skew * Jitter, Long Term (y()) * Jitter, Period (peak-peak) * Rise Time * Fall Time * dt tskw tj(LT) tj(P) tr min tr max tf min tf max Ratio of high pulse width to one clock period, measured at 1.5V APIC to APIC @ 1.25V, CL=20pF On rising edges 500s apart at 1.25V relative to an ideal clock, CL=20pF, all PLLs active 45 50 -70 204 82 1.2 1.5 1.8 2.1 55 45 50 -70 122 88 1.2 1.5 1.5 1.8 55 % ps ps ns ns From rising edge to rising edge at 1.25V, CL=20pF, all PLLs active Measured @ 0.4V - 2.0V; CL=10pF Measured @ 0.4V - 2.0V; CL=20pF Measured @ 2.0V - 0.4V; CL=10pF Measured @ 2.0V - 0.4V; CL=20pF CPU/2_0:1 Clock Outputs (2.5V Type 1 Clock Buffer) Duty Cycle * Clock Skew * Jitter, Long Term (y()) * Jitter, Period (peak-peak) * Rise Time * Fall Time * dt tskw tj(LT) tj(P) tr min tr max tf min tf max Ratio of high pulse width to one clock period, measured at 1.5V CPU/2 to CPU/2 @ 1.25V, CL=20pF On rising edges 500s apart at 1.25V relative to an ideal clock, CL=20pF, all PLLs active From rising edge to rising edge at 1.25V, CL=20pF, all PLLs active Measured @ 0.4V - 2.0V; CL=10pF Measured @ 0.4V - 2.0V; CL=20pF Measured @ 2.0V - 0.4V; CL=10pF Measured @ 2.0V - 0.4V; CL=20pF 45 52 +10 136 108 0.9 1.1 1.0 1.2 55 45 52 +10 122 112 0.8 1.1 1.0 1.2 55 % ps ps ns ns ,62 1.31.00 11 )6 0RWKHUERDUG &ORFN *HQHUDWRU ,& X T January 2000 Table 9: AC Timing Specifications, continued Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature TA = 25C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 from typical. Spread spectrum modulation is disabled except for Rise/Fall time measurements. PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. 133MHz TYP. MAX. MIN. 100MHz TYP. MAX. UNITS CPU_0:3 Clock Outputs (2.5V Type 1 Clock Buffer) Duty Cycle * Clock Skew * Jitter, Long Term (y()) * Jitter, Period (peak-peak) * Rise Time * Fall Time * Enable Delay * Disable Delay * dt tskw tj(LT) tj(P) tr min tr max tf min tf max tDLH tDHL Ratio of high pulse width to one clock period, measured at 1.5V CPU to CPU @ 1.25V, CL=20pF On rising edges 500s apart at 1.25V relative to an ideal clock, CL=20pF, all PLLs active From rising edge to rising edge at 1.25V, CL=20pF, all PLLs active Measured @ 0.4V - 2.0V; CL=10pF Measured @ 0.4V - 2.0V; CL=20pF Measured @ 2.0V - 0.4V; CL=10pF Measured @ 2.0V - 0.4V; CL=20pF 45 49 +60 136 123 1.1 1.4 1.0 1.1 55 45 49 +60 134 97 0.9 1.4 0.9 1.2 55 % ps ps ns ns 8.0 8.0 ns ns via CPU_STOP# via CPU_STOP# 1.0 1.0 8.0 8.0 1.0 1.0 REF_0:1 Clock Outputs (3.3V Type 3 Clock Buffer) Duty Cycle * Jitter, Long Term (y()) * Jitter, Period (peak-peak) * Rise Time * Fall Time * dt tj(LT) tj(P) tr min tr max tf min tf max Ratio of high pulse width to one clock period, measured at 1.5V On rising edges 500s apart at 1.5V relative to an ideal clock, CL=20pF, all PLLs active From rising edge to rising edge at 1.5V, CL=20pF, all PLLs active Measured @ 0.4V - 2.4V; CL=10pF Measured @ 0.4V - 2.4V; CL=20pF Measured @ 2.4V - 0.4V; CL=10pF Measured @ 2.4V - 0.4V; CL=20pF 45 50 27 177 0.9 1.4 1.0 1.6 55 45 50 23 111 0.9 1.4 1.0 1.6 55 % ps ps ns ns CK48 Clock Output (3.3V Type 3 Clock Buffer) Duty Cycle * Jitter, Long Term (y()) * Jitter, Period (peak-peak) * Rise Time * Fall Time * dt tj(LT) tj(P) tr min tr max tf min tf max Ratio of high pulse width to one clock period, measured at 1.5V On rising edges 500s apart at 1.5V relative to an ideal clock, CL=20pF, all PLLs active From rising edge to rising edge at 1.5V, CL=20pF, all PLLs active Measured @ 0.4V - 2.4V; CL=10pF Measured @ 0.4V - 2.4V; CL=20pF Measured @ 2.4V - 0.4V; CL=10pF Measured @ 2.4V - 0.4V; CL=20pF 45 51 244 143 0.8 1.3 0.9 1.4 55 45 51 246 202 0.8 1.3 0.9 1.4 55 % ps ps ns ns ,62 1.31.00 12 X T 0RWKHUERDUG &ORFN *HQHUDWRU ,& )6 January 2000 Table 9: AC Timing Specifications, continued Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature TA = 25C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 from typical. Spread spectrum modulation is disabled except for Rise/Fall time measurements. PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. 133MHz TYP. MAX. MIN. 100MHz TYP. MAX. UNITS PCI_1:7, PCI_F Clock Outputs (3.3V Type 5 Clock Buffer) Duty Cycle * Clock Skew * dt tskw tj(LT) tj(P) tr min tr max tf min tf max tDLH tDHL Ratio of high pulse width to one clock period, measured at 1.5V PCI_F to PCI @ 1.5V, CL=30pF PCI to PCI @ 1.5V, CL=30pF On rising edges 500s apart at 1.5V relative to an ideal clock, CL=30pF, all PLLs active From rising edge to rising edge at 1.5V, CL=30pF, all PLLs active Measured @ 0.4V - 2.4V; CL=10pF Measured @ 0.4V - 2.4V; CL=30pF Measured @ 2.4V - 0.4V; CL=10pF Measured @ 2.4V - 0.4V; CL=30pF 45 47 +660 +60 220 76 1.2 1.8 1.3 1.6 55 45 50 +660 +60 131 95 1.3 1.8 1.2 1.5 55 % ps Jitter, Long Term (y()) * Jitter, Period (peak-peak) * Rise Time * Fall Time * Enable Delay * Disable Delay * ps ps ns ns 8.0 8.0 ns ns via PCI_STOP# via PCI_STOP# 1.0 1.0 8.0 8.0 1.0 1.0 CK66_0:3 Clock Outputs (3.3V Type 5 Clock Buffer) Duty Cycle * Clock Skew * Jitter, Long Term (y()) * Jitter, Period (peak-peak) * Rise Time * Fall Time * Enable Delay * Disable Delay * dt tskw tj(LT) tj(P) tr min tr max tf min tf max tDLH tDHL Ratio of high pulse width to one clock period, measured at 1.5V CK66 to CK66 @ 1.5V, CL=30pF On rising edges 500s apart at 1.5V relative to an ideal clock, CL=30pF, all PLLs on From rising edge to rising edge at 1.5V, CL=30pF, all PLLs active Measured @ 0.4V - 2.4V; CL=10pF Measured @ 0.4V - 2.4V; CL=30pF Measured @ 2.4V - 0.4V; CL=10pF Measured @ 2.4V - 0.4V; CL=30pF 45 52 120 137 75 0.9 1.5 1.0 1.4 55 45 51 120 123 79 0.9 1.5 1.0 1.4 55 % ps ps ps ns ns via CPU_STOP# via CPU_STOP# 1.0 1.0 8.0 8.0 1.0 1.0 8.0 8.0 ns ns Figure 9: Clock Skew Diagrams CK66 1.25V 2.5V 1.5V 3.3V CPU 1.25V 2.5V CPU tskw CK66 3.3V APIC tskw 1.25V 2.5V PCI tskw 3.3V 1.5V 1.5V 2.5V to 3.3V Clock Offset 2.5V to 2.5V Clock Skew 3.3V to 3.3V Clock Skew 1.31.00 ,62 13 )6 0RWKHUERDUG &ORFN *HQHUDWRU ,& X T January 2000 Figure 10: DC Measurement Points 3.3V VOH 3.3 = 2.4V 1.5V VOL 3.3 = 0.4V (device interface) VIL 3.3 = 0.8V VOL 2.5 = 2.5V VIH 3.3 = 2.0V VOH 2.5 = 2.0V 1.25V 0.4V VIL 2.5 = 0.7V VIH 2.5 = 1.7V (system interface) (device interface) (system interface) A. 3.3V Clock Interface B. 2.5V Clock Interface Figure 11: Timing Diagrams KP tr tKH tKL Duty Cycle tf 2.4V 1.5V 0.4V KP tr tKH tf tKL Duty Cycle 2.0V 1.25V 0.4V A. 3.3V Clock Interface B. 2.5V Clock Interface Table 10: CPU_0:3, CPU/2_0:1, APIC_0:2 Clock Outputs Voltage (V) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.6 1.8 2.2 2.375 2.5 2.625 High Drive Current (mA) MIN. 0 3 6 9 12 15 17 19 21 23 24 25 27 27 28 29 29 29 29 TYP. 0 7 13 19 24 30 35 39 43 47 50 53 56 58 60 62 63 63 63 63 MAX. 0 11 21 30 40 48 56 63 70 77 83 88 93 97 100 106 110 111 111 111 111 Voltage (V) 0 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 1.9 2 2.1 2.2 2.3 2.375 2.5 2.625 Low Drive Current (mA) MIN. -28 -28 -28 -28 -27 -26 -24 -21 -17 -15 -12 -9 -6 -3 0 TYP. -61 -61 -61 -61 -60 -58 -53 -48 -40 -36 -31 -25 -20 -14 -9 0 MAX. -107 -107 -107 -107 -105 -101 -94 -85 -73 -67 -59 -51 -43 -34 -27 -14 0 120 100 80 60 Output Current (mA) 40 20 0 -20 -40 -60 -80 -100 -120 0 0.5 1 1.5 2 2.5 30 Output Voltage (V) 50 90 Data in this table represents nominal characterization data only ,62 1.31.00 14 X T 0RWKHUERDUG &ORFN *HQHUDWRU ,& )6 January 2000 Table 11: REF_0:1, CK48 Clock Outputs Voltage (V) 0 0.4 0.65 0.85 1 1.4 1.5 1.65 1.8 1.95 3.135 3.6 High Drive Current (mA) MIN. 0 9 14 17 20 25 26 27 28 29 29 TYP. 0 13 21 26 29 37 39 41 43 45 45 45 MAX. 0 27 41 52 59 76 79 84 88 92 102 102 Voltage (V) 0 1 1.4 1.5 1.65 1.8 2 2.4 2.6 3.135 3.3 3.465 Low Drive Current (mA) MIN. -29 -29 -27 -27 -25 -24 -22 -16 -12 0 TYP. -46 -46 -44 -43 -41 -39 -36 -28 -22 -6 0 MAX. -99 -99 -94 -92 -89 -85 -79 -63 -53 -23 -12 0 120 100 80 60 Output Current (mA) 40 20 0 -20 -40 -60 -80 -100 -120 0 0.5 1 1.5 2 2.5 3 3.5 30 Output Voltage (V) 50 90 Data in this table represents nominal characterization data only Table 12: PCI_1:7, PCI_F, CK66_0:3 Clock Outputs Voltage (V) 0 0.4 0.65 0.85 1 1.4 1.5 1.65 1.8 1.95 3.135 3.6 High Drive Current (mA) MIN. 0 9.4 14 17.7 20 26.5 28 29 30 30 31 32 TYP. 0 18 30 38 43 53 55 56 57 58 59 59 MAX. 0 38 64 84 100 139 148 163 175 178 187 188 Voltage (V) 0 1 1.4 1.5 1.65 1.8 2 2.4 2.6 3.135 3.3 3.465 Low Drive Current (mA) MIN. -34 -33 -31 -30 -28 -25.5 -22 -14.5 -11 0 TYP. -59 -58 -55 -54 -52 -50 -46 -35 -28 -6 0 MAX. -195 -194 -189 -184 -172 -159 -140 -100 -83 -33 -19 0 200 150 100 Output Current (mA) 50 0 0 -50 -100 -150 -200 0.5 1 1.5 2 2.5 3 3.5 30 Output Voltage (V) 50 90 Data in this table represents nominal characterization data only ,62 1.31.00 15 )6 0RWKHUERDUG &ORFN *HQHUDWRU ,& X T January 2000 7.0 Package Information Table 13: 56-pin SSOP (0.300") Package Dimensions DIMENSIONS INCHES MIN. A A1 A2 B C D E e H L 0.095 0.008 0.088 0.008 0.005 0.720 0.292 0.400 0.024 0 MAX. 0.110 0.016 0.092 0.0135 0.010 0.730 0.299 0.410 0.040 8 MILLIMETERS MIN. 2.41 0.203 2.24 0.203 0.127 18.29 7.42 10.16 0.610 0 MAX. 2.79 0.406 2.34 0.343 0.254 18.54 7.59 A2 D BASE PLANE SEATING PLANE 1 ALL RADII: 0.005" TO 0.01" AE"CAAC"#)#$E#AC 56 E H 7 typ. B e 0.025 BSC 0.64 BSC 10.41 1.02 8 A1 A C L Table 14: 56-pin SSOP (0.300") Package Characteristics PARAMETER Thermal Impedance, Junction to Free-Air Lead Inductance, Self SYMBOL JA L11 L12 Lead Inductance, Mutual L13 Lead Capacitance, Bulk C11 C12 Lead Capacitance, Mutual C13 CONDITIONS/DESCRIPTION Air flow = 0 m/s Longest trace + wire Shortest trace + wire Longest trace + wire to first adjacent trace Shortest trace + wire to first adjacent trace Longest trace + wire to next adjacent trace Shortest trace + wire to next adjacent trace Longest trace + wire to VSS Shortest trace + wire to VSS Longest trace + wire to first adjacent trace Shortest trace + wire to first adjacent trace Longest trace + wire to next adjacent trace Shortest trace + wire to next adjacent trace TYP. 81 6.41 2.49 3.65 1.35 2.50 0.90 0.94 0.49 0.48 0.20 0.04 0.01 pF pF nH UNITS C/W nH ,62 1.31.00 16 X T 0RWKHUERDUG &ORFN *HQHUDWRU ,& )6 January 2000 8.0 Ordering Information Table 15: Device Ordering Codes DEVICE NUMBER ORDERING CODE 11565-801 FS6261-01 11565-811 PACKAGE TYPE 48-pin (7.5mm/0.300") SSOP (Shrink Small Outline Package) 48-pin (7.5mm/0.300") SSOP (Shrink Small Outline Package) OPERATING TEMPERATURE RANGE 0C to 70C (Commercial) 0C to 70C (Commercial) SHIPPING CONFIGURATION Tape and Reel Tubes 9.0 DATE Revision Information PAGE 11-13 DESCRIPTION Updated characterization data 1/31/00 Copyright (c) 1999, 2000 American Microsystems, Inc. Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI reserves the right to discontinue production and change specifications and prices at any time and without notice. AMI's products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by AMI for such applications. American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796, WWW Address: http://www.amis.com E-mail: tgp@amis.com ,62 1.31.00 17 |
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