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IDT8535-01 LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
FEATURES:
* Four differential 3.3V LVPECL outputs * Selectable CLK0 or CLK1 inputs for redundant and multiple frequency fanout applications * Maximum output frequency: 266MHz * CLK0 or CLK1 can accept LVCMOS or LVTTL input levels * Translates LVCMOS and LVTTL levels to 3.3V LVPECL levels * Output skew: 30ps (max.) * Part-to-part skew: as low as 150ps * Propagation delay: 1.9ns (max.) * 3.3V operating supply * Available in TSSOP package
IDT8535-01
DESCRIPTION:
The IDT8535-01 is a low skew, high performance 1-to-4 LVCMOS-to-3.3V LVPECL fanout buffer. It has two single-ended clock inputs. The single-ended clock input accepts LVCMOS or LVTTL input levels and translates them to 3.3V LVPECL levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the IDT853501 ideal for those applications demanding well-defined performance and repeatability.
FUNCTIONAL BLOCK DIAGRAM
CLK_EN
D Q LE
CLK0
0
Q0 xQ0
CLK1
1
Q1 xQ1 Q2
CLK_SEL
xQ2 Q3 xQ3
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
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c 2004 Integrated Device Technology, Inc.
APRIL 2004
DSC 6196/6
IDT8535-01 LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VDD VI VO Input Voltage Output Voltage Package Thermal Impedance (0 lfpm) Storage Temperature Description Power Supply Voltage Max 4.6 -0.5 to VDD+0.5 Unit V V
VEE CLK_EN CLK_SEL CLK0 NC CLK1 NC NC NC VDD
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
Q0 xQ0 VDD Q1 xQ1 Q2 xQ2 VDD Q3 xQ3
JA
TSTG
-0.5 to VDD+0.5 V 92.6 C/W -65 to +150 C
NOTE: 1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
CAPACITANCE(TA = +25C, f = 1MHz, VIN = 0V)
Parameter CIN RPULLUP RPULLDOWN Description Input Capacitance Input Pullup Resistor Input Pulldown Resistor Typ. -- 51 51 Max. 4 -- -- Unit pF K K
TSSOP TOP VIEW
PIN DESCRIPTION(1)
Symbol VEE CLK_EN Number 1 2 PWR Input Pullup Type Negative Supply Pin Synchronizing Clock Enable. When HIGH, clock outputs follow clock input. When LOW, Q outputs are forced LOW, xQ outputs are forced HIGH. LVCMOS / LVTTL interface levels. CLK_SEL CLK0 CLK1 NC VDD xQ3, Q3 xQ2 Q2 xQ1, Q1 xQ0, Q0 3 4 6 5, 7, 8, 9 10, 13, 18 11, 12 14, 15 16, 17 19, 20 Input Input Input Unused Power Output Output Output Output Pulldown Pulldown Pulldown Clock Select Input. When HIGH, selects CLK1 input. When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels. LVCMOS / LVTTL Clock Input LVCMOS / LVTTL Clock Input No Connection Positive Supply Pins Differential Output Pair. LVPECL interface levels. Differential Output Pair. LVPECL interface levels. Differential Output Pair. LVPECL interface levels. Differential Output Pair. LVPECL interface levels. Description
NOTE: 1. Pullup and Pulldown refer to internal input resistors. See Capacitance table for typical values.
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IDT8535-01 LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
CONTROL INPUT FUNCTION TABLE(1,2)
Inputs CLK_EN 0 0 1 1 CLK_SEL 0 1 0 1 Selected Source CLK0 CLK1 CLK0 CLK1 Q0 to Q3 Disabled; LOW Disabled; LOW Enabled Enabled Outputs xQ0 to xQ3 Disabled; HIGH Disabled; HIGH Enabled Enabled
NOTES: 1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in the CLK_EN Timing Diagram below. 2. In active mode, the state of the outputs is a function of the CLK / xCLK and PCLK / xPCLK inputs as described in the Clock Input Function table.
Disabled CLK0, CLK1
Enabled

CLK_EN Timing Diagram
CLK EN
xQ0, xQ1, xQ2, xQ3 Q0, Q1, Q2, Q3
CLOCK INPUT FUNCTION TABLE(1)
Inputs CLK0 or CLK1 0 1
NOTE: 1. H = HIGH L = LOW
Outputs Q0 to Q3 L H xQ0 to xQ3 H L
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IDT8535-01 LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS - COMMERCIAL
Symbol VDD IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Min. 3.135 -- Typ. 3.3 -- Max. 3.465 50 Unit V mA
DC ELECTRICAL CHARACTERISTICS, LVCMOS / LVTTL - COMMERCIAL
Symbol VIH VIL IIH IIL Parameter Input Voltage HIGH Input Voltage LOW Input Current HIGH Input Current LOW CLK0, CLK1 CLK_EN, CLK_SEL CLK0, CLK1, CLK_SEL CLK_EN CLK0, CLK1, CLK_SEL CLK_EN VIN = VDD = 3.465V VIN = VDD = 3.465V VIN = 0V, VDD = 3.465V VIN = 0V, VDD = 3.465V -5 -150 Test Conditions Min. 2 -0.3 -0.3 Typ. Max. VDD + 0.3 1.3 0.8 150 5 A A Unit V V
DC ELECTRICAL CHARACTERISTICS, LVPECL - COMMERCIAL
Symbol VOH VOL VSWING Parameter Output Voltage HIGH
(1)
Test Conditions
Min. VDD - 1.4 VDD - 2 0.6
Typ.
Max. VDD - 1 VDD - 1.7 0.85
Unit V V V
Output Voltage LOW(1) Peak-to-Peak Output Voltage Swing
NOTE: 1. Outputs terminated with 50 to VDD - 2V.
AC ELECTRICAL CHARACTERISTICS - COMMERCIAL
All parameters measured at 266MHz unless noted otherwise; Cycle-to-cycle jitter on input = jitter on output; the part does not add jitter
Symbol FMAX tPD tSK(O) tSK(PP) tR tF odc Parameter Output Frequency Propagation Delay(1) Output Skew(2,4) Part-to-Part Skew Output Rise Time Output Fall Time Output Duty Cycle
(3,4)
Test Conditions f 266MHz
Min. 1
Typ.
Max. 266 1.9
Unit MHz ns ps ps ps ps %
11 20 - 80% @ 50MHz 20 - 80% @ 50MHz 300 300 48 50
30 150 700 700 52
NOTES: 1. Measured from the VDD/2 of the input to the differential output crossingpoint. 2. Defined as skew between outputs as the same supply voltage and with equal load conditions. Measured at the output differential crosspoints 3. Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoints. 4. This parameter is defined in accordance with JEDEC Standard 65.
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IDT8535-01 LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS - INDUSTRIAL
Symbol VDD IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Min. 3.135 -- Typ. 3.3 -- Max. 3.465 55 Unit V mA
DC ELECTRICAL CHARACTERISTICS, LVCMOS / LVTTL - INDUSTRIAL
Symbol VIH VIL IIH IIL Parameter Input Voltage HIGH Input Voltage LOW Input Current HIGH Input Current LOW CLK0, CLK1 CLK_EN, CLK_SEL CLK0, CLK1, CLK_SEL CLK_EN CLK0, CLK1, CLK_SEL CLK_EN VIN = VDD = 3.465V VIN = VDD = 3.465V VIN = 0V, VDD = 3.465V VIN = 0V, VDD = 3.465V -5 -150 Test Conditions Min. 2 -0.3 -0.3 Typ. Max. VDD + 0.3 1.3 0.8 150 5 A A Unit V V
DC ELECTRICAL CHARACTERISTICS, LVPECL - INDUSTRIAL
Symbol VOH VOL VSWING Parameter Output Voltage HIGH
(1)
Test Conditions
Min. VDD - 1.4 VDD - 2 0.6
Typ.
Max. VDD - 1 VDD - 1.7 0.85
Unit V V V
Output Voltage LOW(1) Peak-to-Peak Output Voltage Swing
NOTE: 1. Outputs terminated with 50 to VDD - 2V.
AC ELECTRICAL CHARACTERISTICS - INDUSTRIAL
All parameters measured at 266MHz unless noted otherwise; Cycle-to-cycle jitter on input = jitter on output; the part does not add jitter
Symbol FMAX tPD tSK(O) tSK(PP) tR tF odc Parameter Output Frequency Propagation Delay(1) Output Skew(2,4) Part-to-Part Skew Output Rise Time Output Fall Time Output Duty Cycle
(3,4)
Test Conditions f 266MHz
Min. 1
Typ.
Max. 266 1.9 30 200
Unit MHz ns ps ps ps ps %
20 - 80% @ 50MHz 20 - 80% @ 50MHz
300 300 48 50
700 700 52
NOTES: 1. Measured from the VDD/2 of the input to the differential output crossingpoint. 2. Defined as skew between outputs as the same supply voltage and with equal load conditions. Measured at the output differential crosspoints 3. Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoints. 4. This parameter is defined in accordance with JEDEC Standard 65.
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IDT8535-01 LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PARAMETER MEASUREMENT INFORMATION
VDD Scope Z = 50 Qx 50 Z = 50
LVPECL
VDD = 2V xQx
50
VEE = -1.3V 0.135V
Output Load Test Circuit
xQx Qx
xQy Qy tSK(0)
Output Skew
xQx Part 1 Qx
xQy Part 2 Qy tSK(PP)
Part-to-Part Skew
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IDT8535-01 LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PARAMETER MEASUREMENT INFORMATION - CONTINUED
80%
80% VSWING
Clock Outputs
20%
20%
tR
tF
Output Rise and Fall Time
CLK0, CLK1
xQ0, xQ1, xQ2, xQ3 Q0, Q1, Q2, Q3 tPD
Propagation Delay
xQ0, xQ1, xQ2, xQ3 Q0, Q1, Q2, Q3 Pulse Width tPERIOD tW odc = tPERIOD
odc and tPERIOD
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IDT8535-01 LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
APPLICATION INFORMATION
TERMINATION FOR LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and xFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. The diagrams below show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist. It is recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50
5 2
FOUT Zo = 50 FIN
Zo
5 2
Zo
Zo = 50
FOUT
50 50
FIN Zo = 50
VDD - 2V 1 RTT = (VOH + VOL / VDD - 2) - 2 Zo RTT
3 2
Zo
3 2
Zo
LVPECL Output Termination, layout A
LVPECL Output Termination, layout B
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IDT8535-01 LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the IDT8535-01. Equations and example calculations are also provided. POWER DISSIPATION: The total power dissipation for the IDT8535-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for the VDD = 3.3V + 5% = 3.465V, which gives worst case results. Please refer to the following section, Calculations and Equations, for details on calculating power dissipated in the load. Power (core)MAX = VDD_MAX * ICC_MAX = 3.465 * 50mA = 173.25mW Power (outputs)MAX = 30.2mW/Loaded Output Pair If all outputs are loaded, the total power is 4 * 30.2mW = 120.8Mw Total Power_MAX (3.465V, with all outputs switching) = 173.25mW + 120.8mW = 294.05mW JUNCTION TEMPERATURE: Junction temperature (tJ) is the temperature at the junction of the bond wire and bond pad. It directly affects the reliability of the device. The maximum recommended junction temperature for this device is 125C. The equation for is as follows: tJ = JA * Pd_total + TA tJ = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in Power Dissipation, above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance (JA) must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 77.6C/W per the following Thermal Resistance table. Therefore, tJ for an ambient temperature of 70C with all its outputs switching is: 70C + 0.294W * 77.6C/W = 92.81C. This is well below the limit of 125C. This calculation is only an example. tJ will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (singlelayer or multi-layer).
THERMAL RESISTANCE
JA for 20-pin TSSOP, forced convenction JA by Velocity (Linear Feet per mInute)
0 Multi-Layer PCB, JEDEC Standard Test boards 92.6 200 77.6 400 70.9 Unit
C/W
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IDT8535-01 LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
CALCULATIONS AND EQUATIONS
VDD
Q1
VOUT RL 50 VDD - 2V
LVPECL Output Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations, which assume a 50 load and a termination voltage of VDD - 2V. For Logic HIGH: VOUT = VOH_MAX = VDD_MAX - 1V. (VDD_MAX - VOH_MAX) = 1V For Logic LOW: VOUT = VOL_MAX = VDD_MAX - 1.7V. (VDD_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives HIGH. Pd_L is power dissipation when the output drives LOW. Pd_H = {[ VOH_MAX - (VDD_MAX - 2V)] / RL} * (VDD_MAX - VOH_MAX) = {[ 2V - (VDD_MAX - VOH_MAX)] / RL} * (VDD_MAX - VOH_MAX) = [( 2V - 1V) / 50] * 1V = 20mW. Pd_L = {[ VOL_MAX - (VDD_MAX - 2V)] / RL} * (VDD_MAX - VOL_MAX) = {[ 2V - (VDD_MAX - VOL_MAX)] / RL} * (VDD_MAX - VOL_MAX) = [( 2V - 1.7V) / 50] * 1.7V = 10.2mW. Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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IDT8535-01 LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXX Device Type XX Package X Process
Blank I
Commercial (0C to +70C) Industrial (-40C to +85C)
PG
Thin Shrink Small Outline Package
8535-01
Low Skew, 1-to-4 LVCMOS-to-3.3V LVPECL Fanout Buffer
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