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ISL8011
Data Sheet July 11, 2006 FN9254.0
1.2A Integrated FETs, High Efficiency Synchronous Buck Regulator
ISL8011 is an integrated FET, 1.2A synchronous buck regulator for general purpose point-of load applications. It is optimized for generating low output voltages down to 0.8V. The supply voltage range is from 2.7V to 5.5V allowing the use from common 3.3V or 5V supply rails and Lithium ion battery inputs. It has guaranteed minimum output current of 1.2A. 1.5MHz pulse-width modulation (PWM) switching frequency allowing the use of small external components. The ISL8011 includes a pair of low on-resistance P-channel and N-channel internal MOSFETs to maximize efficiency and minimize external component count. 100% duty-cycle operation allows less than 200mV dropout voltage at 1.2A. The ISL8011 offers a 200ms Power-On-Reset (POR) timer at power-up. When shutdown, the ISL8011 discharges the output capacitor. Other features include internal digital softstart, enable for power sequence, overcurrent protection, and thermal shutdown. The ISL8011 is offered in a 10 Ld 3x3mm DFN package with 1mm maximum height. The complete converter occupies less than 1cm2 area.
Features
* High Efficiency Synchronous Buck Regulator with Up to 95% Efficiency * 2.7V to 5.5V Supply Voltage * 1.2A Guaranteed Output Current * 100% Maximum Duty Cycle * Peak Current Limiting, Short Circuit Protection * 200ms Power-On Reset * 3% Output Accuracy Over Temperature/Load/Line * Less than 1A Logic Controlled Shutdown Current * Internal Loop Compensation * Internal Digital Soft-Start * Over-Temperature Protection * Enable * Small 10 Ld 3x3mm DFN * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* DC/DC POL Modules * C/P, FPGA & DSP Power
Ordering Information
TEMP. RANGE PART NUMBER PART (C) (NOTE) MARKING ISL8011IRZ ISL8011IRZ-T 011Z 011Z PACKAGE (Pb-Free) PKG. DWG. #
* Plug-in DC/DC Modules for Routers and Switchers * Portable Instruments * Test and Measurement Systems
-40 to 85 10 Ld 3x3 DFN L10.3x3 -40 to 85 10 Ld 3x3 DFN L10.3x3
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinout
ISL8011 (10 LD 3x3 DFN) TOP VIEW
PVIN VCC EN POR GND
1 2 3 4 5
10 PHASE 9 PGND 8 SGND 7 FB 6 N/C
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL8011
Absolute Maximum Ratings (Reference to SGND)
Supply Voltage (PVIN, VCC) . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V EN, MODE, PHASE, POR . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3V FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
Thermal Information
Thermal Resistance (Notes 1, 2) JA (C/W) JC (C/W) 3x3 DFN Package . . . . . . . . . . . . . . . . 46 4 Junction Temperature Range. . . . . . . . . . . . . . . . . . . -55C to 150C Storage Temperature Range . . . . . . . . . . . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300C
Recommended Operating Conditions
PVIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 1.2A Ambient Temperature Range . . . . . . . . . . . . . . . . . . . .-40C to 85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. JC, "case temperature" location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications
Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and the typical specification are measured at the following conditions: TA = 25C, VPVIN = VVCC = 3.6V, EN = VCC, L = 1.8H, C1 = 10F, C2 = 10F, IOUT = 0A (see the Typical Application Circuit). SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER SUPPLY VCC Undervoltage Lockout Threshold
VUVLO
Rising Falling
2.2 -
2.5 2.4 5 0.1
2.7 8 2
V V mA A
Quiescent Supply Current Shut Down Supply Current OUTPUT REGULATION FB Regulation Voltage
IPVIN ISD
No load at the output VCC = PVIN = 5.5V, EN = low
VFB
TA = 0C to 85C TA = -40C to 85C
0.784 0.78 -3 1.2
0.8 0.8 0.1 0.2 -
0.816 0.82 3 -
V V A % %/V A
FB Bias Current Output Voltage Accuracy Line Regulation Maximum Output Current COMPENSATION Error Amplifier Trans-conductance PHASE P-Channel MOSFET On Resistance
IFB
FB = 0.75V PVIN = VO + 0.5V to 5.5V, IO = 0 to 1.2A, TA = -40C to 85C PVIN = VO + 0.5V to 5.5V (minimal 2.7V)
Adjustable version, design info only
-
20
-
A/V
PVIN = 3.6V, Io = 200mA PVIN = 2.7V, Io = 200mA
1.5 -
0.12 0.16 0.11 0.15 2.1 100 1.6 1.1
0.22 0.27 0.22 0.27 2.6 1.75 140 -
A % MHz ns ms
N-Channel MOSFET On Resistance
PVIN = 3.6V, Io = 200mA PVIN = 2.7V, Io = 200mA
P-Channel MOSFET Peak Current Limit PHASE Maximum Duty Cycle PWM Switching Frequency PHASE Minimum On Time Soft Start-Up Time
IPK
fS
TA = -40C to 85C
1.35 -
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FN9254.0 July 11, 2006
ISL8011
Electrical Specifications
Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and the typical specification are measured at the following conditions: TA = 25C, VPVIN = VVCC = 3.6V, EN = VCC, L = 1.8H, C1 = 10F, C2 = 10F, IOUT = 0A (see the Typical Application Circuit). (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER POR Output Low Voltage Delay Time POR Pin Leakage Current Minimum Supply Voltage for Valid POR Signal Internal PGOOD Low Rising Threshold Internal PGOOD Low Falling Threshold Internal PGOOD High Rising Threshold Internal PGOOD High Falling Threshold Internal PGOOD Delay Time EN Logic Input Low Logic Input High Logic Input Leakage Current Thermal Shutdown Thermal Shutdown Hysteresis
Sinking 1mA, FB = 0.7V
150
200 0.01 92 88 108 105 50
0.3 275 0.1 94.5 91 110.5 108 -
V ms A V % % % % s
POR = VCC = 3.6V
1.2
Percentage of Nominal Regulation Voltage Percentage of Nominal Regulation Voltage Percentage of Nominal Regulation Voltage Percentage of Nominal Regulation Voltage
89.5 85 105.5 102 -
1.4 Pulled up to 5.5V -
0.1 150 25
0.4 1 -
V V A C C
Typical Operating Performance
100 VOUT = 3.3V 2.60
90 EFFICIENCY (%) VOUT = 2.5V VOUT (V) VOUT = 1.8V 80
2.55
2.50
70
2.45
60 50 200 350 500 650 800 950 1100 LOAD CURRENT (mA)
2.40 50
250
450
650
850
1050
LOAD CURRENT (mA)
FIGURE 1. EFFICIENCY vs LOAD CURRENT (VIN = 5.0V)
FIGURE 2. VOUT vs LOAD CURRENT (VIN = 5V)
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FN9254.0 July 11, 2006
ISL8011 Typical Operating Performance
7 SWITCHING FREQUENCY (MHz) VO = 2.8V 6 INPUT CURRENT (mA) 5 4 3 2 1 0 2.9
(Continued)
1.605 1.6 1.595 1.59 1.585 1.58 1.575 1.57
3.4
3.9
4.4
4.9
5.4
2.7
3.2
3.7
4.2 VIN (V)
4.7
5.2
VIN VOLTAGE RANGE (2.9V-5.5V)
FIGURE 3. IQ vs VIN
FIGURE 4. SWITCHING FREQUENCY vs VIN
1.61
1.61
1.608 1.605 1.606 VO (V) VO (V) 2.7 3.7 VIN (V) 4.7 1.6
1.604
1.602
1.595
1.6
5.7
1.59
0
200
400 IO (mA)
600
800
1000
FIGURE 5. LINE REGULATION (IO = 1A)
FIGURE 6. LOAD REGULATION (VIN = 3.6V)
FIGURE 7. SOFT-START
FIGURE 8. STEADY-STATE (VIN = 3.6V; VO = 1.6V; IO = 1A)
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ISL8011 Typical Operating Performance
(Continued)
FIGURE 9. LOAD TRANSIENT (VIN = 3.6V; VO = 1.6V; IO = 0A~1A)
Pin Descriptions
PVIN
Input supply voltage. Connect a 10F ceramic capacitor to power ground.
FB
Buck regulator output feedback. Connect to the output through a resistor divider for adjustable the output voltage.
Exposed Pad
The exposed pad must be connected to the PGND pin for proper electrical performance and optimal thermal performance.
VCC
Supply voltage for internal analog and digital control circuits, delivered from PVIN. Bypass with 0.1F ceramic capacitor to signal ground.
EN
Regulator enable pin. Force this pin above 1.4V enable the chip. Force this pin below 0.4V shutdown the chip and discharge output capacitor when driven to low. Do not leave this pin floating.
POR
200ms timer output. At power-up or EN HI, this output is a 200ms delayed Power-Good signal for the output voltage.
GND
Ground.
PHASE
Switching node connection. Connect to one terminal of inductor.
PGND
Power ground. Connect all power grounds to this pin.
SGND
Analog ground. SGND and PGND should only have one point connection.
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FN9254.0 July 11, 2006
ISL8011 Typical Applications
ISL8011
VIN 2.7V to 5.5V
C1 10F C3 0.1F L
PVIN
PHASE
1.8H C2 10F R2 61.9kO
VOUT 1.3V, 1.2V
VCC
PGND
SGND EN
R1 100kO R3 100kO
FB
POR GND
FIGURE 10. TYPICAL APPLICATION FOR ADJUSTABLE VERSION
Block Diagram
VCC
Shutdown Soft-Start Shutdown
400kO 25pF 0.8pF 5O
PVIN
Oscillator EA EN Bandgap 0.8V COMP PWM Control and Drivers PGND PHASE
Slope Compensation
CSA1 FB OCP 0.864V 0.85V
0.736V
POR
200ms Delay
SCP 0.2V SGND GND
FIGURE 11. FUNCTIONAL BLOCK DIAGRAM
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FN9254.0 July 11, 2006
ISL8011 Theory of Operation
ISL8011 is an integrated FET, 1.2A synchronous buck
regulator for general purpose point-of load applications. The regulator operates at 1.5MHz fixed switching frequency under heavy load condition to allow small external inductor and capacitors to be used for minimal printed-circuit board (PCB) area. The supply current is typically only 0.1A when the regulator is shut down.
Short-Circuit Protection
A short-circuit protection (SCP) comparator monitors the FB pin voltage for output short-circuit protection. When the FB is lower than 0.2V, the SCP comparator forces the PWM oscillator frequency to drop to 1/3 of the normal operation value. This comparator is effective during start-up or an output short-circuit event.
V EAMP V CSA1 Duty Cycle IL
PWM Control Scheme
The ISL8011 employs the current-mode pulse-width modulation (PWM) control scheme for fast transient response and pulse-by-pulse current limiting. Figure 11 shows the block diagram. The current loop consists of the oscillator, the PWM comparator COMP, current sensing circuit, and the slope compensation for the current loop stability. The current sensing circuit consists of the resistance of the P-channel MOSFET when it is turned on and the current sense amplifier (CSA). The gain for the current sensing circuit is typically 0.4V/A. The control reference for the current loops comes from the error amplifier EAMP of the voltage loop. The PWM operation is initialized by the clock from the oscillator. The P-channel MOSFET is turned on at the beginning of a PWM cycle and the current in the MOSFET starts to ramp up. When the sum of the CSA and the compensation slope (0.675V/s) reaches the control reference of the current loop, the PWM comparator COMP sends a signal to the PWM logic to turn off the P-MOSFET and to turn on the N-channel MOSFET. The N-MOSFET stays on until the end of the PWM cycle. Figure 12 shows the typical operating waveforms during the PWM operation. The dotted lines illustrate the sum of the compensation ramp and the CSA output. The output voltage is regulated by controlling the reference voltage to the current loop. The bandgap circuit outputs a 0.8V reference voltage to the voltage control loop. The feedback signal comes from the FB pin. The soft-start block only affects the operation during the start-up and will be discussed separately shortly. The error amplifier is a transconductance amplifier that converts the voltage error signal to a current output. The voltage loop is internally compensated with the 25pF and 400k RC network. The maximum EAMP voltage output is precisely clamped to the bandgap voltage (1.172V).
V OUT
FIGURE 12. PWM OPERATION WAVEFORMS
POR Signal
The ISL8011 offers a power-on reset (POR) signal for resetting the microprocessor at the power-up. When the output voltage is not within a power-good window, the POR pin outputs an open-drain low signal to reset the microprocessor. The output voltage is monitored through the FB pin. When the voltage of the monitored node is within the window of 0.736V and 0.864V, a power-good signal is issued to turn off the open-drain POR pin. The rising edge of the POR output is delayed by 200ms.
UVLO
When the input voltage is below the undervoltage lock out (UVLO) threshold, the regulator is disabled.
Soft Start-Up
The soft start-up eliminates the inrush current during the start-up. The soft-start block outputs a ramp reference to both the voltage loop and the current loop. The two ramps limit the inductor current rising speed as well as the output voltage speed so that the output voltage rises in a controlled fashion. At the very beginning of the start-up, the output voltage is less than 0.2V; hence the PWM operating frequency is 1/3 of the normal frequency. Figure 7 shows the start-up waveforms.
Overcurrent Protection
The overcurrent protection is realized by monitoring the CSA output with the OCP comparator, as shown in Figure 11. The current sensing circuit has a gain of 0.4V/A, from the N-MOSFET current to the CSA output. When the CSA output reaches 1V, which is equivalent to 2.5A for the switch current, the OCP comparator is tripped to turn off the P-MOSFET immediately.
Power MOSFETs
The power MOSFETs are optimized for best efficiency. The on resistance for the P-MOSFET is typically 150m and the on resistance for the N-MOSFET is typically 150m.
100% Duty Cycle
The ISL8011 features 100% duty cycle operation to maximize the battery life. When the battery voltage drops to
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FN9254.0 July 11, 2006
ISL8011
a level that the ISL8011 can no longer maintain the regulation at the output, the regulator completely turns on the P-MOSFET. The maximum drop out voltage under the 100% duty-cycle operation is the product of the load current and the on resistance of the P-MOSFET.
TABLE 1. OUTPUT CAPACITOR VALUE vs VOUT VOUT 0.8V 1.2V 1.6V 1.8V 2.5V 3.3V 3.6V COUT 10F 10F 10F 10F 10F 6.8F 4.7F L 1.0H~2.2H 1.2H~2.2H 1.8H~2.2H 1.8H~3.3H 1.8H~3.3H 1.8H~4.7H 1.8H~4.7H
Enable
The enable (EN) input allows user to control the turning on or off the regulator for purposes such as power-up sequencing. The the regulator is enabled, there is typically a 300s delay for waking up the bandgap reference. Then the soft start-up begins. When the regulator is disabled, the P-MOSFET is turned off immediately and the N-MOSFET is turned on.
Thermal Shut Down
The ISL8011 has built-in thermal protection. When the internal temperature reaches 150C, the regulator is completely shut down. As the temperature drops to 130C, the ISL8011 resumes operation by stepping through a soft start-up.
In Table 1, the minimum output capacitor value is given for different output voltage to make sure the whole converter system stable. Due to the limitation on power dissipation when the regulator disable and discharge output capacitor, there is the maximum output capacitor value. The maximum output capacitor value is variable with the output voltage. The plot curve is shown in Figure 13.
600 OUTPUT CAPACITOR VALUE (F)
VCC By-Passing
The VCC is voltage is the supply to the internal control circuit and is derived from the PVIN pin. An internal 5 resistor connects the two pins and also serves as an filtering resistor. An external 0.1F ceramic capacitor is recommended to by-pass the VCC supply.
505
410
315
Applications Information
Output Inductor and Capacitor Selection
To consider state steady and transient operation, ISL8011 typically uses a 1.8H output inductor. Higher or lower inductor values can be used to optimize the total converter system performance. For example, for higher output voltage 3.3V application, in order to decrease the inductor current ripple and output voltage ripple, the output inductor value can be increased as shown in Table 1. The inductor ripple current can be expressed as follows:
VO V O * 1 - --------- V IN I = -------------------------------------L * fS
220
125
30 0.8
1.27
1.73 2.2 2.67 OUTPUT VOLTAGE (V)
3.13
3.6
FIGURE 13. THE MAXIMUM CAP vs THE OUTPUT VOLTAGE
Input Capacitor Selection
The main functions for the input capacitor are to provide decoupling of the parasitic inductance and to provide filtering function to prevent the switching current flowing back to the supply rail. A 10F X5R or X7R ceramic capacitor is a good starting point for the input capacitor selection.
The inductor's saturation current rating needs be at least larger than the peak current. The maximum peak current of ISL8011 is 2.1A. The saturation current needs be over 2.1A for maximum output current application. ISL8011 uses internal compensation network and the output capacitor value is dependant on the output voltage. The ceramic capacitor is recommended to be X5R or X7R. The recommended minimum output capacitor values are shown in Table 1.
Output Voltage Setting Resistor Selection
The resistors R2 and R3 shown in Figure 10 set the output voltage for the adjustable version. The output voltage can be calculated by:
R 2 V O = 0.8 * 1 + ------ R 3
where the 0.8V is the reference voltage. To minimize the accuracy impact on the output voltage, select the R2 and R3 no larger than 100k.
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FN9254.0 July 11, 2006
ISL8011
Layout Recommendation
The layout is a very important converter design step to make sure the designed converter works well. For ISL8011 buck converter, the power loop is composed of the output inductor L, the output capacitor COUT, Phase pin and PGND pin. It is necessary to make the power loop as small as possible. In order to make the output voltage regulate well and avoid the noise coupling from the power loop, SGND pin should be connected with PGND pin at the terminals of the load. The heat of the IC is mainly dissipated through the thermal pad. Maximizing the copper area connected to the thermal pad is preferable. In addition, a solid ground plane is helpful for EMI performance.
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FN9254.0 July 11, 2006
ISL8011 Dual Flat No-Lead Plastic Package (DFN)
2X 0.15 C A A D 2X 0.15 C B
L10.3x3
10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1 MIN 0.80 0.18 1.95 1.55 0.25 0.30 NOMINAL 0.90 0.20 REF 0.23 3.00 BSC 2.00 3.00 BSC 1.60 0.50 BSC 0.35 10 5 0.40 1.65 2.05 0.28 MAX 1.00 0.05 NOTES 5,8 7,8 7,8 8 2 3 Rev. 3 6/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.
E 6 INDEX AREA TOP VIEW B
A3 b D D2 E E2
0.10 C
e k L N Nd
A 0.08 C C SEATING PLANE SIDE VIEW A3
7 (DATUM B) 6 INDEX AREA (DATUM A) 1 2 D2
8
D2/2 NX k E2 E2/2
NX L N 8 N-1 NX b e (Nd-1)Xe REF. BOTTOM VIEW 5 0.10 M C A B
C L 0.415 NX (b) 5 SECTION "C-C" C NX b (A1) 0.200 L NX L e CC TERMINAL TIP
FOR ODD TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FN9254.0 July 11, 2006

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