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OBSOLETE
2, 4 MEG x 72 NONBUFFERED DRAM DIMMs
DRAM MODULE
FEATURES
* JEDEC-standard, eight-CAS#, ECC pinout in a 168-pin, dual in-line memory module (DIMM) * 16MB (2 Meg x 72) and 32MB (4 Meg x 72) * Nonbuffered * High-performance CMOS silicon-gate process * Single +3.3V 0.3V power supply * All inputs, outputs and clocks are TTL-compatible * Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS# (CBR) and HIDDEN * 2,048-cycle refresh distributed across 32ms * FAST-PAGE-MODE (FPM) or Extended Data-Out (EDO) PAGE MODE access cycles * Serial presence-detect (SPD)
MT9LD272A(X), MT18LD472A(X)
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PIN ASSIGNMENT (Front View) 168-Pin DIMM
OPTIONS
* Package 168-pin DIMM (gold) * Timing 50ns access 60ns access * Access Cycles FAST PAGE MODE EDO PAGE MODE
*EDO version only
MARKING
G -5* -6 None X
KEY TIMING PARAMETERS
EDO Operating Mode
SPEED -5 -6
tRC tRAC tPC tAA tCAC tCAS
84ns 104ns
50ns 60ns
20ns 25ns
25ns 30ns
13ns 15ns
8ns 10ns
FPM Operating Mode
SPEED -6
tRC tRAC tPC tAA tCAC tRP
110ns
60ns
35ns
30ns
15ns
40ns
NOTE: Pin symbols in parentheses are not used on these modules but may be used for other modules in this product family. They are for reference only.
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
SYMBOL VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 CB1 VSS NC NC VDD WE0# CAS0# CAS1# RAS0# OE0# VSS A0 A2 A4 A6 A8 A10 NC (A12) VDD VDD RFU
PIN 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
SYMBOL VSS OE2# RAS2# CAS2# CAS3# WE2# VDD NC NC CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 VDD DQ20 NC RFU NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS NC NC NC SDA SCL VDD
PIN 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126
SYMBOL VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 CB4 CB5 VSS NC NC VDD RFU CAS4# CAS5# NC RFU VSS A1 A3 A5 A7 A9 NC (A11) NC (A13) VDD RFU RFU
PIN SYMBOL 127 VSS 128 RFU 129 NC/RAS3#* 130 CAS6# 131 CAS7# 132 RFU 133 VDD 134 NC 135 NC 136 CB6 137 CB7 138 VSS 139 DQ48 140 DQ49 141 DQ50 142 DQ51 143 VDD 144 DQ52 145 NC 146 RFU 147 NC 148 VSS 149 DQ53 150 DQ54 151 DQ55 152 VSS 153 DQ56 154 DQ57 155 DQ58 156 DQ59 157 VDD 158 DQ60 159 DQ61 160 DQ62 161 DQ63 162 VSS 163 NC 164 NC 165 SA0 166 SA1 167 SA2 168 VDD
2, 4 Meg x 72 Nonbuffered DRAM DIMMs DM60.p65 - Rev. 6/98
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OBSOLETE
2, 4 MEG x 72 NONBUFFERED DRAM DIMMs
PART NUMBERS
EDO Operating Mode
PART NUMBER MT9LD272AG-5 X MT9LD272AG-6 X MT18LD472AG-5 X MT18LD472AG-6 X CONFIGURATION 2 Meg x 72 ECC 2 Meg x 72 ECC 4 Meg x 72 ECC 4 Meg x 72 ECC SPEED 50ns 60ns 50ns 60ns
EDO PAGE MODE
EDO PAGE MODE, designated by the "X" version, is an accelerated FAST-PAGE-MODE cycle. The primary advantage of EDO is the availability of data-out even after CAS# goes back HIGH. EDO provides for CAS# precharge time (tCP) to occur without the output data going invalid. This elimination of CAS# output control provides for pipelined READs. FAST-PAGE-MODE modules have traditionally turned the output buffers off (High-Z) with the rising edge of CAS#. EDO-PAGE-MODE DRAMs operate like FASTPAGE-MODE DRAMs, except data will remain valid or become valid after CAS# goes HIGH during READs, provided RAS# and OE# are held LOW. If OE# is pulsed while RAS# and CAS# are LOW, data will toggle from valid data to High-Z and back to the same valid data. If OE# is toggled or pulsed after CAS# goes HIGH while RAS# remains LOW, data will transition to and remain High-Z. During an application, if the DQ outputs are wire OR'd, OE# must be used to disable idle banks of DRAMs. Alternatively, pulsing WE# to the idle banks during CAS# HIGH time will also High-Z the outputs. Independent of OE# control, the outputs will disable after tOFF, which is referenced from the rising edge of RAS# or CAS#, whichever occurs last. (Refer to the 4 Meg x 4 [MT4LC4M4E8] DRAM data sheet for additional information on EDO functionality.)
FPM Operating Mode
PART NUMBER MT9LD272AG-6 MT18LD472AG-6 CONFIGURATION 2 Meg x 72 ECC 4 Meg x 72 ECC SPEED 60ns 60ns
GENERAL DESCRIPTION
The MT9LD272A(X) and MT18LD472A(X) are randomly accessed 16MB and 32MB memories organized in a x72 configuration. They are specially processed to operate from 3V to 3.6V for low-voltage memory systems. During READ or WRITE cycles, each bit is uniquely addressed through the 21/22 address bits, which are entered 11 bits (A0 -A10) at RAS# time and 10/11 bits (A0A10) at CAS# time. READ and WRITE cycles are selected with the WE# input. A logic HIGH on WE# dictates read mode, while a logic LOW on WE# dictates write mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE# or CAS#, whichever occurs last. An EARLY WRITE occurs when WE# is taken LOW prior to CAS# falling. A LATE WRITE or READ-MODIFY-WRITE occurs when WE# falls after CAS# was taken LOW. During EARLY WRITE cycles, the data-outputs (Q) will remain High-Z regardless of the state of OE#. During LATE WRITE or READ-MODIFYWRITE cycles, OE# must be taken HIGH to disable the dataoutputs prior to applying input data. If a LATE WRITE or READ-MODIFY-WRITE is attempted while keeping OE# LOW, no WRITE will occur, and the data-outputs will drive read data from the accessed location.
REFRESH
Returning RAS# and CAS# HIGH terminates a memory cycle and decreases chip current to a reduced standby level. Also, the chip is preconditioned for the next cycle during the RAS# HIGH time. Correct memory cell data is preserved by maintaining power and executing any RAS# cycle (READ, WRITE) or RAS# REFRESH cycle (RAS#ONLY, CBR or HIDDEN) so that all combinations of RAS# addresses (A0-A9/A10) are executed at least every tREF, regardless of sequence. The CBR REFRESH cycle will invoke the internal refresh counter for automatic RAS# addressing.
FAST PAGE MODE
FAST-PAGE-MODE operations allow faster data operations (READ or WRITE) within a row-address-defined page boundary. The FAST-PAGE-MODE cycle is always initiated with a row address strobed in by RAS#, followed by a column address strobed in by CAS#. Additional columns may be accessed by providing valid column addresses, strobing CAS# and holding RAS# LOW , thus executing faster memory cycles. Returning RAS# HIGH terminates the FAST-PAGE-MODE operation.
SERIAL PRESENCE-DETECT OPERATION
This module family incorporates serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various DRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/ WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard IIC bus using the DIMM's SCL (clock) and SDA (data) signals,
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2, 4 Meg x 72 Nonbuffered DRAM DIMMs DM60.p65 - Rev. 6/98
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2, 4 MEG x 72 NONBUFFERED DRAM DIMMs
together with SA(2:0), which provide eight unique DIMM/ EEPROM addresses. SPD CLOCK AND DATA CONVENTIONS Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (Figures 1 and 2). SPD START CONDITION All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. SPD STOP CONDITION All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode. SPD ACKNOWLEDGE Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data (Figure 3). The SPD device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the SPD device will respond with an acknowledge after the receipt of each subsequent eight-bit word. In the read mode the SPD device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode.
SCL
SCL
SDA
SDA
DATA STABLE DATA CHANGE DATA STABLE
START BIT STOP BIT
Figure 1 DATA VALIDITY
Figure 2 DEFINITION OF START AND STOP
SCL from Master
8
9
Data Output from Transmitter
Data Output from Receiver Acknowledge
Figure 3 ACKNOWLEDGE RESPONSE FROM RECEIVER
2, 4 Meg x 72 Nonbuffered DRAM DIMMs DM60.p65 - Rev. 6/98
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FUNCTIONAL BLOCK DIAGRAM MT9LD272A(X) (16MB)
DQ0-DQ7 DQ8-DQ15 CB0-CB7 DQ16-DQ23 DQ24-DQ31
DQ0-DQ7
DQ0-DQ7 WE# WE# U3 OE# RAS# OE# RAS# A0-A10 CAS#
DQ0-DQ7 WE# U4 OE# RAS# A0-A10 CAS#
DQ0-DQ7 U5
WE0# OE0# RAS0# CAS0# CAS1# CAS2# CAS3#
WE# U1 OE# RAS# CAS# A0-A10
WE# U2 OE# RAS# CAS# A0-A10
CAS#
A0-A10
11
11
11
11
11
A0-A10
DQ32-DQ39
DQ40-DQ41
DQ48-DQ55
DQ56-DQ63
DQ0-DQ7
DQ0-DQ7 WE# WE# U7 OE# RAS# OE# RAS# A0-A10 CAS#
DQ0-DQ7 WE# U8 OE# RAS# A0-A10 CAS#
DQ0-DQ7 U9
WE2# OE2# RAS2# CAS4# CAS5# CAS6# CAS7#
WE# U6 OE# RAS# CAS# A0-A10
CAS#
A0-A10
11
11
11
11
SPD SCL A0 A1 A2 SDA VDD VSS SA0 SA1 SA2 U1-U9 U1-U9
U1-U9 = MT4LC2M8B1 FAST PAGE MODE U1-U9 = MT4LC2M8E7 EDO PAGE MODE
2, 4 Meg x 72 Nonbuffered DRAM DIMMs DM60.p65 - Rev. 6/98
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FUNCTIONAL BLOCK DIAGRAM MT18LD472A(X) (32MB)
DQ0-DQ3 DQ4-DQ7 DQ8-DQ11 DQ12-DQ15 CB4-CB7 DQ16-DQ19 DQ20-DQ23 DQ24-DQ27 DQ28-DQ31
DQ0-DQ3 WE0# OE0# RAS0# CAS0# CAS1# CAS2# CAS3# A0-A10 WE# OE# RAS# CAS# A0-A10 U1
DQ0-DQ3 WE# OE# RAS# CAS# A0-A10 U2
DQ0-DQ3 WE# OE# RAS# CAS# A0-A10 U3
DQ0-DQ3 WE# OE# RAS# CAS# A0-A10 U4
DQ0-DQ3 WE# OE# RAS# CAS# A0-A10 U5
DQ0-DQ3 WE# OE# RAS# CAS# A0-A10 U6
DQ0-DQ3 WE# OE# RAS# CAS# A0-A10 U7
DQ0-DQ3 WE# OE# RAS# CAS# A0-A10 U8
DQ0-DQ3 WE# OE# RAS# CAS# A0-A10 U9
11
11
11
11
11
11
11
11
11
DQ32-DQ35
DQ36-DQ39
DQ40-DQ43
DQ44-DQ47
CB4-CB7
DQ48-DQ51
DQ52-DQ55
DQ56-DQ59
DQ06-DQ63
DQ0-DQ3 WE2# OE2# RAS2# CAS4# CAS5# CAS6# CAS7# WE# OE# RAS# CAS# A0-A10 U10
DQ0-DQ3 WE# OE# RAS# CAS# A0-A10 U11
DQ0-DQ3 WE# OE# RAS# CAS# A0-A10 U12
DQ0-DQ3 WE# OE# RAS# CAS# A0-A10 U13
DQ0-DQ3 WE# OE# RAS# CAS# A0-A10 U14
DQ0-DQ3 WE# OE# RAS# CAS# A0-A10 U15
DQ0-DQ3 WE# OE# RAS# CAS# A0-A10 U16
DQ0-DQ3 WE# OE# RAS# CAS# A0-A10 U17
DQ0-DQ3 WE# OE# RAS# CAS# A0-A10 U18
11
11
11
11
11
11
11
11
11
SPD SCL A0 SA0 A1 SA1 A2 SDA
U1-U18 = MT4LC4M4B1 FAST PAGE MODE
VDD VSS
SA2
U1-U18 U1-U18
U1-U18 = MT4LC4M4E8 EDO PAGE MODE
2, 4 Meg x 72 Nonbuffered DRAM DIMMs DM60.p65 - Rev. 6/98
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PIN DESCRIPTIONS
PIN NUMBERS 30, 45 SYMBOL RAS0#, RAS2# TYPE Input DESCRIPTION Row-Address Strobe: RAS# is used to clock-in the rowaddress bits. Two RAS# inputs allow for one x72 bank or two x36 banks. Column-Address Strobe: CAS# is used to clock-in the column-address bits, enable the DRAM output buffers and strobe the data inputs on WRITE cycles. Eight CAS# inputs allow byte access control for any memory bank configuration. Write Enable: WE# is the READ/WRITE control for the DQ pins. If WE# is LOW prior to CAS# going LOW, the access is an EARLY WRITE cycle. If WE# is HIGH while CAS# is LOW, the access is a READ cycle, provided OE# is also LOW. If WE# goes LOW after CAS# goes LOW, then the cycle is a LATE WRITE cycle. A LATE WRITE cycle is generally used in conjunction with a READ cycle to form a READ-MODIFY-WRITE cycle. Output Enable: OE# is the input/output control for the DQ pins. These signals may be driven, allowing LATE WRITE cycles. Address Inputs: These inputs are multiplexed and clocked by RAS# and CAS#. Data I/O: For WRITE cycles, DQ0-DQ63 act as inputs to the addressed DRAM location. For READ access cycles, DQ0-DQ63 act as outputs for the addressed DRAM location.
28, 29, 46, 47, 112, 113, 130, 131
CAS0#-CAS7#
Input
27, 48
WE0#, WE2#
Input
31, 44
OE0#, OE2#
Input
33-38, 117-121 2-5, 7-11, 13-17, 19-20, 55-58, 60, 65-67, 69-72, 74-77, 86-89,91-95, 97-101, 103-104, 139-142, 144, 149-151, 153-156, 158-161 21-22, 52-53, 105-106, 136-137 42, 62, 111, 115, 125-126, 128, 132, 146 6, 18, 26, 40, 41, 49, 59, 73, 84, 90, 102, 110, 124, 133, 143, 157, 168 1, 12, 23, 32, 43, 54, 64, 68, 78, 85, 96, 107, 116, 127, 138, 148, 152, 162 82
A0-A10 DQ0-DQ63
Input Input/ Output
CB0-CB7 RFU VDD
Input/Output - Supply
Check Bits. Reserved for Future Use: These pins should be left unconnected. Power Supply: +3.3V 0.3V.
VSS
Supply
Ground.
SDA
Input/Output
Serial Presence-Detect Data. SDA is a bidirectional pin used to transfer addresses and data into and data out of the presence-detect portion of the module. Serial Clock for Presence-Detect. SCL is used to synchronize the presence-detect data transfer to and from the module. Presence-Detect Address Inputs. These pins are used to configure the presence-detect device.
83
SCL
Input
165-167
SA0-SA2
Input
2, 4 Meg x 72 Nonbuffered DRAM DIMMs DM60.p65 - Rev. 6/98
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SERIAL PRESENCE-DETECT MATRIX
BYTE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15-61 62 63 DESCRIPTION NUMBER OF BYTES USED BY MICRON TOTAL NUMBER OF SPD MEMORY BYTES MEMORY TYPE NUMBER OF ROW ADDRESSES NUMBER OF COLUMN ADDRESSES NUMBER OF BANKS DATA WIDTH DATA WIDTH (continued) VOLTAGE INTERFACE RAS# ACCESS TIME (tRAC) CAS# ACCESS TIME (tCAC) MODULE CONFIGURATION TYPE REFRESH RATES DRAM WIDTH (PRIMARY DRAM) ERROR CHECKING DRAM DATA WIDTH RESERVED SPD REVISION CHECKSUM FOR BYTES 0-62 ENTRY (VERSION) 128 256 FAST PAGE MODE EDO PAGE MODE 11 10 (16MB) 11 (32MB) 1 x72 NONE LVTTL 50ns (-5) 60ns (-6) 13ns (-5) 15ns (-6) ECC 15.625s/NORMAL x8 (16MB) x4 (32MB) x8 (16MB) x4 (32MB) REV. 0 16MB -5 (EDO) 16MB -6 (EDO) 16MB -6 (FPM) 32MB -5 (EDO) 32MB -6 (EDO) 32MB -6 (FPM) MICRON BIT7 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 x 0 0 0 0 0 x x x - BIT6 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 x 0 0 0 0 0 x x x - BIT5 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1 0 0 0 0 x 0 0 0 0 0 x x x - BIT4 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 x 0 0 0 0 0 x x x - BIT3 0 1 0 0 1 1 1 0 1 0 0 0 1 1 1 0 0 1 0 1 0 0 0 1 0 0 0 1 1 1 1 0 0 0 0 x 0 0 0 0 0 x x x - BIT2 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 1 0 0 0 1 1 0 1 1 1 1 0 0 0 1 x 0 0 0 1 0 x x x - BIT1 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 1 0 1 1 1 0 1 0 1 1 0 x 0 1 1 0 0 x x x - BIT0 0 0 1 0 1 0 1 1 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 1 0 x 1 0 1 0 0 x x x - HEX 80 08 01 02 0B 0A 0B 01 48 00 01 32 3C 0D 0F 02 00 08 04 08 04 00 00 3A 46 45 33 3F 3E 2C FF 01 02 03 04 xx 01 02 03 04 00 xx xx xx -
64 65-71 72
MANUFACTURER'S JEDEC ID CODE MANUFACTURER'S JEDEC CODE (CONT.) MANUFACTURING LOCATION
73-90 91
MODULE PART NUMBER (ASCII) PCB IDENTIFICATION CODE
92 93 94 95-98 99-125 NOTE:
IDENTIFICATION CODE (CONT.) YEAR OF MANUFACTURE IN BCD WEEK OF MANUFACTURE IN BCD MODULE SERIAL NUMBER MANUFACTURE SPECIFIC DATA (RSVD)
1 2 3 4 0
1. "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW." 2. x = Variable Data.
2, 4 Meg x 72 Nonbuffered DRAM DIMMs DM60.p65 - Rev. 6/98
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ABSOLUTE MAXIMUM RATINGS*
Voltage on VDD Pin Relative to VSS ................. -1V to +4.6V Voltage on Inputs or I/O Pins Relative to VSS ................................................ -1V to +4.6V Operating Temperature, TA (ambient) .......... 0C to +70C Storage Temperature (plastic) .................... -55C to +125C Power Dissipation ............................................................. 9W *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1) (VDD = +3.3V 0.3V) PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs INPUT LEAKAGE CURRENT: Any input 0V VIN VDD + 0.3V (All other pins not under test = 0V) CAS0#-CAS7# A0-A10 WE0#, WE2#, OE0#, OE2# RAS0#-RAS3# OUTPUT LEAKAGE CURRENT: DQ is disabled; 0V VOUT VDD + 0.3V OUTPUT LEVELS: Output High Voltage (IOUT = -2mA) Output Low Voltage (IOUT = 2mA) DQ0-DQ63, CB0-CB7 SYMBOL VDD VIH VIL II1 II2 II3 II4 IOZ VOH VOL SIZE ALL ALL ALL 16MB 32MB 16MB 32MB 16MB 32MB 16MB 32MB 16MB 32MB ALL ALL MIN 3 2 -0.5 -4 -6 -18 -36 -10 -18 -10 -18 -5 -5 2.4 - MAX 3.6 VDD + 0.3 0.8 4 6 18 36 10 18 10 18 5 5 - 0.4 UNITS V V V A A A 30 30 NOTES
A A V V
2, 4 Meg x 72 Nonbuffered DRAM DIMMs DM60.p65 - Rev. 6/98
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ICC OPERATING CONDITIONS AND MAXIMUM LIMITS
(Notes: 1, 5, 6) (VDD = +3.3V 0.3V) PARAMETER/CONDITION STANDBY CURRENT: TTL (RAS# = CAS# = VIH) STANDBY CURRENT: CMOS (RAS# = CAS# = VDD - 0.2V) OPERATING CURRENT: Random READ/WRITE Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) OPERATING CURRENT: FAST PAGE MODE Average power supply current (RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN]) OPERATING CURRENT: EDO PAGE MODE ("X" version only) Average power supply current (RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN]) REFRESH CURRENT: RAS#-ONLY Average power supply current (RAS# cycling, CAS# = VIH: tRC = tRC [MIN]) REFRESH CURRENT: CBR Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) * EDO version only SYMBOL ICC1 ICC2 ICC3 SIZE 16MB 32MB 16MB 32MB 16MB 32MB 16MB 32MB 16MB 32MB 16MB 32MB 16MB 32MB -5* 9 18 9 9 990 1,980 - - 990 1,980 990 1,980 990 1,980 MAX -6 9 18 9 9 900 1,800 720 1,440 900 1,800 900 1,800 900 1,800 UNITS mA mA mA 3, 24 NOTES
ICC4
mA
3, 24
ICC5 (X only) ICC6
mA
3, 24
mA
3, 24
ICC7
mA
3, 4
2, 4 Meg x 72 Nonbuffered DRAM DIMMs DM60.p65 - Rev. 6/98
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CAPACITANCE
PARAMETER Input Capacitance: A0-A10 Input Capacitance: WE0#, WE2#, OE0#, OE2# Input Capacitance: RAS0#, RAS2# Input Capacitance: CAS0#-CAS7# Input Capacitance: SCL, SA0-SA2 Input/Output Capacitance: DQ0-DQ63, CB0-CB7, SDA SYMBOL CI1 CI2 CI3 CI4 CI5 CIO
MAX 16MB 32MB 51 39 39 17 6 10 96 67 67 24 6 10
UNITS pF pF pF pF pF pF
NOTES 2 2 2 2 2 2
FAST PAGE MODE AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 12, 29) (VDD = +3.3V 0.3V)
AC CHARACTERISTICS - FAST PAGE MODE OPTION PARAMETER Access time from column address Column-address hold time (referenced to RAS#) Column-address setup time Row-address setup time Column address to WE# delay time Access time from CAS# Column-address hold time CAS# pulse width CAS# hold time (CBR Refresh) CAS# to output in Low-Z CAS# precharge time Access time from CAS# precharge CAS# to RAS# precharge time CAS# hold time CAS# setup time (CBR Refresh) CAS# to WE# delay time WRITE command to CAS# lead time Data-in hold time Data-in setup time Output disable Output enable OE# hold time from WE# during READ-MODIFY-WRITE cycle Output buffer turn-off delay OE# setup prior to RAS# during HIDDEN REFRESH cycle FAST-PAGE-MODE READ or WRITE cycle time -6 SYMBOL tAA tAR tASC tASR tAWD tCAC tCAH tCAS tCHR tCLZ tCP tCPA tCRP tCSH tCSR tCWD tCWL tDH tDS tOD tOE tOEH tOFF tORD tPC MIN 45 0 0 55 15 10 15 10 3 10 5 60 5 40 15 10 0 3 15 3 0 35 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES
23 14
4 25 15
35
4 23 22 22
15 15 15
21 19, 25, 26
2, 4 Meg x 72 Nonbuffered DRAM DIMMs DM60.p65 - Rev. 6/98
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FAST PAGE MODE AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 12, 29) (VDD = +3.3V 0.3V)
AC CHARACTERISTICS - FAST PAGE MODE OPTION PARAMETER FAST-PAGE-MODE READ-WRITE cycle time Access time from RAS# RAS# to column-address delay time Row-address hold time RAS# pulse width RAS# pulse width (FAST PAGE MODE) Random READ or WRITE cycle time RAS# to CAS# delay time READ command hold time (referenced to CAS#) READ command setup time Refresh period (2,048 cycles) RAS# precharge time RAS# to CAS# precharge time READ command hold time (referenced to RAS#) RAS# hold time READ-WRITE cycle time RAS# to WE# delay time WRITE command to RAS# lead time Transition time (rise or fall) WRITE command hold time WRITE command hold time (referenced to RAS#) WE# command setup time WRITE command pulse width WE# hold time (CBR Refresh) WE# setup time (CBR Refresh) -6 SYMBOL tPRWC tRAC tRAD tRAH tRAS tRASP tRC tRCD tRCH tRCS tREF tRP tRPC tRRH tRSH tRWC tRWD tRWL tT tWCH tWCR tWCS tWP tWRH tWRP MIN 85 15 10 60 60 110 20 0 0 40 0 0 15 155 85 15 2 10 45 0 10 10 10 MAX 60 UNITS ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 13 17
10,000 125,000
16 18
32
18
23
50
23
2, 4 Meg x 72 Nonbuffered DRAM DIMMs DM60.p65 - Rev. 6/98
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EDO PAGE MODE AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 12, 29) (VDD = +3.3V 0.3V)
AC CHARACTERISTICS - EDO PAGE MODE OPTION PARAMETER Access time from column address Column-address setup to CAS# precharge Column-address hold time (referenced to RAS#) Column-address setup time Row-address setup time Column-address to WE# delay time Access time from CAS# Column-address hold time CAS# pulse width CAS# hold time (CBR Refresh) CAS# to output in Low-Z Data output hold after CAS# LOW CAS# precharge time Access time from CAS# precharge CAS# to RAS# precharge time CAS# hold time CAS# setup time (CBR Refresh) CAS# to WE# delay time WRITE command to CAS# lead time Data-in hold time Data-in setup time Output disable Output enable OE# hold time from WE# during READ-MODIFY-WRITE cycle OE# HIGH hold time from CAS# HIGH OE# HIGH pulse width OE# LOW to CAS# HIGH setup time Output buffer turn-off delay OE# setup prior to RAS# during HIDDEN REFRESH cycle EDO-PAGE-MODE READ or WRITE cycle time EDO-PAGE-MODE READ-WRITE cycle time Access time from RAS# RAS# to column-address delay time Row-address hold time RAS# pulse width RAS# pulse width (EDO PAGE MODE) Random READ or WRITE cycle time RAS# to CAS# delay time READ command hold time (referenced to CAS#) READ command setup time Refresh period (2,048 cycles) RAS# precharge time -5 SYMBOL tAA tACH tAR tASC tASR tAWD tCAC tCAH tCAS tCHR tCLZ tCOH tCP tCPA tCRP tCSH tCSR tCWD tCWL tDH tDS tOD tOE tOEH
tOEHC tOEP tOES tOFF tORD tPC tPRWC tRAC tRAD tRAH tRAS tRASP tRC tRCD tRCH tRCS tREF tRP
-6 MAX 25 MIN 15 45 0 0 49 13 15 10 10 10 0 3 10 5 45 5 35 10 10 0 0 10/12* 10 5 5 0 0 25 56 50 60 12 10 60 60 104 14 0 0 40 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns NOTES
MIN 12 38 0 0 42 8 8 8 0 3 8 5 38 5 28 8 8 0 0 8 5 5 4 0 0 20 47 9 9 50 50 84 11 0 0 30
23 14
10,000
4
15
28
35
4 23 22 22
12 12
15 15
21 21
12
15
19, 26
13 17
10,000 125,000
10,000 125,000
16 18
32
32
2, 4 Meg x 72 Nonbuffered DRAM DIMMs DM60.p65 - Rev. 6/98
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EDO PAGE MODE AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 12, 29) (VDD = +3.3V 0.3V)
AC CHARACTERISTICS - EDO PAGE MODE OPTION PARAMETER RAS# to CAS# precharge time READ command hold time (referenced to RAS#) RAS# hold time READ WRITE cycle time RAS# to WE# delay time WRITE command to RAS# lead time Transition time (rise or fall) WRITE command hold time WRITE command hold time (referenced to RAS#) WE# command setup time Output disable delay from WE# (CAS# HIGH) WRITE command pulse width WE# pulse to disable at CAS# HIGH WE# hold time (CBR Refresh) WE# setup time (CBR Refresh) -5 SYMBOL tRPC tRRH tRSH tRWC tRWD tRWL tT tWCH tWCR tWCS tWHZ tWP tWPZ tWRH tWRP MIN 5 0 13 116 67 13 2 8 38 0 0 5 10 8 8 MAX MIN 5 0 15 140 79 15 2 10 45 0 0 5 10 10 10 -6 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 18
23
50
50
23
12
15
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SERIAL PRESENCE-DETECT EEPROM OPERATING CONDITIONS
(Notes: 1) (VDD = +3.3V 0.3V) PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE: IOUT = 3mA INPUT LEAKAGE CURRENT: VIN = GND to VDD OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = GND or 3.3V +10% POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz SYMBOL VDD VIH VIL VOL ILI ILO ISB ICC MIN 3 -1 - - - - - MAX 3.6 VDD x 0.3 0.4 10 10 30 2 UNITS V V V V A A A mA NOTES
VDD x 0.7 VDD + 0.5
SERIAL PRESENCE-DETECT EEPROM AC ELECTRICAL CHARACTERISTICS
(Notes: 1) (VDD = +3.3V 0.3V)
PARAMETER/CONDITION SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time SYMBOL tAA tBUF tDH tF tHD:DAT tHD:STA tHIGH tI tLOW tR tSCL tSU:DAT tSU:STA tSU:STO tWR MIN 0.3 4.7 300 0 4 4 100 4.7 1 100 250 4.7 4.7 10 MAX 3.5 UNITS s s ns ns s s s ns s s KHz ns s s ms NOTES
300
28
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NOTES
1. All voltages referenced to VSS. 2. This parameter is sampled. VDD = +3.3V; f = 1 MHz. 3. ICC is dependent on output loading. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 6. An initial pause of 100s is required after power-up, followed by eight RAS# REFRESH cycles (RAS#ONLY or CBR with WE# HIGH), before proper device operation is ensured. The eight RAS# cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 5ns for FPM and 2.5ns for EDO. 8. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL (or between VIL and VIH). 9. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 10. If CAS# = V IH, data output is High-Z. 11. If CAS# = VIL, data output may contain data from the last valid READ cycle. 12. Measured with a load equivalent to two TTL gates and 100pF and VOL = 0.8V and VOH = 2V. 13. Requires that tAA and tRAC are not violated. 14. Requires that tAA and tCAC are not violated. 15. If CAS# is LOW at the falling edge of RAS#, Q will be maintained from the previous cycle. To initiate a new cycle and clear the data-out buffer, CAS# must be pulsed HIGH for tCP. 16. The tRCD (MAX) limit is no longer specified. tRCD (MAX) was specified as a reference point only. If tRCD was greater than the specified tRCD (MAX) limit, then access time was controlled exclusively by tCAC (tRAC [MIN] no longer applied). With or without the tRCD (MAX) limit, tAA and tCAC must always be met. 17. The tRAD (MAX) limit is no longer specified. tRAD (MAX) was specified as a reference point only. If tRAD was greater than the specified tRAD (MAX) limit, then access time was controlled exclusively by and tCAC no longer applied). With or without the tRAD (MAX) limit, tAA, tRAC and tCAC must always be met. 18. Either tRCH or tRRH must be satisfied for a READ cycle. 19. tOFF (MAX) defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 20. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# = LOW and OE# = HIGH. 21. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE# HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The DQs will provide the previously read data if CAS# remains LOW and OE# is taken back LOW after tOEH is met. If CAS# goes HIGH prior to OE# going back LOW, the DQs will remain open. 22. These parameters are referenced to CAS# leading edge in EARLY WRITE cycles and WE# leading edge in LATE WRITE or READ-MODIFY-WRITE cycles. 23. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters. tWCS applies to EARLY WRITE cycles. tRWD, tAWD and tCWD apply to READ-MODIFY-WRITE cycles. If tWCS tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If tWCS < tWSC (MIN) and tRWD tRWD (MIN), tAWD tAWD (MIN) and tCWD tCWD (MIN), the cycle is a READ-MODIFY-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of data-out is indeterminate. OE# held HIGH and WE# taken LOW after CAS# goes LOW result in a LATE WRITE (OE#-controlled) cycle. tWCS, tRWD, tCWD and tAWD are not applicable in a LATE WRITE cycle. 24. Column address changed once each cycle. 25. The 3ns minimum parameter guaranteed by design. 26. With the FPM option, tOFF is determined by the first RAS# or CAS# signal to transition HIGH. In comparison, tOFF on an EDO option is determined by the latter of the RAS# and CAS# signals to transition HIGH. 27. Applies to both FPM and EDO modules.
tAA (tRAC
2, 4 Meg x 72 Nonbuffered DRAM DIMMs DM60.p65 - Rev. 6/98
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NOTES (continued)
28. The SPD EEPROM WRITE cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit are disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. 29. If OE# is tied permanently LOW, LATE WRITE or READ-MODIFY-WRITE operations are not possible. 30. VIH overshoot: VIH (MAX) = VDD + 2V for a pulse width 10ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width 10ns, and the pulse width cannot be greater than one third of the cycle rate.
2, 4 Meg x 72 Nonbuffered DRAM DIMMs DM60.p65 - Rev. 6/98
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READ CYCLE 27
tRC tRAS V IH V IL tCSH tRSH tCRP CAS# V IH V IL tRCD tCAS tRRH tRP
RAS#
ADDR
WE#
DQ
OE#
FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS
-5* SYMBOL tAA tACH (EDO) tAR
tASC tASR tCAC tCAH tCAS tCAS tCLZ tCRP tCSH tCSH tOD tOD tOE
, ,,, ,,,,, , ,, ,, , , ,, , ,, , , ,, ,,,,,,,,,,,,,,,,,, , ,, ,, , ,
tAR tRAD tRAH tASR tASC tCAH tACH V IH V IL ROW COLUMN ROW tRCS tRCH V IH V IL tAA tRAC tCAC tCLZ NOTE 1 tOFF V OH V OL OPEN VALID DATA OPEN t OE t OD V IH V IL
DON'T CARE UNDEFINED
-6 MAX 25 MIN 15 45 0 0 13 15 10 10 15 0 3 5 45 12 - 12 60 0 3 15 15 15 10,000 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOFF (EDO) tOFF (FPM) tRAC
tRAD tRAD tRAH tRAS tRC tRC
-5* MIN 0 - 9 - 9 50 84 - 11 - 0 0 30 0 13 10,000 MAX 12 - 50 MIN 0 3 12 15 10 60 104 110 14 20 0 0 40 0 15
-6 MAX 15 15 60 UNITS ns ns ns ns ns 10,000 ns ns ns ns ns ns ns ns ns ns ns
MIN 12 38 0 0 8 8 - 0 - 5 38 - 0 -
(EDO) (FPM)
(EDO)
10,000 -
(EDO)
(FPM) tCLZ (EDO) (FPM) (EDO)
(FPM) tRCD (EDO)
tRCD tRCH tRCS tRP tRRH tRSH
(FPM)
(FPM) (EDO) (FPM)
*EDO version only NOTE: 1. For EDO, tOFF is referenced from rising edge of RAS# or CAS#, whichever occurs last. For FPM, tOFF is referenced from rising edge of RAS# or CAS#, whichever occurs first.
2, 4 Meg x 72 Nonbuffered DRAM DIMMs DM60.p65 - Rev. 6/98 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1998, Micron Technology, Inc.
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2, 4 MEG x 72 NONBUFFERED DRAM DIMMs
EARLY WRITE CYCLE 27
tRC tRAS V IH V IL tCSH tRSH tCAS tRP
RAS#
, ,,, ,,,,, ,, , ,, , ,,,,, ,,,, ,,,, ,,, , ,,,, , , , ,,,, , ,, , ,, , , ,, , , , ,, ,, ,,
tCRP tRCD CAS# V IH V IL tAR tRAD tRAH tASC tCAH tASR tACH ADDR V IH V IL ROW COLUMN ROW tCWL tRWL tWCR tWCH tWP tWCS WE# V IH V IL tDS tDH V DQ V IOH IOL V IH V IL VALID DATA OE#
FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS
-5* SYMBOL tACH (EDO)
tAR tASC tASR tCAH tCAS tCAS tCRP tCSH tCSH
,,
-6 MIN 12 10 60 110 104 20 14 40 15 15 10 45 0 10 5
DON'T CARE UNDEFINED
-6 MAX MIN 15 45 0 0 10 15 10 5 60 45 15 10 10 0 15 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tRAD (EDO)
tRAH tRAS tRC tRC
-5* MIN 9 9 50 - 84 - 11 30 13 13 8 38 0 - 5 MAX
MIN 12 38 0 0 8 - 8 5 - 38 - 8 8 0 -
MAX
UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
10,000
10,000
(FPM) (EDO)
- 10,000
10,000 10,000
(FPM) (EDO) tRCD (FPM)
tRCD tRP tRSH tRWL tWCH tWCR tWCS tWP tWP
(EDO)
(FPM) (EDO) tCWL (FPM)
tCWL tDH tDS tRAD
(EDO)
(FPM)
(FPM) (EDO)
*EDO version only
2, 4 Meg x 72 Nonbuffered DRAM DIMMs DM60.p65 - Rev. 6/98
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FAST-PAGE-MODE READ CYCLE
tRASP V IH V IL tCSH tCRP tRCD tCAS tPC tCP tCAS tCP tRSH tCAS tCP tRP
RAS#
CAS#
ADDR
WE#
DQ
OE#
, , ,,, ,,, ,,,,, ,, ,, , , , ,, , , ,, , , , , , ,,,,, ,, ,,,, ,, ,, ,, ,, , ,, , ,, ,,,,, ,
V IH V IL tAR tRAD tRAH tASR tASC tCAH tASC tCAH tASC tCAH V IH V IL ROW COLUMN COLUMN COLUMN ROW tRCS tRCS tRCS tRCH tRCH tRCH tRRH V IH V IL tAA tAA tAA tRAC tCAC tCPA tCPA tOFF tCAC tOFF tCAC tOFF tCLZ tCLZ tCLZ V IOH V IOL OPEN tOE VALID DATA tOD tOE VALID DATA tOD tOE VALID DATA tOD OPEN V IH V IL
,
-6
DON'T CARE UNDEFINED
FAST PAGE MODE TIMING PARAMETERS
-6 SYMBOL tAA
tAR tASC tASR tCAC tCAH tCAS tCLZ tCP tCPA tCRP tCSH tOD
MIN 45 0 0
MAX 30
UNITS ns ns ns ns ns ns ns ns ns ns ns ns
SYMBOL
tOE tOFF tPC tRAC tRAD tRAH tRASP tRCD tRCH tRCS tRP tRRH tRSH
MIN 3 35 15 10 60 20 0 0 40 0 15
MAX 15 15 60
UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns
15 10 15 3 10 35 5 60 3 15 10,000
125,000
ns
2, 4 Meg x 72 Nonbuffered DRAM DIMMs DM60.p65 - Rev. 6/98
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EDO-PAGE-MODE READ CYCLE
tRASP V IH V IL tCSH tCRP tRCD tCAS tPC tCP tCAS tCP tRSH tCAS tCP tRP
RAS#
CAS#
ADDR
WE#
DQ
OE#
,, ,,, ,,, ,,, ,,,,, ,, ,, ,, ,, ,, , , ,, , ,, ,,,,, , ,,,, , , ,, , ,, , ,
V IH V IL tAR tRAD tRAH tASR tACH tASC tACH tACH tASC tCAH tASC tCAH tCAH V IH V IL ROW COLUMN COLUMN COLUMN ROW tRCS tRCH V IH V IL tAA tRRH tAA tAA tCPA tRAC tCAC tCPA tCAC tCAC tCLZ tCLZ tCOH tOEHC tOFF V OH V OL OPEN VALID DATA VALID DATA VALID DATA OPEN tOE tOD tOE tOD V IH V IL tOES tOES tOEP
DON'T CARE UNDEFINED
EDO PAGE MODE TIMING PARAMETERS
-5 SYMBOL tAA
tACH tAR tASC tASR tCAC tCAH tCAS tCLZ tCOH tCP tCPA tCRP tCSH tOD tOE
-6 MAX 25 MIN 15 45 0 0 13 15 10 10 0 3 10 28 35 5 12 12 45 0 15 15 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOEHC
tOEP tOES tOFF tPC tRAC tRAD tRAH tRASP tRCD tRCH tRCS tRP tRRH tRSH
-5 MIN 5 5 4 0 20 9 9 50 11 0 0 30 0 13 125,000 12 50 12 10 60 14 0 0 40 0 15 MAX MIN 10 5 5 0 25
-6 MAX UNITS ns ns ns 15 60 ns ns ns ns ns 125,000 ns ns ns ns ns ns ns
MIN 12 38 0 0 8 8 0 3 8 5 38 0
10,000
2, 4 Meg x 72 Nonbuffered DRAM DIMMs DM60.p65 - Rev. 6/98
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FAST/EDO-PAGE-MODE EARLY WRITE CYCLE 27
tRASP V IH V IL tCSH tPC tCP tRSH tCAS tCRP tRCD tCAS tCAS tCP tCP tRP
RAS#
CAS#
ADDR
WE#
V DQ V IOH IOL V IH V IL
OE#
,, , , , , , ,,,,, , , , , , ,,,, ,,, ,, ,,,,, ,,, , , ,, , , ,, , ,,,,,,,,,,,,,,,,,,,, ,, ,
V IH V IL tAR tRAD tACH tACH tACH tASR tRAH tASC tCAH tASC tCAH tASC tCAH V IH V IL ROW COLUMN COLUMN COLUMN ROW tCWL tWP tCWL tWP tCWL tWP tWCS tWCH tWCS tWCH tWCS tWCH V IH V IL tWCR tDH tDS tDS tDH tDS tRWL tDH VALID DATA VALID DATA VALID DATA
FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS
-5* SYMBOL
tACH tAR tASC tASR tCAH tCAS tCAS tCP tCRP tCSH tCSH tCWL tCWL tDH tDS tPC
,
-6
DON'T CARE UNDEFINED
-6 MAX MIN 15 45 0 0 10,000 - 10 10 15 10 5 45 60 10 15 10 0 25 10,000 10,000 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tPC (FPM) tRAD (EDO)
tRAD tRAH tRASP tRCD tRP tRSH tRWL tWCH tWCR tWCS tWP tWP
-5* MIN - 9 - 9 50 11 - 30 13 13 8 38 0 5 - 125,000 MAX MIN 35 12 15 10 60 14 20 40 15 15 10 45 0 5 10
MIN 12 38 0 0
MAX
(EDO)
UNITS ns ns ns ns
(FPM)
(EDO) (FPM)
8 8 - 8 5 38 - 8 - 8 0 20
125,000
(EDO) tRCD (FPM)
ns ns ns ns ns ns ns ns ns ns ns
(EDO) (FPM) (EDO) (FPM)
(EDO) (FPM)
(EDO)
*EDO version only
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READ-WRITE CYCLE 27 (LATE WRITE and READ-MODIFY-WRITE cycles)
tRWC tRAS V IH V IL tCSH tRSH tCAS tRP
RAS#
FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS
-5* SYMBOL tAA tACH (EDO) tAR tASC tASR
tAWD tAWD tCAC tCAH tCAS tCAS tCLZ tCLZ tCRP tCSH tCSH tCWD tCWD tCWL tDH tDS
,, ,,, ,,,, ,, ,, , , , , , ,, , ,,, , ,, , ,, , ,,,,, ,,,, ,,,,, , ,, , , ,, , , , ,
tCRP tRCD CAS# V IH V IL tAR tRAD tASC tCAH tASR tRAH tACH ADDR V IH V IL ROW COLUMN ROW tRWD tCWL tRWL tWP tRCS tCWD tAWD WE# V IH V IL tAA tRAC tCAC t CLZ tDS tDH V DQ V IOH IOL OPEN VALID D OUT tOD VALID D IN OPEN tOE tOEH OE# V IH V IL
DON'T CARE UNDEFINED
-6 MAX 25 MIN 15 45 0 0 49 55 13 15 10 10,000 - 10 15 0 3 5 45 60 35 40 10 15 10 0 10,000 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOD (EDO) tOD (FPM) tOE tOEH (EDO) tOEH (FPM)
tRAC tRAD
-5* MIN 0 - 8 - 50 9 - 9 50 11 - 0 30 13 116 - 67 - 13 5 - 10,000 12 15 10 60 14 20 0 40 15 140 155 79 85 15 5 10 MAX 12 - 12 MIN 0 3 10/12** 15
-6 MAX 15 15 15 UNITS ns ns ns ns ns ns ns ns ns 10,000 ns ns ns ns ns ns ns ns ns ns ns ns ns
MIN 12 38 0 0 42 - 8
(EDO) (FPM)
60
(EDO) tRAD (FPM) tRAH
tRAS tRCD tRCD tRCS tRP tRSH tRWC tRWC tRWD tRWL tWP tWP
(EDO) (FPM) (EDO) (FPM) (EDO) (FPM)
8 - 0 - 5 38 - 28 - 8 - 8 0
(EDO) (FPM)
(EDO)
(EDO) (FPM) tCWL (EDO) (FPM)
(FPM) (EDO) tRWD (FPM) (EDO) (FPM)
* EDO version only **16MB DIMM
2, 4 Meg x 72 Nonbuffered DRAM DIMMs DM60.p65 - Rev. 6/98
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FAST/EDO-PAGE-MODE READ-WRITE CYCLE 27 (LATE WRITE and READ-MODIFY-WRITE cycles)
tRASP V IH V IL tCSH t PC tPRWC NOTE 1 tRSH tCAS tCRP tRCD tCAS tCP tCAS tCP tCP tRP RAS#
CAS#
ADDR
FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS
-5* -6
,, ,,,,,,,, , , ,, , , ,,,, ,,,, ,, ,, ,, , , ,,,,,,, ,, , , ,, ,, , , ,,, ,
V IH V IL tAR tRAD tRAH tASR tASC tCAH tASC tCAH tASC tCAH V IH V IL ROW COLUMN COLUMN COLUMN ROW tRWD tRCS tRWL tCWL tCWL tWP tAWD tCWD tWP tAWD tCWD tAWD tCWL tWP tCWD WE# V IH V IL tAA tAA tAA tRAC tDH tDS tCPA tDH tDS tCPA tDH tDS tCAC tCLZ tCAC tCLZ tCAC tCLZ DQ V IOH V IOL OPEN
VALID D OUT VALID D IN VALID D OUT VALID D IN VALID D OUT VALID D IN
OPEN
tOD
tOD
tOD
tOE
tOE
tOE
tOEH
OE#
V IH V IL
DON'T CARE UNDEFINED
-5*
-6
SYMBOL tAA tAR tASC tASR tAWD (EDO) tAWD (FPM) tCAC tCAH
tCAS tCAS tCLZ tCLZ tCP tCPA tCRP tCSH
MIN 38 0 0 42 -
MAX 25
MIN 45 0 0 49 55
MAX 30
13 8 8 - 0 - 8 28 5 38 - 28 - 8 - 8 0 0 12 5 45 60 35 40 10 15 10 0 0 10,000 - 10 10 15 0 3 10
15 10,000 10,000
UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns
SYMBOL
tOD tOE tOEH tOEH
MIN - 8 - 20 - 47 -
MAX - 12
MIN 3 10/12** 15 25 35 56 85
MAX 15 15
UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
(FPM)
(EDO) (FPM) tPC (EDO) tPC (FPM) tPRWC (EDO) tPRWC (FPM)
tRAC tRAD tRAD tRAH tRASP tRCD tRCS tRP tRSH tRWD tRWD tRWL tWP tWP
(EDO) (FPM) (EDO) (FPM)
50 (EDO) (FPM) 9 - 9 50 11 - 0 30 13 (EDO) (FPM) 67 - 13 5 - 12 15 10 60 14 20 0 40 15 79 85 15 5 10
60
125,000
125,000
35
ns ns ns ns ns ns ns ns ns
(EDO) tRCD (FPM)
(EDO) (FPM) tCWD (EDO)
tCSH tCWD tCWL tDH tDS tOD
(FPM) tCWL (EDO) (FPM)
(EDO) (FPM)
(EDO)
15
ns ns
NOTE: 1. tPC is for LATE WRITE cycles only.
* EDO version only **16MB DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1998, Micron Technology, Inc.
2, 4 Meg x 72 Nonbuffered DRAM DIMMs DM60.p65 - Rev. 6/98
23
OBSOLETE
2, 4 MEG x 72 NONBUFFERED DRAM DIMMs
EDO-PAGE-MODE READ EARLY WRITE CYCLE (Pseudo READ-MODIFY-WRITE)
t RASP RAS# V IH V IL t CSH t PC t CRP t RCD t CAS t CP t CAS t PC t CP t CAS t RSH t CP t RP
CAS#
ADDR
WE#
DQ V IOH V IOL
OE#
,, ,, ,,, ,,,, ,,, , ,,,,, ,, ,, ,, , ,, ,, ,
V IH V IL t AR t RAD t ACH t CAH tASR t RAH t ASC t CAH t ASC t CAH t ASC V IH V IL ROW COLUMN (A) COLUMN (B) COLUMN (N) t RCS t RCH t WCS t WCH V IH V IL t AA t AA t RAC t CPA t CAC t CAC t DS t DH t COH t WHZ OPEN VALID DATA (A) VALID DATA (B) VALID DATA IN t OE V IH V IL
ROW
DON'T CARE UNDEFINED
EDO PAGE MODE TIMING PARAMETERS
-5 SYMBOL
tAA tACH tAR tASC tASR tCAC tCAH tCAS tCOH tCP tCPA tCRP tCSH tDH tDS
-6 MAX 25 MIN 15 45 0 0 13 15 10 10,000 10 3 10 5 45 10 0 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL
tOE tPC tRAC tRAD tRAH tRASP tRCD tRCH tRCS tRP tRSH tWCH tWCS tWHZ
-5 MIN 20 50 9 9 50 11 0 0 30 13 8 0 0 12 125,000 12 10 60 14 0 0 40 15 10 0 0 MAX 12 25 MIN
-6 MAX 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns 15 ns ns
MIN 12 38 0 0 8 8 3 8 5 38 8 0
125,000
28
35
2, 4 Meg x 72 Nonbuffered DRAM DIMMs DM60.p65 - Rev. 6/98
24
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72 NONBUFFERED DRAM DIMMs
FAST-PAGE-MODE READ EARLY WRITE CYCLE (Pseudo READ-MODIFY-WRITE)
tRASP V IH V IL tRSH tCSH tCRP CAS# V IH V IL tRCD tCAS tCP tPC tCAS tCP tRP
RAS#
ADDR
WE#
DQ
OE#
,, ,, ,, ,,, ,, ,, ,,
tRAD tASR tRAH V IH V IL ROW V IH V IL V OH V OL OPEN V IH V IL
tAR
tASC
COLUMN
tRCS
tAA t RAC
FAST PAGE MODE TIMING PARAMETERS
-6 SYMBOL tAA
tAR tASC tASR tCAC tCAH tCAS tCLZ tCP tCRP tCSH tCWL tDH tDS
,, ,,,, , , ,, ,,,, , , , , , ,
tCAH tASC tCAH COLUMN ROW tCWL tRWL tWP tWCH tWCS tCAC t CLZ NOTE 1 t OFF tDS tDH VALID DATA VALID DATA
DON'T CARE UNDEFINED
-6 MAX 30 UNITS ns ns ns ns 15 ns ns ns ns ns ns ns ns ns ns SYMBOL tOFF
tPC tRAC tRAD tRAH tRASP tRCD tRCS tRP tRSH tRWL tWCH tWCS tWP
MIN 45 0 0 10 15 3 10 5 60 15 10 0
MIN 3 35
MAX 15 60
UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns
15 10 60 20 0 40 15 15 10 0 10 125,000
10,000
NOTE: 1. Do not drive data prior to tristate.
2, 4 Meg x 72 Nonbuffered DRAM DIMMs DM60.p65 - Rev. 6/98
25
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72 NONBUFFERED DRAM DIMMs
EDO READ CYCLE (with WE#-controlled disable)
RAS# V IH V IL tCSH
CAS#
ADDR
WE#
DQ
OE#
, ,,,, ,,,,, ,,, , , ,, , ,,,,,,,,,,,,,,,,, ,, , ,, ,, ,
tCRP tRCD tCAS tCP V IH V IL tAR tRAD tRAH tASR tASC tCAH tASC V IH V IL ROW COLUMN COLUMN tRCS tRCH tWPZ tRCS V IH V IL tAA tRAC tCAC tCLZ tWHZ tCLZ V OH V OL OPEN VALID DATA t OD OPEN t OE V IH V IL
DON'T CARE UNDEFINED
EDO PAGE MODE TIMING PARAMETERS
-5 SYMBOL
tAA tAR tASC tASR tCAC tCAH tCAS tCLZ tCP tCRP tCSH
-6 MAX 25 MIN 45 0 0 13 15 10 10 0 10 5 45 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns SYMBOL
tOD tOE tRAC tRAD tRAH tRCD tRCH tRCS tWHZ tWPZ
-5 MIN 0 MAX 12 12 50 9 9 11 0 0 0 10 12 12 10 14 0 0 0 10 MIN 0
-6 MAX 15 15 60 UNITS ns ns ns ns ns ns ns 15 ns ns ns
MIN 38 0 0 8 8 0 8 5 38
10,000
2, 4 Meg x 72 Nonbuffered DRAM DIMMs DM60.p65 - Rev. 6/98
26
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72 NONBUFFERED DRAM DIMMs
RAS#-ONLY REFRESH CYCLE 27
tRC tRAS V IH V IL tRP
RAS#
CAS#
ADDR
V DQ V OH OL
WE#
, ,,,,,,,,, ,,, , , ,,,,,,,,,,,,,,,,,, , ,, ,
tCRP tRPC V IH V IL tASR tRAH V IH V IL ROW ROW OPEN V IH V IL
CBR REFRESH CYCLE 27 (Addresses, OE# = DON'T CARE)
tRAS NOTE 1 tRP
tRP RAS# V IH V IL tRPC
tRAS
CAS#
DQ
WE#
,,,,,,,,,,,,,,,,, ,, ,, ,, ,
tCP tCSR tCHR tRPC tCSR tCHR V IH V IL V OH V OL OPEN tWRP tWRH tWRP tWRH V IH V IL
FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS
-5* SYMBOL tASR
tCHR tCP tCRP tCSR tRAH tRAS
,
DON'T CARE UNDEFINED
-6 MAX MIN 0 10 10 5 5 10 10,000 60 10,000 MAX UNITS ns ns ns ns ns ns ns SYMBOL tRC (FPM)
tRC tRP tRPC tRPC
-5* MIN - 84 30 - 5 8 8 MAX MIN 110 104 40 0 5 10 10
-6 MAX UNITS ns ns ns ns ns ns ns
MIN 0 8 8 5 5 9 50
(EDO)
(FPM) (EDO) tWRH
tWRP
*EDO version only
2, 4 Meg x 72 Nonbuffered DRAM DIMMs DM60.p65 - Rev. 6/98
27
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72 NONBUFFERED DRAM DIMMs
HIDDEN REFRESH CYCLE 20, 27 (WE# = HIGH; OE# = LOW)
tRC tRAS V IH V IL tRP tRAS
RAS#
CAS#
ADDR
OE#
,, ,, ,,,,,, ,,,, ,, ,, , , , , ,, ,, ,,,,,,,, ,, ,, ,, ,, ,,
tCRP tRCD tRSH tCHR V IH V IL tAR tRAD tASR tRAH tASC tCAH V IH V IL ROW COLUMN tAA tRAC tCAC tCLZ tOFF V DQ V IOH IOL OPEN VALID DATA OPEN tOE tOD V IH V IL tORD
DON'T CARE UNDEFINED
FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS
-5* SYMBOL tAA tAR
tASC tASR tCAC tCAH tCHR tCLZ
-6 MAX 25 MIN 45 0 0 13 15 10 10 3 0 - 12 12 - 5 3 0 3 15 15 15 15 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOFF (EDO) tORD
tRAC tRAD tRAD tRAH tRAS tRC
-5* MIN 0 0 - 9 9 50 - 84 - 11 30 13 MAX 12 50 (FPM) (EDO) 15 12 10 60 110 104 20 14 40 15 MIN 0 0
-6 MAX 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns
MIN 38 0 0 8 8 - 0 5 - 0 -
10,000
10,000
(FPM) tCLZ (EDO)
tCRP tOD tOE tOFF
(FPM) tRC (EDO)
tRCD tRCD tRP tRSH
(FPM) tOD (EDO) (FPM)
(FPM) (EDO)
*EDO version only
2, 4 Meg x 72 Nonbuffered DRAM DIMMs DM60.p65 - Rev. 6/98
28
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72 NONBUFFERED DRAM DIMMs
SPD EEPROM
tF tLOW
tHIGH
tR
SCL
t SU:STA t HD:STA t HD:DAT t SU:DAT t SU:STO
SDA IN
SDA OUT
,,,,,,
tAA
tDH
tBUF
,
SYMBOL tHIGH tLOW tR tSU:DAT tSU:STA tSU:STO MIN 4 4.7 250 4.7 4.7
UNDEFINED
SERIAL PRESENCE-DETECT EEPROM TIMING PARAMETERS
SYMBOL tAA tBUF tDH tF tHD:DAT tHD:STA MIN 0.3 4.7 300 0 4 MAX 3.5 UNITS s s ns ns s s MAX UNITS s s s ns s s
1
300
2, 4 Meg x 72 Nonbuffered DRAM DIMMs DM60.p65 - Rev. 6/98
29
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72 NONBUFFERED DRAM DIMMs
168-PIN DIMM DF-12 (16MB)
FRONT VIEW
5.256 (133.50) 5.244 (133.20) .200 (5.08) MAX
.079 (2.00) R (2X) 1.005 (25.53) .995 (25.27) .118 (3.00) (2X) .118 (3.00) TYP .250 (6.35) TYP .118 (3.00) TYP 1.661 (42.18) 2.625 (66.68) .039 (1.00) R(2X) .039 (1.00) TYP .050 (1.27) TYP .128 (3.25) (2X) .118 (3.00) .054 (1.37) .046 (1.17) .700 (17.78) TYP
PIN 1 (PIN 85 on backside)
4.550 (115.57)
PIN 84 (PIN 168 ON BACKSIDE)
168-PIN DIMM DF-13 (32MB)
FRONT VIEW
5.256 (133.50) 5.244 (133.20) .350 (8.89) MAX
.079 (2.00) R (2X) 1.005 (25.53) .995 (25.27) .118 (3.00) (2X) .118 (3.00) TYP .054 (1.37) .046 (1.17) .039 (1.00) R(2X) .039 (1.00) TYP .050 (1.27) TYP .700 (17.78) TYP
.250 (6.35) TYP .118 (3.00) TYP
PIN 1
4.550 (115.57)
PIN 84
BACK VIEW
.128 (3.25) (2X) .118 (3.00) 1.661 (42.18)
PIN 168
2.625 (66.68)
PIN 85
NOTE:
1. All dimensions in inches (millimeters)
MAX or typical where noted. MIN
2, 4 Meg x 72 Nonbuffered DRAM DIMMs DM60.p65 - Rev. 6/98
30
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1998, Micron Technology, Inc.

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