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PCK9447
3.3 V/2.5 V 1 : 9 LVCMOS clock fan-out buffer
Rev. 01 -- 13 October 2005 Product data sheet
1. General description
The PCK9447 is a 3.3 V or 2.5 V compatible, 1 : 9 clock fan-out buffer targeted for high performance clock tree applications. With output frequencies up to 350 MHz, and output skews less than 150 ps, the device meets the needs of most demanding clock applications. The PCK9447 is specifically designed to distribute LVCMOS compatible clock signals up to a frequency of 350 MHz. Each output provides a precise copy of the input signal with near zero skew. The output buffers support driving of 50 terminated transmission lines on the incident edge: each is capable of driving either one parallel terminated or two series terminated transmission lines. Two selectable independent LVCMOS compatible clock inputs are available, providing support of redundant clock source systems. The PCK9447 CLK_STOP control is synchronous to the falling edge of the input clock. It allows the start and stop of the output clock signal only in a logic LOW state, thus eliminating potential output runt pulses. Applying the OE control will force the outputs into high-impedance mode. All inputs have an internal pull-up or pull-down resistor preventing unused and open inputs from floating. The device supports a 2.5 V or 3.3 V power supply and an ambient temperature range of -40 C to +85 C. The PCK9447 is pin and function compatible but performance-enhanced to the PCK947.
2. Features
s s s s s s s s s s s 9 LVCMOS compatible clock outputs 2 selectable, LVCMOS compatible inputs Maximum clock frequency of 350 MHz Maximum clock skew of 150 ps Synchronous output stop in logic LOW state eliminates output runt pulses High-impedance output control 3.3 V or 2.5 V power supply Drives up to 18 series terminated clock lines Tamb = -40 C to +85 C Available in LQFP32 package Supports clock distribution in networking, telecommunications and computer applications s Pin and function compatible to PCK947
Philips Semiconductors
PCK9447
3.3 V/2.5 V 1 : 9 LVCMOS clock fan-out buffer
3. Ordering information
Table 1: Ordering information Package Name PCK9447BD LQFP32 Description plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm Version SOT358-1 Type number
4. Functional diagram
PCK9447
VCC
25 k 60 k
CCLK0
Q0 0 CLK STOP Q1 Q2
CCLK1 VCC
25 k
1
Q3 Q4 Q5 SYNC Q6 Q7
CLK_SEL VCC
25 k
CLK_STOP
VCC
25 k
Q8
OE
002aaa716
Fig 1. Functional diagram of PCK9447
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Product data sheet
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PCK9447
3.3 V/2.5 V 1 : 9 LVCMOS clock fan-out buffer
5. Pinning information
5.1 Pinning
29 GND 25 GND 24 GND 23 Q3 22 VCC 21 Q4 20 GND 19 Q5 18 VCC 17 GND VCC 10 Q8 11 GND 12 Q7 13 VCC 14 Q6 15 GND 16 9
002aaa715
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
32 GND
31 VCC 30 Q0
GND CLK_SEL CCLK0 CCLK1 CLK_STOP OE VCC GND
1 2 3 4 5 6 7 8
PCK9447BD
Fig 2. Pin configuration for LQFP32
5.2 Pin description
Table 2: Symbol CCLK0 CCLK1 CLK_SEL CLK_STOP OE Q0 to Q8 Pin description Pin 3 4 2 5 6 30, 28, 26, 23, 21, 19, 15, 13, 11 1, 8, 9, 12, 16, 17, 20, 24, 25, 29, 32 7, 10, 14, 18, 22, 27, 31 Type I I I I I O Description clock signal input alternative clock signal input clock input select clock output enable/disable output enable/disable (high-impedance, 3-state) clock outputs
GND
ground
negative power supply (GND)
VCC
power
Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation.
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Product data sheet
Rev. 01 -- 13 October 2005
GND
27 VCC 26 Q2
28 Q1
3 of 17
Philips Semiconductors
PCK9447
3.3 V/2.5 V 1 : 9 LVCMOS clock fan-out buffer
6. Functional description
6.1 Function table
Table 3: Control CLK_SEL OE CLK_STOP
[1]
Function table Default 1 1 1 Logic 0 CCLK0 input selected outputs disabled (high-impedance state) [1] Logic 1 CCLK1 input selected outputs enabled
outputs synchronously stopped outputs active in logic LOW state
OE = 0 will high-impedance 3-state all outputs independent of CLK_STOP.
7. Limiting values
Table 4: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC VI VO II IO Tstg Parameter supply voltage input voltage output voltage input current output current storage temperature Conditions Min -0.3 -0.3 -0.3 -65 Max +3.9 VCC + 0.3 VCC + 0.3 20 50 +125 Unit V V V mA mA C
8. Characteristics
8.1 General characteristics
Table 5: Symbol VTT Vesd General characteristics Parameter termination voltage (output) electrostatic discharge voltage latch-up protection current power dissipation capacitance input capacitance per output inputs Machine Model Human Body Model
[1] [2]
Conditions
Min 200 2000 200 -
Typ VCC/2 10 4.0
Max -
Unit V V V mA pF pF
Ilatch(prot) CPD Ci
[1] [2]
200 pF capacitor discharged via a 10 resistor and a 0.75 H inductor 100 pF capacitor discharged via a 1.5 k resistor
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Product data sheet
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PCK9447
3.3 V/2.5 V 1 : 9 LVCMOS clock fan-out buffer
8.2 Static characteristics
Table 6: Static characteristics (3.3 V) Tamb = -40 C to +85 C; VCC = 3.3 V 5 % Symbol VIH VIL VOH VOL Zo II Iq(max)
[1]
Parameter HIGH-state input voltage LOW-state input voltage HIGH-state output voltage LOW-state output voltage output impedance input current maximum quiescent current
Conditions LVCMOS LVCMOS IOH = -24 mA IOL = 24 mA IOL = 12 mA VI = VCC or GND all VCC pins
[2] [3] [1]
Min 2.0 -0.3 2.4 -
Typ 17 -
Max +0.8 0.55 0.30 300 2.0
Unit V V V V A mA
VCC + 0.3 V
The PCK9447is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines (VCC = 3.3 V). Inputs have pull-down or pull-up resistors affecting the input current. Iq(max) is the DC current consumption of the device with all outputs open and the input in its default state or open.
[2] [3]
Table 7: Static characteristics (2.5 V) Tamb = -40 C to +85 C; VCC = 2.5 V 5 % Symbol VIH VIL VOH VOL Zo II Iq(max)
[1]
Parameter HIGH-state input voltage LOW-state input voltage HIGH-state output voltage LOW-state output voltage output impedance input current maximum quiescent current
Conditions LVCMOS LVCMOS IOH = -15 mA IOL = 15 mA VI = VCC or GND all VCC pins
[2] [3] [1]
Min 1.7 -0.3 1.8 -
Typ 19 -
Max +0.7 0.6 300 2.0
Unit V V V A mA
VCC + 0.3 V
The PCK9447 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives one 50 series terminated transmission line per output (VCC = 2.5 V). Inputs have pull-down or pull-up resistors affecting the input current. Iq(max) is the DC current consumption of the device with all outputs open and the input in its default state or open.
[2] [3]
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Product data sheet
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Philips Semiconductors
PCK9447
3.3 V/2.5 V 1 : 9 LVCMOS clock fan-out buffer
8.3 Dynamic characteristics
Table 8: Dynamic characteristics (3.3 V) Tamb = -40 C to +85 C; VCC = 3.3 V 5 % [1] [2] Symbol fi fo tW(i)(ref) tPLH, tPHL tPLZ, tPHZ tPZL, tPZH tsu th tsk(o) tsk(pr) tsk(p) o tr, tf
[1] [2] [3] [4]
Parameter input frequency output frequency reference input pulse width propagation delay output disable time output enable time setup time hold time output skew time process skew time pulse skew time (output) output duty cycle output rise/fall time
Conditions
Min 0 0 1.4
Typ 50 -
Max 350 350 3.3 11 11 150 2.0 300 55 1.0
Unit MHz MHz ns ns ns ns ns ns ps ns ps % ns
CCLK0 or CCLK1 to any Q
1.3 -
CCLK0 or CCLK1 to CLK_STOP CCLK0 or CCLK1 to CLK_STOP output-to-output part-to-part
[3] [3]
0.0 1.0 -
[4]
45 0.1
fq < 170 MHz; ref = 50 % 0.55 V to 2.4 V
Dynamic characteristics apply for parallel output termination of 50 to VTT. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle, and maximum frequency specifications. CCLK0, CCLK1; 0.7 V to 1.7 V. Setup and hold times are referenced to the falling edge of the selected clock signal input. Pulse skew time is the absolute difference of the propagation delay times: | tPLH - tPHL |.
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Product data sheet
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PCK9447
3.3 V/2.5 V 1 : 9 LVCMOS clock fan-out buffer
Table 9: Dynamic characteristics (2.5 V) Tamb = -40 C to +85 C; VCC = 2.5 V 5 % [1] [2] Symbol fi fo tW(i)(ref) tPLH, tPHL tPLZ, tPHZ tPZL, tPZH tsu th tsk(o) tsk(pr) tsk(p) o tr, tf
[1] [2] [3] [4]
Parameter input frequency output frequency reference input pulse width propagation delay output disable time output enable time setup time hold time output skew time process skew time pulse skew time (output) output duty cycle output rise/fall time
Conditions
Min 0 0 1.4
Typ 50 -
Max 350 350 4.4 11 11 150 2.7 200 55 1.0
Unit MHz MHz ns ns ns ns ns ns ps ns ps % ns
CCLK0 or CCLK1 to any Q
1.7 -
CCLK0 or CCLK1 to CLK_STOP CCLK0 or CCLK1 to CLK_STOP output-to-output part-to-part
[3] [3]
0.0 1.0 -
[4]
45 0.1
fq < 170 MHz; ref = 50 % 0.6 V to 1.8 V
Dynamic characteristics apply for parallel output termination of 50 to VTT. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle, and maximum frequency specifications. CCLK0, CCLK1; 0.7 V to 1.7 V. Setup and hold times are referenced to the falling edge of the selected clock signal input. Pulse skew time is the absolute difference of the propagation delay times: | tPLH - tPHL |.
CCLK0 or CCLK1
CLK_STOP
Q0 to Q8
002aaa717
Fig 3. Output clock stop (CLK_STOP) timing diagram
tN
tN+1
002aab293
tjit(cc) = | tN - tN+1 |
The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs.
Fig 4. Cycle-to-cycle jitter time
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Product data sheet
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PCK9447
3.3 V/2.5 V 1 : 9 LVCMOS clock fan-out buffer
VCC CCLK VCC/2 GND tPD VCC Qn
002aab288
VCC CCLK VCC/2 GND tPLH Qn tsk(p) = | tPLH - tPHL |
002aab290
tPHL VCC VCC/2 GND
VCC/2 GND
Fig 5. Propagation delay (tPD) test reference
VCC VCC/2 GND tsk(o) tsk(o) VCC VCC/2 GND
002aab289
Fig 6. Pulse skew time (tsk(p)) test reference
VCC VCC/2 tP T0 = (tP / T0 x 100 %)
002aab291
GND
The pin-to-pin skew is defined as the worst-case difference in propagation delay between any similar delay path within a single device.
The time from the output controlled edge to the non-controlled edge, divided by the time between output controlled edges, expressed as a percentage.
Fig 7. Output skew time (tsk(o))
(1) (2)
Fig 8. Output Duty Cycle (o)
tf
tr
002aab292
CCLK0 CCLK1 tsu th
VCC VCC/2 GND
(1) 2.4 V (VCC = 3.3 V) 1.8 V (VCC = 2.5 V) (2) 0.55 V (VCC = 3.3 V) 0.6 V (VCC = 2.5 V)
002aab294
VCC CLK_STOP VCC/2 GND
Fig 9. Output transition time test reference
Fig 10. Setup and hold time (tsu, th)
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Product data sheet
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Philips Semiconductors
PCK9447
3.3 V/2.5 V 1 : 9 LVCMOS clock fan-out buffer
9. Application information
9.1 Driving transmission lines
The PCK9447 clock driver was designed to drive high-speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of 17 (VCC = 3.3 V) or 19 (VCC = 2.5 V), the outputs can drive either parallel or series terminated transmission lines.
PCK9447
OUTPUT BUFFER
17 RS = 33 Zo = 50
IN
OutA
PCK9447
OUTPUT BUFFER
17
RS = 33
Zo = 50
OutB0
IN
RS = 33 Zo = 50
OutB1
002aaa718
Fig 11. Single versus dual transmission lines
In most high performance clock networks, point-to-point distribution of signals is the method of choice. In a point-to-point scheme, either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current, and thus only a single terminated line can be driven by each output of the PCK9447 clock driver. For the series terminated case, however, there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 11, illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme, the fan-out of the PCK9447 clock driver is effectively doubled due to its capability to drive multiple lines. The waveform plots of Figure 12 show simulation results of an output driving a single line versus two lines. In both cases the drive capability of the PCK9447 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurement in the simulations a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the PCK9447. The output waveform in Figure 12 shows a step in the waveform; this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 33 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: ZO V L = V S ------------------------------- R S + R O + Z 0
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Product data sheet
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PCK9447
3.3 V/2.5 V 1 : 9 LVCMOS clock fan-out buffer
Z O = 50 || 50 R S = 33 || 33 R O = 17 25 V L = 3.0 ---------------------------------- = 1.28 V 16.5 + 17 + 25 At the load end the voltage will double, due to the near unity reflection coefficient, to 2.5 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns).
3.0 voltage (V) 2.0 IN
002aaa679
OutA td = 3.8956 ns OutB td = 3.9386 ns
1.0
0 -0.5 0 4 8 12 time (ns) 14
Fig 12. Single versus dual line termination waveforms
Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines, the situation in Figure 13 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched.
PCK9447
OUTPUT BUFFER
17
RS = 16
Zo = 50
IN
RS = 16 Zo = 50
002aaa719
17 + 16 || 16 = 50 || 50 25 = 25 Fig 13. Optimized dual line termination
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Product data sheet
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Philips Semiconductors
PCK9447
3.3 V/2.5 V 1 : 9 LVCMOS clock fan-out buffer
10. Test information
PCK9447 D.U.T.
PULSE GENERATOR Z = 50
Zo = 50
Zo = 50
RT = 50
RT = 50
VTT
VTT
002aab287
Fig 14. CCLK AC test reference for VCC = 3.3 V and VCC = 2.5 V
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Product data sheet
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PCK9447
3.3 V/2.5 V 1 : 9 LVCMOS clock fan-out buffer
11. Package outline
LQFP32: plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm SOT358-1
c
y X
24 25
17 16 ZE
A
e E HE wM bp pin 1 index 32 1 e bp D HD wM B vM B 8 ZD vM A 9 detail X L Lp A A2 A 1 (A 3)
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.4 0.3 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.8 HD 9.15 8.85 HE 9.15 8.85 L 1 Lp 0.75 0.45 v 0.2 w 0.25 y 0.1 Z D (1) Z E (1) 0.9 0.5 0.9 0.5 7 o 0
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT358 -1 REFERENCES IEC 136E03 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-25
Fig 15. Package outline SOT358-1 (LQFP32)
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PCK9447
3.3 V/2.5 V 1 : 9 LVCMOS clock fan-out buffer
12. Soldering
12.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.
12.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 C to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:
* below 225 C (SnPb process) or below 245 C (Pb-free process)
- for all BGA, HTSSON..T and SSOP..T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages.
* below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
12.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
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PCK9447
3.3 V/2.5 V 1 : 9 LVCMOS clock fan-out buffer
- smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle to
the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
12.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C.
12.5 Package related soldering information
Table 10: Package [1] BGA, HTSSON..T [3], LBGA, LFBGA, SQFP, SSOP..T [3], TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC [5], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L [8], PMFP [9], WQCCN..L [8]
[1] [2]
Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave not suitable not suitable [4] Reflow [2] suitable suitable
suitable not not recommended [5] [6] recommended [7]
suitable suitable suitable not suitable
not suitable
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods.
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Product data sheet
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PCK9447
3.3 V/2.5 V 1 : 9 LVCMOS clock fan-out buffer
[3]
These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. Hot bar soldering or manual soldering is suitable for PMFP packages.
[4]
[5] [6] [7] [8]
[9]
13. Abbreviations
Table 11: Acronym ESD HBM MM LVCMOS Abbreviations Description ElectroStatic Discharge Human Body Model Machine Model Low Voltage Complementary Metal Oxide Silicon
14. Revision history
Table 12: Revision history Release date 20051013 Data sheet status Product data sheet Change notice Doc. number 9397 750 12522 Supersedes Document ID PCK9447_1
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3.3 V/2.5 V 1 : 9 LVCMOS clock fan-out buffer
15. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
16. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
18. Trademarks
Notice -- All referenced brands, product names, service names and trademarks are the property of their respective owners.
17. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors
19. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 12522
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 -- 13 October 2005
16 of 17
Philips Semiconductors
PCK9447
3.3 V/2.5 V 1 : 9 LVCMOS clock fan-out buffer
20. Contents
1 2 3 4 5 5.1 5.2 6 6.1 7 8 8.1 8.2 8.3 9 9.1 10 11 12 12.1 12.2 12.3 12.4 12.5 13 14 15 16 17 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 4 General characteristics . . . . . . . . . . . . . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Application information. . . . . . . . . . . . . . . . . . . 9 Driving transmission lines . . . . . . . . . . . . . . . . . 9 Test information . . . . . . . . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Introduction to soldering surface mount
packages . . . . . . . . . . . . . . . . . . . . . . . . 13
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . Manual soldering . . . . . . . . . . . . . . . . . . . . . . Package related soldering information . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . 13 13 14 14 15 15 16 16 16 16 16
(c) Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 13 October 2005 Document number: 9397 750 12522
Published in The Netherlands

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