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(R)
Integrated Device Technology, Inc.
3.3V CMOS 16-BIT BUS TRANSCEIVER/ REGISTERS
IDT54/74FCT163652/A/C PRODUCT PREVIEW
FEATURES:
* 0.5 MICRON CMOS Technology * Typical tSK(o) (Output Skew) < 250ps * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack * Extended commercial range of -40C to +85C * VCC = 3.3V 0.3V, Normal Range or VCC = 2.7 to 3.6V, Extended Range * CMOS power levels (0.4W typ. static) * Rail-to-Rail output swing for increased noise margin * Military product compliant to MIL-STD-883, Class B * Low Ground Bounce (0.3V typ.) * Inputs (except I/O) can be driven by 3.3V or 5V components
DESCRIPTION:
The IDT54/74FCT163652/A/C 16-bit registered transceivers are built using advanced dual metal CMOS technology.
These high-speed, low-power devices are organized as two independent 8-bit bus transceivers with 3-state D-type registers. For example, the xOEAB and xOEBA signals control the transceiver functions. The xSAB and xSBA control pins are provided to select either real time or stored data transfer. The circuitry used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during the transition between stored and real time data. A LOW input level selects real-time data and a HIGH level selects stored data. Data on the A or B data bus, or both, can be stored in the internal D-flip-flops by LOW-to-HIGH transitions at the appropriate clock pins (xCLKAB or xCLKBA), regardless of the select or enable control pins. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The IDT54/74FCT163652/A/C have series current limiting resistors. This offers low ground bounce, minimal undershoot, and controlled output fall times-reducing the need for external series terminating resistors.
FUNCTIONAL BLOCK DIAGRAM
1OEAB 1OEBA 1CLKBA 1SBA 1CLKAB 1SAB B REG
2OEAB 2OEBA 2CLKBA 2SBA 2CLKAB 2SAB B REG
D C
1A1 A REG 1B1
2A1 A REG
D C
2B1
D C
D C
TO 7 OTHER CHANNELS
3084 drw 01
TO 7 OTHER CHANNELS
3084 drw 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1996 Integrated Device Technology, Inc.
AUGUST 1996
DSC-3084/2
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IDT54/74FCT163652/A/C 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
1OEAB 1CLKAB 1SAB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 SO56-1 43 SO56-2 SO56-3 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1OEBA 1CLKBA 1SBA
1OEAB 1CLKAB 1SAB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 E56-1
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
3084 drw 04
1OEBA 1CLKBA 1SBA
GND
1A1 1A2
GND
1B1 1B2
GND
1A1 1A2
GND
1B1 1B2
VCC
1A3 1A4 1A5
VCC
1B3 1B4 1B5
VCC
1A3 1A4 1A5
VCC
1B3 1B4 1B5
GND
1A6 1A7 1A8 2A1 2A2 2A3
GND
1B6 1B7 1B8 2B1 2B2 2B3
GND
1A6 1A7 1A8 2A1 2A2 2A3
GND
1B6 1B7 1B8 2B1 2B2 2B3
GND
2A4 2A5 2A6
GND
2B4 2B5 2B6
GND
2A4 2A5 2A6
GND
2B4 2B5 2B6
VCC
2A7 2A8
VCC
2B7 2B8
VCC
2A7 2A8
VCC
2B7 2B8
GND
2SAB 2CLKAB
GND
2SBA 2CLKBA 2OEBA
GND
2SAB 2CLKAB
GND
2SBA 2CLKBA 2OEBA
2OEAB
2OEAB
SSOP/ TSSOP/TVSOP TOP VIEW
3084 drw 03
CERPACK TOP VIEW
PIN DESCRIPTION
Description Data Register A Inputs Data Register B Outputs xBx Data Register B Inputs Data Register A Outputs xCLKAB, xCLKBA Clock Pulse Inputs xSAB, xSBA xOEAB, xOEBA Output Data Source Select Inputs Output Enable Inputs
3084 tbl 01
Pin Names xAx
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IDT54/74FCT163652/A/C 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(2)
Inputs xOEAB L L X H L L L L H H H xOEBA OEBA H H H H X L L L H H L xCLKAB xCLKBA H or L H or L X X X H or L H or L H or L H or L X H or L X X H or L xSAB X X X X(2) X X X X L H H xSBA X X X X X X(2) L H X X H xAx Input Input Input Unspecified(1) Output Output Input Output Data I/O(1) xBx Input Isolation Store A and B Data Operation or Function
Unspecified(1) Store A, Hold B Output Store A in Both Registers Input Input Input Output Output Hold A, Store B Store B in both Registers Real Time B Data to A Bus Stored B Data to A Bus Real Time A Data to B Bus Stored A Data to B Bus Stored A Data to B Bus and Stored B Data to A Bus
3084 tbl 03
NOTES: 1. The data output functions may be enabled or disabled by various signals at the xOEAB or xOEBA inputs. Data input functions are always enabled, i.e. data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. 2. Select control = L: clocks can occur simultaneously. Select control = H: clocks must be staggered to load both registers. 3. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = LOW-to-HIGH Transition
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol Parameter(1) CIN Input Capacitance CI/O I/O Capacitance Conditions VIN = 0V VOUT = 0V Typ. 3.5 3.5 Max. Unit 6.0 pF 8.0 pF
3084 lnk 02
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM(2) VTERM(3) VTERM(4) TSTG IOUT Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Max. -0.5 to +4.6 -0.5 to +7.0 -0.5 to VCC + 0.5 -65 to +150 -60 to +60 Unit V V V C mA
NOTE: 1. This parameter is measured at characterization but not tested.
3084 lnk 04 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Vcc terminals. 3. Input terminals. 4. Output and I/O terminals.
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IDT54/74FCT163652/A/C 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
BUS A
BUS B
BUS A
BUS B
3084 drw 05
3084 drw 06
xOEAB
xOEBA
xCLKAB
xCLKBA
xSAB
xSBA
xOEAB
xOEBA
xCLKAB
xCLKBA
xSAB
xSBA
L
L
X
X
X
L
H
H
X
X
L
X
REAL-TIME TRANSFER BUS B TO A
REAL-TIME TRANSFER BUS A TO B
BUS A
BUS B
BUS A
BUS B
3084 drw 07
3084 drw 08
xOEAB
xOEBA
xCLKAB
xCLKBA
xSAB
xSBA
xOEAB xOEBA
xCLKAB
xCLKBA
xSAB
xSBA
X L L
H X H
X
X
X X X
X X X
H
L
H or L
H or L
H
H
STORAGE FROM A AND/OR B
TRANSFER STORED DATA TO A AND/OR B
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IDT54/74FCT163652/A/C 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = -40C to +85C, VCC = 2.7V to 3.6V; Military: TA = -55C to +125C, VCC = 2.7V to 3.6V
Symbol VIH VIL II H II L IOZH IOZL VIK IODH IODL VOH Parameter Input HIGH Level (Input pins) Input HIGH Level (I/O pins) Input LOW Level (Input and I/O pins) Input HIGH Current (Input pins)(6) Input HIGH Current (I/O Input LOW Current (I/O (3-State Output pins) (6) pins)(6) pins)(6) VCC = Max. Input LOW Current (Input pins)(6) High Impedance Output Current Clamp Diode Voltage Output HIGH Current Output LOW Current Output HIGH Voltage VCC = Max. VI = 5.5V VI = VCC VI = GND VI = GND VO = VCC VO = GND VCC = Min., IIN = -18mA VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3) VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3) VCC = Min. VIN = VIH or VIL VCC = 3.0V VIN = VIH or VIL VCC = Min. VIN = VIH or VIL IOH = -0.1mA IOH = -3mA IOH = -6mA MIL. IOH = -8mA COM'L. IOL = 0.1mA IOL = 16mA IOL = 24mA VCC = 3.0V IOL = 24mA VIN = VIH or VIL VCC = Max., VO = GND(3)
--
Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level
Min. 2.0 2.0 -0.5 -- -- -- -- -- -- -- -36 50 VCC-0.2 2.4 2.4 (5) -- -- -- -- -60 -- -- --
Typ.(2) -- --
--
Max. 5.5 VCC+0.5 0.8
Unit V V
-- -- -- -- -- -- -0.7
1 1 1 1 1 1
-1.2
A
A
V mA mA V
-60 90 -- 3.0 3.0 -- 0.2 0.3 0.3
-135
-110 200 -- -- -- 0.2 0.4 0.55 0.50 -240
--
VOL
Output LOW Voltage
V
IOS VH ICCL ICCH ICCZ
Short Circuit Current(4) Input Hysteresis Quiescent Power Supply Current
mA mV
150 0.1 0.1
VCC = Max., VIN = GND or VCC
COM'L. MIL.
10 100
A
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 3.3V, +25C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. VOH = VCC -0.6V at rated current. 6. The test limit for this parameter is 5A at TA = -55C.
3084 lnk 05
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IDT54/74FCT163652/A/C 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current (4) VCC = Max. Test Conditions(1) VIN = VCC -0.6V(3) Min. -- -- Typ.(2) 2.0 60 Max. 30 100 Unit A
VIN = VCC VCC = Max. Outputs Open VIN = GND xOEAB = xOEBA=GND One Input Toggling 50% Duty Cycle VCC = Max. Outputs Open fCP = 10MHz (xCLKBA) 50% Duty Cycle xOEAB = xOEBA=GND One Bit Toggling fi = 5MHz 50% Duty Cycle VCC = Max. Outputs Open fCP = 10MHz (xCLKBA) 50% Duty Cycle xOEAB = xOEBA=GND Sixteen Bits Toggling fi = 2.5MHz 50% Duty Cycle VIN = VCC VIN = GND
A/ MHz
IC
Total Power Supply Current (6)
--
0.6
1.0
mA
VIN = VCC -0.6V VIN = GND
--
0.6
1.0
VIN = VCC VIN = GND
--
3.0
5.0 (5)
VIN = VCC -0.6V VIN = GND
--
3.0
5.3 (5)
NOTES: 1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25C ambient. 3. Per TTL driven input; all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi
3084 tbl 08
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IDT54/74FCT163652/A/C 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(4)
FCT163652 Com'l. Symbol Parameter Condition(1) Min.(2) Max. Mil. Min.(2) Max. FCT163652A Com'l. Min.(2) Max. Mil. Min.(2) Max. FCT163652C Com'l. Min.(2) Max. Mil. Min.(2) Max. Unit
Propagation Delay Bus to Bus Output Enable Time xOEAB or xOEBA to Bus Output Disable Time xOEAB or xOEBA to Bus Propagation Delay Clock to Bus Propagation Delay xSBA or xSAB to Bus Set-up Time HIGH or LOW Bus to Clock tH Hold Time HIGH or LOW Bus to Clock tW Clock Pulse Width HIGH or LOW tSK(o) Output Skew (3)
tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPLH tPHL tSU
CL = 50pF RL = 500
2.0 2.0 2.0 2.0 2.0 4.0 2.0 6.0 --
9.0 14.0 9.0 9.0 11.0 -- -- -- 0.5
2.0 2.0 2.0 2.0 2.0 4.5 2.0 6.0 --
11.0 15.0 11.0 10.0 12.0 -- -- -- 0.5
2.0 2.0 2.0 2.0 2.0 2.0 1.5 5.0 --
6.3 9.8 6.3 6.3 7.7 -- -- -- 0.5
2.0 2.0 2.0 2.0 2.0 2.0 1.5 5.0 --
7.7 10.5 7.7 7.0 8.4 -- -- -- 0.5
1.5 1.5 1.5 1.5 1.5 2.0 1.5 5.0 --
5.4 7.8 6.3 5.7 6.2 -- -- -- 0.5
-- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- --
ns ns ns ns ns ns ns ns ns
3084 tbl 09 NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew between any two outputs of the same package, switching in the same direction. This parameter is guaranteed by design. 4. Propagation Delays and Enable/Disable times are with VCC = 3.3V 0.3V, Normal Range. For VCC = 2.7V to 3.6V, Extended Range, all Propagation Delays and Enable/Disable times should be degraded by 20%.
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IDT54/74FCT163652/A/C 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS
6V V
CC
SWITCH POSITION
Open GND
500 V Pulse Generator R
T IN
V D.U.T.
OUT
Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests
Switch 6V
50pF C
L
500
SET-UP, HOLD AND RELEASE TIMES
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tSU
tH
tREM
tSU
tH
PROPAGATION DELAY
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V
GND Open
3084 lnk 10 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
3084 drw 09
PULSE WIDTH
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
1.5V
1.5V
3084 drw 11
3084 drw 10
ENABLE AND DISABLE TIMES
ENABLE CONTROL INPUT tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH 6V tPZH SWITCH GND 1.5V 0V 3V 1.5V tPHZ 0.3V VOH 0V
3084 drw 13
DISABLE 3V 1.5V 0V 3V 0.3V VOL
tPLZ
3084 drw 12
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns. 3. If VCC is below 3V, input voltage swings should be adjusted not to exceed VCC.
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IDT54/74FCT163652/A/C 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XX FCT XXXX Device Type Temperature Range X Package X Process
Blank B PV PA PF E 163652 163652A 163652C 54 74
Commercial MIL-STD-883, Class B Shrink Small Outline Package (SO56-1) Thin Shrink Small Outline Package (SO56-2) Thin Very Small Outline Package (SO56-3) CERPACK (E56-1) Non-Inverting 16-Bit Bus Transceiver/Register
-55C to +125C -40C to +85C
3084 drw 14
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