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ISL59112
Data Sheet March 15, 2007 FN6142.4
40MHz Rail-to-Rail Video Buffer
The ISL59112 is a single rail-to-rail 6dB video buffer with a 3dB roll-off frequency of 40MHz and a slew rate of 60V/s. Input signal DC restoration is accomplished with an internal sync tip clamp. Operating from single supplies ranging from +2.5V to +3.6V and sinking an ultra-low 2mA quiescent current, the ISL59112 is ideally suited for low power, battery-operated applications. It also features inputs capable of reaching down to 0.15V below the negative rail. Additionally, an enable high pin shuts the part down in under 20ns. The ISL59112 is designed to meet the needs for very low power and bandwidth criteria inherent to battery operated communication, instrumentation and modern industrial applications, such as video on demand, cable set-top boxes, DVD players and HDTV. The ISL59112 is offered in a spacesaving SC-70 package guaranteed to a 1mm maximum height constraint and specified for operation from -40C to +85C temperature range.
Features
* 40MHz -3dB bandwidth * 85V/s slew rate * Low supply current = 2mA * Power-down current less than 1A * Supplies from 2.5V to 3.6V * Rail-to-rail output * Input to 0.15V below ground * Internal sync tip clamp * SAG correction reduces coupling capacitor size * Pb-free plus anneal available (RoHS compliant)
Applications
* Video amplifiers * Digital cameras * Camera phones
Ordering Information
PART NUMBER (Note) PART MARKING TAPE & REEL PACKAGE (Pb-Free) PKG. DWG. # P6.049A
* Portable/handheld products * Communications devices * Video on demand * Cable set-top box * Satellite set-top box * DVD players * HDTV * Personal video recorders
ISL59112IEZ-T7 CPA
7" (3k pcs) 6 Ld SC-70
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinout
ISL59112 (6 LD SC-70)* TOP VIEW
IN+ 1 LPF + 6 V+
GND 2
5 EN
SAG 3
4 OUT
*1mm MAXIMUM HEIGHT GUARANTEED
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2005, 2006, 2007. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL59112
Absolute Maximum Ratings (TA = +25C)
Supply Voltage from VS+ to VS- . . . . . . . . . . . . . . . . . . . . . . . . 3.6V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . VS+ +0.3V to VS- -0.3V Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7) . . .3000V Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . .300V
Thermal Information
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +125C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
DESCRIPTION INPUT CHARACTERISTICS VCC IDD(ON) IDD(OFF) VOLS VCLAMP ICLAMP IB RIN AV ASAG PSRR VOH ISC
VS+ = 3.3V, VS- = GND, TA = +25C, RL = 150 to GND, unless otherwise specified CONDITIONS MIN TYP MAX UNIT
PARAMETER
Supply Voltage Range Quiescent Supply Current Shutdown Supply Current Output Level Shift Voltage Input Voltage Clamp Clamp Current Input Bias Current Input Resistance Voltage Gain SAG Correction DC Gain to VOUT DC Power Supply Rejection Output Voltage High Swing Output Short-Circuit Current VIN = 500mV, EN = VDD, no load EN = 0V VIN = 0V, no load IIN = -1mA VIN = VCLAMP - 100mV VIN = 500mV 0.5V < VIN < 1.0V RL = 150 SAG open VDD = 2.7V to 3.3V VIN = 2V, RL = 150 to GND VIN = 2V, to GND through 10 VIN = 100mV, out short to VDD through 10
2.5 2
3.6 2.75 3
V mA A mV mV mA A M
60 -40
130 -15 -6
200 +10 -3 7.5
2.5 0.5 5.8
5 3 6.0 2.25
6.2
dB V/V dB V
43 2.85
63 3.2 -94 -65
mA mA
65 -3
115 0 +3 0.8
IENABLE VIL VIH ROUT
Enable Current EN Logic Low Threshold EN Logic High Threshold Shutdown Output Impedance
Enable pin = 0V to 3.6V VDD = 2.7V to 3.3V VDD = 2.7V to 3.3V EN = 0V DC EN = 0V, f = 4.5MHz
A V V
1.6 3.6 4.5 3.4 5.9
k k
AC PERFORMANCE BW BW dG -3dB Bandwidth 0.1dB Bandwidth Differential Gain RL = 150, CL = 5pF RL = 150, CL = 5pF NTSC and PAL DC coupled NTSC and PAL AC coupled dP Differential Phase NTSC and PAL DC coupled NTSC and PAL AC coupled D/DT SNR tON Group Delay Variation Signal To Noise Ratio Enable Time f = 100kHz, 5MHz 100% white signal VIN = 500mV, VOUT to 1% 40 27 0.02 0.02 0.4 0.04 5.4 65 570 MHz MHz % % ns dB ns
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FN6142.4 March 15, 2007
ISL59112
Electrical Specifications
DESCRIPTION tOFF SR(Ih) SR(hl) tF tR Disable Time Positive Slew Rate Negative Slew Rate Fall Time Rise Time VS+ = 3.3V, VS- = GND, TA = +25C, RL = 150 to GND, unless otherwise specified (Continued) CONDITIONS VIN = 500mV, VOUT to 1% VIN = 1VSTEP, 10% - 90% VIN = 1VSTEP 1.0VSTEP 1.0VSTEP, 20% - 80% 30 MIN TYP 14 85 -80 9 9 -30 MAX UNIT ns V/s V/s ns ns
PARAMETER
Typical Performance Curves
VDD = +3.3V RL = 150 CL = 27pF CL = 18pF CL = 10pF VDD = +3.3V CL = 5pF RL = 570 RL = 210
CL = 5pF CL = 0pF
RL = 150 RL = 27 RL = 10
FIGURE 1. FREQUENCY RESPONSE FOR VARIOUS CLOAD
FIGURE 2. FREQUENCY RESPONSE FOR VARIOUS RLOAD
VDD = +3.3V RL = 150 SOURCE = -15dB
1V 500mV 200mV
VDD = +3.3V RL = 150 SOURCE = -30dB
VIN = -20dBm
VIN = -10dBm
100mV 42mV
VIN = -5dBm VIN = 0dBm
FIGURE 3. FREQUENCY RESPONSE FOR VARIOUS VOS
FIGURE 4. FREQUENCY RESPONSE FOR VARIOUS VIN
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FN6142.4 March 15, 2007
ISL59112 Typical Performance Curves (Continued)
VDD = +3.3V RL = 150 FREQ = 500kHz VDD = +3.3V RL = 150 VOPP = 2V
THD
THD
2nd HD
2nd HD
3rd HD 3rd HD
FIGURE 5. HARMONIC DISTORTION vs OUTPUT VOLTAGE
FIGURE 6. HORMONIC DISTORTION vs FREQUENCY
VDD = +3.3V
VDD = +3.3V
FIGURE 7. OUTPUT IMPEDENCE vs FREQUENCY
FIGURE 8. PSRR vs FREQUENCY
0.50 0.45 POWER DISSIPATION (W) 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD
0.55 0.50 POWER DISSIPATION (W) 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 500mW
450mW
JA
=
SC +2
J
SC
20 C
70 -
A
-6 /W 70 0C 0 +2
=
6
/W
0
25
50
75 85 100
125
150
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
AMBIENT TEMPERATURE (C)
FIGURE 9. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 10. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
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FN6142.4 March 15, 2007
ISL59112
SYNC CLAMP VDD VDD VDD
+ CIN IN RIN 75 100nF VDC + -
SAG NETWORK OUT R6 R7 R5 SAG + -
AC COUPLING CAPACITOR C5 47F C4 22F 75 75
IN
EN EN = GND: SHUTDOWN IDD~0 EN = VDD: ACTIVE IDD~2.0mA R4
GND
FIGURE 11. BLOCK DIAGRAM
Application Information
The ISL59112 is a single supply rail-to-rail output buffer achieving a -3dB bandwidth of around 40MHz and slew rate of about 85V/s while demanding only 2mA of supply current. This part is ideally suited for applications with specific micropower consumption and high bandwidth demands. As described in both the performance characteristics section and the features section, the ISL59112 is designed to be very attractive for portable composite video applications. The ISL59112 features a sync clamp and SAG network at the output facilitating reduction of typically large AC coupling capacitors. See Figure 11.
stage of the amplifier by setting the signal closer to the best voltage range. The simplified block diagram of the ISL59112 in Figure 11 is divided into four sections. The first (Section A) is the Sync Clamp. The AC coupled video sync signal is pulled negative by a current source at the input of the comparator amplifier. When the sync tip goes below the comparator threshold, the output comparator is driven negative and the PMOS device turns on clamping sync tip to near ground level.
AC Output Coupling and the SAG Network
Composite video signals carry viable information at frequencies as low as 30Hz up to 5MHz. When a video system output is AC coupled it is critical that the filter represented by the output coupling capacitor and the surrounding resistance network provide a band pass function with a low pass band low enough to exclude very low frequencies down to DC, and with a high pass band pass sufficiently high to include frequencies at the higher end of the video spectrum.
Internal Sync Clamp
The typical embedded video DAC operates from a ground referenced single supply. This becomes an issue because the lower level of the sync pulse output may be at a 0V reference level to some positive level. The problem is presenting a 0V input to most single supply driven amplifiers will saturate the output stage of the amplifier, resulting in a clipped sync tip and degrading the video image. A larger positive reference may offset the input above its positive range. The ISL59112 features an internal sync clamp and an offset function to level shift the entire video signal to the best level before it reaches the input of the amplifier stage. These features are also helpful to avoid saturation of the output
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FN6142.4 March 15, 2007
ISL59112
SAG NETWORK AC COUPLING CAPACITOR C5 R6 ROUT RL
R7
C4
Short-circuit protection can be provided externally with a back match resistor in series with the output placed close as possible to the output pin. In video applications this would be a 75 resistor and will provide adequate short-circuit protection to the device. Care should still be taken not to stress the device with a short at the output.
R5 R4
Power Dissipation
With the high output drive capability of the ISL59112, it is possible to exceed the +125C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for an application to determine if load conditions or package types need to be modified to assure operation of the amplifier in a safe operating area. The maximum power dissipation allowed in a package is determined according to Equation 1:
T JMAX - T AMAX PD MAX = ------------------------------------------- JA
FIGURE 12. SAG NETWORK AND AC COUPLING CAPACITORS
Typically, this is accomplished with 220F coupling capacitor, a large and somewhat costly solution providing a low frequency pole around 5Hz. If the size of this capacitor is even slightly reduced we have found that the accompanying phase shift in the 50Hz to 100Hz frequency range results in field tilt, which results in a degraded video image. The internal SAG network of the ISL59112 replaces the 220F AC coupling capacitor with a network of two smaller capacitors as shown, in Figure 12. Additionally, the network is designed to place a zero in the ~30Hz range, providing a small amount of peaking to compensate the phase response associated with field tilt.
(EQ. 1)
Where: TJMAX = Maximum junction temperature TAMAX = Maximum ambient temperature JA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or for sourcing:
V OUT i PD MAX = V S x I SMAX + ( V S - V OUT i ) x ----------------RL i (EQ. 2)
DC Output Coupling
The ISL59112 internal sync clamp makes it possible to DC couple the output to a video load, eliminating the need for any AC coupling capacitor, thereby saving board space and additional expense for capacitors. Additionally, this solution completely eliminates the issue of field tilt in the lower frequency. The trade off is greater demand of supply current. Typical load current for AC coupled is around 3mA compared to typical 6mA used when DC coupling.
for sinking:
PD MAX = V S x I SMAX + ( V OUT i - V S ) x I LOAD i
(EQ. 3)
ENABLE + -
ROUT
Where: VS = Supply voltage ISMAX = Maximum quiescent supply current
TELEVISION OR VCR
VOUT = Maximum output voltage of the application RLOAD = Load resistance tied to ground ILOAD = Load current
FIGURE 13. DC COUPLE
Output Drive Capability
The ISL59112 does not have internal short-circuit protection circuitry. If the output is shorted indefinitely, the power dissipation could easily overheat the die or the current could eventually compromise metal integrity. Maximum reliability is maintained if the output current never exceeds 40mA. This limit is set by the design of the internal metal interconnect. Note that in transient applications, the part is robust.
By setting the two PDMAX equations equal to each other, we can solve the output current and RLOAD to avoid the device overheat.
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FN6142.4 March 15, 2007
ISL59112
Power Supply Bypassing Printed Circuit Board Layout
As with any modern operational amplifier, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as short as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to the ground plane, a single 4.7F tantalum capacitor in parallel with a 0.1F ceramic capacitor from VS+ to GND will suffice. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. In this case, the VS- pin becomes the negative supply rail.
Printed Circuit Board Layout
For good AC performance, parasitic capacitance should be kept to minimum. Use of wire wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance that can result in compromised performance. Minimizing parasitic capacitance at the amplifier's inverting input pin is very important. The feedback resistor should be placed very close to the inverting input pin. Strip line design techniques are recommended for the signal traces.
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FN6142.4 March 15, 2007
ISL59112 Small Outline Transistor Plastic Packages (SC70-6)
0.20 (0.008) M C L b e C VIEW C
P6.049A
6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE INCHES SYMBOL MIN 0.031 0.001 0.034 0.006 0.006 0.004 0.004 0.073 0.045 MAX 0.039 0.004 0.036 0.012 0.010 0.008 0.006 0.085 0.053 MILLIMETERS MIN 0.80 0.025 0.85 0.15 0.15 0.10 0.10 1.85 1.15 MAX 1.00 0.10 0.90 0.30 0.25 0.20 0.15 2.15 1.35 NOTES 6 6 3 3 4 5 8 Rev. 0 7/05
6 C L 1
5
4 C L E E1
A A1 A2 b b1 c c1 D E E1 e e1 L L1 L2 N R
2
3
e1 D C L
C
0.084 BSC 0.0256 Ref 0.0512 Ref 0.010 0.018 0.016 Ref. 0.006 BSC 6 0.004 0 8
2.1 BSC 0.65 Ref 1.30 Ref 0.26 0.46 0.400 Ref. 0.15 BSC 6 0.10 0
A
A2
A1
SEATING PLANE -C-
0.10 (0.004) C
WITH PLATING c
b b1 c1
NOTES:
BASE METAL
1. Dimensioning and tolerance per ASME Y14.5M-1994. 2. Package conforms to EIAJ SC70 and JEDEC MO203AB. 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs.
4X 1 R1 R GAUGE PLANE SEATING PLANE L C 4X 1 VIEW C L1
4. Footlength L measured at reference to gauge plane. 5. "N" is the number of terminal positions. 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
L2
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 8
FN6142.4 March 15, 2007

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