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19-2727; Rev 2; 6/04
KIT ATION EVALU BLE AVAILA
1.5Gbps Serial ATA-Compatible Mux/Buffer with Loopback and Equalization
General Description
The MAX3786 is an AC-coupled, serial-ATA (SATA)compatible, 1.5Gbps multiplexer/buffer (mux/buffer) IC that provides the capability to switch a single serial data signal between two redundant I/O channels. SATA out-of-band (OOB) signaling is supported using loss-of-signal (LOS) detect on all three inputs and shutdown on the corresponding outputs. The high-speed inputs and outputs are all internally terminated, compatible with 100 differential systems, and must be AC-coupled to the controller IC and SATA-compatible disk drive. Receive equalization (EQ) and transmit preemphasis (PE) are provided on the dual I/O channels to mitigate the effects of intersymbol interference in the signal path. Loopback can be enabled on the nonselected I/O channel. The MAX3786 operates from a single +3.3V supply and typically consumes 520mW with PE and EQ enabled. It is available in a 5mm x 5mm, 32-lead thin QFN exposed-pad package and operates over a 0C to +85C temperature range.
Features
< 50psP-P Total Residual Jitter (20in FR-4, EQ and PE On) Supports SATA OOB Signaling Loopback of Nonselected Channel Receive Equalization and Transmit Preemphasis on Controller-Side I/O Channels 0C to +85C Operation 32-Pin, 5mm 5mm Thin QFN Package +3.3V Power Supply
MAX3786
Ordering Information
PART MAX3786UTJ MAX3786UTJ+ TEMP RANGE PIN-PACKAGE PKG CODE 0C to +85C 0C to +85C 32 Thin QFN-EP* (5mm x 5mm) 32 Thin QFN-EP* (5mm x 5mm) T3255-2 --
Applications
1.5Gbps Serial ATA Redundancy
+Denotes lead-free package. *EP = Exposed pad.
Typical Application Circuit
CONNECTOR
CONNECTOR
2in TO 24in FR-4
CONTROLLER 1
OUT1
IN1 RX SATA CONNECTOR SATA CONNECTOR DISK DRIVE
MAX3786 TX OUT0 CONNECTOR CONNECTOR IN0
2in TO 24in FR-4
CONTROLLER 2
Pin Configuration and Functional Diagram appear at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
1.5Gbps Serial ATA-Compatible Mux/Buffer with Loopback and Equalization MAX3786
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC ............................................-0.5V to +5.0V Continuous Current at Outputs (TX, OUT1, OUT0)..............................................22mA Input Voltage (RX, IN1, IN0) ..................................-0.5V to (VCC + 0.5V) Differential Input Voltage (RX, IN1, IN0) .......................................................2.0V Voltage at PE1EN, PE0EN, EQ1EN, EQ0EN, LB_EN, SEL, CM1, CM0 .........................-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +85C) 32-Pin Thin QFN (derate 21.3mW/C above +85C) .1384mW Operating Temperature Range .............................0C to +85C Storage Temperature Range ............................-55C to +150C Lead Temperature (soldering, 10s) ..............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = 0C to +85C. Typical values at VCC = +3.3V, TA = +25C, unless otherwise noted.)
PARAMETER Supply Current Maximum Data Rate Differential Input Voltage (RX, IN1, IN0) Input Termination Input Return Loss Input Equalization Differential Output Voltage (TX, OUT0, OUT1) (Note 2) Output Termination Output Transition Time Output Preemphasis Output Jitter Total Residual Jitter Differential Output Skew LOS Detector Threshold Output Startup/Shutdown Time LVCMOS Input High Voltage VIH (Note 7) 1.5 |S11| SYMBOL ICC EQ and PE off EQ and PE on (Note 1) (Note 2) Differential 100MHz to 2.5GHz At 750MHz PE off Output disabled by OOB signaling Single ended to VCC 1.5Gbps data, 20% to 80% (Notes 1, 3) At 750MHz (Note 4) DJ + 14RJ, EQ and PE off (Notes 1, 5, 8) DJ + 14RJ, EQ and PE on (Notes 1, 6, 8) (Note 1) 50 42.5 135 50 200 4.5 30 40 40 50 20 150 5 400 1.5 250 85 100 14 4.5 500 600 30 57.5 270 600 115 CONDITIONS MIN TYP 125 158 MAX 150 220 UNITS mA Gbps mVP-P dB dB mVP-P ps dB psP-P psP-P ps mVP-P ns V
2
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1.5Gbps Serial ATA-Compatible Mux/Buffer with Loopback and Equalization
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = 0C to +85C. Typical values at VCC = +3.3V, TA = +25C, unless otherwise noted.)
PARAMETER LVCMOS Input Low Voltage LVCMOS Input High Current LVCMOS Input Low Current SYMBOL VIL IOH IOL VIH = +2.0V to (VCC + 0.3V) VIL = -0.3V to +0.8V CONDITIONS MIN TYP MAX 0.5 150 150 UNITS V A A
MAX3786
AC specifications are guaranteed by design and characterization. Differential voltage is defined as VP-P = (V+ - V-). Inputs and outputs must be AC-coupled for proper operation. Output transition time measured using a 0000011111 pattern, with transmit PE off. Transmit PE compensates for 20in of 6-mil-wide differential stripline in FR-4 or equivalent path loss. Jitter after paths from RX to OUT_ or IN_ to TX. Measured with no jitter on the input, using a K28.5 pattern, and a path consisting of the MAX3786 alone. Note 6: Jitter after EQ for the paths from RX to OUT_ or IN_ to TX. Measured with no jitter on the input, using a K28.5 pattern, and a path consisting of the MAX3786 plus 20in of 6-mil-wide differential stripline in FR-4 on the output. Note 7: Total time for LOS to enable/disable the outputs. Note 8: Measured with a 100mV sinusoidal common-mode signal in the 2MHz f 200MHz range. Note 1: Note 2: Note 3: Note 4: Note 5:
Typical Operating Characteristics
(VCC = 3.3V, TA = +25C, unless otherwise noted.)
TOTAL RESIDUAL JITTER vs. PATH LENGTH (FR-4 STRIPLINE AT OUT0, K28.5 PATTERN)
MAX3786 toc02
SUPPLY CURRENT vs. TEMPERATURE
MAX3786 toc01
DIFFERENTIAL INPUT RETURN LOSS
0 -5 -10
240 220 200 180 160 140 120 100 80 60 40 0
70 TOTAL RESIDUAL JITTER (psP-P) 60 50 40 30 20 10 0
CURRENT (mA)
PE AND EQ ON |S11| (dB)
-15 -20 -25
PE AND EQ OFF
-30 -35 -40
10
20
30
40
50
60
70
80
0
0.5
1.0
1.5
2.0
2.5
0
5
10
15
20
25
30
TEMPERATURE (C)
FREQUENCY (GHz)
FR-4 LENGTH (in)
_______________________________________________________________________________________
MAX3786 toc03
280 260
80
3
1.5Gbps Serial ATA-Compatible Mux/Buffer with Loopback and Equalization MAX3786
Typical Operating Characteristics (continued)
(VCC = 3.3V, TA = +25C, unless otherwise noted.)
OUTPUT SWING vs. INPUT SWING (K28.5 PATTERN)
MAX3786 toc04
600 500 OUTPUT SWING (mVP-P) 400 300 200 100 0 0 100 200 300 400 500
600
INPUT SWING (mVP-P)
OUTPUT EYE DIAGRAM, RECEIVE EQ ON (10in FR-4 STRIPLINE AT IN0, K28.5 PATTERN)
MAX3786 toc05
OUTPUT EYE DIAGRAM, TRANSMIT PE ON (10in FR-4 STRIPLINE AT OUT0, K28.5 PATTERN)
MAX3786 toc06
70mV/div
70mV/div
100ps/div
100ps/div
OUTPUT EYE DIAGRAM, RECEIVE EQ ON (20in FR-4 STRIPLINE AT IN0, K28.5 PATTERN)
MAX3786 toc07
OUTPUT EYE DIAGRAM, TRANSMIT PE ON (20in FR-4 STRIPLINE AT OUT0, K28.5 PATTERN)
MAX3786 toc08
70mV/div
70mV/div
100ps/div
100ps/div
4
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1.5Gbps Serial ATA-Compatible Mux/Buffer with Loopback and Equalization
Pin Description
PIN 1, 4, 8, 15, 17, 20, 21, 24, 26, 30 2 3 5 6 7 9 10 11 12 13 14 16, 25 18 19 22 23 27 28 29 31 32 EP NAME VCC TX+ TXSEL RXRX+ PE1EN EQ1EN LB_EN CM1 IN1IN1+ GND OUT1OUT1+ OUT0OUT0+ IN0IN0+ CM0 EQ0EN PE0EN Exposed pad +3.3V Supply Voltage Positive TX Data Output, CML. Serial ATA compatible. Negative TX Data Output, CML. Serial ATA compatible. Multiplex Select Control Input, LVCMOS. Set high to connect RX/TX to OUT1/IN1. Negative RX Data Input, CML. Serial ATA compatible. Positive RX Data Input, CML. Serial ATA compatible. Channel 1 Preemphasis Enable Input, LVCMOS. Set low to enable OUT1 PE. Channel 1 Equalization Enable Input, LVCMOS. Set low to enable IN1 EQ. Loopback Enable Input, LVCMOS. Set low to loopback data on nonselected channel. Input 1 Common-Mode Point. Normally not connected; can be connected to VCC through 1.0F capacitor. See Figure 1. Negative Channel 1 Data Input, CML. Serial ATA compatible. Positive Channel 1 Data Input, CML. Serial ATA compatible. Supply Ground Negative Channel 1 Data Output, CML. Serial ATA compatible. Positive Channel 1 Data Output, CML. Serial ATA compatible. Negative Channel 0 Data Output, CML. Serial ATA compatible. Positive Channel 0 Data Output, CML. Serial ATA compatible. Negative Channel 0 Data Input, CML. Serial ATA compatible. Positive Channel 0 Data Input, CML. Serial ATA compatible. Input 0 Common-Mode Point. Normally not connected; can be connected to VCC through 1.0F capacitor. See Figure 1. Channel 0 Equalization Enable Input, LVCMOS. Set low to enable IN0 EQ. Channel 0 Preemphasis Enable Input, LVCMOS. Set low to enable OUT0 PE. Ground. The exposed pad must be soldered to the circuit board ground for proper thermal and electrical performance. FUNCTION
MAX3786
Detailed Description
The MAX3786 consists of three multiplexers, I/O buffers, and LOS-detection circuitry (see the Functional Diagram). The buffers on the controller side provide EQ on the inputs and PE on the outputs.
from redundant controllers. Loopback is provided on the IN_/OUT_ side and is controlled by the LVCMOS input LB_EN. When LB_EN is low, the nonselected IN_/OUT_ loops back (see Table 1). The SEL and LB_EN control lines are internally pulled high through 40k resistors (see the Functional Diagram).
Mux/Buffer Logic
By means of the LVCMOS input SEL, a SATA-compatible device at TX/RX can be connected to either IN0/OUT0 or IN1/OUT1. When SEL is low, TX/RX are connected to IN0/OUT0, and when SEL is high, TX/RX are connected to IN1/OUT1. Use of the SEL input provides the ability to operate a single SATA disk drive
Loss-of-Signal Logic
At each high-speed input to the MAX3786, an LOS circuit is provided. In this circuit, a differential signal of 50mVP-P or less is detected as OFF, and a signal of greater than 150mVP-P is detected as ON. The LOS detectors, in combination with the select logic, control their associated high-speed output-disable circuits, so
5
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1.5Gbps Serial ATA-Compatible Mux/Buffer with Loopback and Equalization MAX3786
VCC VCC
IN_+
MAX3786
50 1.6k
50
50 OUT_+ OUT_-
CM_ VCC
VCC 0.2mA
50
2pF
IN_-
MAX3786
Figure 1. Input Structure (IN0, IN1)
Figure 2. Output Structure (OUT0, OUT1)
that OOB signaling is transmitted through the MAX3786 (see Table 1). The time for the LOS circuit to detect an inactive input and disable the associated output, or detect an active input and enable the output, is less than 5ns.
Output Terminations
The MAX3786 uses CML for its high-speed outputs. They are SATA compatible and provide 50 terminations to VCC (see Figure 2). The high-speed outputs must be AC-coupled to the controller IC and SATAcompatible disk drive for proper operation.
Equalization and Preemphasis
High-speed inputs IN0 and IN1 have integrated equalization, and high-speed outputs OUT0 and OUT1 have integrated PE to mitigate the effects of intersymbol interference in an FR-4 transmission line signal path. These circuits provide EQ or PE that matches the typical path loss of a 20in, 6-mil FR-4 differential stripline. Four active-low LVCMOS inputs, EQ0EN, EQ1EN, PE0EN, and PE1EN are provided to enable EQ and PE independently. All four control lines are internally pulled high through 40k resistors (see the Functional Diagram). EQ and PE should be enabled when the total path loss exceeds approximately 2.5dB.
Applications Information
Hot Swap
The MAX3786 is designed so that arbitrary sequencing of VCC and I/O signals during startup does not affect operation of the part.
Exposed-Pad Package
The MAX3786 is available in a 5mm 5mm, 32-pin thin QFN package with EP for signal integrity and placement flexibility. The exposed pad provides thermal and electrical connectivity to the IC, and must be soldered to a high-frequency ground plane. It is recommended to use at least nine vias to connect the ground pad underneath the 32-lead thin QFN package to the PC board ground plane.
Input Terminations
All high-speed inputs accept current-mode logic (CML) and are SATA compatible. The inputs contain internal 100 differential termination, and must be AC-coupled to the controller IC and SATA-compatible disk drive for proper operation. Two pins (CM0 and CM1) provide access to the IN0 and IN1 common-mode points. CM0 and CM1 are normally left unconnected; however, a capacitor up to 1.0F can be connected from each CM_ pin to VCC, providing a low-impedance AC common-mode path to VCC (see Figure 1).
6
Layout Considerations
Use controlled-impedance transmission lines to interface with the MAX3786 high-speed inputs and outputs. Power-supply decoupling capacitors should be placed as close as possible to the VCC pins.
_______________________________________________________________________________________
1.5Gbps Serial ATA-Compatible Mux/Buffer with Loopback and Equalization MAX3786
Table 1. Operation Truth Table
INPUT CONTROLS SEL Low Low Low Low Low Low Low Low Low Low Low Low High High High High High High High High High High High High LB_EN Low Low Low Low Low Low Low Low High High High High Low Low Low Low Low Low Low Low High High High High LOSS-OF-SIGNAL DETECT LOS_RX False False False False True True True True False False True True False False False False True True True True False False True True LOS_0 False False True True False False True True False True False True False False True True False False True True X X X X LOS_1 False True False True False True False True X X X X False True False True False True False True False True False True TX IN0 IN0 Off Off IN0 IN0 Off Off IN0 Off IN0 Off IN1 Off IN1 Off IN1 Off IN1 Off IN1 Off IN1 Off OUTPUT FUNCTION OUT0 RX RX RX RX Off Off Off Off RX RX Off Off IN0 IN0 Off Off IN0 IN0 Off Off Off Off Off Off OUT1 IN1 OFF IN1 Off IN1 Off IN1 Off Off Off Off Off RX RX RX RX Off Off Off Off RX RX Off Off
SEL = Low connects TX/RX to IN0/OUT0, high connects TX/RX to IN1/OUT1. LOS = True indicates loss of signal.
LB_EN = Low enables loopback of nonselected channel.
X = Don't care.
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7
1.5Gbps Serial ATA-Compatible Mux/Buffer with Loopback and Equalization MAX3786
Functional Diagram
EQ0EN LOS_0 0 TX 2 CML 1 LOS_1 RX PE0EN 2 CML VCC 1 40k SEL 0 1 (LOS_RX (AND) SEL) (OR) (LB_EN (AND) SEL) (OR) (LOS_1 (AND) SEL (AND) LB_EN) VCC 40k VCC 40k VCC 40k VCC 40k PE OUT1 2 LOS_RX 0 (LOS_RX (AND) SEL) (OR) (LB_EN (AND) SEL) (OR) (LOS_0 (AND) SEL (AND) LB_EN) PE OUT0 2 EQ 2 IN1 EQ1EN EQ 2 IN0
LOS_0 (AND) SEL (OR) LOS_1 (AND) SEL
PE1EN
VCC
MAX3786
40k
PE0EN
PE1EN
EQ0EN
EQ1EN
LB_EN
Pin Configuration
EQ0EN PE0EN CMO IN0+ IN0VCC VCC
Chip Information
TRANSISTOR COUNT: 2848 PROCESS: SiGe BiCMOS
32
31
30
29
28
27
26
25 24 23 22 21
GND
TOP VIEW
VCC
1 2 3 4 5 6 7 8 10 11 12 13 14 15 16
VCC OUT0+ OUT0VCC VCC OUT1+ OUT1VCC
TX+ TXVCC
SEL RXRX+
VCC
MAX3786
20 19 18 17
9
LB_EN
CM1
PE1EN
EQ1EN
QFN*
*THE EXPOSED PAD OF THE QFN PACKAGE MUST BE SOLDERED TO GROUND FOR PROPER THERMAL AND ELECTRICAL OPERATION.
8
_______________________________________________________________________________________
IN1+
GND
IN1-
VCC
1.5Gbps Serial ATA-Compatible Mux/Buffer with Loopback and Equalization
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QFN THIN.EPS
MAX3786
D2 D D/2 MARKING k L
C L
b D2/2
0.10 M C A B
XXXXX
E/2 E2/2 E (NE-1) X e
C L
E2
PIN # 1 I.D.
DETAIL A
e (ND-1) X e
PIN # 1 I.D. 0.35x45 DETAIL B
e
L1
L
C L
C L
L
L
e 0.10 C A 0.08 C
e
C
A1 A3
PACKAGE OUTLINE, 16, 20, 28, 32L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
G
1 2
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9
1.5Gbps Serial ATA-Compatible Mux/Buffer with Loopback and Equalization MAX3786
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
COMMON DIMENSIONS PKG. 20L 5x5 28L 5x5 32L 5x5 16L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. A A1 A3 b D E e k L L1 N ND NE JEDEC 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. PKG. CODES T1655-1 T1655-2 T1655N-1 T2055-2 T2055-3 T2055-4 T2055-5 T2855-1 T2855-2 T2855-3 T2855-4 T2855-5 T2855-6 T2855-7 T2855-8 T2855N-1 T3255-2 T3255-3 T3255-4 T3255N-1
EXPOSED PAD VARIATIONS
D2
MIN. NOM. MAX. MIN.
E2
NOM. MAX.
L
0.15
DOWN BONDS ALLOWED
3.00 3.00 3.00 3.00 3.00 3.00 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00
3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00
3.10 3.20 3.10 3.20 3.10 3.20 3.10 3.20 3.10 3.20 3.10 3.20 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20
0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.80 BSC. 0.65 BSC. 0.50 BSC. 0.50 BSC. - 0.25 - 0.25 0.25 - 0.25 0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 16 4 4 WHHB 20 5 5 WHHC 28 7 7 WHHD-1 32 8 8 WHHD-2 -
** ** ** ** ** ** 0.40 ** ** ** ** ** ** ** 0.40 ** ** ** ** **
NO YES NO NO YES NO Y NO NO YES YES NO NO YES Y N NO YES NO NO
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
** SEE COMMON DIMENSIONS TABLE
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1, T2855-3 AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. 11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. PACKAGE OUTLINE, 16, 20, 28, 32L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
G
2 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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