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74FST6800 10-Bit Bus Switch with Precharged Outputs
The ON Semiconductor 74FST6800 is a 10-bit bus switch with precharged outputs. The device is CMOS TTL compatible when operating between 4.0 and 5.5 Volts. The device exhibits extremely low RON and adds nearly zero propagation delay. The device adds no noise or ground bounce to the system.
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* * * * * * * *
RON t 4 W Typical Less Than 0.25 ns-Max Delay Through Switch Nearly Zero Standby Current No Circuit Bounce Control Inputs are TTL/CMOS Compatible Pin-For-Pin Compatible With QS6800, FST6800, CBT6800 All Popular Packages: SOIC-24, TSSOP-24, QSOP-24 All Devices in Package TSSOP are Inherently Pb-Free*
24 OE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BIASV
MARKING DIAGRAMS
24 24 1 SOIC-24 DW SUFFIX CASE 751E 1 FST6800 AWLYWW
24 FST 6800 ALYW 1
1 TSSOP-24 DT SUFFIX CASE 948H
24 1 QSOP-24 QS SUFFIX CASE 492B
24 FST6800 AWLYYWW 1
Figure 1. 24-Lead Pinout
TRUTH TABLE
OE L H B0-B9 A0-A9 Bias V Function Connect Precharge
A L, WL Y, YY W, WW
= = = =
Assembly Location Wafer Lot Year Work Week
NOTE: H = HIGH Voltage Level L = LOW Voltage Level
PIN NAMES
Pin OE A B Description Bus Switch Enable Bus A Bus B
ORDERING INFORMATION
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
June, 2006 - Rev. 6
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Publication Order Number: 74FST6800/D
74FST6800
13 2 23 Bias V B0
A0
A9
11
14
B9
OE
1
Figure 2. Logic Diagram ORDERING INFORMATION
Device Order Number 74FST6800DW 74FST6800DWR2 74FST6800DT 74FST6800DTR2 74FST6800QS Package SOIC-24 SOIC-24 TSSOP-24* (Pb-Free) TSSOP-24* (Pb-Free) QSOP-24 Shipping 48 Units / Rail 2500 Units / Tape & Reel 96 Units / Rail 2500 Units / Tape & Reel 96 Units / Rail
74FST6800QSR QSOP-24 2500 Units / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
MAXIMUM RATINGS
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG TL TJ qJA DC Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Range Lead Temperature, 1 mm from Case for 10 Seconds Junction Temperature Under Bias Thermal Resistance SOIC TSSOP QSOP Oxygen Index: 28 to 34 Human Body Model (Note 1) Machine Model (Note 2) Charged Device Model (Note 3) Above VCC and Below GND at 85C (Note 4) VI t GND VO t GND Parameter Value *0.5 to )7.0 *0.5 to )7.0 *0.5 to )7.0 *50 *50 128 $100 $100 *65 to )150 260 )150 125 170 200 Level 1 UL 94 V-0 @ 0.125 in u2000 u200 N/A $500 V Unit V V V mA mA mA mA mA C C C C/W
MSL FR VESD
Moisture Sensitivity Flammability Rating ESD Withstand Voltage
ILatchup
Latchup Performance
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Tested to EIA/JESD22-A114-A. 2. Tested to EIA/JESD22-A115-A. 3. Tested to JESD22-C101-A. 4. Tested to EIA/JESD78.
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74FST6800
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO TA Dt/DV Supply Voltage Input Voltage Output Voltage Operating Free-Air Temperature Input Transition Rise or Fall Rate Switch I/O Switch Control Input VCC = 5.0 V $ 0.5 V Parameter Operating, Data Retention Only (Note 5) (HIGH or LOW State) Min 4.0 0 0 *40 0 Max 5.5 5.5 5.5 )85 DC 5 Unit V V V C ns/V
5. Unused control inputs may not be left open. All control inputs must be tied to a high or low logic input voltage level.
DC ELECTRICAL CHARACTERISTICS
Symbol VIK VIH VIL II IOZ RON Parameter Clamp Diode Resistance High-Level Input Voltage Low-Level Input Voltage Input Leakage Current OFF-STATE Leakage Current Switch On Resistance (Note 6) 0 v VIN v 5.5 V 0 v A, B v VCC VIN = 0 V, IIN = 64 mA VIN = 0 V, IIN = 30 mA VIN = 2.4 V, IIN = 15 mA VIN = 2.4 V, IIN = 15 mA ICC DICC Quiescent Supply Current Increase In ICC per Input VIN = VCC or GND, IOUT = 0 One input at 3.4 V, Other inputs at VCC or GND IIN = *18mA Conditions VCC (V) 4.5 4.0 to 5.5 4.0 to 5.5 5.5 5.5 4.5 4.5 4.5 4.0 5.5 5.5 4 4 8 11 2.0 0.8 $1.0 $1.0 7 7 15 20 3 2.5 mA mA TA = *405C to )855C Min Typ* Max *1.2 Unit V V V mA mA W
*Typical values are at VCC = 5.0 V and TA = 25C. 6. Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the voltages on the two (A or B) pins.
AC ELECTRICAL CHARACTERISTICS
TA = *405C to )855C CL = 50 pF, RU = RD = 500 W VCC = 4.5-5.5 V Symbol tPHL, tPLH tPZH, tPZL tPHZ, tPLZ Parameter Prop Delay Bus to Bus (Note 7) Output Enable Time, IOE to Bus A, B Output Disable Time, IOE to Bus A, B Conditions VI = OPEN Bias V = GND VI = OPEN for tPZH Bias V = GND VI = OPEN for tPHZ 1.0 1.0 Min Max 0.25 5.1 5.5 VCC = 4.0 V Min Max 0.25 5.6 5.5 Unit ns ns ns
7. This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance).
CAPACITANCE (Note 8)
Symbol CIN CI/O Parameter Control Pin Input Capacitance A/B Port Input/Output Capacitance Conditions VCC = 5.0 V VCC, OE = 5.0 V Typ 3 5 Max Unit pF pF
8. TA = )25C, f = 1 MHz, Capacitance is characterized but not tested.
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74FST6800
AC Loading and Waveforms
VI FROM OUTPUT UNDER TEST 500 W
CL*
500 W
NOTES: 1. Input driven by 50 W source terminated in 50 W. 2. CL includes load and stray capacitance. *CL = 50 pF
Figure 3. AC Test Circuit
tf = 2.5 nS 90 % SWITCH INPUT 1.5 V 10 % tPLH 1.5 V 90 % 1.5 V
tf = 2.5 nS
3.0 V
10 % tPLH
GND VOH
OUTPUT
1.5 V VOL
Figure 4. Propagation Delays
tf = 2.5 nS tf = 2.5 nS ENABLE INPUT 90 % 1.5 V 10 % tPZL OUTPUT 1.5 V tPZH 10 % 90 % 1.5 V GND tPZL 3.0 V
VOL + 0.3 V VOL tPHZL VOH
1.5 V OUTPUT
VOH - 0.3 V
Figure 5. Enable/Disable Delays
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74FST6800
PACKAGE DIMENSIONS
SOIC-24 D SUFFIX CASE 751E-04 ISSUE E
13
-A-
24
-B-
12X
P 0.010 (0.25)
M
B
M
1
12
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0_ 8_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0_ 8_ 0.395 0.415 0.010 0.029
24X
D 0.010 (0.25)
M
J TA
S
B
S
F R C -T-
SEATING PLANE 22X X 45 _
G
K
M
TSSOP-24 DT SUFFIX CASE 948H-01 ISSUE A
24X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
2X
L/2
24
13
L
PIN 1 IDENT. 1 12
B -U-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 7.70 7.90 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.303 0.311 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
0.15 (0.006) T U
S
A -V-
C 0.10 (0.004) -T- SEATING
PLANE
D N
G 0.25 (0.010) M N F DETAIL E
H
K K1 J1
-W-
SECTION N-N J
CCC EE CCC EE
DETAIL E
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74FST6800
PACKAGE DIMENSIONS
QSOP-24 QS SUFFIX CASE 492B-01 ISSUE O
-A- R U -B-
RAD. 0.013 X 0.005 DP. MAX RAD. 0.005-0.010 TYP
Q H x 45_
MOLD PIN MARK
L
P 0.25 (0.010)
M
G T
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. THE BOTTOM PACKAGE SHALL BE BIGGER THAN THE TOP PACKAGE BY 4 MILS (NOTE: LEAD SIDE ONLY). BOTTOM PACKAGE DIMENSION SHALL FOLLOW THE DIMENSION STATED IN THIS DRAWING. 4. PLASTIC DIMENSIONS DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 6 MILS PER SIDE. 5. BOTTOM EJECTOR PIN WILL INCLUDE THE COUNTRY OF ORIGIN (COO) AND MOLD CAVITY I.D. INCHES DIM MAX MIN A 0.337 0.344 B 0.150 0.157 C 0.061 0.068 D 0.008 0.012 F 0.016 0.035 G 0.025 BSC H 0.008 0.018 J 0.0098 0.0075 K 0.004 0.010 L 0.230 0.244 M 0_ 8_ N 0_ 7_ P 0.027 0.037 Q 0.035 DIA R 0.035 0.045 U 0.035 0.045 V 0_ 8_ MILLIMETERS MAX MIN 8.56 8.74 3.81 3.99 1.55 1.73 0.20 0.31 0.41 0.89 0.64 BSC 0.20 0.46 0.249 0.191 0.10 0.25 5.84 6.20 0_ 8_ 0_ 7_ 0.69 0.94 0.89 DIA 0.89 1.14 0.89 1.14 0_ 8_
DETAIL E
V N 8 PL K -T-
SEATING PLANE M
J M
C
24 PL
D TB
S
F DETAIL E
0.25 (0.010)
A
S
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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74FST6800/D

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