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MC10175 Quint Latch
The MC10175 is a high speed, low power quint latch. It features five D type latches with common reset and a common two-input clock. Data is transferred on the negative edge of the clock and latched on the positive edge. The two clock inputs are "OR"ed together. Any change on the data input will be reflected at the outputs while the clock is low. The outputs are latched on the positive transition of the clock. While the clock is in the high state, a change in the information present at the data inputs will not affect the output information. The reset input is enabled only when the clock is in the high state. * PD = 400 mW typ/pkg (No Load) * tpd = 2.5 ns typ (Data to Output) * tr, tf = 2.0 ns typ (20%-80%)
LOGIC DIAGRAM
D0 10 D CR PLCC-20 FN SUFFIX CASE 775 A WL YY WW Q 14 Q0
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16 CDIP-16 L SUFFIX CASE 620 1 16 PDIP-16 P SUFFIX CASE 648 1 MC10175P AWLYYWW 1 10175 AWLYYWW MC10175L AWLYYWW
D1 12
D CR
Q
15 Q1
D2 13
D CR
Q
2
Q2
= Assembly Location = Wafer Lot = Year = Work Week
DIP PIN ASSIGNMENT
D3 9 D CR D4 5 C0 6 C1 7 RESET 11 D CR Q 4 Q4 VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 Q 3 Q3 VCC1 Q2 Q3 Q4 D4 C0 C1 Qn+1 L H Qn Qn L L VEE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC2 Q1 Q0 D2 D1 RESET D0 D3
TRUTH TABLE
D L H X X X X C0 L L H X H X C1 L L X H X H Reset X X L L H H
Pin assignment is for Dual-in-Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D).
ORDERING INFORMATION
Device MC10175L MC10175P MC10175FN Package CDIP-16 PDIP-16 PLCC-20 Shipping 25 Units / Rail 25 Units / Rail 46 Units / Rail
(c) Semiconductor Components Industries, LLC, 2002
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January, 2002 - Rev. 7
Publication Order Number: MC10175/D
MC10175
ELECTRICAL CHARACTERISTICS
Test Limits Pin Under Test 8 6 7 10 11 All 14 15 14 15 14 15 14 15 0.5 -1.060 -1.060 -1.890 -1.890 -1.080 -1.080 -1.655 -1.655 -0.890 -0.890 -1.675 -1.675 -30C Min Max 107 460 460 460 1000 0.5 -0.960 -0.960 -1.850 -1.850 -0.980 -0.980 -1.630 -1.630 -0.810 -0.810 -1.650 -1.650 Min +25C Typ 78 Max 97 290 290 290 650 0.3 -0.890 -0.890 -1.825 -1.825 -0.910 -0.910 -1.595 -1.595 -0.700 -0.700 -1.615 -1.615 Min +85C Max 107 290 290 290 650 Unit mAdc Adc
Characteristic Power Supply Drain Current Input Current
Symbol IE IinH
IinL Output Voltage Output Voltage Threshold Voltage Threshold Voltage Logic 1 Logic 0 Logic 1 Logic 0 VOH VOL VOHA VOLA
Adc Vdc Vdc Vdc Vdc ns
Switching Times (50 Load) Data Input Clock Input Reset Input Setup TIme Hold Time Rise Time Fall Time (20 to 80%) (20 to 80%) t10+14+ t10-14- t6-14+ t6-14- t11+4- t11+14- tsetup thold t+ t- 14 14 14 14 4 14 14 14 14 14 1.0 1.0 1.0 1.0 1.0 1.0 2.5 1.5 1.0 1.0 3.6 3.6 3.6 3.6 4.7 4.7 4.0 4.0 1.0 1.0 1.0 1.0 1.0 1.0 2.5 1.5 1.1 1.1 3.5 3.5 3.5 3.5 4.3 4.3 3.9 3.9 1.0 1.0 1.0 1.0 1.0 1.0 2.5 1.5 1.1 1.1 3.7 3.7 3.6 3.6 4.4 4.4 4.2 4.2
1. Individually test each input; apply VILmin to pin under test. 2. Output latched to high logic state prior to test.
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MC10175
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts) @ Test Temperature -30C +25C +85C Pin Under Test 8 6 7 10 11 All 14 15 14 15 14 15 14 15 +1.11V t10+14+ t10-14- t6-14+ t6-14- t11+4- t11+14- tsetup thold (20 to 80%) (20 to 80%) t+ t- 14 14 14 14 4 14 14 14 14 14 5 10 10 12 6 7 10 11 Note 1. 6 6 6, 10 6, 12 6 6 6 6 +0.31V 6, 7 6, 7 7 7 6 6 7 7 6, 7 6, 7 Pulse In 10 10 10, 6 10, 6 7, 11 7, 11 6, 10 6, 10 10 10 10 12 10 12 Pulse Out 14 14 14 14 4 (2.) 14 (2.) 14 14 14 14 VIHmax -0.890 -0.810 -0.700 VILmin -1.890 -1.850 -1.825 VIHAmin -1.205 -1.105 -1.035 VILAmax -1.500 -1.475 -1.440 VEE -5.2 -5.2 -5.2 (VCC) Gnd 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 +2.0 V 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16
TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIHmax VILmin VIHAmin VILAmax VEE 8 8 8 8 8 8 8 8 8 8 8 8 8 8 -3.2 V 8 8 8 8 8 8 8 8 8 8
Characteristic Power Supply Drain Current Input Current
Symbol IE IinH
IinL Output Voltage Output Voltage Threshold Voltage Threshold Voltage Switching Times Logic 1 Logic 0 Logic 1 Logic 0 (50 Load) Data Input Clock Input Reset Input Setup TIme Hold Time Rise Time Fall Time VOH VOL VOHA VOLA
1. Individually test each input; apply V ILmin to pin under test. 2. Output latched to high logic state prior to test. Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner.
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MC10175
PACKAGE DIMENSIONS
PLCC-20 FN SUFFIX PLASTIC PLCC PACKAGE CASE 775-02 ISSUE C
B -N- Y BRK D -L- -M- W D X V A Z R 0.007 (0.180) 0.007 (0.180)
M
0.007 (0.180) U
M
T L-M
M
S
N
S S
0.007 (0.180)
T L-M
N
S
Z
20
1
G1
0.010 (0.250)
S
T L-M
S
N
S
VIEW D-D T L-M T L-M
S
N N
S
H
0.007 (0.180)
M
T L-M
S
N
S
M
S
S
K1 K
C
E 0.004 (0.100) G G1 0.010 (0.250) S T L-M J -T-
SEATING PLANE
F VIEW S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
0.007 (0.180)
M
T L-M
S
N
S
VIEW S
S
N
S
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --0.025 --0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 --0.020 2_ 10 _ 0.310 0.330 0.040 ---
MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --0.64 --8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 --0.50 2_ 10 _ 7.88 8.38 1.02 ---
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MC10175
PACKAGE DIMENSIONS
CDIP-16 L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE T
-A-
16 9
-B-
1 8
C
L
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 --0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01
-T-
SEATING PLANE
N E F D G
16 PL
K M J
16 PL
0.25 (0.010)
M
M
TB
S
0.25 (0.010)
TA
S
-A-
16 9
PDIP-16 P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
B
1
8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
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MC10175
Notes
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MC10175
Notes
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MC10175
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-0031 Phone: 81-3-5740-2700 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative.
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MC10175/D

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