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| NTHS4111P Power MOSFET -30 V, -6.1 A, Single P-Channel, ChipFETt Features * * * * * * * * * Offers an Ultra Low RDS(on) Solution in the ChipFET Package ChipFET Package 40% Smaller Footprint than TSOP-6 Low Profile (<1.1 mm) for Extremely Thin Environments Standard Logic Level Gate Drive Pb-Free Package is Available http://onsemi.com V(BR)DSS -30 V RDS(on) Typ 33 mW @ -10 V 52 mW @ -4.5 V S ID Max -6.1 A Applications Notebook Computer Load Switch Battery and Load Management Applications in Portable Equipment Charge Control in Battery Chargers Buck and Boost Converters Rating Symbol VDSS VGS Steady State t 10 s Steady State t 10 s Steady State TA = 25C TA = 85C TA = 25C TA = 25C PD ID Value -30 20 -4.4 -3.2 -6.1 1.3 2.5 TA = 25C TA = 85C TA = 25C tp = 10 ms PD IDM TJ, TSTG IS TL ID -3.3 -2.3 0.7 -30 -55 to 150 -2.1 260 W A C A C TH M G A W 1 Unit V V A G MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current (Note 1) Power Dissipation (Note 1) Continuous Drain Current (Note 2) Power Dissipation (Note 2) Pulsed Drain Current D P-Channel MOSFET 8 ChipFET CASE 1206A STYLE 1 MARKING DIAGRAM 1 2 3 4 TH M G G 8 7 6 5 PIN CONNECTIONS D D D S 8 7 6 5 1 2 3 4 D D D G Operating Junction and Storage Temperature Source Current (Body Diode) Lead Temperature for Soldering Purposes (1/8 from case for 10 s) THERMAL RESISTANCE RATINGS Rating Junction-to-Ambient - Steady State (Note 1) Junction-to-Ambient - t 10 s (Note 1) Junction-to-Ambient - Steady State (Note 2) Symbol RqJA RqJA RqJA Max 95 50 175 Unit C/W = Specific Device Code = Date Code = Pb-Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device NTHS4111PT1 NTHS4111PT1G Package ChipFET ChipFET (Pb-free) Shipping 3000/Tape & Reel 3000/Tape & Reel Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface-mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces). 2. Surface-mounted on FR4 board using the minimum recommended pad size (Cu area = 0.045 in sq). For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Publication Order Number: NTHS4111P/D (c) Semiconductor Components Industries, LLC, 2006 August, 2006 - Rev. 2 1 NTHS4111P ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage Drain-to-Source Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate-to-Source Leakage Current ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain-to-Source On Resistance Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Gate-to-Source Charge Gate-to-Drain Charge VGS(TH) VGS(TH)/TJ RDS(on) gFS CISS COSS CRSS QG(TOT) QGS QGD td(ON) tr td(OFF) tf td(ON) tr td(OFF) tf Characteristic Forward Diode Voltage Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge Symbol VSD tRR ta tb QRR VGS = 0 V dIS/dt = 100 A/ms, IS = -1.1 A Test Condition VGS = 0 V, IS = -1.1 A TJ = 25C TJ = 125C Min VGS = -4.5 V, VDD = -15 V, ID = -1.0 A, RG = 6.0 W VGS = -10 V, VDD = -15 V, ID = -1.0 A, RG = 6.0 W VGS = -10 V, ID = -4.4 A VGS = -4.5 V, ID = -3.4 A VDS = -15 V, ID = -4.4 A CHARGES, CAPACITANCES AND GATE RESISTANCE 882 VGS = 0 V, f = 1.0 MHz, VDS = -24 V 143 105 18.2 VGS = -10 V, VDD = -15 V, ID = -4.4 A 2.95 4.25 ns 28 nC 1500 pF VGS = VDS, ID = -250 mA -1.0 -1.7 5.0 33 52 7.7 45 75 S -3.0 V mV/C mW V(BR)DSS V(BR)DSS/TJ IDSS IGSS VGS = 0 V, VDS = -24 V TJ = 25C TJ = 125C VGS = 0 V, ID = -250 mA -30 -19 -1.0 -100 100 nA V mV/C mA Symbol Test Condition Min Typ Max Unit VDS = 0 V, VGS = 20 V SWITCHING CHARACTERISTICS, VGS = -10 V (Note 4) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time 9.0 8.0 45 26 18 16 90 52 ns SWITCHING CHARACTERISTICS, VGS = -4.5 V (Note 4) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time DRAIN - SOURCE DIODE CHARACTERISTICS Typ -0.76 -0.60 27 10 17 12 nC 54 ns Max -1.2 Unit V 11 14 32 23 3. Pulse Test: pulse width v 300 ms, duty cycle v 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 NTHS4111P TYPICAL PERFORMANCE CURVES (TJ = 25C unless otherwise noted) 12 11 10 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 0 VGS = -10 V to -5.0 V -4.5 V -4.2 V -4.0 V -3.8 V -ID, DRAIN CURRENT (AMPS) -3.6 V 12 11 10 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 1.0 1.5 -55C VDS = -15 V -ID, DRAIN CURRENT (AMPS) -3.4 V TJ = 100C -3.2 V -3.0 V TJ = 25C 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 25C 2.0 2.5 3.0 3.5 4.0 4.5 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) Figure 1. On-Region Characteristics RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) 0.25 0.20 0.15 0.10 0.05 0 0.100 Figure 2. Transfer Characteristics ID = -4.4 A TJ = 25C TJ = 25C 0.075 VGS = -4.5 V VGS = -10 V 0.025 0.050 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 11 12 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) -ID, DRAIN CURRENT (AMPS) Figure 3. RDS(on) vs. VGS 100000 ID = -4.4 A VGS = -10 V -IDSS, LEAKAGE (nA) 10000 Figure 4. On-Resistance vs. Drain Current and Gate Voltage 1.5 RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) VGS = 0 V TJ = 150C 1.25 1.00 1000 TJ = 100C 0.75 0.5 -50 -25 0 25 50 75 100 125 150 100 10 20 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 30 TJ, JUNCTION TEMPERATURE (C) Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current vs. Voltage http://onsemi.com 3 NTHS4111P TYPICAL PERFORMANCE CURVES (TJ = 25C unless otherwise noted) -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 1600 1500 1400 Crss Ciss 1300 1200 1100 1000 900 800 700 600 500 400 Coss Crss 300 200 100 VDS = 0 V VGS = 0 V 0 10 0 10 5 5 -VGS -VDS TJ = 25C 10 8 VDS 6 10 4 2 0 QGS QGD VGS QT 20 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) C, CAPACITANCE (pF) Ciss 15 20 25 30 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Qg, TOTAL GATE CHARGE (nC) ID = -4.4 A TJ = 25C -GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation 100 -ID, DRAIN CURRENT (AMPS) 10 ms 100 ms 1 ms 1.0 VGS = -20 V Single Pulse TC = 25C RDS(on) Limit Thermal Limit Package Limit 1 10 10 ms 10 -IS, SOURCE CURRENT (AMPS) Figure 8. Gate-to-Source and Drain-to-Source Voltage vs. Total Charge 10 VGS = 0 V TJ = 25C 1 0.1 dc 100 0.01 0.1 0.1 0.4 150C 0.5 100C 0.6 25C 0.7 0.8 -55C 0.9 1.0 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) -VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) Figure 9. Maximum Rated Forward Biased Safe Operating Area Figure 10. Diode Forward Voltage vs. Current -VGS(TH), GATE-TO-SOURCE THRESHOLD VOLTAGE (NORMALIZED) 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 -50 -25 0 25 50 75 100 125 150 ID = -250 mA VGS = VDS TJ, JUNCTION TEMPERATURE (C) Figure 11. VGS(TH) Variation with Temperature http://onsemi.com 4 NTHS4111P Rthja(t), EFFECTIVE TRANSIENT THERMAL RESPONSE 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 Single Pulse 0.001 1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01 1E+02 1E+03 t, TIME (s) Figure 12. FET Thermal Response http://onsemi.com 5 NTHS4111P PACKAGE DIMENSIONS D 8 7 6 5 ChipFETt CASE 1206A-03 ISSUE G q L 5 6 3 7 2 8 1 HE 1 2 3 4 E 4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE. 4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL AND VERTICAL SHALL NOT EXCEED 0.08 MM. 5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS. 6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD SURFACE. DIM A b c D E e e1 L HE q MIN 1.00 0.25 0.10 2.95 1.55 MILLIMETERS NOM MAX 1.05 1.10 0.30 0.35 0.15 0.20 3.05 3.10 1.65 1.70 0.65 BSC 0.55 BSC 0.28 0.35 0.42 1.80 1.90 2.00 5 NOM MIN 0.039 0.010 0.004 0.116 0.061 INCHES NOM 0.041 0.012 0.006 0.120 0.065 0.025 BSC 0.022 BSC 0.011 0.014 0.071 0.075 5 NOM MAX 0.043 0.014 0.008 0.122 0.067 0.017 0.079 e1 e b c STYLE 1: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. GATE 5. SOURCE 6. DRAIN 7. DRAIN 8. DRAIN A 0.05 (0.002) SOLDERING FOOTPRINT* 2.032 0.08 1.727 0.068 0.457 0.018 0.711 0.028 0.178 0.007 mm 0.66 SCALE 20:1 inches 0.026 *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ChipFET is a trademark of Vishay Siliconix. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 6 NTHS4111P/D |
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