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 USBULC6-2F3
IPADTM Dual ultra low capacitance protection for high speed USB
Main application
Hi-Speed USB port in wireless handsets (up to 480 Mb/s according to USB 2.0 High Speed Specification)
Features

Ultra low diode capacitance (1.2 pF max) Two data lines (D+ and D-) protected against 15 kV ESD Breakdown Voltage VBR = 6.0 V min Flip-Chip 400 m pitch, lead-free Very low leakage current Very small PCB area RoHS compliant
Flip-Chip (4 Bumps)
Pin configuration (bump side)
A B 1 2
Description
The USBULC6-2F3 is a monolithic, application specific discrete device dedicated to ESD protection of high speed interfaces. Its ultra low line capacitance secures a high level of signal integrity without compromizing the protection of downstream sensitive chips against the most stringently characterized ESD strikes.
Configuration
A1 B1
Benefits

Minimized impact on rise and fall times for maximum data integrity Low PCB space occupation Higher reliability offered by monolithic integration
A2
B2
Note: B1 and B2 bumps must be grounded on the PCB together
Complies with the following standards:
IEC 61000-4-2: 15 kV (air discharge) 8 kV (contact discharge) MIL STD 883G - Method 3015.7 25 kV (Human body model)
Order code
Part Number USBULC6-2F3 Marking EH
TM: IPAD is a trademark of STMicroelectronics
December 2006
Rev 1
1/8
www.st.com
Characteristics
USBULC6-2F3
1
Characteristics
Table 1.
Symbol VPP PPP Tj Top Tstg
Absolute Maximum Ratings (Tamb = 25 C)
Parameter ESD discharge IEC 61000-4-2, air discharge ESD discharge IEC 61000-4-2, contact discharge Peak pulse power dissipation (8/20 s) Maximum junction temperature Operating temperature range Storage temperature range Value 15 8 60 125 -30 to + 85 -55 to +150 Unit kV W C C C
Table 2.
Symbol VBR IRM VRM VCL Rd IPP T VF
Electrical characteristics (Tamb = 25 C)
Parameter Breakdown voltage Leakage current @ VRM Stand-off voltage Clamping voltage Dynamic impedance Peak pulse current Voltage temperature coefficient Forward voltage drop Test conditions IR = 1 mA VRM = 3 V Exponential wave form 8/20 s, Ipp = 1 to 5 A IR = 1 mA VLINE = 0 V, VOSC = 30 mV, F = 1 MHz 1.6 5 1.2 Min. 6 Typ. Max. 9 100 Unit V nA 10-4/ pF C
Slope = 1/Rd
I
IF
VCL VBR VRM IRM
VF V
IPP
Symbol VBR IRM Rd T Cline
Figure 1.
Application diagram
USB CONNECTOR
Vbus
Vbus
B2 A2
D-
D-
D+
B1
A1
D+ GND
GND
TO USB TRANSCEIVER
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USBULC6-2F3
Characteristics
Figure 2.
Eye diagram, board only (according Figure 3. to USB High Speed)
Eye diagram, board with USBULC6-2F3 (according to USB 2.0 High Speed)
Board 480 Mb/s
USBULC6-2F3 480 Mb/s
Horiz: 350 ps/div Ver: 200 mV/div
Horiz: 350 ps/div Ver: 200 mV/div
Figure 4.
ESD response to IEC 61000-4-2 (+15 kV air discharge)
Figure 5.
ESD response to IEC 61000-4-2 (-15 kV air discharge
X: 50 ns/division Y: 20 V/division 1 Gs/s
X: 50 ns/division Y: 20 V/division 1 Gs/s
Figure 6.
C(pF)
Junction capacitance versus frequency (typical values)
VOSC=30 mVRMS Tj=25 C
Figure 7.
Analog crosstalk measurements
1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0
0.00
dB
USBULC6 -2F3
-30.00
-60.00
-90.00
F(Hz) 1.E+08 1.E+09
-120.00 100.0k 1.0M 10.0M
F (Hz)
100.0M 1.0G
1.E+07
3/8
Characteristics
USBULC6-2F3
Figure 8.
dB
0.00
S21 (dB) attenuation measurements
USBULC6-2F3
-2.00
-4.00
-6.00
-8.00
F (Hz)
-10.00 100.0k 1.0M 10.0M 100.0M 1.0G
Figure 9.
Digital crosstalk
90% Rise time = 1.647 ns INPUT: 1 V/div 0 mV offset 2 ns/div 5 Gs/s
10%
Vpkpk = 205 mV
OUTPUT: 100 m V/div -300 mV offset 2 ns/div 5 Gs/s
Figure 10. Relative variation of peak pulse power versus initial junction temperature
1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 25 50 75 100 125 150 Tj(C)
Figure 11. Peak pulse power versus exponential pulse duration
PPP(W)
Tj initial = 25 C
PPP[T j initial] / PPP [T j initial=25C]
1000
100
tP(s) 10 1 10 100
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USBULC6-2F3
Ordering information scheme
Figure 12. Clamping voltage versus peak pulse current (typical values, exponential waveform)
100.0
Figure 13. Relative variation of leakage current versus junction temperature (typical values)
IR [T j] / IR [T j=25C]
1.E+02
VR =3 V
IPP(A)
10.0
1.E+01
1.0
VCL(V) 0.1 0 10 20 30 40 50
8/20 s Tj initial =25 C
T j(C) 1.E+00
60
70
25
50
75
100
125
2
Ordering information scheme
USB ULC 6 - 2 F3
USB protection Ultra Low Capacitance Breakdown voltage 6 = 6 VMIN Number of lines 2 = 2 lines Package F = Flip-Chip 3: Lead free, Pitch = 400 m, Bump = 255 m
5/8
Package information
USBULC6-2F3
3
Package information
Figure 14. Flip-Chip dimensions
400 m 40
400 m 40 605 m 55
0.92 mm 30 m
255 m 40
Figure 15. Foot print recommendations Figure 16. Marking
0.97 mm 30m
Dot xx = marking z = manufacturing location yww = datecode (y = year ww = week)
Copper pad Diameter: 220m recommended 260m maximum Solder mask opening: 300m minimum
Solder stencil opening : 220m recommended
xxz y ww
6/8
USBULC6-2F3 Figure 17. Flip-Chip tape and reel specifications
Dot identifying Pin A1 location 4 +/- 0.1
Ordering information
O 1.5 +/- 0.1
1.75 +/- 0.1 3.5 +/- 0.1
1.07
8 +/- 0.3
1.02
xxz yww
xxz yww
xxz yww
0.71
4 +/- 0.1
All dimensions in mm
User direction of unreeling
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Note: More information is available in the application notes: AN2348: "400 m Flip-Chip: Package description and recommendations for use" AN1751: "EMI Filters: Recommendations and measurements"
4
Ordering information
Part Number USBULC6-2F3 Marking EH Package Flip-Chip Weight 1.16 mg Base qty 5000 Delivery mode Tape and reel (7")
5
Revision history
Date 15-Dec-2006 Revision 1 Initial release Changes
7/8
USBULC6-2F3
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