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| Features * High Performance, Low Power AVR(R)32 32-Bit Microcontroller - 210 DMIPS throughput at 150 MHz - 16 KB instruction cache and 16 KB data caches - Memory Management Unit enabling use of operating systems - Single-cycle RISC instruction set including SIMD and DSP instructions - Java Hardware Acceleration Multimedia Co-Processor - Vector Multiplication Unit for video acceleration through color-space conversion (YUV<->RGB), image scaling and filtering, quarter pixel motion compensation Multi-hierarchy bus system - High-performance data transfers on separate buses for increased performance Data Memories - 32KBytes SRAM External Memory Interface - SDRAM, DataFlashTM, SRAM, Multi Media Card (MMC), Secure Digital (SD), - Compact Flash, Smart Media, NAND Flash Direct Memory Access Controller - External Memory access without CPU intervention Interrupt Controller - Individually maskable Interrupts - Each interrupt request has a programmable priority and autovector address System Functions - Power and Clock Manager - Crystal Oscillator with Phase-Lock-Loop (PLL) - Watchdog Timer - Real-time Clock 6 Multifunction timer/counters - Three external clock inputs, I/O pins, PWM, capture and various counting capabilities 4 Universal Synchronous/Asynchronous Receiver/Transmitters (USART) - 115.2 kbps IrDA Modulation and Demodulation - Hardware and software handshaking 3 Synchronous Serial Protocol controllers - Supports I2S, SPI and generic frame-based protocols Two-Wire Interface - Sequential Read/Write Operations, Philips' I2C(c) compatible Liquid Crystal Display (LCD) interface - Supports TFT displays - Configurable pixel resolution supporting QCIF/QVGA/VGA/SVGA configurations. Image Sensor Interface - 12-bit Data Interface for CMOS cameras Universal Serial Bus (USB) 2.0 High Speed (480 Mbps) Device - On-chip Transceivers with physical interface 2 Ethernet MAC 10/100 Mbps interfaces - 802.3 Ethernet Media Access Controller - Supports Media Independent Interface (MII) and Reduced MII (RMII) 16-bit stereo audio DAC - Sample rates up to 50 kHz On-Chip Debug System - Nexus Class 3 - Full speed, non-intrusive data and program trace - Runtime control and JTAG interface Package/Pins - AT32AP7000: 256-ball CTBGA 1.0mm pitch/160 GPIO pins Power supplies - 1.65V to1.95V VDDCORE - 3.0V to 3.6V VDDIO * * * * AVR(R)32 32-bit Microcontroller AT32AP7000 Preliminary Summary * * * * * * * * * * * * * * * 32003HS-AVR32-02/07 AT32AP7000 1. Part Description The AT32AP7000 is a complete System-on-chip application processor with an AVR32 RISC processor achieving 210 DMIPS running at 150 MHz. AVR32 is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density and high application performance. AT32AP7000 implements a Memory Management Unit (MMU) and a flexible interrupt controller supporting modern operating systems and real-time operating systems. The processor also includes a rich set of DSP and SIMD instructions, specially designed for multimedia and telecom applications. AT32AP7000 incorporates SRAM memories on-chip for fast and secure access. For applications requiring additional memory, external 16-bit SRAM is accessible. Additionally, an SDRAM controller provides off-chip volatile memory access as well as controllers for all industry standard off-chip non-volatile memories, like Compact Flash, Multi Media Card (MMC), Secure Digital (SD)-card, SmartCard, NAND Flash and Atmel DataFlashTM. The Direct Memory Access controller for all the serial peripherals enables data transfer between memories without processor intervention. This reduces the processor overhead when transferring continuous and large data streams between modules in the MCU. The Timer/Counters includes three identical 16-bit timer/counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. AT32AP7000 also features an onboard LCD Controller, supporting single and double scan monochrome and color passive STN LCD modules and single scan active TFT LCD modules. On monochrome STN displays, up to 16 gray shades are supported using a time-based dithering algorithm and Frame Rate Control (FRC) method. This method is also used in color STN displays to generate up to 4096 colors. The LCD Controller is programmable for supporting resolutions up to 2048 x 2048 with a pixel depth from 1 to 24 bits per pixel. A pixel co-processor provides color space conversions for images and video, in addition to a wide variety of hardware filter support The media-independent interface (MII) and reduced MII (RMII) 10/100 Ethernet MAC modules provides on-chip solutions for network-connected devices. Synchronous Serial Controllers provide easy access to serial communication protocols, audio standards like I2S and frame-based protocols. The Java hardware acceleration implementation in AVR32 allows for a very high-speed Java byte-code execution. AVR32 implements Java instructions in hardware, reusing the existing RISC data path, which allows for a near-zero hardware overhead and cost with a very high performance. The Image Sensor Interface supports cameras with up to 12-bit data buses. PS2 connectivity is provided for standard input devices like mice and keyboards. 2 32003HS-AVR32-02/07 AT32AP7000 AT32AP7000 integrates a class 3 Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive real-time trace, full-speed read/write memory access in addition to basic runtime control. The C-compiler is closely linked to the architecture and is able to utilize code optimization features, both for size and speed. 3 32003HS-AVR32-02/07 AT32AP7000 2. Blockdiagram Figure 2-1. Blockdiagram TRST_N TCK TDO TDI TMS JTAG INTERFACE MCKO MDO[5..0] MSEO[1..0] EVTI_N EVTO_N NEXUS CLASS 3 OCD AP CPU MEMORY MANAGEMENT UNIT PIXEL COPROCESSOR INSTR CACHE PBB DATA CACHE D+ D- USB INTERFACE DMA DATA[11..0] HSYNC VSYNC PCLK COL, CRS, RXD[3..0], RX_CLK, RX_DV, RX_ER MDC, TXD[3..0], TX_CLK, TX_EN, TX_ER, SPEED MDIO LCD CONTRO LLER S M DMA IMAGE SENSOR INTERFACE INTRAM0 INTRAM1 DMA S M M M M M VSYNC, HSYNC, PW R, PCLK, MODE, DVAL, CC, DATA[22..0], GPL[7..0] HIGH SPEED BUS MATRIX S S M S MM S CONFIGURATION S REGISTERS BUS M MACB0 MACB1 PB HSB HSB HSB-PB BRIDGE B HSB-HSB BRIDGE PERIPHERAL DMA CONTROLLER HSB-PB BRIDGE A PB PBA EXTERNAL BUS INTERFACE (SDRAM & STATIC MEMORY CONTROLLER & ECC) S RAS, CAS, SDW E, NANDOE, NANDW E, SDCK, SDCKE, NW E3, NW E1, NW E0, NRD, NCS[3,1,0], ADDR[22..0] DATA[15..0] NW AIT SDCS, NCS[5,4,2] CFRNW , CFCE1, CFCE2, ADDR[23..25] DATA[31..16] RXD TXD CLK RTS, CTS Parallel Input/Output Controllers DMA CONTROLLER PA PB PC PD PE DATA0N DATA1N CLK CMD DATA[7..0] DMA DATA0 DATA1 AUDIO BITSTREAM DAC USART0 USART1 USART2 USART3 SERIAL PERIPHERAL INTERFACE 0/1 SYNCHRONOUS SERIAL CONTROLLER 0/1/2 Parallel Input/Output Controllers PA PB PC PD PE PDC SCK MISO, MOSI NPCS0 NPCS[3..1] TX_CLOCK, TX_FRAME_SYNC TX_DATA RX_CLOCK, RX_FRAME_SYNC RX_DATA MULTIMEDIA CARD INTERFACE SCLK SDI SSYNC SDO POW ER MANAGER XIN32 XOUT32 XIN0 XOUT0 XIN1 XOUT1 PLL0 PLL1 PDC AC97 CONTROLLER DMA DMA PDC 32 KHz OSC OSC0 OSC1 PLL0 PLL1 GCLK[3..0] OSCEN_N RESET_N TW O-W IRE INTERFACE SCL SDA CLOCK GENERATOR CLOCK[1..0] CLOCK CONTROLLER SLEEP CONTROLLER RESET CONTROLLER PS2 INTERFACE DATA[1..0] REAL TIME COUNTER W ATCHDOG TIMER INTERRUPT CONTROLLER PULSE W IDTH MODULATION CONTROLLER PW M0 PW M1 PW M2 PW M3 A[2..0] B[2..0] CLK[2..0] TIMER/COUNTER 0/1 EXTINT[7..0] KPS[7..0] NMI_N EXTERNAL INTERRUPT CONTROLLER 4 32003HS-AVR32-02/07 AT32AP7000 2.1 2.1.1 Processor and architecture AVR32AP CPU * 32-bit load/store AVR32B RISC architecture. Up to 15 general-purpose 32-bit registers. 32-bit Stack Pointer, Program Counter and Link Register reside in register file. Fully orthogonal instruction set. Privileged and unprivileged modes enabling efficient and secure Operating Systems. Innovative instruction set together with variable instruction length ensuring industry leading code density. - DSP extention with saturating arithmetic, and a wide variety of multiply instructions. - SIMD extention for media applications. 7 stage pipeline allows one instruction per clock cycle for most instructions. - Java Hardware Acceleration. - Byte, half-word, word and double word memory access. - Unaligned memory access. - Shadowed interrupt context for INT3 and multiple interrupt priority levels. - Dynamic branch prediction and return address stack for fast change-of-flow. - Coprocessor interface. Full MMU allows for operating systems with memory protection. 16Kbyte Instruction and 16Kbyte data caches. - Virtually indexed, physically tagged. - 4-way associative. - Write-through or write-back. Nexus Class 3 On-Chip Debug system. - Low-cost NanoTrace supported. - - - - - * * * * 2.1.2 Pixel Coprocessor (PiCo) * Coprocessor coupled to the AVR32 CPU Core through the TCB Bus. * Three parallel Vector Multiplication Units (VMU) where each unit can: - Multiply three pixel components with three coefficients. - Add the products from the multiplications together. - Accumulate the result or add an offset to the sum of the products. * Can be used for accelerating: - Image Color Space Conversion. * Configurable Conversion Coefficients. * Supports packed and planar input and output formats. * Supports subsampled input color spaces (i.e 4:2:2, 4:2:0). - Image filtering/scaling. * Configurable Filter Coefficients. * Throughput of one sample per cycle for a 9-tap FIR filter. * Can use the built-in accumulator to extend the FIR filter to more than 9-taps. * Can be used for bilinear/bicubic interpolations. - MPEG-4/H.264 Quarter Pixel Motion Compensation. * Flexible input Pixel Selector. - Can operate on numerous different image storage formats. * Flexible Output Pixel Inserter. - Scales and saturates the results back to 8-bit pixel values. 5 32003HS-AVR32-02/07 AT32AP7000 - Supports packed and planar output formats. * Configurable coefficients with flexible fixed-point representation. 2.1.3 Debug and Test system * * * * * * * IEEE1149.1 compliant JTAG and boundary scan Direct memory access and programming capabilities through JTAG interface Extensive On-Chip Debug features in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 3 Auxiliary port for high-speed trace information Hardware support for 6 Program and 2 data breakpoints Unlimited number of software breakpoints supported Advanced Program, Data, Ownership, and Watchpoint trace supported 2.1.4 DMA controller * 2 HSB Master Interfaces * 3 Channels * Software and Hardware Handshaking Interfaces * * * - 11 Hardware Handshaking Interfaces Memory/Non-Memory Peripherals to Memory/Non-Memory Peripherals Transfer Single-block DMA Transfer Multi-block DMA Transfer - Linked Lists - Auto-Reloading - Contiguous Blocks DMA Controller is Always the Flow Controller Additional Features - Scatter and Gather Operations - Channel Locking - Bus Locking - FIFO Mode - Pseudo Fly-by Operation * * 2.1.5 Peripheral DMA Controller * Transfers from/to peripheral to/from any memory space without intervention of the processor. * Next Pointer Support, forbids strong real-time constraints on buffer management. * Eighteen channels - Two for each USART - Two for each Serial Synchronous Controller - Two for each Serial Peripheral Interface 2.1.6 Bus system * HSB bus matrix with 10 Masters and 8 Slaves handled - Handles Requests from the CPU Icache, CPU Dcache, HSB bridge, HISI, USB 2.0 Controller, LCD Controller, Ethernet Controller 0, Ethernet Controller 1, DMA Controller 0, DMA Controller 1, and to internal SRAM 0, internal SRAM 1, PB A, PB B, EBI and, USB. 6 32003HS-AVR32-02/07 AT32AP7000 - Round-Robin Arbitration (three modes supported: no default master, last accessed default master, fixed default master) - Burst Breaking with Slot Cycle Limit - One Address Decoder Provided per Master * 2 Peripheral buses allowing each bus to run on different bus speeds. - PB A intended to run on low clock speeds, with peripherals connected to the PDC. - PB B intended to run on higher clock speeds, with peripherals connected to the DMAC. * HSB-HSB Bridge providing a low-speed HSB bus running at the same speed as PBA - Allows PDC transfers between a low-speed PB bus and a bus matrix of higher clock speeds An overview of the bus system is given in Figure 2-1 on page 4. All modules connected to the same bus use the same clock, but the clock to each module can be individually shut off by the Power Manager. The figure identifies the number of master and slave interfaces of each module connected to the HSB bus, and which DMA controller is connected to which peripheral. 7 32003HS-AVR32-02/07 AT32AP7000 2.2 Package and PinoutAVR32AP7000 256 CTBGA Pinout Figure 2-2. TOP VIEW Ball A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A B C D E F G H J K L M N P R T BOTTOM VIEW 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T AVR32 Table 2-1. 1 A VDDIO B GNDIO C PD01 D PE17 E PX48 F PX32 G PX04 H PD06 J TRST_N K PA05 L PA09 M PA14 N PA18 P PA20 R PA22 T VDDIO CTBGA256 Package Pinout A1..T8 2 PE15 PE16 PD00 PE18 PX50 PX00 VDDCORE VDDIO TMS PA01 PB25 PA11 PA16 PA19 PD10 GND 3 PE13 PE12 PE14 PD02 PX49 PX33 PX05 PD07 TDI PA02 VDDIO PA13 PA17 PA21 PA23 PA24 4 PE11 PE09 PE10 PE08 PX47 VDDIO PX03 PD05 TCK PA00 PA08 PA10 PA15 PD11 PD13 PD12 5 PE07 PE04 PE06 PE03 PE05 PX51 PX02 PD04 TDO RESET_N GND PA12 PD14 PD16 PD17 PD15 6 PE02 PLL0 PE00 GND PE01 AVDDPLL PX01 PD03 PD09 PA03 PB24 VDDIO GND XOUT1 AVDDUSB XIN1 7 AGNDPLL AVDDOSC PLL1 AGNDOSC XOUT32 XIN0 XOUT0 GND PD08 PA04 AGNDUSB VDDIO FSDM GND HSDM FSDP 8 OSCEN_N PC30 PC31 PC29 PC28 PC27 PC26 XIN32 EVTI_N HSDP VDDCORE GND VBG PA25 PA26 VDDIO 8 32003HS-AVR32-02/07 AT32AP7000 Table 2-2. 9 A PC23 B PC25 C PC24 D PC22 E VDDIO F PC21 G PC20 H PC09 J PB27 K PA27 L PA28 M PA29 N PA30 P WAKE_N R PA31 T PB26 CTBGA256 Package Pinout A9..T16 10 PA06 PC19 PA07 PC18 GND VDDCORE PC15 PC05 PX27 GND VDDIO PB28 PX53 PX41 PX52 PE25 11 PB21 PB23 PB22 PB20 PB19 GND PC14 PC06 PX28 PX22 PE24 PE20 PE22 PE21 PE23 PE19 12 PB16 PB18 PB17 PB15 PB00 PX44 PC10 PE26 PX29 PX23 PX38 PX08 PX06 PX09 PX07 PX10 13 PB13 PB14 PB12 PB03 PX46 PX42 PC11 VDDIO PX30 PX24 PX18 PX34 PX11 PB30 PB29 PX12 14 PB11 PB10 PB09 PB05 PB01 PX43 PC13 PC07 VDDCORE PX26 PX20 PX36 PX15 PC02 PC00 PC01 15 GND PC17 PB07 PB04 VDDIO PX40 PC12 PX39 GND VDDIO PX21 PX37 PX17 PX13 PC04 PC03 16 VDDIO PC16 PB08 PB06 PB02 PX45 VDDCORE PC08 PX31 PX25 PX19 PX35 PX16 PX14 GND VDDIO 9 32003HS-AVR32-02/07 AT32AP7000 3. Signals Description The following table gives details on the signal name classified by peripheral. The pinout multiplexing of these signals is given in the Peripheral Muxing table in the Peripherals chapter. Table 3-1. Signal Name Signal Description List Function Power Type Active Level Comments AVDDPLL AVDDUSB AVDDOSC VDDCORE VDDIO AGNDPLL AGNDUSB AGNDOSC GND PLL Power Supply USB Power Supply Oscillator Power Supply Core Power Supply I/O Power Supply PLL Ground USB Ground Oscillator Ground Ground Power Power Power Power Power Ground Ground Ground Ground Clocks, Oscillators, and PLL's 1.65 to 1.95 V 1.65 to 1.95 V 1.65 to 1.95 V 1.65 to 1.95 V 3.0 to 3.6V XIN0, XIN1, XIN32 XOUT0, XOUT1, XOUT32 PLL0, PLL1 Crystal 0, 1, 32 Input Crystal 0, 1, 32 Output PLL 0,1 Filter Pin JTAG Analog Analog Analog TCK TDI TDO TMS TRST_N Test Clock Test Data In Test Data Out Test Mode Select Test Reset Input Input Output Input Input Auxiliary Port - AUX Low MCKO MDO0 - MDO5 MSEO0 - MSEO1 EVTI_N Trace Data Output Clock Trace Data Output Trace Frame Control Event In Output Output Output Input Low 10 32003HS-AVR32-02/07 AT32AP7000 Table 3-1. Signal Name EVTO_N Signal Description List Function Event Out Type Output Power Manager - PM Active Level Low Comments GCLK0 - GCLK4 OSCEN_N RESET_N WAKE_N Generic Clock Pins Oscillator Enable Reset Pin Wake Pin Output Input Input Input External Interrupt Module - EIM Low Low Low EXTINT0 - EXTINT3 NMI_N External Interrupt Pins Non-Maskable Interrupt Pin Input Input AC97 Controller - AC97C Low SCLK SDI SDO SYNC AC97 Clock Signal AC97 Receive Signal AC97 Transmit Signal AC97 Frame Synchronization Signal DAC - DAC Input Output Output Input DATA0 - DATA1 DATAN0 - DATAN1 D/A Data Out D/A Inverted Data Out Output Output Ethernet MAC - MACB0, MACB1 COL CRS MDC MDIO RXD0 - RXD3 RX_CLK RX_DV RX_ER SPEED TXD0 - TXD3 Collision Detect Carrier Sense and Data Valid Management Data Clock Management Data Input/Output Receive Data Receive Clock Receive Data Valid Receive Coding Error Speed Transmit Data Input Input Output I/O Input Input Input Input Output Output 11 32003HS-AVR32-02/07 AT32AP7000 Table 3-1. Signal Name TX_CLK TX_EN TX_ER Signal Description List Function Transmit Clock or Reference Clock Transmit Enable Transmit Coding Error Type Input Output Output External Bus Interface - EBI Active Level Comments ADDR0 - ADDR25 CAS CFCE1 CFCE2 CFRNW DATA0 - DATA31 NANDOE NANDWE NCS0 - NCS5 NRD NWAIT NWE0 NWE1 NWE3 RAS SDA10 SDCK SDCKE SDCS SDWE Address Bus Column Signal Compact Flash 1 Chip Enable Compact Flash 2 Chip Enable Compact Flash Read Not Write Data Bus NAND Flash Output Enable NAND Flash Write Enable Chip Select Read Signal External Wait Signal Write Enable 0 Write Enable 1 Write Enable 3 Row Signal SDRAM Address 10 Line SDRAM Clock SDRAM Clock Enable SDRAM Chip Select SDRAM Write Enable Output Output Output Output Output I/O Output Output Output Output Input Output Output Output Output Output Output Output Output Output Image Sensor Interface - ISI Low Low Low Low Low Low Low Low Low Low Low Low Low Low DATA0 - DATA11 HSYNC PCLK Image Sensor Data Horizontal Synchronization Image Sensor Data Clock Input Input Input 12 32003HS-AVR32-02/07 AT32AP7000 Table 3-1. Signal Name VSYNC Signal Description List Function Vertical Synchronization Type Input LCD Controller - LCDC Active Level Comments CC DATA0 - DATA23 DVAL GPL0 - GPL7 HSYNC MODE PCLK PWR VSYNC LCD Contrast Control LCD Data Bus LCD Data Valid LCD General Purpose Lines LCD Horizontal Synchronization LCD Mode LCD Clock LCD Power LCD Vertical Synchronization Output Input Output Output Output Output Output Output Output Mulitmedia Card Interface - MMCI CLK CMD0 - CMD1 DATA0 - DATA7 Multimedia Card Clock Multimedia Card Command Multimedia Card Data Output I/O I/O Parallel Input/Output 2 - PIOA, PIOB, PIOC, PIOD, PIOE PA0 - PA31 PB0 - PB30 PC0 - PC31 PD0 - PD17 PE0 - PE26 Parallel I/O Controller PIOA Parallel I/O Controller PIOB Parallel I/O Controller PIOC Parallel I/O Controller PIOD Parallel I/O Controller PIOE PS2 Interface - PSIF CLOCK0 - CLOCK1 DATA0 - DATA1 PS2 Clock PS2 Data Input I/O Serial Peripheral Interface - SPI0, SPI1 MISO MOSI NPCS0 - NPCS3 Master In Slave Out Master Out Slave In SPI Peripheral Chip Select I/O I/O I/O Low I/O I/O I/O I/O I/O 13 32003HS-AVR32-02/07 AT32AP7000 Table 3-1. Signal Name SCK Signal Description List Function Clock Type Output Synchronous Serial Controller - SSC0, SSC1, SSC2 Active Level Comments RX_CLOCK RX_DATA RX_FRAME_SYNC TX_CLOCK TX_DATA TX_FRAME_SYNC SSC Receive Clock SSC Receive Data SSC Receive Frame Sync SSC Transmit Clock SSC Transmit Data SSC Transmit Frame Sync I/O Input I/O I/O Output I/O DMA Controller - DMAC DMARQ0 - DMARQ3 DMA Requests Input Timer/Counter - TIMER0, TIMER1 A0 A1 A2 B0 B1 B2 CLK0 CLK1 CLK2 Channel 0 Line A Channel 1 Line A Channel 2 Line A Channel 0 Line B Channel 1 Line B Channel 2 Line B Channel 0 External Clock Input Channel 1 External Clock Input Channel 2 External Clock Input I/O I/O I/O I/O I/O I/O Input Input Input Two-wire Interface - TWI SCL SDA Serial Clock Serial Data I/O I/O Universal Synchronous Asynchronous Receiver Transmitter - USART0, USART1, USART2, USART3 CLK CTS RTS RXD Clock Clear To Send Request To Send Receive Data I/O Input Output Input 14 32003HS-AVR32-02/07 AT32AP7000 Table 3-1. Signal Name TXD Signal Description List Function Transmit Data Type Output Pulse Width Modulator - PWM Active Level Comments PWM0 - PWM3 PWM Output Pins Output Universal Serial Bus Device - USB DDM DDP USB Device Port Data USB Device Port Data + Analog Analog Connected to a 6810 Ohm 0.5% resistor to gound and a 10 pF capacitor to ground. VBG USB bandgap Analog 15 32003HS-AVR32-02/07 AT32AP7000 4. Power Considerations 4.1 Power Supplies The AT32AP7000 has several types of power supply pins: * * * * * VDDCORE pins: Power the core, memories, and peripherals. Voltage is 1.8V nominal. VDDIO pins: Power I/O lines. Voltage is 3.3V nominal. VDDPLL pin: Powers the PLL. Voltage is 1.8V nominal. VDDUSB pin: Powers the USB. Voltage is 1.8V nominal. VDDOSC pin: Powers the oscillators. Voltage is 1.8V nominal. The ground pins GND are common to VDDCORE and VDDIO. The ground pin for VDDPLL is GNDPLL, and the GND pin for VDDOSC is GNDOSC. See "Electrical Characteristics" on page 928 for power consumption on the various supply pins. 4.2 Power Supply Connections Special considerations should be made when connecting the power and ground pins on a PCB. Figure 4-1 shows how this should be done. Figure 4-1. Connecting analog power supplies C54 0.10u AVDDUSB AVDDPLL AVDDOSC AGNDUSB AGNDPLL AGNDOSC C56 0.10u C55 0.10u 3.3uH VDDCORE VCC_1V8 16 32003HS-AVR32-02/07 AT32AP7000 5. I/O Line Considerations 5.1 JTAG pins The TMS, TDI and TCK pins have pull-up resistors. TDO is an output, driven at up to VDDIO, and have no pull-up resistor. The TRST_N pin is used to initialize the embedded JTAG TAP Controller when asserted at a low level. It is a schmitt input and integrates permanent pull-up resistor to VDDIO, so that it can be left unconnected for normal operations. 5.2 WAKE_N pin The WAKE_N pin is a schmitt trigger input integrating a permanent pull-up resistor to VDDIO. 5.3 RESET_N pin The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIO. As the product integrates a power-on reset cell, the RESET_N pin can be left unconnected in case no reset from the system needs to be applied to the product. 5.4 EVTI_N pin The EVTI_N pin is a schmitt input and integrates a non-programmable pull-up resistor to VDDIO. 5.5 TWI pins When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and inputs with inputs with spike-filtering. When used as GPIO-pins or used for other peripherals, the pins have the same characteristics as PIO pins. 5.6 PIO pins All the I/O lines integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers. After reset, I/O lines default as inputs with pull-up resistors enabled, except when indicated otherwise in the column "Reset State" of the PIO Controller multiplexing tables. 17 32003HS-AVR32-02/07 AT32AP7000 6. Memories 6.1 Embedded Memories * 32 Kbyte SRAM - Implemented as two 16Kbyte blocks - Single cycle access at full bus speed 6.2 Physical Memory Map The system bus is implemented as an HSB bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even in boot. Note that AT32AP7000 by default uses segment translation, as described in the AVR32 Architecture Manual. The 32 bit physical address space is mapped as follows: Table 6-1. Start Address 0x0000_0000 0x0400_0000 0x0800_0000 0x0C00_0000 0x1000_0000 0x2000_0000 0x2400_0000 0x2400_4000 0xFF00_0000 0xFF20_0000 0xFF30_0000 0xFFE0_0000 0xFFF0_0000 AT32AP7000 Physical Memory Map Size 64 Mbyte 64 Mbyte 64 Mbyte 64 Mbyte 256 Mbyte 64 Mbyte 16 Kbyte 16 Kbyte 4 Kbyte 1 KByte 1 MByte 1 MByte 1 MByte Device EBI SRAM CS0 EBI SRAM CS4 EBI SRAM CS2 EBI SRAM CS3 EBI SRAM/SDRAM CS1 EBI SRAM CS5 Internal SRAM 0 Internal SRAM1 LCDC configuration DMAC configuration USB Data PBA PBB Accesses to unused areas returns an error result to the master requesting such an access. The bus matrix has the several masters and slaves. Each master has its own bus and its own decoder, thus allowing a different memory mapping per master. The master number in the table below can be used to index the HMATRIX control registers. For example, MCFG2 is associated with the HSB-HSB bridge. 18 32003HS-AVR32-02/07 AT32AP7000 Table 6-2. Master 0 Master 1 Master 2 Master 3 Master 4 Master 5 Master 6 Master 7 Master 8 Master 9 HSB masters CPU Dcache CPU Icache HSB-HSB Bridge ISI DMA USB DMA LCD Controller DMA Ethernet MAC0 DMA Ethernet MAC1 DMA DMAC Master Interface 0 DMAC Master Interface 1 Each slave has its own arbiter, thus allowing a different arbitration per slave. The slave number in the table below can be used to index the HMATRIX control registers. For example, SCFG3 is associated with PBB. Table 6-3. Slave 0 Slave 1 Slave 2 Slave 3 Slave 4 Slave 5 Slave 6 Slave 7 HSB slaves Internal SRAM 0 Internal SRAM1 PBA PBB EBI USB data LCDC configuration DMAC configuration 19 32003HS-AVR32-02/07 AT32AP7000 7. Peripherals 7.1 Peripheral address map Peripheral Address Mapping Address Peripheral Name Bus Table 7-1. 0xFF000000 LCDC LCD Controller Slave Interface - LCDC HSB 0xFF200000 DMAC DMA Controller Slave Interface- DMAC HSB 0xFF300000 USB USB 2.0 Slave Interface - USB HSB 0xFFE00000 SPI0 Serial Peripheral Interface - SPI0 PB A 0xFFE00400 SPI1 Serial Peripheral Interface - SPI1 PB A 0xFFE00800 TWI Two-wire Interface - TWI Universal Synchronous Asynchronous Receiver Transmitter - USART0 Universal Synchronous Asynchronous Receiver Transmitter - USART1 Universal Synchronous Asynchronous Receiver Transmitter - USART2 Universal Synchronous Asynchronous Receiver Transmitter - USART3 Synchronous Serial Controller - SSC0 PB A 0xFFE00C00 USART0 PB A 0xFFE01000 USART1 PB A 0xFFE01400 USART2 PB A 0xFFE01800 USART3 PB A 0xFFE01C00 SSC0 PB A 0xFFE02000 SSC1 Synchronous Serial Controller - SSC1 PB A 0xFFE02400 SSC2 Synchronous Serial Controller - SSC2 PB A 0xFFE02800 PIOA Parallel Input/Output 2 - PIOA PB A 0xFFE02C00 PIOB Parallel Input/Output 2 - PIOB PB A 0xFFE03000 PIOC Parallel Input/Output 2 - PIOC PB A 0xFFE03400 PIOD Parallel Input/Output 2 - PIOD PB A 20 32003HS-AVR32-02/07 AT32AP7000 Table 7-1. Peripheral Address Mapping (Continued) Address Peripheral Name Bus 0xFFE03800 PIOE Parallel Input/Output 2 - PIOE PB A 0xFFE03C00 PSIF PS2 Interface - PSIF PB A 0xFFF00000 SM System Manager - SM PB B 0xFFF00400 INTC Interrupt Controller - INTC PB B 0xFFF00800 HMATRIX HSB Matrix - HMATRIX PB B 0xFFF00C00 TC0 Timer/Counter - TC0 PB B 0xFFF01000 TC1 Timer/Counter - TC1 PB B 0xFFF01400 PWM Pulse Width Modulation Controller - PWM PB B 0xFFF01800 MACB0 Ethernet MAC - MACB0 PB B 0xFFF01C00 MACB1 Ethernet MAC - MACB1 PB B 0xFFF02000 DAC DAC - Audio DAC PB B 0xFFF02400 MCI Mulitmedia Card Interface - MCI PB B 0xFFF02800 AC97C AC97 Controller - AC97C PB B 0xFFF02C00 ISI Image Sensor Interface - ISI PB B 0xFFF03000 USB USB 2.0 Configuration Interface - USB PB B 0xFFF03400 SMC Static Memory Controller - SMC PB B 0xFFF03800 SDRAMC SDRAM Controller - SDRAMC PB B 0xFFF03C00 ECC Error Correcting Code Controller - ECC PB B 21 32003HS-AVR32-02/07 AT32AP7000 7.2 Interrupt Request Signal Map The various modules may output interrupt request signals. These signals are routed to the Interrupt Controller (INTC). The Interrupt Controller supports up to 64 groups of interrupt requests. Each group can have up to 32 interrupt request signals. All interrupt signals in the same group share the same autovector address and priority level. Refer to the documentation for the individual submodules for a description of the semantic of the different interrupt requests. The interrupt request signals in AT32AP7000 are connected to the INTC as follows: Table 7-2. Group 0 Interrupt Request Signal Map Line 0 1 Signal COUNT-COMPARE match Performance Counter Overflow LCDC EOF LCDC LN LCDC LSTLN LCDC MER LCDC OWR LCDC UFLW DMAC BLOCK DMAC DSTT DMAC ERR DMAC SRCT DMAC TFR SPI 0 SPI 1 TWI USART0 USART1 USART2 USART3 SSC0 SSC1 SSC2 PIOA PIOB PIOC PIOD PIOE PSIF 1 0 1 2 3 4 5 2 0 1 2 3 4 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22 32003HS-AVR32-02/07 AT32AP7000 Table 7-2. Group 19 Interrupt Request Signal Map Line 0 1 2 3 Signal EIM0 EIM1 EIM2 EIM3 PM RTC TC00 TC01 TC02 TC10 TC11 TC12 PWM MACB0 MACB1 DAC MCI AC97C ISI USB EBI 20 21 22 0 0 0 1 2 23 0 1 2 24 25 26 27 28 29 30 31 32 0 0 0 0 0 0 0 0 0 7.3 DMAC Handshake Interface Map The following table details the hardware handshake map between the DMAC and the peripherals attached to it: : Table 7-3. Request MCI RX MCI TX DAC TX AC97C CHANNEL A RX AC97C CHANNEL A TX AC97C CHANNEL B RX AC97C CHANNEL B TX EXTERNAL DMA REQUEST 0 Hardware Handshaking Connection Hardware Handshaking Interface 0 1 2 3 4 5 6 7 23 32003HS-AVR32-02/07 AT32AP7000 Table 7-3. Request EXTERNAL DMA REQUEST 1 EXTERNAL DMA REQUEST 2 EXTERNAL DMA REQUEST 3 Hardware Handshaking Connection Hardware Handshaking Interface 8 9 10 24 32003HS-AVR32-02/07 AT32AP7000 7.4 7.4.1 Clock Connections Timer/Counters Each Timer/Counter channel can independently select an internal or external clock source for its counter: Table 7-4. Timer/Counter clock connections Source Internal Name TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 External XC0 XC1 XC2 1 Internal TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 External XC0 XC1 XC2 clk_slow clk_pbb / 4 clk_pbb / 8 clk_pbb / 16 clk_pbb / 32 See Section 7.7 Connection clk_slow clk_pbb / 4 clk_pbb / 8 clk_pbb / 16 clk_pbb / 32 See Section 7.7 Timer/Counter 0 7.4.2 USARTs Each USART can be connected to an internally divided clock: Table 7-5. USART 0 1 2 3 USART clock connections Source Internal Name CLK_DIV Connection clk_pba / 8 25 32003HS-AVR32-02/07 AT32AP7000 7.4.3 SPIs Each SPI can be connected to an internally divided clock: Table 7-6. SPI 0 1 SPI clock connections Source Internal Name CLK_DIV Connection clk_pba / 32 7.5 External Interrupt Pin Mapping External interrupt requests are connected to the following pins:: Table 7-7. Source NMI_N EXTINT0 EXTINT1 EXTINT2 EXTINT3 External Interrupt Pin Mapping Connection PB24 PB25 PB26 PB27 PB28 7.6 Nexus OCD AUX port connections If the OCD trace system is enabled, the trace system will take control over a number of pins, irrespectively of the PIO configuration. Two different OCD trace pin mappings are possible, depending on the configuration of the OCD AXS register. For details, see the AVR32 AP Technical Reference Manual. Table 7-8. Pin EVTI_N MDO[5] MDO[4] MDO[3] MDO[2] MDO[1] MDO[0] EVTO_N MCKO MSEO[1] MSEO[0] Nexus OCD AUX port connections AXS=0 EVTI_N PB09 PB08 PB07 PB06 PB05 PB04 PB03 PB02 PB01 PB00 AXS=1 EVTI_N PC18 PC14 PC12 PC11 PC06 PC05 PB28 PC02 PC01 PC00 26 32003HS-AVR32-02/07 AT32AP7000 7.7 Peripheral Multiplexing on IO lines The AT32AP7000 features five PIO controllers, PIOA to PIOE, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls up to thirty-two lines. Each line can be assigned to one of two peripheral functions, A or B. The tables in the following pages define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers. Note that some output only peripheral functions might be duplicated within the tables. 7.7.1 PIO Controller A Multiplexing Table 7-9. I/O Line PA00 PA01 PA02 PA03 PA04 PA05 PA06 PA07 PA08 PA09 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PIO Controller A Multiplexing Peripheral A SPI0 - MISO SPI0 - MOSI SPI0 - SCK SPI0 - NPCS[0] SPI0 - NPCS[1] SPI0 - NPCS[2] TWI - SDA TWI - SCL PSIF - CLOCK PSIF - DATA MCI - CLK MCI - CMD MCI - DATA[0] MCI - DATA[1] MCI - DATA[2] MCI - DATA[3] USART1 - CLK USART1 - RXD USART1 - TXD USART1 - RTS USART1 - CTS SSC0 - RX_FRAME_SYNC SSC0 - RX_CLOCK SSC0 - TX_CLOCK SSC0 - TX_FRAME_SYNC SSC0 - TX_DATA SSC0 - RX_DATA SPI1 - NPCS[3] PWM - PWM[0] Peripheral B SSC1 - RX_FRAME_SYNC SSC1 - TX_FRAME_SYNC SSC1 - TX_CLOCK SSC1 - RX_CLOCK SSC1 - TX_DATA SSC1 - RX_DATA USART0 - RTS USART0 - CTS USART0 - RXD USART0 - TXD USART0 - CLK TC0 - CLK0 TC0 - A0 TC0 - A1 TC0 - A2 TC0 - B0 TC0 - B1 TC0 - B2 TC0 - CLK2 TC0 - CLK1 SPI0 - NPCS[3] PWM - PWM[2] PWM - PWM[3] TC1 - A0 TC1 - A1 TC1 - B0 TC1 - B1 TC1 - CLK0 TC1 - A2 27 32003HS-AVR32-02/07 AT32AP7000 Table 7-9. PA29 PA30 PA31 PIO Controller A Multiplexing PWM - PWM[1] SM - GCLK[0] SM - GCLK[1] TC1 - B2 TC1 - CLK1 TC1 - CLK2 7.7.2 PIO Controller B Multiplexing Table 7-10. I/O Line PB00 PB01 PB02 PB03 PB04 PB05 PB06 PB07 PB08 PB09 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PIO Controller B Multiplexing Peripheral A ISI - DATA[0] ISI - DATA[1] ISI - DATA[2] ISI - DATA[3] ISI - DATA[4] ISI - DATA[5] ISI - DATA[6] ISI - DATA[7] ISI - HSYNC ISI - VSYNC ISI - PCLK PSIF - CLOCK[1] PSIF - DATA[1] SSC2 - TX_DATA SSC2 - RX_DATA SSC2 - TX_CLOCK SSC2 - TX_FRAME_SYNC SSC2 - RX_FRAME_SYNC SSC2 - RX_CLOCK SM - GCLK[2] DAC - DATA[1] DAC - DATA[0] DAC - DATAN[1] DAC - DATAN[0] NMI_N EXTINT0 EXTINT1 EXTINT2 EXTINT3 SM - GCLK[3] SM - GCLK[4] Peripheral B SPI1 - MISO SPI1 - MOSI SPI1 - NPCS[0] SPI1 - NPCS[1] SPI1 - NPCS[2] SPI1 - SCK MCI - CMD[1] MCI - DATA[4] MCI - DATA[5] MCI - DATA[6] MCI - DATA[7] ISI - DATA[8] ISI - DATA[9] ISI - DATA[10] ISI - DATA[11] USART3 - CTS USART3 - RTS USART3 - TXD USART3 - RXD USART3 - CLK AC97C - SDO AC97C - SYNC AC97C - SCLK AC97C - SDI DMAC - DMARQ[0] DMAC - DMARQ[1] USART2 - RXD USART2 - TXD USART2 - CLK USART2 - CTS USART2 - RTS 28 32003HS-AVR32-02/07 AT32AP7000 7.7.3 PIO Controller C Multiplexing Table 7-11. I/O Line PC00 PC01 PC02 PC03 PC04 PC05 PC06 PC07 PC08 PC09 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 PIO Controller C Multiplexing Peripheral A MACB0 - COL MACB0 - CRS MACB0 - TX_ER MACB0 - TXD[0] MACB0 - TXD[1] MACB0 - TXD[2] MACB0 - TXD[3] MACB0 - TX_EN MACB0 - TX_CLK MACB0 - RXD[0] MACB0 - RXD[1] MACB0 - RXD[2] MACB0 - RXD[3] MACB0 - RX_ER MACB0 - RX_CLK MACB0 - RX_DV MACB0 - MDC MACB0 - MDIO MACB0 - SPEED LCDC - CC LCDC - HSYNC LCDC - PCLK LCDC - VSYNC LCDC - DVAL LCDC - MODE LCDC - PWR LCDC - DATA[0] LCDC - DATA[1] LCDC - DATA[2] LCDC - DATA[3] LCDC - DATA[4] LCDC - DATA[5] MACB1 - TX_ER MACB1 - TXD[2] MACB1 - TXD[3] MACB1 - RXD[2] MACB1 - RXD[3] MACB1 - CRS MACB1 - RX_CLK MACB1 - COL DMAC - DMARQ[2] DMAC - DMARQ[3] Peripheral B 29 32003HS-AVR32-02/07 AT32AP7000 7.7.4 PIO Controller D Multiplexing Table 7-12. I/O Line PD00 PD01 PD02 PD03 PD04 PD05 PD06 PD07 PD08 PD09 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PIO Controller D Multiplexing Peripheral A LCDC - DATA[6] LCDC - DATA[7] LCDC - DATA[8] LCDC - DATA[9] LCDC - DATA[10] LCDC - DATA[11] LCDC - DATA[12] LCDC - DATA[13] LCDC - DATA[14] LCDC - DATA[15] LCDC - DATA[16] LCDC - DATA[17] LCDC - DATA[18] LCDC - DATA[19] LCDC - DATA[20] LCDC - DATA[21] LCDC - DATA[22] LCDC - DATA[23] MACB1 - RXD[0] MACB1 - TX_EN MACB1 - TX_CLK MACB1 - TXD[0] MACB1 - TXD[1] MACB1 - SPEED MACB1 - MDIO MACB1 - MDC MACB1 - RX_DV MACB1 - RX_ER MACB1 - RXD[1] Peripheral B 7.7.5 PIO Controller E Multiplexing Table 7-13. I/O Line PE00 PE01 PE02 PE03 PE04 PE05 PE06 PE07 PE08 PIO Controller E Multiplexing Peripheral A EBI - DATA[16] EBI - DATA[17] EBI - DATA[18] EBI - DATA[19] EBI - DATA[20] EBI - DATA[21] EBI - DATA[22] EBI - DATA[23] EBI - DATA[24] Peripheral B LCDC - CC LCDC - DVAL LCDC - MODE LCDC - DATA[0] LCDC - DATA[1] LCDC - DATA[2] LCDC - DATA[3] LCDC - DATA[4] LCDC - DATA[8] 30 32003HS-AVR32-02/07 AT32AP7000 Table 7-13. PE09 PE10 PE11 PE12 PE13 PE14 PE15 PE16 PE17 PE18 PE19 PE20 PE21 PE22 PE23 PE24 PE25 PE26 PIO Controller E Multiplexing EBI - DATA[25] EBI - DATA[26] EBI - DATA[27] EBI - DATA[28] EBI - DATA[29] EBI - DATA[30] EBI - DATA[31] EBI - ADDR[23] EBI - ADDR[24] EBI - ADDR[25] EBI - CFCE1 EBI - CFCE2 EBI - NCS[4] EBI - NCS[5] EBI - CFRNW EBI - NWAIT EBI - NCS[2] EBI - SDCS LCDC - DATA[9] LCDC - DATA[10] LCDC - DATA[11] LCDC - DATA[12] LCDC - DATA[16] LCDC - DATA[17] LCDC - DATA[18] LCDC - DATA[19] LCDC - DATA[20] LCDC - DATA[21] 31 32003HS-AVR32-02/07 AT32AP7000 7.7.6 IO Pins Without Multiplexing Many of the external EBI pins are not controlled by the PIO modules, but directly driven by the EBI. These pins have programmable pullup resistors. These resistors are controlled by Special Function Register 4 (SFR4) in the HMATRIX. The pullup on the lines multiplexed with PIO is controlled by the appropriate PIO control register. This SFR can also control CompactFlash, SmartMedia or NandFlash Support, see the EBI chapter for details 7.7.6.1 Name: Access Type: 31 - 23 - 15 - 7 - HMatrix SFR4 EBI Control Register HMATRIX_SFR4 Read/Write 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 EBI_CS5A 28 - 20 - 12 - 4 EBI_CS4A 27 - 19 - 11 - 3 EBI_CS3A 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 EBI_CS1A 24 - 16 - 8 EBI_DBPUC 0 - * CS1A: Chip Select 1 Assignment 0 = Chip Select 1 is assigned to the Static Memory Controller. 1 = Chip Select 1 is assigned to the SDRAM Controller. * CS3A: Chip Select 3 Assignment 0 = Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC. 1 = Chip Select 3 is assigned to the Static Memory Controller and the NAND Flash/SmartMedia Logic is activated. * CS4A: Chip Select 4 Assignment 0 = Chip Select 4 is assigned to the Static Memory Controller and NCS4, NCS5 and NCS6 behave as defined by the SMC. 1 = Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic is activated. * CS5A: Chip Select 5 Assignment 0 = Chip Select 5 is assigned to the Static Memory Controller and NCS4, NCS5 and NCS6 behave as defined by the SMC. 1 = Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic is activated. 32 32003HS-AVR32-02/07 AT32AP7000 Accessing the address space reserved to NCS5 and NCS6 may lead to an unpredictable outcome. * EBI_DBPUC: EBI Data Bus Pull-up Control 0: EBI D[15:0] are internally pulled up to the VDDIO power supply. The pull-up resistors are enabled after reset. 1: EBI D[15:0] are not internally pulled up. Table 7-14. I/O Line PX00 PX01 PX02 PX03 PX04 PX05 PX06 PX07 PX08 PX09 PX10 PX11 PX12 PX13 PX14 PX15 PX16 PX17 PX18 PX19 PX20 PX21 PX22 PX23 PX24 PX25 PX26 PX27 PX28 PX29 PX30 PX31 IO Pins without multiplexing Function EBI - DATA[0] EBI - DATA[1] EBI - DATA[2] EBI - DATA[3] EBI - DATA[4] EBI - DATA[5] EBI - DATA[6] EBI - DATA[7] EBI - DATA[8] EBI - DATA[9] EBI - DATA[10] EBI - DATA[11] EBI - DATA[12] EBI - DATA[13] EBI - DATA[14] EBI - DATA[15] EBI - ADDR[0] EBI - ADDR[1] EBI - ADDR[2] EBI - ADDR[3] EBI - ADDR[4] EBI - ADDR[5] EBI - ADDR[6] EBI - ADDR[7] EBI - ADDR[8] EBI - ADDR[9] EBI - ADDR[10] EBI - ADDR[11] EBI - ADDR[12] EBI - ADDR[13] EBI - ADDR[14] EBI - ADDR[15] 33 32003HS-AVR32-02/07 AT32AP7000 Table 7-14. PX32 PX33 PX34 PX35 PX36 PX37 PX38 PX39 PX40 PX41 PX42 PX43 PX44 PX45 PX46 PX47 PX48 PX49 PX50 PX51 PX52 PX53 IO Pins without multiplexing (Continued) EBI - ADDR[16] EBI - ADDR[17] EBI - ADDR[18] EBI - ADDR[19] EBI - ADDR[20] EBI - ADDR[21] EBI - ADDR[22] EBI - NCS[0] EBI - NCS[1] EBI - NCS[3] EBI - NRD EBI - NWE0 EBI - NWE1 EBI - NWE3 EBI - SDCK EBI - SDCKE EBI - RAS EBI - CAS EBI - SDWE EBI - SDA10 EBI - NANDOE EBI - NANDWE 34 32003HS-AVR32-02/07 AT32AP7000 7.8 7.8.1 Peripheral overview External Bus Interface * Optimized for Application Memory Space support * Integrates Three External Memory Controllers: - Static Memory Controller - SDRAM Controller - ECC Controller * Additional Logic for NAND Flash/SmartMediaTM and CompactFlashTM Support - SmartMedia support: 8-bit as well as 16-bit devices are supported - CompactFlash support: all modes (Attribute Memory, Common Memory, I/O, True IDE) are supported but the signals _IOIS16 (I/O and True IDE modes) and _ATA SEL (True IDE mode) are not handled. * Optimized External Bus: - 16- or 32-bit Data Bus - Up to 26-bit Address Bus, Up to 64-Mbytes Addressable - Optimized pin multiplexing to reduce latencies on External Memories * Up to 6 Chip Selects, Configurable Assignment: - Static Memory Controller on NCS0 - SDRAM Controller or Static Memory Controller on NCS1 - Static Memory Controller on NCS2 - Static Memory Controller on NCS3, Optional NAND Flash/SmartMediaTM Support - Static Memory Controller on NCS4 - NCS5, Optional CompactFlashTM Support 7.8.2 Static Memory Controller * 6 Chip Selects Available * 64-Mbyte Address Space per Chip Select * 8-, 16- or 32-bit Data Bus * Word, Halfword, Byte Transfers * Byte Write or Byte Select Lines * Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select * Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select * Programmable Data Float Time per Chip Select * Compliant with LCD Module * External Wait Request * Automatic Switch to Slow Clock Mode * Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes SDRAM Controller * Numerous Configurations Supported - 2K, 4K, 8K Row Address Memory Parts - SDRAM with Two or Four Internal Banks - SDRAM with 16- or 32-bit Data Path * Programming Facilities - Word, Half-word, Byte Access - Automatic Page Break When Memory Boundary Has Been Reached - Multibank Ping-pong Access - Timing Parameters Specified by Software - Automatic Refresh Operation, Refresh Rate is Programmable 7.8.3 35 32003HS-AVR32-02/07 AT32AP7000 * Energy-saving Capabilities - Self-refresh, Power-down and Deep Power Modes Supported - Supports Mobile SDRAM Devices Error Detection - Refresh Error Interrupt SDRAM Power-up Initialization by Software CAS Latency of 1, 2, 3 Supported Auto Precharge Command Not Used * 7.8.4 * * * Error Corrected Code Controller * Hardware Error Corrected Code (ECC) Generation - Detection and Correction by Software * Supports NAND Flash and SmartMediaTM Devices with 8- or 16-bit Data Path. * Supports NAND Flash/SmartMedia with Page Sizes of 528, 1056, 2112 and 4224 Bytes, Specified by Software 7.8.5 Serial Peripheral Interface * Supports communication with serial external devices - Four chip selects with external decoder support allow communication with up to 15 peripherals - Serial memories, such as DataFlashTM and 3-wire EEPROMs - Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors - External co-processors * Master or slave serial peripheral bus interface - 8- to 16-bit programmable data length per chip select - Programmable phase and polarity per chip select - Programmable transfer delays between consecutive transfers and between clock and data per chip select - Programmable delay between consecutive transfers - Selectable mode fault detection * Very fast transfers supported - Transfers with baud rates up to MCK - The chip select line may be left active to speed up transfers on the same device 7.8.6 Two-wire Interface * Compatibility with standard two-wire serial memory * One, two or three bytes for slave address * Sequential read/write operations 36 32003HS-AVR32-02/07 AT32AP7000 7.8.7 USART * Programmable Baud Rate Generator * 5- to 9-bit full-duplex synchronous or asynchronous serial communications - 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode - Parity generation and error detection - Framing error detection, overrun error detection - MSB- or LSB-first - Optional break generation and detection - By 8 or by-16 over-sampling receiver frequency - Hardware handshaking RTS-CTS - Receiver time-out and transmitter timeguard - Optional Multi-drop Mode with address generation and detection - Optional Manchester Encoding RS485 with driver control signal ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards - NACK handling, error counter with repetition and iteration limit IrDA modulation and demodulation - Communication at up to 115.2 Kbps Test Modes 46 - Remote Loopback, Local Loopback, Automatic Echo * * * * 7.8.8 Serial Synchronous Controller * Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader, etc.) * Contains an independent receiver and transmitter and a common clock divider * Offers a configurable frame sync and data length * Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal 7.8.9 * Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal AC97 Controller * Compatible with AC97 Component Specification V2.2 * Capable to Interface with a Single Analog Front end * Three independent RX Channels and three independent TX Channels - One RX and one TX channel dedicated to the AC97 Analog Front end control - One RX and one TX channel for data transfers, connected to the DMAC - One RX and one TX channel for data transfers, connected to the DMAC * Time Slot Assigner allowing to assign up to 12 time slots to a channel * Channels support mono or stereo up to 20 bit sample length - Variable sampling rate AC97 Codec Interface (48KHz and below) 37 32003HS-AVR32-02/07 AT32AP7000 7.8.10 Audio DAC * Digital Stereo DAC * Oversampled D/A conversion architecture - Oversampling ratio fixed 128x - FIR equalization filter - Digital interpolation filter: Comb4 - 3rd Order Sigma-Delta D/A converters * Digital bitstream outputs * Parallel interface * Connected to DMA Controller for background transfer without CPU intervention 7.8.11 Timer Counter * Three 16-bit Timer Counter Channels * Wide range of functions including: - Frequency Measurement - Event Counting - Interval Measurement - Pulse Generation - Delay Timing - Pulse Width Modulation - Up/down Capabilities * Each channel is user-configurable and contains: - Three external clock inputs - Five internal clock inputs - Two multi-purpose input/output signals * Two global registers that act on all three TC Channels 7.8.12 Pulse Width Modulation Controller * 4 channels, one 16-bit counter per channel * Common clock generator, providing Thirteen Different Clocks - A Modulo n counter providing eleven clocks - Two independent Linear Dividers working on modulo n counter outputs * Independent channel programming - Independent Enable Disable Commands - Independent Clock - Independent Period and Duty Cycle, with Double Bufferization - Programmable selection of the output waveform polarity - Programmable center or left aligned output waveform 38 32003HS-AVR32-02/07 AT32AP7000 7.8.13 Multimedia Card Interface * * * * * * * 2 double-channel Multimedia Card Interface, allowing concurrent transfers with 2 cards Compatibility with MultiMedia Card Specification Version 2.2 Compatibility with SD Memory Card Specification Version 1.0 Compatibility with SDIO Specification Version V1.0. Cards clock rate up to Master Clock divided by 2 Embedded power management to slow down clock rate when not used Each MCI has two slot, each supporting - One slot for one MultiMediaCard bus (up to 30 cards) or - One SD Memory Card * Support for stream, block and multi-block data read and write 7.8.14 PS/2 Keyboard Interface * Peripheral Bus slave * PS/2 Host * Receive and transmit capability * Parity generation and error detection * Overrun error detection USB Device Port * * * * * * USB V2.0 high-speed compliant, 480 Mbits per second Embedded USB V2.0 high-speed transceiver Embedded dual-port RAM for endpoints Suspend/Resume logic Ping-pong mode (two memory banks) for isochronous and bulk endpoints Six general-purpose endpoints - Endpoint 0, Endpoint 3: 8 bytes, no ping-pong mode - Endpoint 1, Endpoint 2: 64 bytes, ping-pong mode - Endpoint 4, Endpoint 5: 256 bytes, ping-pong mode 7.8.15 7.8.16 LCD Controller * * * * * * * * * * * Single and Dual scan color and monochrome passive STN LCD panels supported Single scan active TFT LCD panels supported 4-bit single scan, 8-bit single or dual scan, 16-bit dual scan STN interfaces supported Up to 24-bit single scan TFT interfaces supported Up to 16 gray levels for mono STN and up to 4096 colors for color STN displays 1, 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono STN 1, 2, 4, 8 bits per pixel (palletized), 16 bits per pixel (non-palletized) for color STN 1, 2, 4, 8 bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT Single clock domain architecture Resolution supported up to 2048x2048 2D-DMA Controller for management of virtual Frame Buffer - Allows management of frame buffer larger than the screen size and moving the view over this virtual frame buffer * Automatic resynchronization of the frame buffer pointer to prevent flickering * Configurable coefficients with flexible fixed-point representation. 39 32003HS-AVR32-02/07 AT32AP7000 7.8.17 Ethernet 10/100 MAC * * * * * * * * * * * * 7.8.18 Compatibility with IEEE Standard 802.3 10 and 100 Mbits per second data throughput capability Full- and half-duplex operations MII or RMII interface to the physical layer Register Interface to address, data, status and control registers DMA Interface, operating as a master on the Memory Controller Interrupt generation to signal receive and transmit completion 28-byte transmit and 28-byte receive FIFOs Automatic pad and CRC generation on transmitted frames Address checking logic to recognize four 48-bit addresses Support promiscuous mode where all valid frames are copied to memory Support physical layer management through MDIO interface control of alarm and update time/calendar data in Image Sensor Interface * * * * * * * ITU-R BT. 601/656 8-bit mode external interface support Support for ITU-R BT.656-4 SAV and EAV synchronization Vertical and horizontal resolutions up to 2048 x 2048 Preview Path up to 640*480 Support for packed data formatting for YCbCr 4:2:2 formats Preview scaler to generate smaller size image 50 Programmable frame capture rate 40 32003HS-AVR32-02/07 AT32AP7000 8. Boot Sequence This chapter summarizes the boot sequence of the AT32AP7000. The behaviour after power-up is controlled by the Power Manager. 8.1 Starting of clocks After power-up, the device will be held in a reset state by the Power-On Reset circuitry, until the power has stabilized throughout the device. Once the power has stabilized, the device will use the XIN0 pin as clock source. XIN0 can be connected either to an external clock, or a crystal. The OSCEN_N pin is connected either to VDD or GND to inform the Power Manager on how the XIN0 pin is connected. If XIN0 receives a signal from a crystal, dedicated circuitry in the Power Manager keeps the part in a reset state until the oscillator connected to XIN0 has settled. If XIN0 receives an external clock, no such settling delay is applied. On system start-up, the PLLs are disabled. All clocks to all modules are running. No clocks have a divided frequency, all parts of the system recieves a clock with the same frequency as the XIN0 clock. 8.2 Fetching of initial instructions After reset has been released, the AVR32AP CPU starts fetching instructions from the reset address, which is 0xA000_0000. This address lies in the P2 segment, which is non-translated, non-cacheable, and permanently mapped to the physical address range 0x0000_0000 to 0x2000_0000. This means that the instruction being fetched from virtual address 0xA000_0000 is being fetched from physical address 0x0000_0000. Physical address 0x0000_0000 is mapped to EBI SRAM CS0. This is the external memory the device boots from. The code read from the SRAM CS0 memory is free to configure the system to use for example the PLLs, to divide the frequency of the clock routed to some of the peripherals, and to gate the clocks to unused peripherals. 41 32003HS-AVR32-02/07 AT32AP7000 9. Ordering Information Figure 9-1. Ordering Information Package CTBGA256 CTBGA256 Package Type Green Green Packing Reel Tray Temperature Operating Range Industrial (-40C to 85C) Industrial (-40C to 85C) Ordering Code AT32AP7000-CTUR AT32AP7000-CTUT 42 32003HS-AVR32-02/07 AT32AP7000 10. Errata 10.1 Rev. C 1. SPI FDIV option does not work Selecting clock signal using FDIV = 1 does not work as specified. Fix/Workaround Do not set FDIV = 1. 2. SPI Chip Select 0 BITS field overrides other Chip Selects The BITS field for Chip Select 0 overrides BITS fields for other Chip selects. Fix/Workaround Update Chip Select 0 BITS field to the relevant settings before transmitting with Chip Selects other than 0. 3. SPI LASTXFER may be overwritten When Peripheral Select (PS) = 0, the LASTXFER-bit in the Transmit Data Register (TDR) should be internally discared. This fails and may cause problems during DMA transfers. Transmitting data using the PDC when PS=0, the size of the transferred data is 8- or 16-bits. The upper 16 bits of the TDR will be written to a random value. If Chip Select Active After Transfer (CSAAT) = 1, the behavior of the Chip Select will be unpredictable. Fix/Workaround - Do not use CSAAT = 1 if PS = 0 - Use GPIO to control Chip Select lines - Select PS=1 and store data for PCS and LASTXFER for each data in transmit buffer. 4. SPI LASTXFER overrides Chip Select The LASTXFER bit overrides Chip Select input when PS = 0 and CSAAT is used. Fix/Workaround - Do not use the CSAAT - Use GPIO as Chip Select input - Select PS = 1. Transfer 32-bit with correct LASTXFER settings. 5. MMC data drite operation with less than 12 bytes is impossible. The Data Write operation with a number of bytes less than 12 is impossible Fix/Workaround The PDC counters must always be equal to 12 bytes for data transfers lower than 12 bytes. The BLKLEN or BCNT field are used to specify the real count number. 43 32003HS-AVR32-02/07 AT32AP7000 6. MMC SDIO interrupt only works for slot A If 1-bit data bus width and on other slots than slot A, the SDIO interrupt can not be captured. Fix/Workaround Use slot A. 7. PSIF TXEN/RXEN may disable the transmitter/receiver Writing a '0' to RXEN will disable the receiver. Writing '0' to TXEN will disable the transmitter. Fix/Workaround When accessing the PS/2 Control Register always write '1' to RXEN to keep the receiver enabled, and write '1' to TXEN to keep the transmitter enabled. 8. PSIF TXRDY interrupt corrupts transfers When writing to the Transmit Holding Register (THR), the data will be transferred to the data shift register immediately, regardless of the state of the data shift register. If a transfer is ongoing, it will be interrupted and a new transfer will be started with the new data written to THR. Fix/Workaround Use the TXEMPTY-interrupt instead of the TXRDY-interrupt to update the THR. This ensures that a transfer is completed. 9. LCD memory error interupt does not work Writing to the MERIT-bit in the LCD Interrupt Test Register (ITR) does not cause an interrupt as intended. The MERIC-bit in the LCD Interrupt Clear Register (ICR) cannot be written. This means that if the MERIS-bit in ISR is set, it cannot be cleared. Fix/Workaround Memory error interrupt should not be used. 10. PWN counter restarts at 0x0001 The PWN counter restarts at 0x0001 and not 0x0000 as specified. Because of this the first PWM period has one more clock cycle. Fix/Workaround - The first period is 0x0000, 0x0001, ..., period - Consecutive periods are 0x0001, 0x0002, ..., period 11. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled. Fix/Workaround When using center aligned mode, enable the channel and read the status before channel interrupt is enabled. 12. PWM update period to a 0 value does not work It is impossible to update a period equal to 0 by the using the PWM update register (PWM_CUPD). 44 32003HS-AVR32-02/07 AT32AP7000 Fix/Workaround Do not update the PWM_CUPD register with a value equal to 0. 13. PWM channel status may be wrong if disabled before a period has elapsed Before a PWM period has elapsed, the read channel status may be wrong. The CHIDx-bit for a PWM channel in the PWM Enable Register will read '1' for one full PWM period even if the channel was disabled before the period elapsed. It will then read '0' as expected. Fix/Workaround Reading the PWM channel status of a disabled channel is only correct after a PWM period 14. TWI transfer error without ACK If the TWI does not receive an ACK from a slave during the address+R/W phase, no bits in the status register will be set to indicate this. Hence, the transfer will never complete. Fix/Workaround To prevent errors due to missing ACK, the software should use a timeout mechanism to terminate the transfer if this happens. 10.2 Rev. B Not sampled. 10.3 Rev. A 1. SPI FDIV option does not work Selecting clock signal using FDIV = 1 does not work as specified. Fix/Workaround Do not set FDIV = 1. 2. SPI Chip Select 0 BITS field overrides other Chip Selects The BITS field for Chip Select 0 overrides BITS fields for other Chip selects. Fix/Workaround Update Chip Select 0 BITS field to the relevant settings before transmitting with Chip Selects other than 0. 3. SPI LASTXFER may be overwritten When Peripheral Select (PS) = 0, the LASTXFER-bit in the Transmit Data Register (TDR) should be internally discared. This fails and may cause problems during DMA transfers. Transmitting data using the PDC when PS=0, the size of the transferred data is 8- or 16-bits. The upper 16 bits of the TDR will be written to a random value. If Chip Select Active After Transfer (CSAAT) = 1, the behavior of the Chip Select will be unpredictable. Fix/Workaround - Do not use CSAAT = 1 if PS = 0 - Use GPIO to control Chip Select lines - Select PS=1 and store data for PCS and LASTXFER for each data in transmit buffer. 4. MMC data drite operation with less than 12 bytes is impossible. The Data Write operation with a number of bytes less than 12 is impossible 45 32003HS-AVR32-02/07 AT32AP7000 Fix/Workaround The PDC counters must always be equal to 12 bytes for data transfers lower than 12 bytes. The BLKLEN or BCNT field are used to specify the real count number. 5. MMC SDIO interrupt only works for slot A If 1-bit data bus width and on other slots than slot A, the SDIO interrupt can not be captured. Fix/Workaround Use slot A. 6. PSIF TXEN/RXEN may disable the transmitter/receiver Writing a '0' to RXEN will disable the receiver. Writing '0' to TXEN will disable the transmitter. Fix/Workaround When accessing the PS/2 Control Register always write '1' to RXEN to keep the receiver enabled, and write '1' to TXEN to keep the transmitter enabled. 7. PSIF TXRDY interrupt corrupts transfers When writing to the Transmit Holding Register (THR), the data will be transferred to the data shift register immediately, regardless of the state of the data shift register. If a transfer is ongoing, it will be interrupted and a new transfer will be started with the new data written to THR. Fix/Workaround Use the TXEMPTY-interrupt instead of the TXRDY-interrupt to update the THR. This ensures that a transfer is completed. 8. PSIF Status Register bits return 0 The PARITY, NACK and OVRUN bits in the PSIF Status Register cannot be read. Reading these bits will always return zero. Fix/Workaround None 9. PSIF Transmit does not work as intended While PSIF receiving works, transmitting using the PSIF does not work. Fix/Workaround Do not transmit using the PSIF. 10. LCD memory error interupt does not work Writing to the MERIT-bit in the LCD Interrupt Test Register (ITR) does not cause an interrupt as intended. The MERIC-bit in the LCD Interrupt Clear Register (ICR) cannot be written. This means that if the MERIS-bit in ISR is set, it cannot be cleared. Fix/Workaround Memory error interrupt should not be used. 11. PWN counter restarts at 0x0001 The PWN counter restarts at 0x0001 and not 0x0000 as specified. Because of this the first PWM period has one more clock cycle. 46 32003HS-AVR32-02/07 AT32AP7000 Fix/Workaround - The first period is 0x0000, 0x0001, ..., period - Consecutive periods are 0x0001, 0x0002, ..., period 12. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled. Fix/Workaround When using center aligned mode, enable the channel and read the status before channel interrupt is enabled. 13. PWM update period to a 0 value does not work It is impossible to update a period equal to 0 by the using the PWM update register (PWM_CUPD). Fix/Workaround Do not update the PWM_CUPD register with a value equal to 0. 14. PWM channel status may be wrong if disabled before a period has elapsed Before a PWM period has elapsed, the read channel status may be wrong. The CHIDx-bit for a PWM channel in the PWM Enable Register will read '1' for one full PWM period even if the channel was disabled before the period elapsed. It will then read '0' as expected. Fix/Workaround Reading the PWM channel status of a disabled channel is only correct after a PWM period has elapsed. 15. Power Manager DIVEN-bit cannot be read The DIVEN-bit in the Generic Clock Control Register in the Power Manager cannot be read. Reading the register will give a wrong value for DIVEN. Writing to DIVEN works as intended. Fix/Workaround Do not read DIVEN. If needed, the written value must be store elsewhere. 16. Watchdog Timer cannot wake the part from sleep When the CPU has entered sleep mode, the watchdog timer will not be able to reset the system if a watchdog reset occurs. The problem is valid for all sleep modes. Fix/Workaround None. 17. Peripherals connected to wrong clock signal The frequency of the divided clocks for the SPI and the USART is set by the clock configuration for peripheral bus B (PBB) and not by peripheral bus A. Fix/Workaround Use clock settings for PBB for the SPI and USART. 18. JTAG CLAMP instruction does not work as intended 47 32003HS-AVR32-02/07 AT32AP7000 During the CLAMP instruction, the Boundary Scan register should be stable and only the BYPASS register selected. Instead, the bscan register will capture and shift as if it was selected, reducing the usefulness of the CLAMP instruction. Fix/Workaround None. 19. High current consumption in reset with no clocks enabled In connection with the datacache RAM access, a higher current consumption than expected can be observed during reset. The error is non-functional and does not affect reliability of the device. Fix/Workaround Via software, access the datacache RAM every 100 s. This prevents the increased current consumption. Example code: mov orh ld.w mov orh ld.w r11, lo(0x24002000) r11, hi(0x24002000) r11, r11[0] r10, lo(0x24000000) r10, hi(0x24000000) r10, r10[0] //access second RAM //access first RAM 20. TWI transfer error without ACK If the TWI does not receive an ACK from a slave during the address+R/W phase, no bits in the status register will be set to indicate this. Hence, the transfer will never complete. Fix/Workaround To prevent errors due to missing ACK, the software should use a timeout mechanism to terminate the transfer if this happens. 48 32003HS-AVR32-02/07 AT32AP7000 11. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 11.1 Rev. H 02/07 1. 2. 3. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. Updated "Features" on page 1. Updated "Part Description" on page 2. Added VBG pin in "Signals Description" on page 5. Changed direction in the EVTI_N signal in "Signals Description" on page 5. Updated "Blockdiagram" on page 4. Updated Registers in "Power Manager" on page 48. "Pulling OSCEN_N low" replaced by "Pulling OSCEN_N high" in "32 KHz oscillator operation" on page 104. Added note in "32 KHz oscillator operation" on page 104. Updated register names in "Real Time Counter" on page 119. Updated register names in "Watchdog Timer" on page 125. Updated register descriptions in "HSB Bus Matrix (HMATRIX)" on page 152. Updated CFRNW to a separate signal in "External Bus Interface (EBI)" on page 147. Updated register descriptions in "DMA Controller (DMAC)" on page 181. Added registers and updated register descriptions in "Parallel Input/Output Controller (PIO)" on page 256. Updated bit names in "Serial Peripheral Interface (SPI)" on page 297. Updated flow charts in "Two-wire Interface (TWI)" on page 326. Updated bit name in the PSR register in "PS/2 Module (PSIF)" on page 345. Added second instance of ps2 interface in "PS/2 Module (PSIF)" on page 345. Updated register descriptions in "Synchronous Serial Controller (SSC)" on page 357. Updated register names in "Static Memory Controller (SMC)" on page 500. Updated register names in "Error Corrected Code (ECC) Controller" on page 570. Updated register descriptions in "Ethernet MAC 10/100 (MACB)" on page 614. Updated register descriptions in "LCD Controller (LCDC)" on page 812. Updated register descriptions in "Image Sensor Interface (ISI)" on page 880. Removed JTAG specification references in "Debug and Test" on page 909. Updated "Electrical Characteristics" on page 928. Updated memory locations. 49 32003HS-AVR32-02/07 AT32AP7000 11.2 Rev. G 10/06 1. 2. 3. 4. Package text changed from CABGA to CTBGA. Occurrences of APB and AHB changed to Peripheral Bus (PB) and High Speed Bus (HSB) respectively. Updated "USB Device - High Speed (480 Mbits/s)" on page 687. Added "Errata" on page 43. 11.3 Rev. F 07/06 1. Removed 150CGU from "Ordering Information" on page 97. 11.4 Rev. E 05/06 1. Added "USB Device - High Speed (480 Mbits/s)" on page 665. 11.5 Rev. D 04/06 1. 2. 3. 4. 5. Some occurences of AP7000 renamed to AT32AP7000. Updated "Real Time Counter" on page 117. Updated "Audio DAC - (DAC)" on page 480 Updated "DC Characteristics" on page 89. Updated "Ordering Information" on page 97. 11.6 Rev. C 04/06 1. Initial revision. 50 32003HS-AVR32-02/07 AT32AP7000 Features ..................................................................................................... 1 1 2 Part Description ....................................................................................... 2 Blockdiagram ........................................................................................... 4 2.1Processor and architecture ........................................................................................5 2.2Package and PinoutAVR32AP7000 ..........................................................................8 3 4 Signals Description ................................................................................ 10 Power Considerations ........................................................................... 16 4.1Power Supplies ........................................................................................................16 4.2Power Supply Connections .....................................................................................16 5 I/O Line Considerations ......................................................................... 17 5.1JTAG pins ................................................................................................................17 5.2WAKE_N pin ............................................................................................................17 5.3RESET_N pin ..........................................................................................................17 5.4EVTI_N pin ..............................................................................................................17 5.5TWI pins ..................................................................................................................17 5.6PIO pins ...................................................................................................................17 6 Memories ................................................................................................ 18 6.1Embedded Memories ..............................................................................................18 6.2Physical Memory Map .............................................................................................18 7 Peripherals .............................................................................................. 20 7.1Peripheral address map ..........................................................................................20 7.2Interrupt Request Signal Map ..................................................................................22 7.3DMAC Handshake Interface Map ............................................................................23 7.4Clock Connections ...................................................................................................25 7.5External Interrupt Pin Mapping ................................................................................26 7.6Nexus OCD AUX port connections ..........................................................................26 7.7Peripheral Multiplexing on IO lines ..........................................................................27 7.8Peripheral overview .................................................................................................35 8 Boot Sequence ....................................................................................... 41 8.1Starting of clocks .....................................................................................................41 8.2Fetching of initial instructions ..................................................................................41 9 Ordering Information ............................................................................. 42 10 Errata ....................................................................................................... 43 i 32003HS-AVR32-02/07 AT32AP7000 10.1Rev. C ....................................................................................................................43 10.2Rev. B ....................................................................................................................45 10.3Rev. A ....................................................................................................................45 11 Datasheet Revision History ................................................................... 49 11.1Rev. H 02/07 ..........................................................................................................49 11.2Rev. G 10/06 .........................................................................................................50 11.3Rev. F 07/06 ..........................................................................................................50 11.4Rev. E 05/06 ..........................................................................................................50 11.5Rev. D 04/06 ..........................................................................................................50 11.6Rev. C 04/06 ..........................................................................................................50 ii 32003HS-AVR32-02/07 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. (c) 2007 Atmel Corporation. All rights reserved. ATMEL (R), logo and combinations thereof, Everywhere You Are (R), AVR (R), AVR Studio (R), and others, are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 32003HS-AVR32-02/07 |
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