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LTC4350 Hot Swappable Load Share Controller
FEATURES

DESCRIPTIO
Build N + 1 Redundant Supply Hot SwapTM Power Supplies Isolates Supply Failures from Output Eliminates ORing Diodes Identifies and Localizes Output Low, Output High and Open-Circuit Faults Output Voltages from 1.5V to 12V 16-Lead Narrow SSOP Package
APPLICATIO S

The LTC(R)4350 is a load share controller that allows systems to equally load multiple power supplies connected in parallel. The output voltage of each supply is adjusted using the SENSE + input until all currents match the share bus. The LTC4350 also isolates supply failures by turning off the series pass transistors and identifying the failed supply. The failed supply can then be removed and replaced with a new unit without turning off the system power. The LTC4350 is available in a 16-pin narrow SSOP package.
, LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation.
Servers and Network Equipment Telecom and Base Station Equipment Distributed Power Systems
TYPICAL APPLICATIO
SENSE + OUT +
5V Load Share (5A per Module)
VOUT+ SHARE BUS VOUT- SUD50N03-07 0.010
51 0.1F VICOR* VI-J30-CY 274k 43.2k 0.1F
100
GATE VCC UV
R
+
R
-
FB IOUT
LTC4350
STATUS SB
0.1F TRIM 470k SENSE - OUT -
121k
12.1k 0.1F
OV TIMER GAIN COMP1
RSET GND COMP2 4.7F 150 100
1000pF 34k
SENSE + OUT + SUD50N03-07 0.010
51 0.1F VICOR* VI-J30-CY 274k 43.2k 0.1F
100
GATE VCC UV
R+
R-
FB IOUT
LTC4350
STATUS SB
0.1F TRIM 470k SENSE - OUT -
121k
12.1k 0.1F
OV TIMER GAIN COMP1
RSET GND COMP2 4.7F 150 100
1000pF 34k
*LOAD SHARING CIRCUIT WORKS WITH MOST POWER SUPPLIES THAT HAVE A SENSE + OR FB PIN
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37.4k 12.1k STATUS 37.4k 12.1k STATUS
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Note 1: A
LTC4350
ABSOLUTE MAXIMUM RATINGS
(Note 1)
PACKAGE/ORDER INFORMATION
TOP VIEW UV OV TIMER GAIN COMP2 COMP1 SB GND 1 2 3 4 5 6 7 8 16 VCC 15 STATUS 14 GATE 13 R + 12 R - 11 IOUT 10 RSET 9 FB
Supply Voltage (VCC) ............................................... 17V Input Voltage TIMER ..................................................- 0.3V to 1.2V R+, R- (Note 2) ......................................- 0.3V to 17V FB ........................................................ - 0.3V to 5.3V OV, UV .......................................................- 0.3V to 17V Output Voltage COMP1 ................................................... - 0.3V to 6V COMP2 ................................................... - 0.3V to 3V GAIN, SB ............................................. - 0.3V to 5.6V GATE (Note 3) ...........................................- 0.3V to 20V IOUT, STATUS ........................................... - 0.3V to 17V RSET ....................................................................... - 0.3V to 1V Operating Temperature Range LTC4350C ............................................... 0C to 70C LTC4350I ........................................... - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC4350CGN LTC4350IGN
GN PART MARKING 4350 4350I
GN PACKAGE 16-LEAD PLASTIC SSOP
TJMAX = 150C, JA = 135C/W
Consult LTC marketing for parts specified with wider operating temperature ranges.
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 5V unless otherwise noted.
SYMBOL PARAMETER DC Characteristics ICC VCC Supply Current VLKOH VCC Undervoltage Lockout High VLKOL VCC Undervoltage Lockout Low VFB FB Pin Voltage VFBLIR VFBLOR VUVTH VOVTH VTM ITM VG VGO VSB(MIN) VSB(MAX) ISB(MAX) RSB VE/A2OFF FB Line Regulation FB Load Regulation UV Pin Threshold OV Pin Threshold TIMER Pin Threshold TIMER Pin Current GAIN Pin Voltage GAIN Pin Offset SB Pin Minimum Voltage SB Pin Maximum Voltage SB Pin Maximum Current SB Pin Resistor Value E/A2 Offset CONDITIONS UV = VCC

ELECTRICAL CHARACTERISTICS
MIN 1.0 2.36 2.24 1.208 1.196
TYP 1.6 2.45 2.34 1.220 1.220 0.02 - 0.0008 0.003 1.244 1.220 1.220 1.205 1.22 -2 -6 2.5 0.02 2 2.7 7.8 - 33 20 25
MAX 2.0 2.52 2.44 1.236 1.244 0.05 - 0.1 0.1 1.258 1.237 1.250 1.229 1.26 - 2.3 - 6.7 2.7 0.20 8 2.9 10.5 - 41 33 50
UNITS mA V V V V %/V % % V V V V V A A V V mV V V mA k mV
0C to 85C (LTC4350I) or 0C to 70C (LTC4350C) - 40C to 85C (LTC4350I) VCC = 3.3V to 12V, COMP1 = 1.240V COMP1 = 2V COMP1 = 0.64V High Going Threshold Low Going Threshold High Going Threshold Low Going Threshold TIMER On, VTIMER = 0V TIMER On, VTIMER = 0V, VOV > VOVTH RGAIN = 25k, (VR+ - VR-) = 100mV RGAIN = 25k, (VR+ - VR-) = 0mV VCC = 3.3V VCC = 12V VSB = 0V VSB - VGAIN

1.215 1.205 1.203 1.180 1.18 - 1.75 - 5.30 2.3 0 2.4 5.6 -8 14 8
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LTC4350
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 5V unless otherwise noted.
SYMBOL PARAMETER DC Characteristics VRSET(MAX) RSET Pin Maximum Voltage VRSET(MIN) IRSET(MAX) VRCTH VGATE IGATE VSOL RSET Pin Minimum Voltage RSET Pin Maximum Current Reverse Current Threshold External N-Channel Gate Drive GATE Pin Current STATUS Pin Output Low CONDITIONS VCC = 3.3V, RSET = 100 VCC = 12V, RSET = 100 VCC = 5V, RSET = 1000 VCC = 5V, RSET = 100 RSET = 50, VIOUT = 1.1V V R+ - V R+ VGATE - VCC Gate On, VGATE = 0V IOUT = 3mA

ELECTRICAL CHARACTERISTICS
MIN 0.94 0.94
TYP 1 1 0.001 0.001 20 30 12 -10 0.3
MAX 1.03 1.03 0.5 0.5 21 40 12.7 - 12 1.2
UNITS V V V V mA mV V A V
18 10 10.8 -8 0.1
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: R+ and R- could be at 17V while VCC = 0V.
Note 3: An internal clamp limits the GATE pin to a minimum of 10.8V above VCC. Driving this pin to voltages beyond the clamp may damage the part.
TYPICAL PERFOR A CE CHARACTERISTICS
ICC vs VCC
3.5 TA = 25C
3.0
1.62
ICC (mA)
ICC (mA)
2.5
UV THRESHOLD (V)
2.0
1.5
1.0 0 2 4 8 6 VCC (V) 10 12 14
UV Threshold vs Temperature
1.255 1.250 1.245 VCC = 5V
1.222 1.220 1.218 OV THRESHOLD (V)
UV THRESHOLD (V)
1.240 1.235 1.230 1.225 1.220 1.215 -50 -25 0 25 50 TEMPERATURE (C) 75 100
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1.214 1.212 1.210 1.208 1.206 1.204 1.202 0 2 4 8 6 VCC (V) 10 12 14
OV THRESHOLD (V)
UW
ICC vs Temperature
1.66 1.64
UV Threshold vs VCC
1.250 TA = 25C 1.245 1.240 1.235 1.230 1.225 1.220 1.215 0 2 4 8 6 VCC (V) 10 12 14
VCC = 5V
1.60 1.58 1.56 1.54 -50
-25
50 25 0 TEMPERATURE (C)
75
100
4350 G02
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OV Threshold vs VCC
TA = 25C
OV Threshold vs Temperature
1.225 VCC = 5V 1.220
1.216
1.215
1.210
1.205
1.200 -50
-25
0 25 50 TEMPERATURE (C)
75
100
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4350 G05
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LTC4350 TYPICAL PERFOR A CE CHARACTERISTICS
FB vs VCC
1.230 TA = 25C
1.225
1.220
1.220
GAIN (V)
FB (V)
FB (V)
1.215
1.210 0 2 4 8 6 VCC (V) 10 12 14
Gain Pin Voltage vs Temperature
2.7 RGAIN = 25k (VR+ - VR-) = 100mV VCC = 5V
13 12 11
2.6
VGATE (V)
GAIN (V)
2.5
10 9 8
VGATE (V)
2.4
2.3
2.2 -50
-25
0 25 50 TEMPERATURE (C)
PI FU CTIO S
UV (Pin 1): Undervoltage Pin. The threshold is set at 1.244V with a 24mV hysteresis. When the UV pin is pulled high, the charge pump ramps the GATE pin. When the UV pin is pulled low, the GATE pin will be pulled low. OV (Pin 2): Overvoltage Pin. The threshold is set at 1.220V with a 15mV hysteresis. When the OV pin is pulled high, the GATE pin is pulled low. After a timer cycle, the STATUS pin is pulled low until the OV pin is pulled low. TIMER (Pin 3): Analog System Timing Generator Pin. This pin is used to set the delay before the load sharing turns on after the UV pin goes high. The other use for the TIMER pin is to delay the indication of a fault on the STATUS pin. When the timer is off, an internal N-channel shorts the TIMER pin to ground. When the timer is turned on, a 2A or 6A timer current (ITIMER) from VCC is connected to the TIMER pin and the voltage starts to ramp up with a slope given by: dV/dt = ITIMER/CT. When the voltage reaches the trip point (1.220V), the timer will be reset by pulling the TIMER pin back to ground. The timer period is given by: (1.220V * CT)/ITIMER. GAIN (Pin 4): Analog Output Pin. The voltage across the R + and R - pins is divided by a 1k resistor and sourced as a current from the GAIN pin. An external resistor on the GAIN pin determines the voltage gain from the current sense resistor to the GAIN pin.
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FB vs Temperature
1.230 VCC = 5V
2.6 2.7
Gain PIn Voltage vs VCC
RGAIN = 25k (VR+ - VR-) = 100mV TA = 25C
1.225
2.5
2.4
1.215
2.3
1.210 -50
2.2
-25
0 25 50 TEMPERATURE (C)
75
100
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0
2
4
8 6 VCC (V)
10
12
14
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VGATE vs VCC
TA = 25C
VGATE vs Temperature
13.0 VCC = 5V 12.5
12.0
11.5
7 6
100
4350 G10
0
2
4
8 6 VCC (V)
10
12
14
11.0 -50
-25
0 25 50 TEMPERATURE (C)
75
100
4350 G12
4350 G11
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LTC4350
PI FU CTIO S
COMP2 (Pin 5): Analog Output Pin. This pin is the output of the share bus error amplifier E/A2. (A compensation capacitor between this pin and ground sets the crossover frequency for the power supply adjustment loop.) In most cases, this pin operates between 0.5V to 1.5V and represents a diode voltage up from the voltage at the RSET pin. It is clamped at 3V. During start-up, this pin is clamped to ground. After a timer cycle (and if the GATE pin is high), the COMP2 pin is released. COMP1 (Pin 6): Analog Output Pin. This pin is the output of the voltage regulating error amplifier E/A1. A compensation capacitor between this pin and ground sets the crossover frequency of the share bus loop. This pin operates a diode voltage up from the voltage at the SB pin and is clamped at 8.4V. SB (Pin 7): Analog Output Pin. This pin drives the share bus used to communicate the value of shared load current between several power supplies. There is an amplifier that drives this pin a diode below the COMP1 pin using an internal NPN as a pull-up and a 20k resistor as a pull-down. GND (Pin 8): Chip Ground. FB (Pin 9): Analog Error Amplifier Input (E/A1). This pin is used to monitor the output supply voltage with an external resistive divider. The FB pin voltage is compared to 1.220V reference. The difference between the FB pin voltage and the reference is amplified and output on the COMP1 pin. RSET (Pin 10): Analog Output Pin. The IOUT amplifier converts the voltage at the COMP2 pin (down a diode voltage) to the RSET pin. Therefore, the current through the external resistor (RSET) placed between the RSET pin and ground is (COMP2 - VDIODE)/RSET. This current is used to adjust the output voltage. IOUT (Pin 11): Analog Output Pin. The current flowing into the IOUT pin is equal to the current flowing out of the RSET pin that was set by the external resistor RSET. This current is used to adjust the output supply voltage by modifying the voltage sensed by the power supply's internal voltage feedback circuitry. R - (Pin 12): Analog Input Pin. With a sense resistor placed in the supply path between the R + and R - pins, the power supply current is measured as a voltage drop between R + and R -. This voltage is measured by the ISENSE block and multiplied at the GAIN pin. R + (Pin 13): Analog Input Pin. With a sense resistor placed in the supply path between the R + and R - pins, the power supply current is measured as a voltage drop between R + and R -. This voltage is measured by the ISENSE block and multiplied at the GAIN pin. GATE (Pin14): The high side gate drive for the external N-Channel power FET. An internal charge pump provides the gate drive necessary to drive the FETs. The slope of the voltage rise or fall at the GATE is set by an external capacitor connected between GATE and GND, and the 10A charge pump output current. When the undervoltage lockout circuit monitoring VCC trips, the OV pin is pulled high or the UV pin is pulled low, the GATE pin is immediately pulled to GND. STATUS (Pin 15): Open-Drain Digital Output. The STATUS pin has an open-drain output to GND. This pin is pulled low to indicate a fault has occurred in the system. There are three types of faults. The first is a undervoltage lockout on VCC or the UV pin is low while the output voltage is active. The second is when the COMP2 pin is above 1.5V or below 0.5V and the voltage on the GAIN pin is greater than 100mV. The final failure is when the OV pin is high. The three faults will activate the pull-down on the STATUS pin after a timing cycle. VCC (Pin 16): The Positive Supply Input, Ranging from 3.3V to 12V for Normal Operation. ICC is typically 1.6mA. An undervoltage lockout circuit disables the chip until the voltage at VCC is greater than 2.47V. A 0.1F bypass capacitor is required on the VCC pin. If the VCC pin is tied to the same power supply output that is being adjusted, then a 51 decoupling resistor is needed to hold up the supply during a short to ground on the supply output. VCC must be greater than or equal to the supply that is connected to the R+ and R- pins.
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LTC4350
BLOCK DIAGRA W
16 14 GATE VCC CHARGE PUMP 13 R+ 12 R- ISENSE gm = 1m 6 COMP1 GAIN 4 REF FB
+
E/A1 SB 20k 7
9
-
+
E/A2 COMP2 5
-
OVER/UNDER CURRENT REVERSE CURRENT IOUT R+ 30mV R-
- +
+
IOUT
+-
-
RSET 10
1
UV
-
REF
+
2
OV
2A/6A
+
LOGIC
REF
-
GND
8
6
-
11 TIMER STATUS 3 15
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LTC4350
APPLICATIO S I FOR ATIO
INTRODUCTION
Many system designers find it economically feasible to parallel power supplies to achieve redundancy. The second trend is providing some load sharing between the many supplies. In some cases, a failure in any one supply will trigger a sequence that disconnects the faulty supply and sends a flag to the system. Then, a service technician will swap in a good supply. For systems that are continuously powered, there is Hot Swap circuitry to prevent glitches on the power buses when power cards are swapped. A block diagram of this system is shown in Figure 1. By combining the features of a load share and a Hot Swap controller into one IC, the LTC4350 simplifies the design of redundant power supplies. A complete redundant power supply is a combination of a power module and the LTC4350 as shown in Figure 2. Note that the power
CONNECTOR
HOT SWAP LOAD CONNECTOR
LOAD SHARE
HOT SWAP
LOAD SHARE
OUTPUT SHARE INPUT BUS BUS BUS
Figure 1. Redundant Power Card System
INPUT BUS OUTPUT BUS POWER MODULE OUT +
SENSE+ SENSE - OUT - SHARE BUS
LTC4350
Figure 2. Redundant Power Supply
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module must have accessible feedback network or a remote sensing pin (SENSE +) to interface to the LTC4350. The LTC4350 provides a means for paralleling power supplies. It also provides for load sharing, fault isolation and power supply hot insertion and removal. The power supply current is accurately measured and then compared to a share bus signal. The power supply's output voltage is adjusted until the load current matches the share bus, which results in load sharing. There are two optional power FETs in series with the load that provide a quick disconnect between a load and a failed power supply. These same power FETs allow a power supply to be connected into a powered backplane in a controlled manner or removed without disruption. CURRENT SHARING The current sharing components will now be discussed. Figure 3 shows a simplified block diagram of these components. The ISENSE block measures the power supply current by amplifying the voltage drop across the sense resistor. An external resistor on the GAIN pin determines the gain of the ISENSE block. The voltage drop across the sense resistor is divided by a precision 1k resistor to produce a current at the GAIN pin. For example, a 10mV sense voltage translates to a 10A current. If a 10k resistor is on the GAIN pin, then the voltage gain is 10k/1k or 10. The voltage at the GAIN pin is compared to the current share bus using the E/A2 block. The output of E/A2 is used to adjust the output voltage of the power supply using the IOUT block. The objective of the E/A2 block is forcing the GAIN pin voltage to equal the SB pin voltage. When the GAIN pin voltages of all the LTC4350s in the system equal the SB pin voltage, the load current is shared. VOLTAGE MONITOR Unique to the LTC4350 is tight output voltage regulation. This is handled by the LTC4350's error amplifier and reference and not the power supply's error amplifier and reference. The E/A1 amplifier monitors the output voltage via the feedback divider connected to the FB pin. The FB pin is compared to the internal reference of the LTC4350. If the FB pin is at or below the reference, then the output of E/A1
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POWER SUPPLY
POWER SUPPLY
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LTC4350
APPLICATIO S I FOR ATIO
PASS-FET USED TO DISCONNECT A BAD POWER SUPPLY AND TO HOT-SWAP A POWER SUPPLY R 1 SENSE 2 3 4
OUT +
CG GATE DRIVE
+
ISENSE
-
gm = 1m
FB PIN
REF THIS VOLTAGE REPRESENTS THE POWER SUPPLY CURRENT MEASURED USING A SENSE RESISTOR
RGAIN
Figure 3. Simplified Block Diagram
drives the SB pin (or share bus). If the FB pin is above the reference, the COMP1 pin is grounded and the SB pin is disconnected from the COMP1 pin using the series diode. The LTC4350 with the highest reference will drive the SB pin and the 20k loads connected to the SB pin. All of the other LTC4350's COMP1 pins are pulled low because their FB pins are at a higher voltage than their references. The series diode between the COMP1 pin and the SB pin is actually a low impedance buffer amplifier with a diode in the output stage. Therefore, the master LTC4350's E/A1 drives the share bus to the proper value that keeps the output voltage tightly regulated. The buffer amplifier is capable of driving at least fifty 20k loads (each 20k load represents an LTC4350). OUTPUT VOLTAGE ADJUSTMENT The LTC4350 is designed to work with supplies featuring remote sense. The output voltage of each power supply needs to be adjusted below the final output voltage at the
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SENSE +
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ROUT
+
IADJ LOAD
THIS VOLTAGE REPRESENTS THE REFERENCE CURRENT VALUE (i.e., SHARE BUS) NEEDED TO FORCE THE OUTPUT VOLTAGE TO EQUAL THE REF
IOUT PIN
-
E/A1
COMP1 PIN SHARE BUS
THIS RESISTOR CONVERTS IADJ TO A VOLTAGE TO MODIFY THE REMOTE SENSE INPUT OF THE POWER SUPPLY (SENSE +). IT CREATES AN ARTIFICIAL SENSE + VOLTAGE THAT ADJUSTS THE POWER SUPPLY'S OUTPUT VOLTAGE UP OR DOWN
+
20k
+
E/A2
COMP2 PIN
THIS AMPLIFIER CONVERTS THE E/A2 VOLTAGE OUTPUT TO A CURRENT OUTPUT (IADJ)
+
IOUT
- -
RSET PIN
THIS AMPLIFIER FORCES THE POWER SUPPLY CURRENT TO EQUAL THE REFERENCE CURRENT VALUE (i.e., SHARE BUS)
RSET
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common load. For example, a 5V system would require the power supply output be set to 4.90V or some value below 5V. This is normally done using the trim pin of the module. The power supply output is then increased by artificially reducing the positive sense voltage by a small amount. The LTC4350 would then adjust the output voltage to 5V, an increase of 2%. The maximum range of adjustment can be set from 2% to 5% to compensate for voltage drops in the wiring, but no more than 300mV. In most power supplies, the voltage sense is tied directly to the output voltage. If a small valued resistor, ROUT, is placed in series with the power supply sense line, a voltage drop across ROUT appears as a lower sensed voltage. This requires the power supply to increase its output voltage to compensate. Thus, the LTC4350 exercises complete control of the final output voltage. The IOUT block converts the E/A2 output (COMP2 pin) to a current that flows through ROUT (see Figure 3). As the voltage at COMP2 increases, the current in ROUT
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LTC4350
APPLICATIO S I FOR ATIO
increases. The output voltage will then increase by an amount equal to the voltage drop across ROUT. The external resistor, RSET, sets the voltage to current relationship in the IOUT block. The current in ROUT is defined as IADJ = (VCOMP2 - 0.58V)/RSET. The maximum voltage that can be applied across RSET is 1V. The range of the output voltage adjustment is set to be VMAXADJ = ROUT /RSET. This sets the worst-case output voltage if the share bus is accidentally shorted to VCC. As mentioned previously, this range is set to be 2% to 10% in value. The compensation elements, CCP1 and CCP2, are used to set the crossover frequencies of the two error amplifiers E/A1 and E/A2. In the Design Example section, the calculations for choosing all of the components will be discussed. Output Adjust Soft-Start In the LTC4350, there is soft-start circuitry that holds the COMP2 pin at ground until both the GATE pin is 4V above the VCC pin and a timer cycle is completed following the UV pin becoming active. Upon power-up, most of the circuitry is active including the circuits that monitor and adjust the output voltage. The external power FETs are initially open circuit when power is applied. It takes about 10ms to 100ms for the FETs to transition from the off to the fully on state (as discussed in the following Hot Swapping section). During this time the FB pin is near ground which forces the SB to the positive rail. The COMP2 pin is then forced to the positive rail, which forces the RSET pin to 1V. The voltage at the output of the power supply is now adjusted to its maximum adjusted value, which can be 10% above nominal. Once the power FETs are turned on, the load will see this adjusted output voltage. This appears to be a voltage overshoot at the load that exists until the loop can correct itself. The dominant pole in the loop exists on the COMP2 pin. Therefore, the overshoot duration is determined by the discharge time of the COMP2 pin. In order to eliminate this overshoot, the COMP2 pin is clamped at ground until the GATE pin is 4V above the VCC pin (power FETs are turned on). Now, the COMP2 pin will begin to charge up until the FB pin regulates at 1.220V.
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In cases where the power FETs are turned on but the power supply is still ramping up, the load voltage may overshoot. For these cases, the COMP2 pin is clamped to ground during one timing cycle. If the UV pin is greater than 1.244V, the chip begins the timer cycle. The timer cycle uses a 2A current source into an external capacitor on the TIMER pin. As soon as the voltage at the TIMER pin exceeds 1.220V, the timer cycle is over. The time-out is defined as t = CT * 1.220V/2A. At the end of the timer cycle, the power supply ramping should be complete. Faults There are several types of power supply output faults. Shorts from the output to ground or to a positive voltage greater than the normal output voltage are considered "hard faults." These faults require the bad power supply to be immediately disconnected from the load in order to prevent disruption of the system. "Soft faults" include power supply failed open-circuit or load current sharing failure where the output voltage is normal but load sharing between several supplies is not equal. The LTC4350 can isolate soft and hard faults and signal a system controller using the STATUS pin. HARD FAULTS The LTC4350 can identify faults in the power supply and isolate them from the load if optional external power FETs are included between the power supply and the load. In the case of a power supply output short to ground, the reverse current block will sense that the voltage across the current sense resistor has changed directions and has exceeded 30mV for more than 5s. The gate of the external power FETs is immediately pulled low disconnecting the short from the load. The gate is allowed to ramp-up and turn-on the power FETs as soon as the reverse voltage across the sense resistor is less than 30mV. The condition where a power supply output shorts to a high voltage is referred to as an overvoltage fault. In this case, the gate of the power FETs is pulled low disconnecting the overvoltage from the load. This feature uses the OV pin to monitor the power supply output voltage. Once the voltage on the OV pin exceeds the 1.220V threshold, the gate of the external power FETs is pulled low.
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LTC4350
APPLICATIO S I FOR ATIO
A timer is started as soon as the OV pin exceeds 1.220V. The timer consists of a 6A current source into an external capacitor on the TIMER pin. As soon as the voltage on the TIMER pin exceeds 1.220V, the STATUS pin is pulled low. There are two external power FETs in Figure 3. The FET with its drain on the power supply side (left) and its source on the load side (right) is used to block high voltage faults from the load. If overvoltage protection is not needed, this FET is omitted. Likewise, the FET with its drain on the load side (right) can be eliminated if protection from a ground short is not needed. The other use for the power FETs is to allow hot swapping of the power supply. Hot swapping will be discussed in a later section. SOFT FAULTS The existence of a share bus that forces tight regulation of the system output voltage allows the system to detect if the load current is not sharing properly. As mentioned previously, the output of E/A2 will adjust until the measured current equals the share bus value. If the power supply output fails to share properly, the E/A2 output will hit the plus or minus supply. The LTC4350 uses the over/ under current block to monitor the E/A2 output. This block signals the logic that a soft fault has occurred if the E/A2 output goes out of the normal 0.5V to 1.5V range where the IOUT block is active. After a timer cycle, the STATUS pin indicates a soft fault. The timer consists of a 2A current source into an external capacitor on the TIMER pin. As soon as the voltage on the TIMER pin exceeds 1.220V, the STATUS pin is pulled low. The fault indication at the STATUS pin is disabled under one condition. The E/A2 output can be less than 0.5V when the load currents are low. In this case, it is desired to disable the soft fault indication until the current is higher. Higher current is defined as when the GAIN pin is greater than 100mV. The most common situations for soft faults are a disconnected power supply and the share bus shorts to VCC or ground.
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HOT SWAPPING The LTC4350 controls external power FETs to allow power supplies to be hot swapped in and out of the powered system without disturbing the power buses. The gate of the power FETs are slowly ramped up. This slowly charges the power supply input and output capacitors, preventing the large inrush currents associated with capacitors being hot plugged into power buses. When power is first applied to the VCC pin, the gate of the power FET is pulled low. As soon as VCC rises above the undervoltage lockout threshold, the chip's UV pin is functional. A 0.1F bypass capacitor is required on the VCC pin. If the VCC pin is tied to the same power supply output that is being adjusted, then a 51 decoupling resistor is needed to hold up the supply during a short to ground on the supply output. If the UV pin is greater than 1.244V, the gate of the external FETs is charged with a 10A current source. The voltage at the GATE pin begins to rise with a slope equal to 10A/ CG (Figure 4), where CG is the external capacitor connected between the GATE pin and GND. This slow charging allows the power supply output to begin load sharing in a nondisruptive manner.
VCC + 10V GATE SLOPE = 10A/CG VCC VOUT t1 t2
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Figure 4. Supply Turn-On
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LTC4350
APPLICATIO S I FOR ATIO
When the power supply is disconnected, the UV pin will drop below 1.220V if the supply is loaded. The LTC4350 then discharges the gate of the power FET isolating the load from the power supply. DESIGN EXAMPLE Load Share Components This section demonstrates the calculations involved in selecting the component values. The design example in Figure 5 is a 5V output. This design can be extended to each of the parallel sections. The first step is to determine the final output voltage and the amount of adjustment on the output voltage. The power supply voltage before the load sharing needs to be lower than the final output voltage. If the load is expecting to see a 5V output, then all of the shared power supplies need to be trimmed to 4.90V or lower. This allows 2% variation in component and reference tolerances so that the output always starts below 5V. Now that the output voltage is preset below the desired output, the LTC4350 will be responsible for increasing the output utilizing the SENSE + input to the power supply. If
4.9V NOMINAL, 5.3V MAXIMUM ROUT 30 0.1F 51
OUT + SENSE+
RSET 100 RGAIN 86.6k
274k
43.2k
CUV 0.1F
121k
12.1k
Figure 5. 5V Load Share (20A per Module)
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a SENSE + line is not available, then the feedback divider at the module's error amplifier can be used. The next step is to determine the maximum positive adjustment needed for each power supply. This adjustment includes any I * R drops across sense resistors, power FETs, wiring and connectors in the supply path between the power supply and the load. For example, if the maximum current is 10A and the parasitic resistance between the power supply and load is 0.01, then the positive adjustment range for I * R drops is 0.1V. Since the starting voltage is 4.9V 0.1V, then the lowest starting voltage can be 4.8V. This voltage is 0.2V below the target. The total adjustment range that the LTC4350 will need for this example is 0.1V + 0.2V = 0.3V. Note that the lowest starting voltage should not be lower than 300mV below the target voltage. The I * R drops should be designed to be low to eliminate the need for additional bulk capacitance at the load. In most cases the bulk capacitance exists at the power supply output before the I * R drops. If a 0.002 sense resistor is used and the FET resistance is below 0.003, then a total 0.005 series resistance is acceptable for loads to 20A. Obviously, the FB pin compensates for the DC output impedance, but the AC output impedance is the I * R drops plus the ESR of the capacitors.
4 x SUD50N03-07 (0.007 EACH) 3 RSENSE 0.002 5V SHARE BUS BUS 2 4 37.4k 1 RG 100 VCC IOUT RSET GATE R+ R- FB TIMER CG 0.1F 12.1k GAIN LTC4350 GND UV OV COMP2 CP2 1F RP1 150 STATUS SB COMP1 CT 0.1F STATUS CP1 1000pF
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LTC4350
APPLICATIO S I FOR ATIO
The resistors ROUT and RSET set the adjustment range. The voltage on RSET is translated to a voltage on ROUT by the ratio of ROUT/RSET. Therefore, the adjustment on the output voltage will track the voltage at the RSET pin which is also the voltage on the COMP2 pin minus a diode voltage. The expression is VADJ = (VRSET) * ROUT/RSET = (VCOMP2 - VDIODE) * ROUT/RSET. The maximum voltage at VRSET is limited to 1V. The maximum adjustment on the output is expressed as VADJMAX = ROUT/RSET. A normal value for RSET is in the 50 to 100 range. If we set RSET to be 100, then an ROUT of 100 allows the output voltage a full 1V adjustment. For the 0.3V range in this example, the ROUT is 30. In some power modules, there already exists a resistor between the SENSE + line and the power output. In this case, the value of ROUT is the parallel combination of two resistors, one in the module and one placed between the SENSE + and output terminals of the module. The value of the gain setting resistor, RGAIN, depends on the maximum voltage drop across the sense resistor and the supply voltage VCC for the chip. The highest possible voltage at the GAIN pin is 1.5V from the VCC voltage. The maximum voltage on the GAIN pin is expressed as: VGAINMAX = RSENSE * IMAX * RGAIN/1k = VCC - 1.5V. The expression for RGAIN: RGAIN = (VCC - 1.5V) * 1k/(RSENSE * IMAX). In this example, VCC is 5V, IMAX is 20A and RSENSE is 0.002. Therefore, RGAIN is 87.5k but using 1% values results in 86.6k. The FB pin divider provides a 1.220V output for a 5V input. The precision of the FB pin divider resistors will impact the accuracy of the final output voltage. The UV resistive divider in this example, turns on the gate when VCC increases above 4V. This corresponds to the UV pin at 1.220V. The capacitor CUV prevents false activation during load steps. The OV set point needs to occur above the adjustment max for VCC. The power supply output (which also is VCC), can start as high as 5V and adjust upwards to 5.3V. The OV set point in this example is 5.5V on VCC when the OV pin is at 1.220V. The timer capacitor CT is set to be 0.1F for a 61ms timer cycle. The expression is t = CT * 1.22V/2A. The gate capacitor CG is set to be 0.1F which sets a slope of 10A/ CG or 1V every 10ms. In this case, the GATE pin must
VOUT (t)
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charge up to 9V before the output can ramp to 5V which happens in 90ms. In this case, the output adjust soft-start turns on when the gate ramps above 9V. The soft-start circuitry releases the COMP2 pin allowing the load sharing loop to function. A 100 resistor RG prevents high frequency oscillations from the power FETs at their turn-on threshold. A 0.1F bypass capacitor is required on the VCC pin. If the VCC pin is tied to the same power supply output that is being adjusted, then a 51 decoupling resistor is needed to hold up the supply during a short to ground on the supply output. COMPENSATION The compensation capacitor, CP1, is needed to set the crossover frequency of the feedback error amplifier E/A1. The crossover frequency of 200kHz is adequate for most applications and requires CP1 to be 1000pF (0.001F). The design of the other compensation capacitor will require some knowledge about the power supply's bandwidth. The bandwidth can be measured easily. First, use a storage oscilloscope to monitor the power supply output voltage. Then place a 1A resistive fixed load and switch in a second resistive load that increases the total load current close to rated maximum. Tapping the second resistor (with the correct power rating) to the power supply output creates this load step. Trigger the scope on the falling edge of the output voltage as it drops more than 100mV (for example from 5V to 4.8V). The recovery time, tR, from the step needs to be measured. tR is defined as the 10% to 90% time measurement (see Figure 6). The
90% 0.1V V 0.1V 10% tr t
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Figure 6. tR Measurement
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LTC4350
APPLICATIO S I FOR ATIO
compensation capacitor CP2 can be looked up in Table 1 using tR. The value for the zero setting resistor, RP1, is 150. This value guarantees the zero is at or above the crossover frequency.
Table 1
tR 5s 10s 20s 40s 60s 80s 100s 150s 200s 300s 400s 500s fC = 0.35/tR 70kHz 35kHz 17.5kHz 8.8kHz 5.8kHz 4.4kHz 3.5kHz 2.3kHz 1.8kHz 1.2kHz 0.9kHz 0.7kHz CP2 0.1F 0.22F 0.47F 1F 1.5F 2.2F 2.7F 3.3F 4.7F 6.8F 10F 12F
OTHER APPLICATIONS The application shown on the first page of this data sheet assumes that the power supplies and the load reside on one main board. If the system is a true N + 1 hot swappable
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power supply, then the LTC4350 will reside with the power supply on a daughter card that plugs into the main board. In this case, the input and output capacitors need to be hot swapped (see Figure 7). The output capacitors are Hot Swap protected by the LTC4350. The input capacitors are Hot Swap protected using the LT(R)4250. Other Hot Swap parts are described in Table 2.
Table 2
VOLTAGE RANGE 3.3V to 12V 3.3V to 15V 2.7V to 16.5V 9V to 80V - 20V to - 80V PART NUMBER LTC1422 Single Channel LTC1645 Dual Chanel LTC1642 Overvoltage Protection LTC1647 Dual Channel LT1641 Positive High Voltage LT4250 Negative High Voltage
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In some cases, the output voltage is below the undervoltage lockout of the LTC4350. In this case, an external supply of 3.3V or greater needs to provide for the chip. Figure 8 shows a 1.5V output redundant power supply that uses 24V to 1.5V switching power supplies. The VCC pin of the LTC4350 can be driven from the INTVCC pin of the LTC1629.
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LTC4350
APPLICATIO S I FOR ATIO
-48V RTN -48V RTN RTN VDD LT4250L OV VEE SENSE
UV
-48V
-48V 3.3VOUT GND SB STATUS
-48V
3 1
4 2
CONNECTOR
LOAD
-48V RTN
RTN VDD LT4250L OV VEE SENSE
UV
-48V 3.3VOUT GND SB STATUS
-48V
3 1
4 2
CONNECTOR
Figure 7. - 48V to 3.3V Hot Swap Power Supply
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POWER SUPPLY 1 VIN+ PWRGD DRAIN GATE OUT + ROUT
+
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1 3
RSENSE
2 4
3.3V
ON/OFF
SENSE
SENSE - RG VIN- OUT - VCC IOUT RSET GATE R R- FB
+
CG
RSET RGAIN
STATUS GAIN SB LTC4350 GND UV TIMER CT OV COMP1 COMP2 CP2 RP2
CUV
CP1
POWER SUPPLY 2 VIN+ PWRGD DRAIN GATE OUT + ROUT 1 3
RSENSE
2 4
3.3V
ON/OFF SENSE+ SENSE -
RG VIN- OUT - VCC IOUT RSET GATE R+ R- FB CG
RSET RGAIN
STATUS GAIN SB LTC4350 GND UV TIMER CT OV COMP1 COMP2 CP2 RP2
CUV
CP1
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PACKAGE DESCRIPTIO U
GN Package 16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.045 .005
.189 - .196* (4.801 - 4.978) 16 15 14 13 12 11 10 9
.009 (0.229) REF
.254 MIN
.150 - .165
.229 - .244 (5.817 - 6.198)
.150 - .157** (3.810 - 3.988)
.0165 .0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1 .015 .004 x 45 (0.38 0.10) .007 - .0098 (0.178 - 0.249) .016 - .050 (0.406 - 1.270)
NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE .0532 - .0688 (1.35 - 1.75)
23
4
56
7
8
.004 - .0098 (0.102 - 0.249)
0 - 8 TYP
.008 - .012 (0.203 - 0.305) TYP
.0250 (0.635) BSC
GN16 (SSOP) 0204
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LTC4350
APPLICATIO S I FOR ATIO
VIN 24V 24VIN VIN
VCC GND GND ON
SENSE GATE LT1641 GND INTVCC LTC1629 VOS+
TIMER
LOAD
1.5VOUT SB STATUS CUV
CONNECTOR
24VIN
VIN CIN COUT RG VCC SENSE GATE LT1641 GND INTVCC LTC1629 VOS+ RSET RGAIN CG ROUT VCC IOUT RSET GATE R+ R- FB
GND
GND
ON
TIMER
VOUT SB STATUS CUV
CONNECTOR
Figure 8. 24V to 1.5V Hot Swap Power Supply
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS LTC1421 Hot Swap Controller Multiple Supplies from 3V to 12V and -12V LT1640AL/LT1640AH Negative Voltage Hot Swap Controllers Negative High Voltage Supplies from -10V to - 80V LT1641 Positive Voltage Hot Swap Controller Positive High Voltage Supplies from 9V to 90V LTC1645 2-Channel Hot Swap Controller Operates from 1.2V to 12V, Power Sequencing LTC1646 Dual CompactPCITM Hot Swap Controller 3.3V/5V Only with Precharge and Local Reset Logic LTC1647-1/LTC1647-2 Dual Hot Swap Controllers Dual ON Pins, Operates from 2.7V to 16.5V LTC4211 Hot Swap Controller with Multifunction Circuit Breaker 2.5V to 16.5V Supplies and RESET Output LTC4251 - 48V Hot Swap Controller in ThinSOTTM Active Current Limiting, -15V to -100V Supplies ThinSOT is a trademark of Linear Technology Corporation. CompactPCI is a trademark of the PCI Industrial Computer Manufacturers Group.
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
www.linear.com
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RSENSE CIN COUT RG CG ROUT VCC IOUT RSET GATE R+ R- FB 1.5V RSET RGAIN STATUS GAIN SB LTC4350 GND UV OV COMP1 COMP2 CP2 RP1 CP1 TIMER CT RSENSE 1.5V STATUS GAIN SB LTC4350 GND UV OV COMP1 COMP2 CP2 RP1 CP1 TIMER CT
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LT/TP 1004 1K REV A * PRINTED IN THE USA
(c) LINEAR TECHNOLOGY CORPORATION 2001

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