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CY2220
133-MHz Spread Spectrum Clock Synthesizer/Driver with Differential CPU Outputs
Features * Compliant to Intel CK00 Clock Synthesizer/Driver Specifications * Multiple output clocks at different frequencies -- Four pairs of differential CPU outputs, up to 133 MHz -- Ten synchronous PCI clocks -- Two Memory Reference clocks, 180 degrees out of phase -- Four AGP and Hub Link clocks at 66 MHz -- Two 48-MHz clocks -- Two reference clocks at 14.318 MHz * Spread Spectrum clocking -- 31 kHz modulation frequency -- Default is -0.6%, which is recommended by Intel * Power-down features * Three Select inputs * Low-skew and low-jitter outputs * OE and Test Mode support * 56-pin SSOP package Enables ACPI compliant designs Supports up to eight CPU clock frequencies Meets tight system timing requirements at high frequency Enables ATE and "bed of nails" testing Widely available, standard package enables lower cost Enables reduction of EMI and overall system cost
(R)
Benefits Supports next generation Pentium(R) processors using differential clock drivers Motherboard clock generator -- Support Multiple CPUs and a chipset -- Support for PCI slots and chipset -- Drives up to two Direct RambusTM Clock Generators (DRCG) -- Supports USB host controller and SuperI/O chip -- Supports ISA slots and I/O chip
Logic Block Diagram
REFCLK [0-1]
Pin Configuration
SSOP Top View
VSSREF REFCLK0/MultSel_0 REFCLK1/MultSel_1 VDDREF 1 2 3 4 5 6 7 8 9 10 11 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDMEM MemRef MemRefB VSSMEM SPREAD CPUCLK_3 CPUCLK_3B VDDCPU CPUCLK_2 CPUCLK_2B VSSCPU CPUCLK_1 CPUCLK_1B VDDCPU CPUCLK_0 CPUCLK_0B VSSCPU IREF AVDD AVSS VDD3V66 3V66_3 3V66_2 VSS3V66 VSS3V66 3V66_1 3V66_0 VDD3V66
MultSel0 MultSel1 XTALIN
XTALOUT
14.318 MHz OSC.
CPUCLK [0-3]
XTALIN XTALOUT VSSPCI
CPU PLL
Divider and Stop Logic
CPUCLKB [0-3] MemRef, MemRefB PCICLK [0-9] (33.33 MHz)
PCICLK_0 PCICLK_1 VDDPCI PCICLK_2 PCICLK_3 VSSPCI PCICLK_4 PCICLK_5 VDDPCI
EPROM
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
SPREAD PWR_DWN
SYS PLL
3V66 [0-3] (66.67 MHz)
PCICLK_6 PCICLK_7 VSSPCI PCICLK_8 PCICLK_9 VDDPCI Sel133 VSSUSB USBCLK0/SelA USBCLK1/SelB VDDUSB PWR_DWN
USBCLK [0-1] (48 MHz)
Intel and Pentium are registered trademarks of Intel Corporation. Direct Rambus is a trademark of Rambus, Inc.
Cypress Semiconductor Corporation Document #: 38-07206 Rev. *A
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Revised December 30, 2002
CY2220
SELA SELB SEL133
12 13
CY2220
Pin Summary
Name VSSREF VDDREF VSSPCI VDDPCI VSS3V66 VDD3V66 VSSUSB VDDUSB VSSCPU VDDCPU VSSMEM VDDMEM AVSS AVDD IREF XTALIN[1] XTALOUT[1] CPUCLK [0-3] CPUCLK [0-3]B PCICLK [0-9] MemRef MemRefB 3V66_ [0-3] USBCLK [0-1]/Sel[A-B] REFCLK[0-1]/MultSel[0-1] PWR_DWN SPREAD[2] SEL133 Pins 1 4 7, 13, 19 10, 16, 22 32, 33 29, 36 24 27 40, 46 43, 49 53 56 37 38 39 5 6 42, 45, 48, 51 41, 44, 47, 50 8, 9, 11, 12, 14, 15, 17, 18, 20, 21 55 54 30, 31, 34, 35 25, 26 2, 3 28 52 23 Description 3.3V Reference ground 3.3V Reference voltage supply 3.3V PCI ground 3.3V PCI voltage supply 3.3V AGP and Hub Link ground 3.3V AGP and Hub Link voltage supply 3.3V USB ground 3.3V USB voltage supply 3.3V CPU ground 3.3V CPU voltage supply 3.3V Memory ground 3.3V Memory voltage supply Analog ground for PLL and Core Analog voltage supply to PLL and Core Reference current for external biasing Reference crystal input Reference crystal feedback CPU clock outputs Inverse CPU clock outputs PCI clock outputs, synchronously running at 33.33 MHz MemRef clock output, drives memory clock generator MemRefB clock output 180 degrees out of phase with MemRef AGP and Hub Link clock outputs, running at 66 MHz Sel [A-B] inputs are sensed then internally latched on power-up before the pins are used for 48-MHz USB clock outputs MultSel[0-1] inputs are sensed then internally latched on power-up before the pins are Reference clock outputs, 14.318 MHz Active LOW input, powers down part when asserted Active LOW input, enables spread spectrum when asserted CPU frequency select input (See Function Table)
Notes: 1. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF. For crystals with different CLOAD, please refer to the application note, "Crystal Oscillator Topics." 2. Input is static HIGH or LOW. Frequency of toggling cannot exceed 30 MHz.
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CY2220
Function Table[3]
SEL133 0 0 0 0 1 1 1 1 SELA 0 0 1 1 0 0 1 1 SELB 0 1 0 1 0 1 0 1 CPUCLK (MHz) 100 N/A N/A Hi-Z 133 N/A N/A TCLK/2 MemRef (MHz) 50 N/A N/A Hi-Z 66 N/A N/A TCLK/4 3V66CLK (MHz) 66 N/A N/A Hi-Z 66 N/A N/A TCLK/4 PCICLK (MHz) 33 N/A N/A Hi-Z 33 N/A N/A TCLK/8 USBCLK (MHz) 48 N/A N/A Hi-Z 48 N/A N/A TCLK/2 REFCLK (MHz) 14.318 N/A N/A Hi-Z 14.318 N/A N/A TCLK
Actual Clock Frequency Values
Clock Output CPUCLK CPUCLK USBCLK Target Frequency (MHz) 100 133 48 CY2220-1 Actual Frequency (MHz) 99.126 132.769 48.008 PPM -8741 -1740 167 CY2220-2 Actual Frequency (MHz) 100.227 133.269 48.008 PPM +2270 +2022 167
Swing Select Functions
MultSel0 0 0 0 0 1 1 1 1 MultSel1 0 0 1 1 0 0 1 1 Board Target 60 50 60 50 60 50 60 50 Reference R, IREF = Rr = 475 1%, Iref = 2.32 mA Rr = 475 1%, Iref = 2.32 mA Rr = 475 1%, Iref = 2.32 mA Rr = 475 1%, Iref = 2.32 mA Rr = 475 1%, Iref = 2.32 mA Rr = 475 1%, Iref = 2.32 mA Rr = 475 1%, Iref = 2.32 mA Rr = 475 1%, Iref = 2.32 mA Output Current IOH = 5*Iref IOH = 5*Iref IOH = 6*Iref IOH = 6*Iref IOH = 4*Iref IOH = 4*Iref IOH = 7*Iref IOH = 7*Iref VOH @ Z, Iref = 2.32 mA 0.71 @ 60 0.59 @ 50 0.85 @ 60 0.71 @ 50 0.56 @ 60 0.47 @ 50 0.99 @ 60 0.82 @ 50
Clock Driver Impedances
Impedance Buffer Name CPUCLK, CPUCLKB USB, REF PCI, 3V66 MemRef, MemRefB 3.135-3.465 3.135-3.465 3.135-3.465 VDD Range Buffer Type Type X1 Type 3 Type 5 Type 5 20 12 12 40 30 30 60 55 55 Minimum Typical Maximum
Note: 3. TCLK is a test clock driven in on the XTALIN input in test mode.
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CY2220
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage....................................................-0.5 to +7.0V Input Voltage...............................................-0.5V to VDD + 0.5 Storage Temperature (Non-Condensing).......-65C to +150C Junction Temperature.................................................. +150C Package Power Dissipation................................................1W Static Discharge Voltage (per JEDEC EIA/JESD22-A114-A)................................2000V
Operating Conditions Over which Electrical Parameters are Guaranteed
Parameter VDDREF, VDDPCI, AVDD, VDD3V66, VDDUSB, VDDCPU, VDDMEM TA Cin CXTAL CL Description 3.3V Supply Voltages Min. 3.135 Max. 3.465 Unit V
Operating Temperature, Ambient Input Pin Capacitance Nominal Value XTAL Pin Capacitance Max. Capacitive Load on MemRef, USBCLK, REF PCICLK, 3V66 Reference Frequency, Oscillator Nominal Value Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic)
0 18 pF
70 18 pF 22.5 20 30
C pF pF pF
f(REF) tPU
14.318 0.05
14.318 50
MHz ms
Electrical Characteristics Over the Operating Range
Parameter VIH VIL VOH VOL IIH IIL IOH Description High-level Input Voltage Low-level Input Voltage Except Crystal Pads IOH = -1 mA IOH = -1 mA IOL = 1 mA IOL = 1 mA -5 -5 Type X1, VOH = 0.65V Type 3, VOH = 2.4V Type 5, VOH = 2.4V Type 3, VOL = 0.4V Type 5, VOL =0.4 V 2.4 2.4 0.4 0.55 5 5 PCI Low-level Output Voltage Input High Current Input Low Current MemRef, USB, REF, 3V66 PCI 0 < VIN < VDD 0 < VIN < VDD Test Conditions Except Crystal Pads. Threshold voltage for crystal pads = VDD/2 Min. Max. Unit 2.0 0.8 V V V V V V A A
High-level Output Voltage MemRef, USB, REF, 3V66
High-level Output Current CPU For IOH =6*IRef Configuration USB, REF 3V66, PCI, MemRef, MemRefB
-12.9 -14.9 mA -15 -30 10 20 -51 -100 24 49 10 250 60 A mA mA mA
IOL IOZ IDD3 IDDPD3
Low-level Output Current Output Leakage Current 3.3V Shutdown Current
USB, REF 3V66, PCI, MemRef, MemRefB Three-state AVDD/VDDQ3 = 3.465V
3.3V Power Supply Current AVDD/VDD33 = 3.465V, FCPU = 133 MHz
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CY2220
-
Switching Characteristics[4] Over the Operating Range
Parameter t1 t2 t2 t2 t3 t3 t3 t4 t5 t6 t7 t8 t9 t9 t9 t9 t9 All CPU USB, REF PCI, 3V66, MemRef CPU USB, REF PCI, 3V66, MemRef CPU 3V66 PCI 3V66,PCI CPU Mref 3V66 USB PCI REF CPU, PCI CPU CPU CPU Voh Vol Vcrossover CPU CPU CPU Output Description Output Duty Rise Time Rising Edge Rate Rising Edge Rate Fall Time Falling Edge Rate Falling Edge Rate CPU-CPU Skew 3V66-3V66 Skew PCI-PCI Skew 3V66-PCI Clock Skew Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Settle Time Rise/Fall Matching Overshoot Undershoot High-level Output Voltage Low-level Output Voltage Crossover Voltage Cycle[5] t1A/(t1B) Measured at 20% to 80% of VOH Between 0.4V and 2.4V Between 0.4V and 2.4V Measured at 80% to 20% of VOH Between 2.4V and 0.4V Between 2.4V and 0.4V Measured at Crossover Measured at 1.5V Measured at 1.5V 3V66 leads. Measured at 1.5V Measured at Crossover t8 = t8A - t8B With all outputs running Measured at 1.5V t9 = t9A - t9B Measured at 1.5V t9 = t9A - t9B Measured at 1.5V t9 = t9A - t9B Measured at 1.5V t9 = t9A - t9B Measured at 1.5V t9 = t9A - t9B CPU and PCI clock stabilization from power-up Measured with test loads[6, 7] Measured with test loads
[7]
Test Conditions
Min. 45 175 0.5 1.0 175 0.5 1.0
Max. 55 700 2.0 4.0 700 2.0 4.0 150 250 500
Unit % ps V/ns V/ns ps V/ns V/ns ps ps ps ns ps ps ps ps ps ps ms
1.5
3.5 200 250 300 350 500 1000 3 20% VOH + 0.2
V V
Measured with test loads[7] Measured with test Measured with test loads[7] loads[7]
-0.2 0.65 0.0 45% of VOH 0.74 0.05 55% of VOH
V V V
Measured with test loads[7]
Notes: 4. All parameters specified with loaded outputs. Parameters not tested in production, but are guaranteed by design characterization. 5. Duty cycle is measured at 1.5V with VDD at 3.3V on all output except CPU. Duty Cycle on CPU is measured at VCrossover. 6. Determined as a fraction of 2*(tRP - tRN)/(tRP + tRN)Where tRP is a rising edge and tRN is an intersecting falling edge. 7. The test load is specified in test circuit.
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CY2220
Switching Waveforms
Duty Cycle Timing (Single Ended Output)
t1B
t1A
Duty Cycle Timing (CPU Differential Output)
t1B t1A
All Outputs Rise/Fall Time
VOH OUTPUT 0V t2 t3
CPU-CPU Clock Skew
Host_b Host Host_b Host t4
3V66-3V66 Clock Skew
3V66
3V66
t5
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CY2220
Switching Waveforms (continued)
PCI-PCI Clock Skew
PCI
PCI t6
3V66-PCI Clock Skew
3V66
PCI t7
CPU Clock Cycle-Cycle Jitter
t8A Host_b Host t8B
Cycle-Cycle Clock Jitter
t9A
t9B
CLK
PWR_DOWN[8]
CPUCLK (Internal) PCICLK (Internal) PWR_DWN CPUCLK (External) PCICLK (External) VCO Crystal
Note: 8. Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock.
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CY2220
Test Circuit[9, 10]
Rs VDDPCI, VDD3V66, VDDUSB, VDDREF, AVDD, VDDCPU, VDDMRef Rp 1, 7, 13, 19, 24, 32, 33, 37, 40, 46, 53 4, 10, 16, 22, 27, 29, 36, 38, 43, 49, 56 Rp Test Node 20 pF PCI, 3V66, MRef Outputs 30 pF Ref, USB Outputs CY2220 Rs CPU OUTPUTS Test Nodes Rs Rp 33.2 49.9
Test Node
Ordering Information
Ordering Code CY2220PVC-1 CY2220PVC-2 Package Name O56 O56 Package Type 56-Pin SSOP 56-Pin SSOP Operating Range Commercial Commercial
Notes: 9. Each supply pin must have an individual decoupling capacitor.
10. All capacitors must be placed as close to the pins as is physically possible.
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CY2220
Layout Example
+3.3V Supply FB
VDDQ3
C4
0.005 F
10 F
C3
G
G
G
G
1 2 3 4 5 6 7 8 9
10
V
V
G
V
G
G
G
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
V
V
V
V V
V V
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
G
FB = Dale ILB1206 - 300 (30 @ 100 MHz) Cermaic Caps C3 = 10-22 F G = VIA to GND plane layer C4 = 0.005 F V =VIA to respective supply plane layer
Note: Each supply plane or strip should have a ferrite bead and capacitors All bypass caps = 0.01 F ceramic
CY2220
G
G
G
G
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CY2220
Package Diagram
56-Lead Shrunk Small Outline Package O56
51-85062-*C
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(c) Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY2220
Document Title: CY2220 133-MHz Spread Spectrum Clock Synthesizer/Driver with Differential CPU Outputs Document Number: 38-07206 REV. ** *A ECN NO. 111730 121841 Issue Date 01/17/02 12/30/02 Orig. of Change DSG RBI Description of Change Change from Spec number: 38-00813 to 38-07206 Power up requirements added to Operating Conditions Information
Document #: 38-07206 Rev. *A
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