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| FUJITSU SEMICONDUCTOR DATA SHEET DS07-13738-1E 16-bit Proprietary Microcontroller CMOS F2MC-16LX MB90820 Series MB90822/F822/F823/V820 s DESCRIPTION The MB90820 series is a line of general-purpose, Fujitsu 16-bit microcontrollers designed for process control applications which require high-speed real-time processing, such as consumer products. While inheriting the AT architecture of the F2MC* family, the instruction set for the F2MC-16LX CPU core of the MB90820 series incorporates additional instructions for high-level languages, supports extended addressing modes, and contains enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. In addition, the MB90820 series has an on-chip 32-bit accumulator which enables processing of long-word data. The peripheral resources integrated in the MB90820 series include : an 8/10-bit A/D converter, 8-bit D/A converters, UARTs (SCI) 0, 1, multi-functional timer (16-bit free-running timer, input capture units (ICUs) 0 to 3, output compare units (OCUs) 0 to 5, 16-bit PPG timer 0, waveform generator), 16-bit PPG timer 1, 2, PWC 0, 1, 16-bit reload timer 0, 1 and DTP/external interrupt. *: F2MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED. s FEATURES * Minimum execution time of instruction : 42 ns / 4 MHz oscillation (uses PLL clock multiplication) maximum multiplier = 6 * Maximum memory space 16M bytes Linear/bank access (Continued) s PACKAGES 80-pin plastic QFP 80-pin plastic LQFP 80-pin plastic LQFP (FPT-80P-M06) (FPT-80P-M05) (FPT-80P-M11) MB90820 Series (Continued) * Instruction set optimized for controller applications Supported data types : bit, byte, word, and long-word types Standard addressing modes : 23 types 32-bit accumulator enhancing high-precision operations Enhanced multiplication/division and RETI instructions * Enhanced high level language (C) and multi-tasking support instructions Use of a system stack pointer Symmetrical instruction set and barrel shift instructions * Program patch function (for two address pointers) * Increased execution speed : 4-byte instruction queue * Powerful interrupt function Up to eight priority levels programmable External interrupt inputs : 8 lines * Automatic data transmission function independent of CPU operation Up to 16 channels for the extended intelligent I/O service DTP request inputs : 8 lines * Internal ROM FLASH : 64/128K bytes with flash security MASKROM : 64K bytes * Internal RAM EVA : 16K bytes FLASH : 4K bytes MASKROM : 4K bytes * General-purpose ports Up to 66 channels (pull-up resistor settable input for : 32 channels) * A/D Converter (RC) : 16 channels 8/10-bit resolution selectable Conversion time : Min 3 s at 24 MHz operating clock (including sampling time) * 8-bit D/A Converter : 2 channels * UART : 2 channels * 16-bit PPG : 3 channels Mode switching function provided (PWM mode or one-shot mode) Channel 0 can be worked with multi-functional timer or independently * 16-bit reload timer : 2 channels * 16-bit PWC timer : 2 channels * Multi-functional timer Input capture : 4 channels Output compare with selectable buffer : 6 channels Free-running timer with up or up-down mode selection and selectable buffer: 1 channel 16-bit PPG : 1 channel Waveform generator : (16-bit timer : 3 channels, 3-phase waveform or dead time) * Timebase counter/watchdog timer : 18-bit * Low-power consumption mode : Sleep mode Stop mode CPU intermittent operation mode (Continued) 2 MB90820 Series (Continued) * Package : LQFP-80 (FPT-80P-M05 : 0.50 mm pitch) LQFP-80 (FPT-80P-M11 : 0.65 mm pitch) QFP-80 (FPT-80P-M06 : 0.80 mm pitch) * CMOS technology 3 MB90820 Series s PRODUCT LINEUP Part number Item MB90V820 Development /evaluation product -- 16K bytes MB90F822 MB90F823 MB90822 Mass-produced product (Mask ROM) 64K bytes Classification ROM size RAM size Mass-produced products (Flash ROM with flash security) 64K bytes 128K bytes 4K bytes CPU function Number of instruction : 351 Minimum execution time : 42 ns / 4 MHz (PLL x 6) Addressing mode : 23 Data bit length : 1, 8, 16 bits Maximum memory space: 16M bytes I/O port (CMOS) : 66 Pulse width counter timer : 2 channels Timer function (select the counter timer from three internal clocks) Various pulse width measuring function (H pulse width, L pulse width, rising edge to falling edge period, falling edge to rising edge period, rising edge to rising edge period and falling edge to falling edge period) UART : 2 channels With full-duplex double buffer (8-bit length) Clock asynchronized or clock synchronized transmission (with start and stop bits) can be selected and used. Transmission can be one-to-one (bidirectional communication) or one-to-n (master-slave communication). Reload timer : 2 channels Reload mode, single-shot mode or event count mode selectable PPG timer : 3 channels PWM mode or single-shot mode selectable Channel 0 can be worked with multi-functional timer or independently. I/O port PWC UART 16-bit reload timer 16-bit PPG timer 16-bit free-running timer with up or up-down mode selection and buffer : 1 channel Multi-functional 16-bit output compare : 6 channels timer 16-bit input capture : 4 channels (for AC/DC 16-bit PPG timer : 1 channel motor control) Waveform generator (16-bit timer : 3 channels, 3-phase waveform or dead time) 8/10-bit A/D converter 8-bit D/A converter DTP/External interrupt Low-power consumption 8/10-bit resolution (16 channels) Conversion time : Min 3 s (24 MHz internal clock, including sampling time) 8/10-bit resolution (2 channels) 8 independent channels Interrupt factors : Rising edge, falling edge, "L" level or "H" level Stop mode / Sleep mode / CPU intermittent operation mode (Continued) 4 MB90820 Series (Continued) Part number Item MB90V820 MB90F822 MB90F823 MB90822 Package PGA-299 LQFP-80 (FPT-80P-M05 : 0.50 mm pitch) LQFP-80 (FPT-80P-M11 : 0.65 mm pitch) QFP-80 (FPT-80P-M06 : 0.80 mm pitch) 3.5 V to 5.5 V : Normal operation when A/D converter and D/A converter are not used 4.0 V to 5.5 V : Normal operation when D/A converter is not used 4.5 V to 5.5 V : Normal operation CMOS Power supply voltage for operation*1 Process Emulator power supply*2 4.5 V to 5.5 V* 1 Included *1 : Assurance for the MB90V820 is operating temperature 0 C to +25 C. *2 : It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used. Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply switching) about details. s PACKAGE AND CORRESPONDING PRODUCTS Package PGA299 FPT-80P-M05 FPT-80P-M11 FPT-80P-M06 : Available X : Not available Note: For more information about each package, see "s PACKAGE DIMENSIONS". X X X MB90V820 MB90F822 X MB90F823 X MB90822 X 5 MB90820 Series s DIFFERENCES AMONG PRODUCTS Memory Size In evaluation with an evaluation product, note the difference between the evaluation product and the product actually used. The following items must be taken into consideration. * The MB90V820 does not have an internal ROM, however, operations equivalent to chips with an internal ROM can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of the development tool. * In the MB90V820, images from FF8000H to FFFFFFH are mapped to bank 00, and FE0000H to FF7FFFH are mapped to bank FE and bank FF only. (This setting can be changed by configuring the development tool.) * In the MB90822/F822/F823, images from FF8000H to FFFFFFH are mapped to bank 00, and FF0000H to FF7FFFH are mapped to bank FF only. In the MB90F823, images from FF8000H to FFFFFFH are mapped to bank 00, and FE0000H to FF7FFFH are mapped to bank FE and bank FF only. 6 MB90820 Series s PIN ASSIGNMENT P70/DA0/AN8 P71/DA1/AN9 P72/SIN1/AN10 P73/SOT1/AN11 P74/SCK1/AN12 P75/FRCK/AN13 P76/IN0/AN14 P77/IN1/AN15 P80/IN2 P81/IN3 P82/RTO0(U) * P83/RTO1(X) * P84/RTO2(V) * P85/RTO3(Y) * P86/RTO4(W) * P87/RTO5(Z) * 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 AVR AVcc AVss P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P51/INT7 P50/PPG2 P47/PWO1 P46/PWI1 P45/SIN0 P44/SOT0 P43/SCK0 RST P42/TO0 P41/TIN0 Vss X0 X1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 QFP-80 (TOP VIEW) (FPT-80P-M06) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 C Vss Vcc P00 * P01 * P02 * P03 * P04 * P05 * P06/PWI0 * P07/PWO0 * P10/INT0/DTTI P11/INT1 P12/INT2 P13/INT3 P14/INT4 P15/INT5 P16/INT6 P17 P20/TIN1 P21/TO1 P22 Vcc P23 * : Heavy current pin. MD0 MD1 MD2 P40/PPG1 P37/PPG0 P36 P35 P34 P33 P32 P31 P30 P27 P26 P25 P24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 (Continued) 7 MB90820 Series (Continued) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 AVcc AVR P70/DA0/AN8 P71/DA1/AN9 P72/SIN1/AN10 P73/SOT1/AN11 P74/SCK1/AN12 P75/FRCK/AN13 P76/IN0/AN14 P77/IN1/AN15 P80/IN2 P81/IN3 P82/RTO0(U) * P83/RTO1(X) * P84/RTO2(V) * P85/RTO3(Y) * P86/RTO4(W) * P87/RTO5(Z) * C Vss AVss P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P51/INT7 P50/PPG2 P47/PWO1 P46/PWI1 P45/SIN0 P44/SOT0 P43/SCK0 RST P42/TO0 P41/TIN0 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 LQFP-80 (TOP VIEW) (FPT-80P-M11) (FPT80P-M05) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 Vcc P00 * P01 * P02 * P03 * P04 * P05 * P06/PWI0 * P07/PWO0 * P10/INT0/DTTI P11/INT1 P12/INT2 P13/INT3 P14/INT4 P15/INT5 P16/INT6 P17 P20/TIN1 P21/TO1 P22 * : Heavy current pin. 8 X0 X1 MD0 MD1 MD2 P40/PPG1 P37/PPG0 P36 P35 P34 P33 P32 P31 P30 P27 P26 P25 P24 P23 Vcc 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 MB90820 Series s PIN DESCRIPTION Pin no. LQFP *1 21, 22 17 59 to 54 53 52 QFP *2 23, 24 19 61 to 56 55 54 Pin name X0,X1 RST P00 to P05 P06 PWI0 P07 PWO0 P10 INT0 51 53 DTTI P11 to P16 50 to 45 52 to 47 INT1 to INT6 P17 P20 TIN1 P21 TO1 P22 to P27 P30 to P36 P37 27 29 PPG0 P40 26 28 PPG1 P41 TIN0 P42 TO0 F E D D I/O circuit A B C C C Pin status during reset Reset input Function Oscillating Oscillation input pins. External reset input pin. General-purpose I/O ports. General-purpose I/O ports. PWC0 signal input pin. General-purpose I/O ports. PWC0 signal output pin. General-purpose I/O ports. Can be used as interrupt request input channel 0. Input is enabled when 1 is set in EN0 in standby mode. RTO0 to 5 pins for fixed-level input. This function is enabled when the waveform generator specifies its input bits. General-purpose I/O ports. Can be used as interrupt request input channel 1 to 6. Input is enabled when 1 is set in EN1 to EN6 in standby mode. General-purpose I/O ports. Port input General-purpose I/O ports. External clock input pin for reload timer1. General-purpose I/O ports. Event output pin for reload timer1. General-purpose I/O ports. General-purpose I/O ports. General-purpose I/O ports. Output pins for PPG channel 0. This function is enabled when output of PPG channel 0 is specified. General-purpose I/O ports. Output pins for PPG channel 1. This function is enabled when output of PPG channel 1 is specified. General-purpose I/O ports. External clock input pin for reload timer0. General-purpose I/O ports. Event output pin for reload timer0. 44 43 42 41, 39 to 35 34 to 28 46 45 44 43, 41 to 37 36 to 30 D D D D E 19 18 21 20 F F (Continued) 9 MB90820 Series Pin no. LQFP *1 QFP *2 Pin name P43 16 18 SCK0 P44 15 17 SOT0 P45 14 16 I/O circuit Pin status during reset Function General-purpose I/O ports. F Serial clock I/O pin for UART channel 0. This function is enabled when clock output of UART channel 0 is specified. General-purpose I/O ports. Serial data output pin for UART channel 0. This function is enabled when data output of UART channel 0 is specified. General-purpose I/O ports. Serial data input pin for UART channel 0. While UART channel 0 is operating for input, the input of this pin is used as required. This pin must not be used for any Port Input other input. CMOS input can be selected by user program. General-purpose I/O ports. PWC1 signal input pin. General-purpose I/O ports. PWC1 signal output pin. General-purpose I/O ports. Output pins for PPG channel 2. This function is enabled when output of PPG channel 2 is specified. General-purpose I/O ports. Usable as interrupt request input channel 7. Input is enabled when 1 is set in EN7 in standby mode. General-purpose I/O ports. A/D converter analog input pins. This function is enabled when the analog input is specified (ADER0). Analog input General-purpose I/O ports. D/A converter analog output pins. This function is enabled when D/A converter is specified. A/D converter analog input pins. This function is enabled when the analog input is specified (ADER1). F SIN0 G 13 12 15 14 P46 PWI1 P47 PWO1 P50 F F 11 13 PPG2 P51 F 10 12 INT7 P60 to P67 F 9 to 2 11 to 4 AN0 to AN7 P70, P71 H 78, 77 80, 79 DA0, DA1 AN8, AN9 I (Continued) 10 MB90820 Series Pin no. LQFP *1 QFP *2 Pin name P72 I/O circuit Pin status during reset Function General-purpose I/O ports. Serial data input pin for UART channel 1. While UART channel 1 is operating for input, the input of this pin is used as required. This pin must not be used for any other input. CMOS input can be selected by user program. A/D converter analog input pins. This function is enabled when the analog input is specified (ADER1). General-purpose I/O ports. Serial data output pin for UART channel 1. This function is enabled when data output of UART channel 1 is specified. A/D converter analog input pins. This function is enabled when the analog input is specified (ADER1). General-purpose I/O port. 76 78 SIN1 J AN10 P73 SOT1 75 77 K AN11 P74 SCK1 Analog input K 74 76 Serial clock I/O pin for UART channel 1. This function is enabled when clock output of UART channel 1 is specified. A/D converter analog input pins. This function is enabled when the analog input is specified (ADER1). General-purpose I/O ports. External clock input pin for free-running timer. A/D converter analog input pins. This function is enabled when the analog input is specified (ADER1). General-purpose I/O ports. Trigger input pins for input capture channels 0, 1. When input capture channels 0, 1 are used for input operation, these pins are enabled as required and must not be used for any other input. A/D converter analog input pins. This function is enabled when the analog input is specified (ADER1). AN12 P75 73 75 FRCK AN13 P76, P77 K 72, 71 74, 73 IN0, IN1 K AN14, AN15 (Continued) 11 MB90820 Series (Continued) Pin no. LQFP *1 QFP *2 Pin name P80, P81 70, 69 72, 71 F I/O circuit Pin status during reset Function General-purpose I/O ports. Trigger input pins for input capture channels 2, 3. When input capture channels 2, 3 are used for input operation, these pins are enabled as required and must not be used for any other input. General-purpose I/O ports. Waveform generator output pins. These pins output the waveforms specified at the waveform generator. Output is generated when waveform generator output is enabled. Input pin for operation mode specification. Connect this pin directly to Vcc or Vss. Input pin for operation mode specification. Connect this pin directly to Vcc or Vss. Vcc power input pin for analog circuits. Vref + input pin for the A/D converter. This voltage must not exceed AVcc. Vref - is fixed to AVss. Vss power input pin for analog circuits. Power (0 V) input pin. Power (5 V) input pin. Capacity pin for power stabilization. Please connect to an approximately 0.1 F ceramic capacitor. IN2, IN3 P82 to P87 68 to 63 70 to 65 RTO0 to RTO5 L Port input 25 24, 23 80 79 1 20, 61 40, 60 62 27 26, 25 2 1 3 22, 63 42, 62 64 MD0 MD1, MD0 AVCC AVR AVSS Vss Vcc C M Mode input N - - - - - - Power - Power *1: FPT-80P-M05, FPT-80P-M11 *2: FPT-80P-M06 12 MB90820 Series s I/O CIRCUIT TYPE Classification X1 N-ch P-ch Xout P-ch N-ch Standby mode control Type Remarks Main clock (main clock crystal oscillator) * Oscillation feedback resistor : approx. 1 M A X0 B R * Hysteresis input * Pull-up resistor : approx. 50 k * CMOS output * Hysteresis input * Selectable pull-up resistor : approx. 50 k * IOL = 12 mA R P-ch Pull-up control P-ch Pout Nout C N-ch Hysteresis input Standby mode control R P-ch Pull-up control P-ch Pout Nout D * CMOS output * Hysteresis input * Selectable pull-up resistor : approx. 50 k * IOL = 4 mA N-ch Hysteresis input Standby mode control R P-ch Pull-up control P-ch Pout Nout E N-ch * CMOS output * CMOS input * Selectable pull-up resistor : approx. 50 k * IOL = 4 mA CMOS input Standby mode control (Continued) 13 MB90820 Series Classification P-ch Type Pout Nout Remarks * CMOS output * Hysteresis input * IOL = 4 mA F N-ch Hysteresis input Standby mode control P-ch Pout Nout N-ch * CMOS output * Hysteresis input * CMOS input (selectable for UART0 data input pin) * IOL = 4 mA G Hysteresis input CMOS input Standby mode control P-ch Pout Nout * * * * CMOS output CMOS input Analog input IOL = 4 mA H N-ch CMOS input Analog input control Analog input P-ch Pout Nout N-ch * * * * * CMOS output Hysteresis input Analog output Analog input IOL = 4 mA I Hysteresis input Analog I/O control Analog output Analog input (Continued) 14 MB90820 Series (Continued) Classification P-ch Type Pout Nout Remarks * CMOS output * Hysteresis input * CMOS input (selectable for UART1 data input pin) * IOL = 4 mA N-ch J Hysteresis input CMOS input Analog input control Analog input P-ch Pout Nout * * * * CMOS output Hysteresis input Analog input IOL = 4 mA K N-ch Hysteresis input Analog input control Analog input P-ch Pout Nout * CMOS output * Hysteresis input * IOL = 12 mA L N-ch Hysteresis input Standby mode control M R Mask ROM / evaluation product * Hysteresis input * Selectable pull-up resistor : approx. 50 k FLASH product * CMOS input * No pull-down resistor Mask ROM / evaluation product * Hysteresis input FLASH product * CMOS input N 15 MB90820 Series s HANDLING DEVICES 1. Preventing latch-up CMOS ICs may cause latch-up in the following situations: * When a voltage higher than VCC or lower than VSS is applied to input or output pins. * When a voltage exceeding the rating is applied between VCC and VSS. * When the AVCC power supply is applied before the VCC voltage. If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Use meticulous care not to exceed the rating. For the same reason, also be careful not to let the analog power-supply voltage exceed the digital power-supply voltage. 2. Handling unused pins Unused input pins left open may cause abnormal operations, or latch-up leading to permanent damage. Unused input pins should be pulled up or pulled down through at least 2 k resistance. Unused input/output pins may be left open in output state, but if such pins are in input state they should be handled in the same way as input pins. If any output pins are unused, set them to open. 3. Use of the external clock To use an external clock, drive only the X0 pin and leave the X1 pin open (See the illustration below). X0 MB90820 series Open X1 4. Power supply pins (VCC/VSS) In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply and a ground lines to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance. It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 F between VCC and VSS near this device. 5. Crystal oscillator circuit Noise near the X0 and X1 pins may cause the device to malfunction. Design the printed circuit board so that X0, X1, the crystal oscillator (or ceramic oscillator) and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended to design the PC board artwork with the X0 and X1 pins surrounded by ground plane because stable operation can be expected with such a layout. 6. Turning-on sequence of power supply to A/D converter and D/A converter Make sure to turn on the A/D converter and D/A converter power supply (AVCC, AVSS, AVR) and analog inputs (AN0 to AN15) after turning-on the digital power supply (VCC). 16 MB90820 Series Turn-off the digital power after turning off the A/D converter and D/A converter supply and analog inputs. In this case, make sure that the voltage of AVR does not exceed AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable). 7. Connection of unused pins of A/D converter and D/A converter When the A/D converter and D/A converter are not used, connect the pins as follows: AVCC = VCC, AVSS = AVR = VSS. 8. N.C. pin The N.C. (internally connected) pin must be opened for use. 9. Notes on energization To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 s or more. 10. Initialization In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers turning on the power again. 11. Return from standby state If the power supply voltage goes below the standby RAM holding voltage in the standby state, the device may fail to return from the standby state. In this case, reset the device via the external reset pin to return to the normal state. 17 MB90820 Series s BLOCK DIAGRAM X0 X1 Clock control circuit Reset circuit (Watchdog timer) Interrupt controller CPU F2MC-16LX series core Other pins Vss x 2, Vcc x 2, MD0 to MD2, C RST Timebase timer Delayed interrupt generator 7 Multi-functional timer P51/INT7 P16/INT6 to P11/INT1 P45/SIN0 P44/SOT0 P43/SCK0 P72/SIN1/AN10 P73/SOT1/AN11 P74/SCK1/AN12 6 8 P30 to P36 P37/PPG0 DTP/External interrupt 16-bit PPG (Ch0) 16-bit input capture (Ch0/1/2/3) 16-bit free-running timer 16-bit output compare (Ch0~5) 4 4 UART (Ch0) UART (Ch1) 16-bit PPG (Ch1) 16-bit PPG (Ch2) PWC (Ch1) P76/IN0/AN14 P77/IN1/AN15 P80/IN2 P81/IN3 P75/FRCK/AN13 P40/PPG1 F2MC-16LX bus P82/RTO0 (U) * P83/RTO1 (X) * P84/RTO2 (V) * P85/RTO3 (Y) * P86/RTO4 (W) * P87/RTO5 (Z) * P10/INT0/DTTI P17 P50/PPG2 Waveform generator PWC (Ch0) 6 P46/PWI1 P47/PWO1 P06/PWI0 * P07/PWO0 * P00 to P05 * P42/TO0 P41/TIN0 16-bit reload timer (Ch0) 16-bit reload timer (Ch1) 6 CMOS I/O port 0, 1, 3, 7, 8 CMOS I/O port 6 P21/TO1 P20/TIN1 P22 to P27 A/D converter (8/10 bit) 16 CMOS I/O port 1, 2, 4, 5, 7 RAM ROM 8-bit D/A converter ROM correction ROM mirroring CMOS I/O port 7 P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 AVR AVCC AVSS P70/DA0/AN8 P71/DA1/AN9 Note : P00 to P07, P10 to P17, P20 to P27 and P30 to P37: With build-in resistors that can be used as input pull-up resistors. * : Heavy current drive pin. 18 MB90820 Series s MEMORY MAP FFFFFFH Address #1 Address #1 - 1H ROM area 010000H 00FFFFH Address #2 Address #2 - 1H ROM area* (FF bank image) : Internal access memory : Access not allowed Address #3 + 1H Address #3 000100H 0000FFH 0000F0H 0000EFH 000000H RAM Register area Peripheral area * : In Single chip mode, the mirror function is supported. Parts no. MB90822 MB90F822 MB90F823 MB90V820 Address#1 FF0000H FF0000H FE0000H (FE0000H) Address#2 008000H 008000H 008000H 008000H Address#3 0010FFH 0010FFH 0010FFH 0040FFH Note: The ROM data of bank FF is reflected to the upper address of bank 00, realizing effective use of the C compiler small model. The lower 16-bit is assigned to the same address, enabling reference of the table on the ROM without stating "far". For example, if an attempt has been made to access 00C000H, the contents of the ROM at FFC000H are accessed actually. Since the ROM area of the FF bank exceeds 32K bytes, the whole area cannot be reflected in the image for the 00 bank. The ROM data at FF8000H to FFFFFFH looks, therefore, as if it were the image for 008000H to 00FFFFH. Thus, it is recommended that the ROM data table be stored in the area of FF8000H to FFFFFFH. 19 MB90820 Series s F2MC-16LX CPU PROGRAMMING MODEL * Dedicated registers AH AL : Accumulator (A) Dual 16-bit register used for storing results of calculation etc. The two 16-bit registers can be combined to be used as a sequence of 32-bit register. : User stack pointer (USP) The 16-bit pointer indicating the user stack address. : System stack pointer (SSP) The 16-bit pointer indicating the system stack address. : Processor status (PS) The 16-bit register indicating the system status. : Program counter (PC) The 16-bit register indicating storing location of the current instruction code. : Direct page register (DPR) The 8-bit register indicating bit 8 through 15 of the operand address in executing of the short direct addressing. : Program bank register (PCB) The 8-bit register indicating the program space. : Data bank register (DTB) The 8-bit register indicating the data space. : User stack bank register (USB) The 8-bit register indicating the user stack space. : System stack bank register (SSB) The 8-bit register indicating the system stack space. : Additional data bank register (ADB) The 8-bit register indicating the additional USP SSP PS PC DPR PCB DTB USB SSB ADB 8 bit 16 bit 32 bit 20 MB90820 Series * General-purpose registers Maximum of 32 banks R7 R5 R3 R1 RW3 R6 R4 R2 R0 RW7 RL3 RW6 RW5 RL2 RW4 RL1 RW2 RW1 RL0 000180H + (RP x 10H) RW0 16 bit * Processor status (PS) ILM RP CCR bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PS Initial value X ILM2 ILM1 ILM0 0 0 0 B4 0 B3 0 B2 0 B1 0 B0 0 I 0 S 1 T X N X Z X V X C X : Unused : Undefined 21 MB90820 Series s I/O MAP Address Abbreviation Register Byte Word access access Resource name Initial value 000000H 000001H 000002H 000003H 000004H 000005H 000006H 000007H 000008H 000009H to 00000FH 000010H 000011H 000012H 000013H 000014H 000015H 000016H 000017H 000018H 000019H to 00001FH 000020H 000021H 000022H 000023H 000024H 000025H 000026H 000027H 000028H 000029H 00002AH 00002BH 00002CH PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Prohibited area DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 DDR8 Port 0 data direction register Port 1 data direction register Port 2 data direction register Port 3 data direction register Port 4 data direction register Port 5 data direction register Port 6 data direction register Port 7 data direction register Port 8 data direction register R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 0 00 00 0 00 B 0 00 00 0 00 B 0 00 00 0 00 B 0 00 00 0 00 B 0 00 00 0 00 B XXXXXX00B 0 00 00 0 00 B 0 00 00 0 00 B 0 00 00 0 00 B Prohibited area SMR0 SCR0 SIDR0 / SODR0 SSR0 SMR1 SCR1 SIDR1 / SODR1 SSR1 PWCSL1 PWCSH1 PWC1 DIV1 Serial mode register 0 Serial control register 0 Serial input data register 0 / Serial output data register 0 Serial status register 0 Serial mode register 1 Serial control register 1 Serial input data register 1 / Serial output data register 1 Serial status register 1 PWC control status register CH1 PWC data buffer register CH1 Divide ratio control register CH1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W PWC timer (CH1) UART1 UART0 00000000B 0 00 00 1 00B XXXXXXXXB 0 00 01 0 00B 00000000B 0 00 00 1 00B XXXXXXXXB 0 00 01 0 00B 00000000B 00000000B XXXXXXXXB XXXXXXXXB XXXXXX00B (Continued) 22 MB90820 Series Address Abbreviation Register Byte Word access access Resource name Initial value 00002DH, 00002EH 00002FH 000030H 000031H 000032H 000033H 000034H 000035H 000036H 000037H 000038H 000039H 00003AH 00003BH 00003CH 00003DH 00003EH 00003FH 000040H 000041H 000042H 000043H 000044H 000045H 000046H 000047H 000048H 000049H 00004AH 00004BH 00004CH 00004DH 00004EH 00004FH CDCR1 PDCR0 PCSR0 PDUT0 PCNTL0 PCNTH0 PDCR1 PCSR1 PDUT1 PCNTL1 PCNTH1 PDCR2 PCSR2 PDUT2 PCNTL2 PCNTH2 CDCR0 PCKCR ENIR EIRR ELVRL ELVRH PLL clock control register Prohibited area W R/W R/W R/W R/W Prohibited area Clock division control register CH0 R/W R/W Communication prescaler 0 Communication prescaler 1 00XXX000B W R/W R/W R/W R/W DTP/ external interrupt PLL XXXX0000B 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B DTP / Interrupt enable register DTP / Interrupt cause register Request level setting register (lower byte) Request level setting register (higher byte) Prohibited area Clock division control register CH1 PPG0 down counter register PPG0 period setting register PPG0 duty setting register PPG0 control status register PPG1 down counter register PPG1 period setting register PPG1 duty setting register PPG1 control status register PPG2 down counter register PPG2 period setting register PPG2 duty setting register PPG2 control status register R/W R/W R/W R/W R/W R/W R/W R/W R W 16-bit PPG timer (CH0) W R/W R/W R W 16-bit PPG timer (CH1) W R/W R/W R W 16-bit PPG timer (CH2) W R/W R/W 00XXX000B 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XX000000B 0 0 0 0 0 0 0 0B 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XX000000B 0 0 0 0 0 0 0 0B 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XX000000B 0 0 0 0 0 0 0 0B (Continued) 23 MB90820 Series Address Abbreviation Register Byte Word access access Resource name Initial value 000050H 000051H 000052H 000053H 000054H 000055H 000056H 000057H 000058H 000059H 00005AH 00005BH 00005CH 00005DH 00005EH 00005FH 000060H 000061H 000062H 000063H 000064H 000065H 000066H 000067H 000068H 000069H 00006AH 00006BH 00006CH to 00006EH TMRR0 TMRR1 TMRR2 DTCR0 DTCR1 DTCR2 SIGCR CPCLRB / CPCLR TCDT TCCSL TCCSH IPCP0 IPCP1 IPCP2 IPCP3 PICSL01 PICSH01 ICSL23 ICSH23 16-bit timer register 0 16-bit timer register 1 16-bit timer register 2 16-bit timer control register 0 16-bit timer control register 1 16-bit timer control register 2 Waveform control register Compare clear buffer register/ Compare clear register (lower) Timer register (lower) Timer control status register (lower) Timer control status register (upper) Input capture data register CH0 Input capture data register CH1 Input capture data register CH2 Input capture data register CH3 Input capture control status register (ch0,1) (lower) PPG output control / Input capture control status register (ch0,1) (upper) Input capture control status register (ch2, 3) (lower) Input capture control status register (ch2, 3) (upper) R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W 16-bit free-running timer R/W R/W R/W R R R R R/W R/W R/W R Waveform generator XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0 00 00 0 00 B 0 00 00 0 00 B 0 00 00 0 00 B 0 00 00 0 00B 11111111B 11111111B 00000000B 00000000B 16-bit free-running timer 00000000B X0000000B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 16-bit input capture (CH0 to CH3) XXXXXXXXB 00000000B 00000000B 00000000B XXXXXX00B Prohibited area (Continued) 24 MB90820 Series Address Abbreviation Register Byte Word access access Resource name Initial value 00006FH 000070H 000071H 000072H 000073H 000074H 000075H 000076H 000077H 000078H 000079H 00007AH 00007BH 00007CH 00007DH 00007EH 00007FH 000080H 000081H 000082H 000083H 000084H 000085H 000086H 000087H 000088H 000089H 00008AH, 00008BH 00008CH 00008DH ROMM OCCPB0 / OCCP0 OCCPB1 / OCCP1 OCCPB2 / OCCP2 OCCPB3 / OCCP3 OCCPB4 / OCCP4 OCCPB5 / OCCP5 OCS0 OCS1 OCS2 OCS3 OCS4 OCS5 TMCSRL0 TMCSRH0 TMR0 / TMRD0 TMCSRL1 TMCSRH1 TMR1 / TMRD1 ROM mirroring function selection register Output compare buffer register / Output compare register 0 Output compare buffer register / Output compare register 1 Output compare buffer register / Output compare register 2 Output compare buffer register / Output compare register 3 Output compare buffer register / Output compare register 4 Output compare buffer register / Output compare register 5 Compare control register CH0 Compare control register CH1 Compare control register CH2 Compare control register CH3 Compare control register CH4 Compare control register CH5 Timer control status register CH0 (lower) Timer control status register CH0 (upper) 16 bit timer register CH0 / 16-bit reload register CH0 Timer control status register CH1 (lower) Timer control status register CH1 (upper) 16 bit timer register CH1 / 16-bit reload register CH1 W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ROM mirroring function XXXXXXX1B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Output compare (CH0 to CH5) XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 00 00 00 0 0 B X 00 00 00 0B 00 00 00 0 0 B X 00 00 00 0B 00 00 00 0 0 B X 00 00 00 0B 0 0 0 0 0 0 0 0B 16-bit reload timer (CH0) XXXX0000B XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B 16-bit reload timer (CH1) XXXX0000B XXXXXXXXB XXXXXXXXB Prohibited area RDR0 RDR1 Port 0 pull-up resistor setting register Port 1 pull-up resistor setting register R/W R/W R/W R/W Port 0 Port 1 00 0 0 0 0 0 0 B 00 0 0 0 0 0 0 B (Continued) 25 MB90820 Series Address Abbreviation Register Byte Word access access Resource name Initial value 00008EH 00008FH 000090H to 00009DH 00009EH 00009FH 0000A0H 0000A1H 0000A2H to 0000A7H 0000A8H 0000A9H 0000AAH to 0000ADH 0000AEH 0000AFH 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH RDR2 RDR3 Port 2 pull-up resistor setting register Port 3 pull-up resistor setting register R/W R/W R/W R/W Port 2 Port 3 00 0 0 0 0 0 0B 00 0 0 0 0 0 0B Prohibited area PACSR DIRR LPMCR CKSCR Program address detection control status register Delayed interrupt cause / clear register Low-power consumption mode control register Clock selection register R/W R/W R/W R/W R/W R/W R/W R/W Address match detection Delayed interrupt 0 0 0 0 0 0 0 0B XXXXXXX0B Low-power 0 0 0 1 1 0 0 0B consumption control register 11 11 1 10 0B Prohibited area WDTC TBTC Watchdog timer control register Timebase timer control register R/W R/W R/W R/W Watchdog timer Timebase timer XXXXX111B 1XX00100 B Prohibited area FMCS Flash memory control status register Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 R/W R/W Flash memory interface circuit 0 0 0 X0 0 0 0B Prohibited area ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Interrupt controller 0 0 0 0 0 1 1 1B 00 00 0 11 1 B 00 00 0 11 1 B 00 00 0 11 1 B 00 00 0 11 1 B 00 00 0 11 1 B 00 00 0 11 1 B 00 00 0 11 1 B 00 00 0 11 1 B 00 00 0 11 1 B 00 00 0 11 1 B 00 00 0 11 1 B 00 00 0 11 1 B 00 00 0 11 1 B 00 00 0 11 1 B 00 00 0 11 1 B (Continued) 26 MB90820 Series (Continued) Address Abbreviation Register Byte Word access access Resource name Initial value 0000C0H 0000C1H 0000C2H 0000C3H 0000C4H 0000C5H 0000C6H 0000C7H 0000C8H 0000C9H 0000CAH 0000CBH 0000CCH 0000CDH 0000CEH 0000CFH 0000D0H 0000D1H to 0000EFH 0000F0H to 0000FFH 001FF0H 001FF1H 001FF2H 001FF3H 001FF4H 001FF5H PWCSL0 PWCSH0 PWC0 DIV0 ADER0 ADCS0 ADCS1 ADCR0 ADCR1 ADSR0 ADSR1 DAT0 DAT1 DACR0 DACR1 ADER1 PWC control status register CH0 PWC data buffer register CH0 Divide ratio control register CH0 A/D input enable register 0 A/D control status register 0 A/D control status register 1 A/D data register 0 A/D data register 1 A/D setting register 0 A/D setting register 1 D/A data register 0 D/A data register 1 D/A control register 0 D/A control register 1 A/D input enable register 1 R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W Port 7, A/D 8-bit D/A converter 8/10-bit A/D converter Port 6, A/D PWC timer (CH0) 00000000B 00000000B XXXXXXXXB XXXXXXXXB XXXXXX00B 1 11 1 11 11 B 000XXXX0B 00 0 00 00 XB 0 00 0 00 00B XXXXXX00B 0 00 0 00 00B 0 00 0 00 00B XXXXXXXXB XXXXXXXXB XXXXXXX0B XXXXXXX0B 1 11 1 11 11 B Prohibited area External area PADRL0 PADRM0 PADRH0 PADRL1 PADRM1 PADRH1 Program address detection register 0 (lower) Program address detection register 0 (middle) Program address detection register 0 (higher) Program address detection register 1 (lower) Program address detection register 1 (middle) Program address detection register 1 (higher) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Address match detection * Meaning of abbreviations used for reading and writing R/W: Read and write enabled R : Read-only W : Write-only * Explanation of initial values 0 : The bit is initialized to 0. 1 : The bit is initialized to 1. X : The initial value of the bit is undefined. 27 MB90820 Series s INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER Interrupt cause Reset INT9 instruction Exception processing A/D converter conversion termination Output compare channel 0 match End of measurement by PWC timer 0 / PWC timer 0 overflow 16-bit PPG timer 0 Output compare channel 1 match 16-bit PPG timer 1 Output compare channel 2 match 16-bit reload timer 1 underflow Output compare channel 3 match DTP/ext. interrupt channels 0/1 detection DTTI Output compare channel 4 match DTP/ext. interrupt channels 2/3 detection Output compare channel 5 match End of measurement by PWC timer 1 / PWC timer 1 overflow DTP/ext. interrupt channels 4 detection DTP/ext. interrupt channels 5 detection DTP/ext. interrupt channels 6 detection DTP/ext. interrupt channels 7 detection Waveform generator 16-bit timers 0/1/2 underflow 16-bit reload timer 0 underflow 16-bit free-running timer zero detect 16-bit PPG timer 2 Input capture channels 0/1 16-bit free-running timer compare clear Input capture channels 2/3 Timebase timer UART1 receive UART1 send UART0 receive UART0 send Flash memory status Delayed interrupt generator module 2 EI2OS support x x x Interrupt vector Number #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H FFFF60H FFFF5CH FFFF58H FFFF54H Interrupt control register ICR Address ICR00 0000B0H Priority High ICR01 0000B1H ICR02 ICR03 0000B2H 0000B3H ICR04 0000B4H ICR05 0000B5H ICR06 0000B6H ICR07 ICR08 0000B7H 0000B8H ICR09 0000B9H ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH Low : Can be used and support the EI OS stop request. : Can be used and interrupt request flag is cleared by EI2OS interrupt clear signal. x : Cannot be used. : Usable when an interrupt cause that shares the ICR is not used. 28 MB90820 Series s PERIPHERAL RESOURCES 1. Low-power Consumption Control Circuit The MB90820 series has the following CPU operating mode configured by selection of an operating clock and clock operation control. * Clock mode PLL clock mode : A PLL clock that is a multiple of the oscillation clock (HCLK) frequency is used to operate the CPU and peripheral functions. Main clock mode : The main clock, with a frequency one-half that of the oscillation clock (HCLK), is used to operate the CPU and peripheral functions. In main clock mode, the PLL divide circuit is inactive. * CPU intermittent operation mode CPU intermittent operation mode causes the CPU to operate intermittently, while high-speed clock pulses are supplied to peripheral functions, reducing power consumption. In CPU intermittent operation mode, clock pulses are supplied intermittently to the CPU when it is accessing a register, internal memory, a peripheral function, or an external unit. * Standby mode In standby mode, the low power consumption control circuit reduces power consumption by stopping; * The supply of the clock to CPU (sleep mode) * CPU and peripheral functions (timebase timer mode) * The oscillation clock itself (stop mode) * PLL sleep mode PLL sleep mode is activated to stop the CPU operating clock when the microcontroller enters PLL clock mode; other components continue to operate on the PLL clock. * Main sleep mode Main sleep mode is activated to stop the CPU operating clock when the microcontroller enters main clock mode; other components continue to operate on the main clock. * PLL timebase timer mode PLL timebase timer mode causes microcontroller operation, with the exception of the oscillation clock, PLL clock and timebase timer, to stop. All functions other than the timebase timer are deactivated. * Main timebase timer mode Main timebase timer mode causes microcontroller operation, with the exception of the oscillation clock, main clock and the timebase timer, to stop. All functions other than the timebase timer are deactivated. * Stop mode Stop mode causes the source oscillation to stop. All functions are deactivated. 29 MB90820 Series (1) Register configuration Clock Selection Register Address: 00000A1H Read/write Initial value 15 14 MCM R 1 14 13 WS1 R/W 1 13 12 WS0 R/W 1 12 11 Reserved 10 MCS R/W 1 10 9 CS1 R/W 0 9 8 CS0 R/W 0 8 CS2 W 0 Bit CKSCR Reserved R/W 1 15 R/W 1 11 PLL Clock Control Register Address: 000002FH Read/write Initial value Bit PCKCR Reserved Reserved Reserved X X X X W 0 W 0 W 0 Low-power Consumption Mode Control Register 7 Address: 0000A0H Read/write Initial value STP W 0 6 SLP W 0 5 SPL R/W 0 4 RST W 1 3 TMD W 1 2 CG1 R/W 0 1 CG0 R/W 0 0 Reserved Bit LPMCR R/W 0 30 MB90820 Series (2) Block diagram Low power mode control register (LPMCR) STP SLP SPL RST TMD CG1 CG0 RESV Pin high impedance control circuit Internal reset generation circuit CPU intermittent operation selecter Pin Hi-z control RST Pin Internal reset Select intermittent cycles CPU clock control circuit CPU clock Release reset 3 Standby control circuit Stop and sleep signals Cancel interruption Stop signal Clock generator Clock selector Machine clock Peripheral clock control circuit Oscillation stabilization waiting time is passed Peripheral clock 3 2 x1 x2 x3 x4 x6 Oscillation stabilization waiting time interval selector PLL multiplier circuit RESV MCM WS1 WS0 RESV MCS CS1 Clock selection register (CKSCR) CS0 CS2 PLL clock control register (PCKCR) X0 Pin System clock generation circuit Divided by 2 Divided by 512 Divided by 2 Divided by 4 Divided by 2 Divided by 2 Main clock Timebase timer X1 Pin 31 MB90820 Series 2. I/O Ports (1) Outline of I/O ports Each I/O port outputs data from CPU to I/O pins or inputs signals from I/O pins to CPU through port data register (PDR). Direction of the data flow (input or output) for each I/O pin can be designated in bit unit by port data direction register (DDR). The function of each port and the resource I/O multiplexed with it are described below: * * * * * * * * General-purpose I/O port/resource (PWC) General-purpose I/O port/resources (DTP / Multi-functional timer) General-purpose I/O port/resource (16-bit reload timer) General-purpose I/O port/resource (16-bit PPG timer) General-purpose I/O port/resources (16-bit PPG timer / 16-bit reload timer / UART / PWC) General-purpose I/O port/resources (16-bit PPG timer / DTP) General-purpose I/O port/resource (8/10-bit A/D converter) General-purpose I/O port/resources (8/10-bit A/D converter / 8-bit D/A converter / UART/ 16-bit free-running timer / 16-bit input capture) * Port 8 : General-purpose I/O port/resources (16-bit input capture / Multi-functional timer) (2) Register configuration Register Port 0 data register (PDR0) Port 1 data register (PDR1) Port 2 data register (PDR2) Port 3 data register (PDR3) Port 4 data register (PDR4) Port 5 data register (PDR5) Port 6 data register (PDR6) Port 7 data register (PDR7) Port 8 data register (PDR8) Port 0 data direction register (DDR0) Port 1 data direction register (DDR1) Port 2 data direction register (DDR2) Port 3 data direction register (DDR3) Port 4 data direction register (DDR4) Port 5 data direction register (DDR5) Port 6 data direction register (DDR6) Port 7 data direction register (DDR7) Port 8 data direction register (DDR8) A/D input enable register (ADER0) A/D input enable register (ADER1) Port 0 pull-up resistor setting register (RDR0) Port 1 pull-up resistor setting register (RDR1) Port 2 pull-up resistor setting register (RDR2) Port 3 pull-up resistor setting register (RDR3) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Address 000000H 000001H 000002H 000003H 000004H 000005H 000006H 000007H 000008H 000010H 000011H 000012H 000013H 000014H 000015H 000016H 000017H 000018H 0000C5H 0000D0H 00008CH 00008DH 00008EH 00008FH Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000000B 00000000B 00000000B 00000000B 00000000B XXXXXX00B 00000000B 00000000B 00000000B 11111111B 11111111B 00000000B 00000000B 00000000B 00000000B Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 : : : : : : : : R/W: Read/write enabled X : Undefined 32 MB90820 Series (3) Block diagram * Block diagram of Port 0 (P00 to P06), Port 1 (P17) and Port 2 (excluding P21) pins Standby control (SPL=1) RDR Port data register (PDR) Pull-up resistor PDR read Output latch Resource input Internal data bus PDR write Pin Port data direction register (DDR) Direction latch DDR write DDR read Standby control (SPL=1) * Block diagram of Port 0 (P07) and Port 2 (P21) pins Standby control (SPL=1) RDR Port data register (PDR) Resource output Resource input Pull-up resistor PDR read Output latch Resource output enable Internal data bus PDR write Pin Port data direction register (DDR) Direction latch DDR write DDR read Standby control (SPL=1) 33 MB90820 Series * Block diagram of Port 1 (P10 to P16) pins Standby control (SPL=1) RDR Port data register (PDR) Pull-up resistor PDR read Internal data bus Output latch Resource input PDR write Pin Port data direction register (DDR) Direction latch DDR write External interrupt enable Standby control (SPL=1) DDR read * Block diagram of Port 3 (excluding P37) pins Standby control (SPL=1) RDR Port data register (PDR) Pull-up resistor PDR read Internal data bus Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write DDR read Standby control (SPL=1) 34 MB90820 Series * Block diagram of Port 3 (P37) pin Standby control (SPL=1) RDR Resource output Port data register (PDR) Resource output enable Pull-up resistor PDR read Internal data bus Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write DDR read Standby control (SPL=1) * Block diagram of Port 4 pins (excluding P41, P45 and P46) pins Resource output Port data register (PDR) Resource input Resource output enable PDR read Internal data bus Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write DDR read Standby control (SPL=1) 35 MB90820 Series * Block diagram of Port 4 (P41 and P46) pins Resource input Port data register (PDR) PDR read Internal data bus Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write DDR read Standby control (SPL=1) * Block diagram of P45 pin UART0 data input UART0 data input level selection bit Port data register (PDR) PDR read Internal data bus Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write DDR read Standby control (SPL=1) 36 MB90820 Series * Block diagram of Port 5 (P50) pin Resource output Port data register (PDR) Resource input Resource output enable PDR read Internal data bus Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write DDR read Standby control (SPL=1) * Block diagram of Port 5 (P51) pin Resource input Port data register (PDR) PDR read Internal data bus Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write External interrupt enable Standby control (SPL=1) DDR read 37 MB90820 Series * Block diagram of Port 6 pins A/D converter input A/D converter channel selection bit Port data register (PDR) PDR read Internal data bus Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write DDR read Standby control (SPL=1) ADER * Block diagram of Port 7 (P70, P71) pins A/D converter channel selection bit A/D converter input Port data register (PDR) D/A converter output PDR read Internal data bus Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write DDR read ADER D/A converter output enable bit Standby control (SPL=1) 38 MB90820 Series * Block diagram of P72 pin A/D converter channel selection bit A/D converter input UART1 data input UART1 data input level selection bit Port data register (PDR) PDR read Internal data bus Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write DDR read Standby control (SPL=1) ADER * Block diagram of Port 7(P73, P74) pins A/D converter input A/D converter channel selection bit Resource input Resource output Port data register (PDR) Resource output enable PDR read Internal data bus Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write DDR read Standby control (SPL=1) ADER 39 MB90820 Series * Block diagram of Port 7 (P75 to P77) pins A/D converter input A/D converter channel selection bit Resource input Port data register (PDR) PDR read Internal data bus Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write DDR read Standby control (SPL=1) ADER * Block diagram of Port 8 (P80, P81) pins Resource input Port data register (PDR) PDR read Internal data bus Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write DDR read Standby control (SPL=1) 40 MB90820 Series * Block diagram of Port 8 (P82 to P87) pins Resource output Port data register (PDR) Resource input Resource output enable PDR read Internal data bus Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write DDR read Standby control (SPL=1) 41 MB90820 Series 3. Timebase Timer The timebase timer is an 18-bit free-running counter (timebase counter) that counts up in synchronization with the internal count clock (divided by 1/2 of oscillation clock). Features of timebase timer : * Generates the interruption at counter-overflow * Supports for EI2OS * Interval timer function: Generates an interrupt at four different time intervals * Clock supply function: Four different clock can be selected as watchdog timer's count clock Supply clock for oscillation stabilization (1) Register configuration Timebase Timer Control Register 15 Address: 0000A9H Read/write Initial value Reserved 14 13 12 TBIE R/W 0 11 TBOF R/W 0 10 TBR W 1 9 TBC1 R/W 0 8 TBC0 R/W 0 Bit number TBTC R/W 1 X X (2) Block diagram To watchdog timer Timebase timer counter Divided by 2 of HCLK x 2 1 x 22 x 2 3 . . . ... x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218 OF OF OF OF To the oscillation setting time selector in the clock control section Interval timer selector TBOF set Counter clear Power-on reset Stop mode start CKSCR: MCS = 1, 0*1 Counter clear circuit TBOF clear Timebase timer interrupt signal #36 (24H)*2 -- -- -- TBIE TBOF Timebase timer TBR TBC1 TBC0 control register (TBTC) OF: Overflow HCLK: Oscillation clock *1: Switching of the machine clock from the oscillation clock to the PLL clock *2: Interrupt number 42 MB90820 Series 4. Watchdog Timer The watchdog timer is a 2-bit counter that uses the timebase timer's supply clock as the count clock. After activation, if the watchdog timer is not cleared within a given period, the CPU will be reset. * Features of watchdog timer : Reset CPU at four different time intervals Indicate the reset causes by status bits (1) Register configuration Watchdog Timer Control Register 7 Address: 0000A8H Read/write Initial value PONR R X X 6 5 WRST R X 4 ERST R X 3 SRST R X 2 WTE W 1 1 WT1 W 1 0 WT0 W 1 Bit WDTC (2) Block diagram Watchdog timer control register (WDTC) PONR STBR WRST ERST SRST WTE WT1 WT0 Watchdog timer 2 Activation with CLR CLR Over flow Watchdog reset generator Start of sleep mode Start of hold status mode Start of stop mode Counter clear control circuit Count clock selector 2-bit counter To the internal reset generator CLR Clear 4 Timebase timer counter Divided by 1/2 of HCLK x21 x22 ... x28 x29 x210 x211 x212 x213 x214 x215 x216 x217 x218 HCLK : Oscillation clock frequency 43 MB90820 Series 5. 16-bit reload timer (x 2) The 16-bit reload timer provides two operating mode, internal clock mode and event count mode. In each operating mode, the 16-bit down counter can be reloaded (reload mode) or stopped by underflow (one-shot mode). Output pins TO1 and TO0 are able to output different waveform according to the counter operating mode. TO1 and TO0 toggles when counter underflows if counter is operated as reload mode. TO1 and TO0 output specified level (H or L) during counting if the counter is in one-shot mode. Features of the 16-bit reload timer : * Interrupt when timer underflows * Supports for EI2OS * Internal clock operating mode : Three internal count clocks can be selected. Counter can be activated by software or external trigger (signal at TIN1 and TIN0 pins). Counter can be reloaded or stopped when underflow after activated. * Event count operating mode : Counter counts down one by one with specified edge at TIN1 and TIN0 pins. Counter can be reloaded or stopped when underflow. (1) Register configuration 16-bit Timer Register/16-bit Reload Timer Register (Upper) 15 14 13 12 Address: ch0 000085H ch1 000089H Read/write Initial value D15 R/W X D14 R/W X D13 R/W X D12 R/W X D11 R/W X 4 D03 R/W X 11 D10 R/W X 3 10 D09 R/W X 2 9 D08 R/W X 1 8 Bit TMR0, TMR1 / TMRD0, TMRD1 16-bit Timer Register/16-bit Reload Timer Register (Lower) 7 6 5 Address: ch0 000084H ch1 000088H Read/write Initial value D07 R/W X D06 R/W X D05 R/W X D04 R/W X 0 Bit TMR0, TMR1 / TMRD0, TMRD1 D02 R/W X D01 R/W X D00 R/W X Timer Control Status Register (Upper) 15 Address: ch0 000083H ch1 000087H Read/write Initial value 14 13 FSEL R/W 1 5 12 CSL1 R/W 0 4 11 10 9 8 Bit TMCSRH0, TMCSRH1 CSL0 MOD2 MOD1 R/W 0 3 UF R/W 0 R/W 0 2 CNTE R/W 0 R/W 0 1 TRG R/W 0 0 X X 7 X 6 Timer Control Status Register (Lower) Address: ch0 000082H ch1 000086H Read/write Initial value Bit TMCSRL0, TMCSRL1 MOD0 OUTE OUTL RELD R/W 0 R/W 0 R/W 0 R/W 0 INTE R/W 0 Note : Registers TMR0, TMR1/TMRD0, TMRD1 are word access only. 44 MB90820 Series (2) Block diagram Internal data bus TMRD0*1 Output signal generation Rever- circuit sed Reload signal Reload control circuit UF FSEL: Initial value "1" Machine clock Prescaler Wait signal to UART0,1*1 Pin EN P42/TO0*1 Count clock generation circuit 3 Function select _ _ _ FSEL CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE Timer control status register (TMCSR0) *1 UF CNTE TRG *1: Used for channel 0/1. <> indicates channel 1. *2: Interrupt number Interrupt request signal #30*2 <#18> 45 MB90820 Series 6. 16-bit PPG Timer ( x 3) The 16-bit PPG timer consists of a 16-bit down counter, prescaler, 16-bit period setting register, 16-bit duty setting register, 16-bit control register and a PPG output pin. This module can be used to output pulses synchronized by software trigger or GATE signal from Multi-functional timer, refer to "7. Multi-functional Timer". Features of 16-bit PPG timer : * Two operating mode : PWM and One-shot mode * 8 types of counter operation clock (, /2, /4, /8, /16, /32, /64, /128) can be selected * Interrupt is generated when trigger signal arrived, or counter borrow, or change of PPG output * Supports for EI2OS (1) Register configuration PPG Control Status Register (Upper) Address: ch0 00003FH ch1 000047H ch2 00004FH Read/write Initial value 15 14 13 12 11 10 9 8 Bit PCNTH0 to PCNTH2 CNTE STGR MDSE RTRG CKS2 R/W 0 7 R/W 0 6 IREN R/W 0 R/W 0 5 IRQF R/W 0 R/W 0 4 IRS1 R/W 0 R/W 0 3 CKS1 CKS0 PGMS R/W 0 2 R/W 0 1 R/W 0 0 PPG Control Status Register (Lower) Bit PCNTL0 to PCNTL2 Address: ch0 00003EH ch1 000046H ch2 00004EH Read/write Initial value IRS0 R/W 0 POEN OSEL R/W 0 R/W 0 X X PPG Duty Setting Register (Upper) 15 14 13 12 11 10 9 8 Address: ch0 00003DH ch1 000045H DU15 DU14 DU13 DU12 DU11 DU10 DU09 DU08 ch2 00004DH Read/write Initial value W X W X 7 DU06 W X 6 DU05 W X 5 DU04 W X 4 W X 3 W X 2 DU01 W X 1 DU00 0 Bit PDUT0 to PDUT2 PPG Duty Setting Register (Lower) Address: ch0 00003CH ch1 000044H ch2 00004CH Read/write Initial value Bit PDUT0 to PDUT2 DU07 DU03 DU02 W W W W W W W W X X X X X X X X PPG Period Setting Register (Upper) 15 14 13 12 11 10 9 8 Address: ch0 00003BH ch1 000043H CS15 CS14 CS13 CS12 CS11 CS10 CS09 CS08 ch2 00004BH Read/write Initial value W X W X W X W X W X W X W X W X Bit PCSR0 to PCSR2 (Continued) 46 MB90820 Series (Continued) PPG Period Setting Register (Lower) Address: ch0 00003AH ch1 000042H ch2 00004AH Read/write Initial value 7 6 5 4 3 CS02 W X 2 CS01 W X 1 CS00 W X 0 Bit PCSR0 to PCSR2 CS07 W X CS06 CS05 W X W X CS04 CS03 W X W X PPG Down Counter Register (Upper) 15 14 13 12 11 10 Address: ch0 000039H ch1 000041H DC15 DC14 DC13 DC12 DC11 DC10 DC09 ch2 000049H Read/write Initial value R 1 R 1 7 Address: ch0 000038H ch1 000040H ch2 000048H Read/write Initial value R 1 6 R 1 5 DC04 R 1 R 1 4 DC03 R 1 R 1 3 DC02 R 1 R 1 2 9 DC08 R 1 1 8 Bit PDCR0 to PDCR2 PPG Down Counter Register (Lower) 0 Bit PDCR0 to PDCR2 DC07 DC06 DC05 R 1 R 1 R 1 DC01 R 1 DC00 R 1 Note : Registers PDCR0 to PDCR2, PDSR0 to PDSR2 and PDUT0 to PDUT2 are word access only. 47 MB90820 Series (2) Block diagram P eriod S etting B uffer R egister 0/1/2 D uty S etting B uffer R egister 0/1/2 Prescaler CKS2 CKS1 CKS0 Period Setting Register 0/1/2 Duty Setting Register 0/1/2 1/1 1/2 1/4 1/8 1/16 1/32 1/64 1/128 CLK LOAD 16-bit down counter MDSE PGMS OSEL POEN Comparator STOP START BORROW P37/PPG0 or P40/PPG1 or P50/PPG2 P in Machine clock F2MC-16LX bus S Down Counter Register 0/1/2 Q PPG0 (multi-functional timer) or PPG1 (multi-pulse generator) or PPG2 R Interrupt selection GATE - from multi-functional timer (for PPG ch. 0 only) Interrupt #14, #16, #32 Edge detection IRS1 IRS0 IRQF IREN (for PPG ch. 1 & 2) STGR CNTE RTRG 48 MB90820 Series 7. Multi-functional Timer The 16-bit multi-functional timer module consists of one 16-bit free-running timer, four input capture circuits, six output comparators and one channel of 16-bit PPG timer. This module allows six independent waveforms generated by PPG timer or waveform generator to be outputted. With the 16-bit free-running timer and the input capture circuit, input pulse width and external clock period measurement can be done. (1) 16-bit free-running timer (1 channel) * The 16-bit free-running timer consists of a 16-bit up/up-down counter, timer control status register, 16-bit compare clear register (with buffer register) and a prescaler. * 8 types of counter operation clock (, /2, /4, /8, /16, /32, /64, /128) can be selected. ( is the machine clock.) * Two types of interrupt causes : - Compare clear interrupt is generated when there is a comparing match with compare clear register and 16bit free-running timer. - Zero detection interrupt is generated while 16-bit free-running timer is detected as zero in count value. * EI2OS supported. * Compare-clear register buffer provided : The selectable buffer enables the 16-bit free-running timer update its compare-clear register automatically without stop the timer operation. User can read the next compare-clear value to the compare-clear register when the timer is running. The compare-clear register will be updated when the timer value is "0000H" * Reset, software clear, compare match with compare clear register in up-count mode will reset the counter value to "0000H". * Supply clock to output compare module : The prescaler output is acted as the count clock of the output compare. (2) Output compare module ( 6 channels) * The output compare module consists of six 16-bit output compare registers (with selectable buffer register), compare output latch and compare control registers. An interrupt is generated and output level is inverted when the value of 16-bit free-running timer and output compare register are matched. * 6 output compare registers can be operated independently. * Output pins and interrupt flag are corresponding to each output compare register. * 2 output compare registers can be paired to control the output pins. * Inverts output pins by using 2 output compare registers together. * Setting the initial value for each output pin is possible. * Interrupt is generated when there is a comparing match with output compare register and 16-bit free-running timer. * EI2OS supported. (3) Input capture module (4 channels) Input capture consists of 4 independent external input pins, the corresponding input capture data register and input capture control status register. By detecting any edge of the input signal from the external pin, the value of the 16-bit free-running timer can be stored in the capture register and an interrupt is generated simultaneously. * Operations synchronized with the 16-bit free-running timer's count clock. * 3 types of trigger edge (rising edge, falling edge and both edge) of the external input signal can be selected and there is indication bit to show the trigger edge is rising or falling. * 4 input captures can be operated independently. * Two independent interrupts are generated when detecting a valid edge from external input. * EI2OS supported. 49 MB90820 Series (4) 16-bit PPG timer (1 channel) The 16-bit PPG timer 0 is used to provide a PPG signal for waveform generator. (See section "6. 16-bit PPG Timer".) (5) Waveform generator module The waveform generator consists of three 16-bit timer registers, three 16-bit timer control registers and a waveform control register. With waveform generator, it is possible to generate real time output, 16-bit PPG waveform output, non-overlap 3-phase waveform output for inverter control and DC chopper waveform output. * It is possible to generate a non-overlap waveform output based on dead-time of 16-bit timer. (Dead-time timer function) * It is possible to generate a non-overlap waveform output when realtime output is operated in 2-channel mode. (Dead-time timer function) * By detecting realtime output compare match, GATE signal of the PPG timer operation will be generated to start or stop PPG timer operation. (GATE function) * When a match is detected by real time output compare, the 16-bit timer is activated. The PPG timer can be started or stopped easily by generating a GATE signal for PPG operation until the 16-bit timer stops. (GATE function) * Force to stop output waveform using DTTI pin input. * Interrupt is generated when DTTI active or 16-bit timer underflow. * EI2OS is supported. (6) Register configuration * 16-bit free-running timer registers Timer Control Status Register (Upper) 15 14 Address: 00005FH Read/write Initial value 13 12 MSI2 R/W 0 4 11 MSI1 R/W 0 3 SCLR R/W 0 11 T11 R/W 0 3 T03 R/W 0 10 MSI0 R/W 0 2 CLK2 R/W 0 10 T10 R/W 0 2 T02 R/W 0 9 ICLR R/W 0 1 CLK1 R/W 0 9 T09 R/W 0 1 T01 R/W 0 8 ICRE R/W 0 0 CLK0 R/W 0 8 T08 R/W 0 0 T00 R/W 0 Bit TCDT Bit TCDT Bit TCCSL Bit TCCSH ECKE IRQZF IRQZE R/W 0 R/W 0 R/W 0 5 Timer Control Status Register (Lower) 7 6 Address: 00005EH Read/write Initial value Timer Data Register (Upper) Address: 00005DH Read/write Initial value Timer Data Register (Lower) Address: 00005CH Read/write Initial value X 15 T15 R/W 0 7 T07 R/W 0 BFE R/W 0 14 T14 R/W 0 6 T06 R/W 0 STOP MODE R/W 1 13 T13 R/W 0 5 T05 R/W 0 R/W 0 12 T12 R/W 0 4 T04 R/W 0 (Continued) 50 MB90820 Series (Continued) Compare Clear Buffer Register / Compare Clear Register (Upper) 15 14 13 12 11 Address: 00005BH Read/write Initial value CL15 R/W 1 CL14 R/W 1 CL13 R/W 1 CL12 R/W 1 CL11 R/W 1 10 CL10 R/W 1 9 CL09 R/W 1 8 CL08 R/W 1 Bit CPCLRB/CPCLR Compare Clear Buffer Register / Compare Clear Register (Lower) 7 6 5 4 3 Address: 00005AH Read/write Initial value CL07 R/W 1 CL06 R/W 1 CL05 R/W 1 CL04 R/W 1 CL03 R/W 1 2 CL02 R/W 1 1 CL01 R/W 1 0 CL00 R/W 1 Bit CPCLRB/CPCLR Note : Registers TCDT, CPCLRB/CPCLR are word access only. * Output compare registers Compare Control Register (Upper) 15 Address: ch1 00007DH ch3 00007FH ch5 000081H Read/write Initial value BTS1 R/W 1 14 13 12 11 10 9 OTD0 R/W 0 8 Bit OCS1/3/5 BTS0 CMOD OTE1 R/W 1 R/W 0 R/W 0 OTE0 OTD1 R/W 0 R/W 0 X Compare Control Register (Lower) 7 Address: ch0 00007CH ch2 00007EH ch4 000080H Read/write Initial value IOP1 R/W 0 IOP0 R/W 0 6 IOE1 R/W 0 5 IOE0 R/W 0 4 BUF1 R/W 1 3 BUF0 R/W 1 2 1 0 Bit OCS0/2/4 CST1 CST0 R/W 0 R/W 0 Output Compare Buffer Register / Output Compare Register (Upper) Address: ch0 000071H ch1 000073H ch2 000075H 15 14 13 12 11 10 9 8 ch3 000077H ch4 000079H ch5 00007BH OP15 OP14 OP13 OP12 OP11 OP10 OP09 OP08 Read/write Initial value R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X Bit OCCPB0 to OCCPB5/ OCCP0 to OCCP5 Output Compare Buffer Register / Output Compare Register (Lower) Address: ch0 000070H ch1 000072H ch2 000074H ch3 000076H ch4 000078H ch5 00007AH Read/write Initial value 7 OP07 R/W X OP06 R/W X 6 OP05 R/W X 5 OP04 R/W X 4 OP03 R/W X 3 2 1 OP00 R/W X 0 Bit OCCPB0 to OCCPB5/ OP02 OP01 R/W X R/W X OCCP0 to OCCP5 Note : Register OCCPB0 to OCCPB5/OCCP0 to OCCP5 are word access only. 51 MB90820 Series * Input capture registers Input Capture Control Status Register (2/3) (Upper) 15 Address: 00006BH Read/write Initial value X X X X X X 14 13 12 11 10 9 IEI3 R 0 8 IEI2 R 0 Bit ICSH23 Input Capture Control Status Register (2/3) (Lower) 7 Address: 00006AH Read/write Initial value ICP3 R/W 0 6 ICP2 R/W 0 5 ICE3 R/W 0 4 ICE2 R/W 0 3 EG31 R/W 0 2 EG30 R/W 0 1 EG21 R/W 0 0 EG20 R/W 0 Bit ICSL23 PPG output control/ Input Capture Control Status Register (0/1) (Upper) 15 14 13 12 11 10 Address: 000069H Read/write Initial value PGEN5 PGEN4 PGEN3 PGEN2 PGEN1 PGEN0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 9 IEI1 R 0 8 IEI0 R 0 Bit PICSH01 Input Capture Control Status Register (0/1) (Lower) 7 Address: 000068H Read/write Initial value ICP1 R/W 0 6 ICP0 R/W 0 5 ICE1 R/W 0 4 ICE0 R/W 0 3 EG11 R/W 0 2 EG10 R/W 0 1 EG01 R/W 0 0 EG00 R/W 0 Bit PICSL01 Input Capture Data Register (Upper) Address: ch0 000061H ch1 000063H ch2 000065H ch3 000067H Read/write Initial value 15 CP15 R X CP14 R X 14 CP13 R X 13 CP12 R X 12 CP11 R X 11 CP10 R X 10 CP09 R X 9 CP08 R X 8 Bit IPCP0 to IPCP3 Input Capture Data Register (Lower) Address: ch0 000060H ch1 000062H ch2 000064H ch3 000066H Read/write Initial value 7 CP07 R X CP06 R X 6 CP05 R X 5 CP04 R X 4 CP03 R X 3 CP02 R X 2 CP01 R X 1 CP00 R X 0 Bit IPCP0 to IPCP3 Note : Registers IPCP0 to IPCP3 are word access only. 52 MB90820 Series * Waveform generator registers Waveform Control Register 15 Address: 000059H Read/write Initial value DTIE R/W 0 14 DTIF R/W 0 7 13 NRSL R/W 0 6 12 DCK2 R/W 0 5 11 DCK1 R/W 0 4 3 10 DCK0 R/W 0 2 9 8 Bit SIGCR NWS1 NWS0 R/W 0 1 R/W 0 0 16-bit Timer Control Register Bit DTCR0, DTCR2 DMOD GTEN1 GTEN0 TMIF R/W 0 R/W 0 R/W 0 R/W 0 TMIE TMD2 TMD1 TMD0 R/W 0 R/W 0 R/W 0 R/W 0 Address: ch0 000056H ch2 000058H Read/write Initial value 16-bit Timer Control Register 15 Address: ch1 000057H Read/write Initial value 14 13 12 11 TMIE R/W 0 10 9 8 Bit DTCR1 DMOD GTEN1 GTEN0 TMIF R/W 0 R/W 0 R/W 0 R/W 0 TMD2 TMD1 TMD0 R/W 0 R/W 0 R/W 0 16-bit Timer Register (Upper) 15 Address: ch0 000051H ch1 000053H ch2 000055H Read/write Initial value 16-bit Timer Register (Lower) Address: ch0 000050H ch1 000052H ch2 000054H Read/write Initial value TR15 R/W X TR14 R/W X 7 TR07 R/W X TR06 R/W X 14 TR13 R/W X 6 TR05 R/W X 13 TR12 R/W X 5 TR04 R/W X 12 TR11 R/W X 4 TR03 R/W X 11 TR10 R/W X 3 TR02 R/W X 10 TR09 R/W X 2 TR01 R/W X 9 TR08 R/W X 1 TR00 R/W X 0 8 Bit TMRR0 to TMRR2 Bit TMRR0 to TMRR2 Note : Registers TMRR0 to TMRR2 are word access only. 53 MB90820 Series (7) Block diagram * Block diagram of Multi-functional timer Real time I/O RTO0 Interrupt #12 Interrupt #15 Interrupt #17 Interrupt #19 Interrupt #21 Interrupt #23 Output compare 0 Output compare 1 Output compare 2 Output compare 3 Output compare 4 Output compare 5 Pin P82/RTO0 (U) RTO1 Pin P83/RTO1 (X) RTO2 Pin P84/RTO2 (V) 16-bit output compare RTO3 RT0 to RT5 RT0 to 5 Pin P85/RTO3 (Y) Waveform generator Buffer transfer Counter value RTO4 Pin P86/RTO4 (W) RTO5 Pin P87/RTO5 (Z) DTTI Pin P10/INT0/DTTI F2MC-16LX bus Interrupt #31 Interrupt #34 Zero detect Compare clear Interrupt #29 16-bit timer 0/1/2 underflow DTTI falling edge detect PPG0 GATE 16-bit free-running timer Interrupt #20 A/D trigger A/D trigger PPG0 GATE EXCK Pin P75/FRCK/AN13 Counter value Interrupt #33 Interrupt #35 Input capture 0/1 Input capture 2/3 P76/IN0/AN14 16-bit input capture IN0 Pin IN1 Pin P77/IN1/AN15 IN2 Pin P80/IN2 IN3 Pin P81/IN3 54 MB90820 Series * Block diagram of 16-bit free-running timer STOP MODE SCLR CLK2 CLK1 CLK0 Prescaler STOP UP/UP-DOWN CLR 16-bit free-running timer Zero detect circuit CK Zero detect (to output compare) To input compare & output compare Transfer 16-bit compare clear register F2MC-16LX bus Compare circuit Compare clear match to output compare 16-bit compare clear buffer register I0 I1 I0 I1 O Selector Interrupt #31 (1FH) Selector O I0 I1 O Mask circuit Selector Interrupt #34 (22H) A/D trigger MSI2 MSI1 MSI0 ICLR ICRE IRQZF IRQZE I0 I1 O Selector 55 MB90820 Series * Block diagram of 16-bit output compare Count value from free-running timer BUF0 BTS0 I0 O I1 Output compare buffer register 0/2/4 Transfer Output compare register 0/2/4 F2MC-16LX bus Selector Zero detect from free-running timer Compare clear match from free-running timer BUF1 Compare circuit BTS1 I0 O Output compare buffer register 1/3/5 Transfer I1 Selector Output compare register 1/3/5 CMOD T Q RT0/2/4 (Waveform generator) RT1/3/5 (Waveform generator) Interrupt #12, #17, #21 #15, #19, #23 Compare circuit T IOP1 IOP0 IOE1 IOE0 Q * Block diagram of 16-bit input capture Count value from free-running timer Input capture data register 0/2 Edge detect IN0/2 F2MC-16LX bus EG11 EG10 EG01 EG00 IEI1 IEI0 Input capture data register 1/3 Edge detect IN1/3 ICP0 ICP1 ICE0 ICE1 Interrupt #33, #35 #33, #35 56 MB90820 Series * Block diagram of waveform generator DCK2 DCK1 DCK0 NRSL DTIF DTIE NWS1 NWS0 DTTI control circuit PICSH01 PGEN1 PGEN0 DTCR0 TMD2 TMD1 TMD0 GTEN1 GTEN0 GATE 0/1 SIGCR DTTI Divider Noise cancellation TO0 RT0 RT1 GATE (to PPG0) Waveform control Output control Output control Output control TO1 Selector 16-bit timer 0 Compare circuit RTO0 (U) Selector U RTO1 (X) 16-bit timer register 0 DTCR1 TMD2 TMD1 TMD0 GTEN1 GTEN0 Dead time generator X GATE 2/3 F2MC-16LX bus PICSH01 PGEN3 PGEN2 RT2 RT3 TO2 Waveform control TO3 Selector 16-bit timer 1 Compare circuit RTO2 (V) Selector V RTO3 (Y) 16-bit timer register 1 DTCR2 TMD2 TMD1 TMD0 GTEN1 GTEN0 PICSH01 PGEN5 PGEN4 RT4 RT5 Dead time generator Y GATE 4/5 TO4 Waveform control TO5 Selector 16-bit timer 2 Compare circuit RTO4 (W) Selector W RTO5 (Z) 16-bit timer register 2 Dead time generator Z PPG0 57 MB90820 Series 8. PWC Timer (x 2) The PWC (pulse width count) timer is a 16-bit multi-functional up counter with reload timer functions and input signal pulse width count functions. The PWC timer consists of a 16-bit counter, an input pulse divider, a division ratio control register, a count input pin, a pulse output pin, and a 16-bit control register. The PWC timer has the following features: * Interruption is generated when timer overflow or end of PWC measurement. * EI2OS is supported. * Timer functions : - Generates an interrupt request at set time intervals. - Outputs pulse signals synchronized with the timer cycle. - Selects the counter clock from three internal clocks. * Pulse-width count functions: - Counts the time between external pulse input events. - Selects the counter clock from three internal clocks. - Count mode: * H pulse width (rising edge to falling edge) / L pulse width (falling edge to rising edge) * Rising-edge cycle (rising edge to falling edge) / Falling-edge cycle (falling edge to rising edge) * Count between edges (rising or falling edge to falling or rising edge) Capable of counting cycles by dividing input pulses by 22, 24, 26, 28 using an 8-bit input divider. Generates an interrupt request upon the completion of count operation. Selects single or consecutive count operation. (1) Register configuration Division Ratio Control Register Address: ch0 0000C4H ch1 00002CH Read/write Initial value Bit DIV0, DIV1 DIV1 R/W 0 DIV0 R/W 0 Bit PWC0, PWC1 PW15 PW14 PW13 PW12 PW11 PW10 Read/write Initial value R/W X R/W X 7 R/W X 6 R/W X 5 R/W X 4 R/W X 3 PW09 PW08 R/W X 2 R/W X 1 0 Bit PWC0, PWC1 7 6 5 4 3 2 1 0 X X X X X X PWC Data Buffer Register (Upper) 15 Address: ch0 0000C3H ch1 00002BH 14 13 12 11 10 9 8 PWC Data Buffer Register (Lower) Address: ch0 0000C2H ch1 00002AH Read/write Initial value PW07 PW06 PW05 PW04 PW03 PW02 PW01 PW00 R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X Note : Registers PWC0 to PWC1 are word access only. (Continued) 58 MB90820 Series (Continued) PWC Control Status Register (Upper) 15 Address: ch0 0000C1H ch1 000029H STRT Read/write Initial value R/W 0 STOP R/W 0 7 CKS0 R/W 0 6 EDIR R 0 EDIE R/W 0 5 OVIR R/W 0 4 S/C R/W 0 OVIE R/W 0 3 2 ERR R 0 POUT R/W 0 1 0 Bit PWCSL0, PWCSL1 14 13 12 11 10 9 8 Bit PWCSH0, PWCSH1 PWC Control Status Register (Lower) Address: ch0 0000C0H ch1 000028H Read/write Initial value CKS1 R/W 0 Reserved Reserved MOD2 MOD1 MOD0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Note : Registers PWC0 to PWC1 are word access only. (2) Block diagram PWC read 16 PWC 16 16 Write enabled Reload Data transfer 16 Overflow Clock 16-bit up counter Timer clear F2MC-16LX bus Count enabled Control circuit Flag setting Start edge selection Count end edge End edge selection Divider ON/OFF Error detection ERR Overflow F.F. P07/PWO0 P47/PWO1 22 23 CKS1, CKS0, Divider clear Clock Clock divider Count bit output Internal clock (machine clock / 4) P06/PWI0 P46/PWI1 8-bit divider Edge detection Count start edge Count end interrupt request Overflow interrupt request CKS1 ERR CKS0 Division ratio selection 2 DIVR 15 PWCS 59 MB90820 Series 9. UART (x 2) The UART is a serial I/O port for asynchronous (start-stop) communication or clock-synchronous communication. The UART has the following features : * Full-duplex double buffering * Capable of asynchronous (start-stop bit) and CLK-synchronous communications * Support for the multiprocessor mode * Various method of baud rate generation : - External clock input possible - Internal clock (a clock supplied from 16-bit reload timer can be used.) - Embedded dedicated baud rate generator Operation Baud rate Asynchronous 31250/9615/4808/2404/1202 bps CLK synchronous 2 M/1 M/500 K/250 K/125 K/62.5K bps Note : Assuming internal machine clock frequencies of 6 MHz, 8 MHz, 10 MHz, 12 MHz, and 16 MHz. * Error detection functions (parity, framing, overrun) * NRZ (Non Return to Zero) signal format * Interrupt request : - Receive interrupt (receive complete, receive error detection) - Transmit interrupt (transmission complete) - Transmit / receive conforms to extended intelligent I/O service (EI2OS). 60 MB90820 Series (1) Register configuration Serial Status Register 15 Address: ch0 000023H ch1 000027H PE Read/write Initial value R 0 ORE R 0 FRE R 0 RDRF TDRE R 0 R 1 BDS R/W 0 RIE R/W 0 TIE R/W 0 14 13 12 11 10 9 8 Bit SSR0, SSR1 Serial Input Data Register / Serial Output Data Register 7 6 5 Address: ch0 000022H ch1 000026H D7 D6 D5 D4 Read/write Initial value Serial Control Register 15 Address: ch0 000021H ch1 000025H PEN Read/write Initial value Serial Mode Register Address: ch0 000020H ch1 000024H Read/write Initial value R/W 0 P R/W 0 7 MOD1 MOD0 R/W 0 R/W 0 SBL R/W 0 6 CS2 R/W 0 CL R/W 0 5 CS1 R/W 0 14 13 R/W X R/W X R/W X R/W X 4 D3 R/W X 3 D2 R/W X 2 D1 R/W X 1 D0 R/W X 0 Bit SIDR0, SIDR1/ SODR0, SODR1 12 A/D R/W 0 4 CS0 R/W 0 11 REC W 1 3 RST R/W 0 10 RXE R/W 0 2 SCKE R/W 0 9 TXE R/W 0 1 SOE R/W 0 8 Bit SCR0, SCR1 0 Bit SMR0, SMR1 Clock Division Control Register 15 Address: ch0 000035H ch1 000037H Read/write Initial value MD R/W 0 ILS R/W 0 X X X 14 13 12 11 DIV2 R/W 0 10 DIV1 R/W 0 9 DIV0 R/W 0 8 Bit CDCR0, CDCR1 61 MB90820 Series (2) Block diagram Reception interrupt #39 (27H)* <#37 (25H)*> Transmission interrupt #40 (28H)* <#38 (26H)*> From communication prescaler Baud rate generator Transmission clock 16-bit reload timer P43/SCK0 External clock Transmission control circuit Transmission start circuit Transmission bit counter Transmission parity counter P44/SOT0 Reception state judgment circuit Shift register for reception SIDR0/1 Reception error generating circuit for EI2OS F2MC-16LX bus SODR0/1 SMR0/1 register MD1 MD0 CS2 CS1 CS0 RST SCKE SOE SCR0/1 register PEN P SBL CL A/D REC RXE TXE SSR0/1 register PE ORE FRE RDRF TDRE BDS RIE TIE Control signal *: Interrupt number 62 Start of transmission Control bus MB90820 Series 10. DTP/External Interrupts The DTP/external interrupt circuit is activated by the signal supplied to a DTP/external interrupt pin. The CPU accepts the signal using the same procedure it uses for normal hardware interrupts and generates external interrupts or activates the extended intelligent I/O service (EI2OS). Features of DTP/External Interrupt : * Total 8 external interrupt channels. * Two request levels ("H" and "L") are provided for the intelligent I/O service. * Four request levels (rising edge, falling edge, "H" level and "L" level) are provided for external interrupt requests. (1) Register configuration DTP/Interrupt Source Register 15 Address: 0000031H Read/write Initial value ER7 R/W 0 14 ER6 R/W 0 13 ER5 R/W 0 12 ER4 R/W 0 11 ER3 R/W 0 10 ER2 R/W 0 9 ER1 R/W 0 8 ER0 R/W 0 Bit EIRR DTP/Interrupt Enable Register 7 Address: 000030H Read/write Initial value EN7 R/W 0 6 EN6 R/W 0 5 EN5 R/W 0 4 EN4 R/W 0 3 EN3 R/W 0 2 EN2 R/W 0 1 EN1 R/W 0 0 EN0 R/W 0 Bit ENIR Request Level Setting Register (Upper) 15 Address: 0000033H Read/write Initial value LB7 R/W 0 14 LA7 R/W 0 13 LB6 R/W 0 12 LA6 R/W 0 11 LB5 R/W 0 10 LA5 R/W 0 9 LB4 R/W 0 8 LA4 R/W 0 Bit ELVRH Request Level Setting Register (Lower) 7 6 Address: 000032H Read/write Initial value LB3 R/W 0 LA3 R/W 0 5 LB2 R/W 0 4 LA2 R/W 0 3 LB1 R/W 0 2 LA1 R/W 0 1 LB0 R/W 0 0 LA0 R/W 0 Bit ELVRL 63 MB90820 Series (2) Block diagram Request level setting register (ELVR) LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 2 2 2 2 2 2 2 2 Pin P51/INT7 Selector Selector Pin P10/INT0/DTTI Pin P16/INT6 Selector Selector Pin P11/INT1 Internal data bus Pin P15/INT5 Selector Selector Pin P12/INT2 Pin P14/INT4 Selector Selector Pin P13/INT3 ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 Interrupt request number #20(14H) #22(16H) #25(19H) #26(1AH) #27(1BH) #28(1CH) EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 64 MB90820 Series 11. Delayed Interrupt Generation Module The delayed interrupt generation module is used to generate a task switching interrupt. Interrupt requests to the F2MC-16LX CPU can be generated and cleared by software using this module. (1) Register configuration Delay interrupt cause/clear register 15 Address: 00009FH Read/write Initial value X X X X X X X 14 13 12 11 10 9 8 R0 R/W 0 Bit DIRR (2) Block diagram F2MC-16LX bus Delayed interrupt cause generating/cancellation decoder Interrupt cause latch 65 MB90820 Series 12. A/D Converter The A/D converter converts the analog voltage input (input voltage) to an analog input pin to a digital value. It has the following features : * The minimum conversion time is 3 s (for a machine clock of 24 MHz; including sampling time). * The converter uses the RC-type successive approximation conversion method with a sample and hold circuit. * A resolution of 10 bits or 8 bits can be set. * Up to 16 channels for analog input pins can be selected by a program. * Various conversion mode : - Single conversion mode : Selectively convert one channel. - Scan conversion mode : Continuously convert multiple channels. Maximum of 16 selectable channels. - Continuous conversion mode : Repeatedly convert specified channels. - Stop conversion mode : Convert one channel then halt until the next activation (enables synchronization of the conversion start timing). * At the end of A/D conversion, an interrupt request can be generated and EIOS can be activated. * In the interrupt-enabled state, the conversion data protection function prevents any part of the data from being lost through continuous conversion. * The conversion can be activated by software, 16-bit reload timer 1 (rising edge) and 16-bit free-running timer zero detection edge. (1) Register configuration A/D Control Status Register (upper) 15 Address: 00000C7H Read/write Initial value BUSY R/W 0 14 INT R/W 0 13 INTE R/W 0 12 PAUS R/W 0 11 STS1 R/W 0 10 STS0 R/W 0 9 STRT W 0 X 8 Bit ADCS1 A/D Control Status Register (lower) 7 Address: 0000C6H Read/write Initial value A/D Data Register (upper) 15 Address: 00000C9H Read/write Initial value A/D Data Register (lower) 7 Address: 0000C8H Read/write Initial value D7 R X X MD1 R/W 0 6 MD0 R/W 0 5 S10 R/W 0 4 3 2 1 0 Reserved Bit ADCS0 X X X X 0 14 13 12 11 10 9 D9 8 D8 R X Bit ADCR1 X X X X X R X 6 D6 R X 5 D5 R X 4 D4 R X 3 D3 R X 2 D2 R X 1 D1 R X 0 D0 R X Bit ADCR0 (Continued) 66 MB90820 Series (Continued) A/D Setting Register (upper) 15 Address: 00000CBH Read/write Initial value ST2 R/W 0 14 ST1 R/W 0 13 ST0 R/W 0 12 CT2 R/W 0 11 CT1 R/W 0 10 CT0 R/W 0 9 Reserved 8 ANS3 R/W 0 Bit ADSR1 R/W 0 A/D Setting Register (lower) 7 Address: 0000CAH Read/write Initial value A/D Input Enable Register 15 Address: 00000C5H Read/write Initial value ADE7 R/W 1 14 ADE6 R/W 1 13 ADE5 R/W 1 12 ADE4 R/W 1 11 ADE3 R/W 1 10 ADE2 R/W 1 9 ADE1 R/W 1 8 ADE0 R/W 1 Bit ADER0 ANS2 R/W 0 6 ANS1 R/W 0 5 ANS0 R/W 0 4 Reserved 3 ANE3 R/W 0 2 ANE2 R/W 0 1 ANE1 R/W 0 0 ANE0 R/W 0 Bit ADSR0 R/W 0 A/D Input Enable Register 7 Address: 0000D0H Read/write Initial value 6 5 4 3 2 1 ADE9 R/W 1 0 ADE8 R/W 1 ADE15 ADE14 ADE13 ADE12 ADE11 ADE10 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit ADER1 67 MB90820 Series (2) Block diagram AVCC AVR AVSS D/A converter MPX AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Input circuit Port 6 Sequential compare register Comparator Sample and hold circuit F2MC-16LX bus Data register ADCR0/1 A/D setting register 0 A/D setting register 1 ADSR0/1 Operation clock AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 Input circuit Decorder Port 7 Prescaler A/D input enable register 0 A/D input enable register 1 ADER0/1 A/D control status register 0 A/D control status register 1 ADCS0/1 16-bit reload timer 1 16-bit free-running timer zero detection : Machine clock 68 MB90820 Series 13. D/A Converter The D/A converter is used to generate an analog output from an 8-bit digital input. By setting the enable bit in the D/A control register (DACR) to 1, it will enable the corresponding D/A output channel. Hence, setting this bit to 0 will disable that channel. If D/A output is disabled, the analog switch inserted to the output of each D/A converter channel in series is turned off. In the D/A converter, the bit is cleared to 0 and the direct-current path is shut off. The above is also true in the stop mode. The output voltage of the D/A converter ranges from 0 V to 255/256 x AVCC. To change the output voltage range, adjust the AVCC voltage externally. The D/A converter output does not have the internal buffer amplifier. The analog switch (= 100 ) is inserted to the output in series. To apply load to the output externally, estimate a sufficient stabilization time. Table below lists the theoretical values of output voltage of the D/A converter. Value written to DA07 to DA00 and DA17 to DA10 00H 01H 02H : FDH FEH FFH Theoretical value of output voltage 0/256 x AVCC (= 0 V) 1/256 x AVCC 2/256 x AVCC : 253/256 x AVCC 254/256 x AVCC 255/256 x AVCC 69 MB90820 Series (1) Register configuration D/A data register 1 Bit Address:0000CDH Read/write Initial value 15 R/W X 14 R/W X 13 R/W X 12 R/W X 11 DA13 R/W X 10 DA12 R/W X 9 R/W X 8 R/W X DA17 DA16 DA15 DA14 DA11 DA10 DAT1 D/A data register 0 Bit Address:0000CCH Read/write Initial value 7 DA07 R/W X 6 5 4 3 DA03 R/W X 2 DA02 R/W X 1 0 DA06 DA05 DA04 R/W X R/W X R/W X DA01 DA00 DAT0 R/W X R/W X D/A control register 1 Bit Address:0000CFH Read/write Initial value 15 X 14 X 13 X 12 X 11 X 10 X 9 X 8 DAE1 DACR1 R/W 0 D/A control register 0 Bit Address:0000CEH Read/write Initial value 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 DAE0 DACR0 R/W 0 70 MB90820 Series (2) Block diagram F 2 MC-16LX bus DA DA DA DA DA DA DA DA 17 16 15 14 13 12 11 10 DA DA DA DA DA DA DA DA 07 06 05 04 03 02 01 00 AVCC DA17 2R R DA16 2R R DA15 DA05 DA06 DA07 AVCC 2R R 2R R DA11 2R R DA10 2R 2R DAE1 DA01 2R R DA00 2R 2R DAE0 Standby control Standby control DA output ch.1 DA output ch.0 71 MB90820 Series 14. ROM Correction Function When the corresponding address matches the value set in the address detection register, the instruction code to be loaded into the CPU is forced to be replaced with the INT9 instruction code (01H). When executing a set instruction, the CPU executes the INT9 instruction. The address detection function is implemented by processing using the INT9 instruction routine. The device contains two address detection registers, each provided with a compare enable bit. When the value set in the address detection register matches an address and the interrupt enable bit is "1", the instruction code to be loaded into the CPU is forced to be replaced with the INT9 instruction code. (1) Register configuration Program Address Detection Control Status Register 7 6 5 4 Address: 00009EH Read/write Initial value X X X X 3 AD1E R/W 0 2 AD1D R/W 0 1 AD0E R/W 0 0 AD0D R/W 0 Bit PADCSR Program Address Detection Register 0 (Upper Byte) 7 Address: 001FF2H Read/write Initial value R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X 6 5 4 3 2 1 0 Bit PADRH0 Program Address Detection Register 0 (Middle Byte) 15 14 13 12 Address: 001FF1H Read/write Initial value R/W X R/W X R/W X R/W X 11 10 9 8 Bit PADRM0 R/W X R/W X R/W X R/W X Program Address Detection Register 0 (Lower Byte) 7 Address: 001FF0H Read/write Initial value R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X 6 5 4 3 2 1 0 Bit PADRL0 Program Address Detection Register 1 (Upper Byte) 15 Address: 001FF5H Read/write Initial value R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X 14 13 12 11 10 9 8 Bit PADRH1 (Continued) 72 MB90820 Series (Continued) Program Address Detection Register 1 (Middle Byte) 7 6 5 4 Address: 001FF4H Read/write Initial value R/W X R/W X R/W X R/W X 3 2 1 0 Bit PADRM1 R/W X R/W X R/W X R/W X Program Address Detection Register 1 (Lower Byte) 15 14 13 12 Address: 001FF3H Read/write Initial value R/W X R/W X R/W X R/W X 11 10 9 8 Bit PADRL1 R/W X R/W X R/W X R/W X (2) Block diagram Address latch Comparator Program address detection register 0/1 F2MC-16LX bus INT9 command F2MC-16LX CPU AD0E/AD1E AD0D/AD1D PACSR 73 MB90820 Series 15. ROM Mirroring Function Selection Module The ROM mirror function selection module sets the data in ROM assigned to FF bank so that the data is read by access to 00 bank. (1) Register configuration ROM Mirror Function Selection Register 15 Address : 00006FH Read/write Initial value 14 13 12 11 10 9 8 M1 R/W Bit ROMM X X X X X X X 1 (2) Block diagram ROM mirroring function selection register F2MC-16LX bus Address area FF bank 00 bank ROM 74 MB90820 Series 16. 512/1024 Kbit Flash Memory The 512K bits flash memory is allocated in the FFH banks on the CPU memory map. The 1024K bits flash memory is allocated in the FEH and FFH banks on the CPU memory map. Like MaskROM, flash memory is read-accessible and program-accessible to the CPU using the flash memory interface circuit. The flash memory can be programmed/erased by the instruction from the CPU via the flash memory interface circuit. The flash memory can therefore be reprogrammed (updated) while still on the circuit board under integrated CPU control, allowing program code and data to be improved efficiently. Note that sector operations such as "enable sector protect" cannot be used. Features of 512/1024K bits flash memory * 64K x 8 bits/32K x 16 bits (32K + 8K x 2 + 16K) sector configuration for 512K bits flash memory * 128K x 8 bits/64K x 16 bits (64K + 32K + 8K x 2 + 16K) sector configuration for 1024K bits flash memory * Automatic program algorithm (same as the Embedded Algorithm* : MBM29F400TA) * Installation of the deletion temporary stop/delete restart function * Write/delete completion detected by the data polling or toggle bit * Write/delete completion detected by the CPU interrupt * Compatibility with the JEDEC standard-type command * Each sector deletion can be executed (sectors can be freely combined) * Flash security function * Number of write/delete operations are guaranteed 10,000 times. * : Embedded Algorithm is a trademark of Advanced Micro Devices, Inc. (1) Register configuration Flash Memory Control Status Register 7 6 Address: 0000AEH Read/write Initial value INTE RDYINT R/W 0 R/W 0 5 WE R/W 0 4 RDY R X 3 2 1 0 Bit number FMCS Reserved Reserved Reserved Reserved 0 0 0 0 75 MB90820 Series (2) Sector configuration of flash memory The flash memory has the sector configuration illustrated below. The addresses in the illustration are the upper and lower addresses of each sector. When 512K bits flash memory is accessed from the CPU, SA0 to SA3 are allocated in the FF bank. Flash memory SA3 (16K bytes) CPU address FFFFFFH FFC000H FFBFFFH FFA000H *Writer address 7FFFFH 7C000H 7BFFFH 7A000H 79FFFH 78000H 77FFFH 70000H SA2 (8K bytes) SA1 (8K bytes) FF9FFFH FF8000H SA0 (32K bytes) FF7FFFH FF0000H When 1024K bits flash memory is accessed from the CPU, SA0 to SA4 are allocated in the FE and FF bank. Flash memory SA4 (16K bytes) CPU address FFFFFFH FFC000H FFBFFFH FFA000H *Writer address 7FFFFH 7C000H 7BFFFH 7A000H 79FFFH 78000H 77FFFH 70000H 6FFFFH 60000H SA3 (8K bytes) SA2 (8K bytes) FF9FFFH FF8000H SA1 (32K bytes) FF7FFFH FF0000H FE7FFFH FE0000H SA0 (64K bytes) * : The writer address is the address to use instead of the CPU address when writing data from a parallel flash memory writer. Use the writer address when programming or erasing using a general-purpose parallel writer. 76 MB90820 Series s ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Symbol VCC Power supply voltage* Input voltage* 1 1 1 Rating Min VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 - 2.0 -40 -55 Max VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 + 2.0 20 15 4 12 100 50 -15 -4 -100 -50 430 +85 +150 Unit V V V V V mA mA mA mA mA mA mA mA mA mA mA mW C C *4 Remarks AVCC AVR VI VO ICLAMP | ICLAMP | IOL IOLAV1 IOLAV2 IOL IOLAV IOH IOHAV IOH IOHAV PD TA Tstg VCC = AVCC *2 AVCC AVR, AVR AVss *3 *3 *5 *5 *4 Except for P00 to P07, P82 to P87 P00 to P07, P82 to P87 Output voltage* Maximum clamp current Total maximum clamp current "L" level maximum output current "L" level average output current "L" level total maximum output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level total maximum output current "H" level total average output current Power consumption Operating temperature Storage temperature *1 : This parameter is based on VSS = AVSS = 0.0 V. *2 : AVCC must never exceed VCC when the power is turned on. *3 : VI and VO must never exceed VCC + 0.3 V. However if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *4 : The maximum output current is a peak value for a corresponding pin. *5 : * * * * Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50, P51, P80 to P87. Use within recommended operating conditions. Use at DC voltage (current). The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. * The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. * Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the Vcc pin, and this may affect other devices. 77 MB90820 Series * Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V), the power supply is provided from the pins, so that incomplete operation may result. * Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. * Care must be taken not to leave the +B input pin open. * Note that analog system input/output pins (LCD drive pins and comparator input pins, etc.) other than the A/D input pins cannot accept +B input. * Sample recommended circuits: Input/output equivalent circuits Protective diode Vcc Limiting resistance +B input (0 V to 16 V) N-ch P-ch R WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 78 MB90820 Series 2. Recommended Operating Conditions Parameter Symbol Value Min 4.5 Power supply voltage VCC AVCC 4.0 3.5 3.0 Smoothing capacitor Operating temperature Max 5.5 5.5 5.5 5.5 Unit V V V V F Normal operation Normal operation when D/A converter is not used Normal operation when A/D converter and D/A converter are not used Maintains state in stop operation Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The bypass capacitor to be connected to the VCC pin must have a capacitance value higher than CS. Remarks (VSS = AVSS = 0.0 V) CS 0.1 1.0 TA -40 +85 C * C pin connection circuit C CS WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 79 MB90820 Series 3. DC Characteristics Parameter "H" level output voltage Symbol VOH VOL1 VOL2 VIH Pin name All output pins (VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Condition Unit Remarks Min Typ Max VCC = 4.5 V, IOH = -4.0 mA VCC - 0.5 0.7 VCC 0.4 0.4 VCC + 0.3 V V V V CMOS input pin "L" level output voltage All pins except VCC = 4.5 V, P00 to P07 IOL1 = 4.0 mA P82 to P87 P00 to P07 P82 to P87 P30 to P37 P60 to P67 P00 to P07 P10 to P17 P20 to P27 P40 to P47 *1 P50 to P51 P70 to P77 *1 P80 to P87 RST MD0 to MD2 P30 to P37 P60 to P67 P00 to P07 P10 to P17 P20 to P27 P40 to P47 *1 P50 to P51 P70 to P77 *1 P80 to P87 RST MD0 to MD2 All input pins P00 to P07 P10 to P17 P20 to P27 P30 to P37 RST MD2 VCC = 5.5 V, VSS < VI< VCC VCC = 4.5 V to 5.5 V VCC = 4.5 V, IOL2 = 12.0 mA "H" level input voltage VIHS 0.8 VCC VCC + 0.3 V CMOS hysteresis input pin VIHM VIL VCC - 0.3 VSS - 0.3 VCC + 0.3 0.3 VCC V V MD input pin CMOS input pin "L" level input voltage VILS VSS - 0.3 0.2 VCC V CMOS hysteresis input pin VILM Input leakage current Pull-up resistance IIL VSS - 0.3 -5 VSS + 0.3 5 V A MD input pin RUP 25 50 100 k Pull-down resistance RDOWN 25 50 100 Not available in k MB90F822/ MB90F823 (Continued) 80 MB90820 Series (Continued) (VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Symbol Pin name Condition VCC = 5.0 V, Internal frequency: 24 MHz, At normal operation VCC = 5.0 V, Internal frequency: 24 MHz, At writing in flash memory VCC = 5.0 V, Internal frequency: 24 MHz, At erasing memory Power supply current* VCC ICCS VCC = 5.0 V, Internal frequency: 24 MHz, At sleep mode VCC = 5.0 V, Internal frequency: 2 MHz, At main timer mode VCC = 5.0 V, Internal frequency: 8 MHz, At timer mode, TA = +25 C In stop mode, TA = +25 C Except AVCC, AVSS, AVR, C, VCC and VSS Value Min 3 7 0.3 0.8 15 25 Typ 35 45 50 60 55 65 Max 50 60 65 75 70 80 Unit Remarks Parameter mA MB90822 mA MB90F822/F823 mA MB90822 mA MB90F822/F823 mA MB90822 mA MB90F822/F823 mA MB90822 mA MB90F822/F823 mA MB90822 mA MB90F822/F823 mA MB90822 A MB90F822/F823 ICC ICTS ICCT ICCH Input capacitance 5 20 mA MB90822 A pF MB90F822/F823 CIN 5 15 *1 : UART0, UART1 data input pins P45/SIN0, P72/SIN1 can be selected as CMOS input by user program. *2 : Current values are tentative. They may be subject to change for enhanced characteristics without previous notice. The power supply current is measured with an external clock. 81 MB90820 Series 4. AC Characteristics (1) Clock Timings (VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Symbol Pin name Unit Remarks Min Typ Max FC tHCYL PWH PWL tCR tCF fCP tCP X0, X1 X0, X1 X0 X0 3 3 62.5 41.67 10 1.5 41.67 16 24 333 333 5 24 666 MHz Crystal oscillator MHz External clock ns ns ns ns MHz ns Crystal oscillator External clock Recommend duty ratio of 30% to 70% External clock operation Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rise/fall time Internal operating clock frequency Internal operating clock cycle time tHCYL X0 PWH tCF PWL tCR 0.8 VCC 0.2 VCC 82 MB90820 Series Relationship between internal operating clock frequency and power supply voltage Power supply voltage VCC (V) Guaranteed D/A Converter operating range 5.5 4.5 4.0 3.5 Normal operation guarantee range Operation guarantee range of PLL Guaranteed A/D Converter operating range 1.5 4 Internal clock fCp (MHz) 24 Relationship between oscillating frequency and internal operating clock frequency X6 Internal operating clock fCP (MHz) 24 X4 X3 X2 X1 16 12 8 4 1.5 34 8 12 16 Oscillation clock FC (MHz) 24 Not multiplied The AC ratings are measured for the following measurement reference voltages * Input signal waveform * Output signal waveform Hysteresis input pin 0.8 VCC 0.2 VCC Output pin 2.4 V 0.8 V Pins other than hysteresis input/MD input 0.7 VCC 0.3 VCC 83 MB90820 Series (2) Reset Input Timing (VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Unit Remarks Min Max 500 Reset input time tRSTL RST Oscillation time of oscillator* + 100 100 ns s s Normal operation Stop mode Timebase timer mode Parameter Symbol Pin name * : Oscillation time of oscillator is the time to reach to 90% of the oscillation amplitude from stand still. In the crystal oscillator, the oscillation time is between several ms to tens of ms. In FAR/ceramic oscillator, the oscillation time is between hundreds of s to several ms. In the external clock, the oscillation time is 0 ms. * In normal operation mode tRSTL, tHSTL RST 0.2 VCC 0.2 VCC * In stop mode tRSTL RST 0.2 VCC 0.2 VCC 90% of the oscillation amplitude X0 Internal operation clock Oscillation time of oscillator 100 s Oscillator stabilization time Instruction execution Internal reset 84 MB90820 Series (3) Power-on Reset (VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Symbol Pin name Condition Unit Remarks Min Max tR tOFF VCC VCC 0.05 1 30 ms ms Due to repeated operations Parameter Power supply rising time Power supply cut-off time Notes : * VCC must be kept lower than 0.2 V before power-on. * The above values are used for causing a power-on reset. Some registers in the device are initialized only upon a power-on reset. To initialize these registers, turn the power supply using the above values. tR VCC 2.7 V 0.2 V 0.2 V tOFF 0.2 V Sudden changes in the power supply voltage may cause a power-on reset. To change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1 V/s, however, you can use the PLL clock. VCC 3.0 V VSS RAM data hold It is recommended to keep the rising speed of the supply voltage at 50 mV/ms or slower. 85 MB90820 Series (4) UART0 to UART1 Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK SCK valid SIN hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX (VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Pin name Condition Unit Remarks Min Max SCK0 to SCK1 SCK0 to SCK1 SOT0 to SOT1 SCK0 to SCK1 SIN0 to SIN1 SCK0 to SCK1 SIN0 to SIN1 SCK0 to SCK1 SCK0 to SCK1 SCK0 to SCK1 SOT0 to SOT1 SCK0 to SCK1 SIN0 to SIN1 SCK0 to SCK1 SIN0 to SIN1 CL = 80 pF + 1 TTL for an output pin of external shift clock mode CL = 80 pF + 1 TTL for an output pin of internal shift clock mode 8 tCP -80 100 60 4 tCP 4 tCP 60 60 80 150 ns ns ns ns ns ns ns ns ns Notes : * These are AC ratings in the CLK synchronous mode. * CL is the load capacitance value connected to pins while testing. * tCP is machine cycle time (unit : ns). 86 MB90820 Series * Internal shift clock mode SCK 0.8 V tSLOV 2.4 V tSCYC 2.4 V 0.8 V SOT 0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC SIN 0.2 VCC * External shift clock mode SCK 0.2 VCC tSLOV 2.4 V tSLSH 0.2 VCC tSHSL 0.8 VCC 0.8 VCC SOT 0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC SIN 0.2 VCC 87 MB90820 Series (5) Resources Input Timing Parameter Symbol (VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Pin name Condition Unit Remarks Min Max IN0 to IN3, TIN0 to TIN1, PWI0 to PWI1, DTTI Input pulse width tTIWH tTIWL 4 tCP ns 0.8 VCC 0.8 VCC 0.2 VCC tTIWH tTIWL 0.2 VCC (6) Trigger Input Timing Parameter Input pulse width Symbol tTRGH tTRGL (VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Pin name Condition Unit Remarks Min Max INT0 to INT7 5 tCP ns 0.8 VCC 0.8 VCC 0.2 VCC tTRGH tTRGL 0.2 VCC 88 MB90820 Series 5. A/D Converter Electrical Characteristics Parameter Resolution Total error Non-linearity error Differential linearity error Zero transition voltage Full-scale transition voltage Compare time Sampling time Analog port input current Analog input voltage Reference voltage Power supply current Reference voltage supply current Offset between channels (3.0 V AVR - AVSS, VCC = AVCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Pin Unit Remarks Symbol name Min Typ Max VOT VFST IAIN VAIN IA IAH IR IRH -- AN0 to AN15 AN0 to AN15 AN0 to AN15 AN0 to AN15 AVR AVCC AVR AN0 to AN15 AVSS - 1.5 LSB AVR - 3.5 LSB 1.0 2.0 0.5 1.2 - 0.3 AVSS AVSS + 2.7 10 AVSS + 0.5 LSB AVR - 1.5 LSB 2.4 600 3.0 2.5 1.9 AVSS + 2.5 LSB AVR + 0.5 LSB + 0.3 AVR AVCC 4.7 5 900 5 4 bit LSB LSB LSB mV mV s s s s A V V mA A * A A * LSB 4.5 V < AVcc < 5.5 V 4.0 V < AVcc < 4.5 V 4.5 V < AVcc < 5.5 V 4.0 V < AVcc < 4.5 V * : The current when the A/D converter is not operating or the CPU is in stop mode (for VCC = AVCC = AVR = 5.0 V) Note : The error increases proportionally as |AVR - AVSS| decreases. 89 MB90820 Series 6. A/D Converter Glossary : Analog variation that is recognized by an A/D converter. : Deviation between a line across zero-transition line ("00 0000 0000" "00 0000 0001") and full-scale transition line ("11 1111 1110""11 1111 1111") and actual conversion characteristics. Differential linearity error : Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value Total error : Difference between an actual value and an ideal value. Atotal error includes zero transition error, full-scale transition error, and linear error. Resolution Non linearity error Total error 3FFH 3FEH 3FDH Actual conversion characteristics 0.5 LSB Digital output {1 LSB x (N - 1) + 0.5 LSB} 004H 003H 002H 001H AVRL VNT (Measurement value) Actual conversion characteristics Ideal characteristics 0.5 LSB AVRH Analog input VNT - {1 LSB x (N - 1) + 0.5 LSB} 1 LSB AVR - AVss [V] 1024 Total error for digital output N = 1 LSB = (Ideal value) [LSB] VOT(Ideal value) = AVss + 0.5 LSB [V] VFST(Ideal value) = AVR - 1.5 LSB [V] VNT : Voltage at which of digital output transitions from (N - 1) to N. (Continued) 90 MB90820 Series (Continued) Linearity error 3FFH 3FEH 3FDH Differential linearity error Ideal characteristics N+1 VFST (Measurement value) Actual conversion characteristics {1 LSB x (N - 1) + VOT } Actual conversion characteristics Digital output Digital output N 004H 003H 002H 001H AVss VNT (Measurement value) V(N + 1)T N-1 VNT Actual conversion characteristics Ideal characteristics VOT (Measurement value) AVR (Measurement value) (Measurement value) N-2 Actual conversion characteristics AVR AVss Analog input Linearity error of = digital output N Analog input VNT - {1 LSB x (N - 1) + VOT} 1 LSB - 1 [LSB] [V] [LSB] Differential linearity error V (N + 1) T - VNT = 1 LSB of digital output N 1 LSB = VFST - VOT 1022 VOT : Voltage at which of digital output transmissions from "000H" to "001H". VFST : Voltage at which of digital output transmissions from "3FEH" to "3FFH". 91 MB90820 Series 7. Notes on Using A/D Converter * About the external impedance of the analog input and its sampling time * A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. * Analog input circuit model R Analog input Comparator C During sampling : ON R 2.0 k (Max) 2.0 k (Max) C 14.4 pF (Max) 16.0 pF (Max) MB90822 MB90F822 Note : The values are reference values. * To satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. * The relationship between the external impedance and minimum sampling time (External impedance = 0 k to 100 k) 100 90 20 18 (External impedance = 0 k to 20 k) External impedance [k] External impedance [k] 80 70 60 50 40 30 20 10 0 0 MB90822 MB90F822 16 14 12 10 8 6 4 2 0 0 MB90822 MB90F822 5 10 15 20 25 30 35 1 2 3 4 5 6 7 8 Minimum sampling time [s] Minimum sampling time [s] * If the sampling time cannot be sufficient, connect a capacitor of about 0.1 F to the analog input pin. * About the error The accuracy gets worse as | AVR-AVSS | becomes smaller. 92 MB90820 Series 8. Electrical Characteristics of D/A convertor Parameter Resolution Differential linearity error Conversion time Analog output impedance Power supply current (VCC = AVCC = 4.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Symbol Pin name Condition Unit Remarks Min Typ Max IDVR IDVRS AVCC 8 0.45 2.9 160 0.1 0.5 3.8 920 bit LSB s k A A D/A stops * * : With load capacitance 20 pF. 93 MB90820 Series 9. Flash Memory Program/Erase Characteristics Parameter Sector erase time Chip erase time Word (16 bit width) programing time Program/Erase cycle Flash data retention time Average TA = +85 C TA = +25 C VCC = 5.0 V Condition Value Min 10,000 20 Typ 1 9 16 Max 15 3,600 Unit s s s cycle Year * Remarks Excludes programming prior to erasure Excludes programming prior to erasure Except for the overhead time of the system * : This value comes from the technorogy qualification (using Arrhenius equation to translate high temperature measurements into normalized value at + 85 C) . s ORDERING INFORMATION Part number MB90F823PFV MB90F822PFV MB90822PFV MB90F823PFM MB90F822PFM MB90822PFM MB90F823PF MB90F822PF MB90822PF Package 80-pin Plastic LQFP (FPT-80P-M05) 80-pin Plastic LQFP (FPT-80P-M11) 80-pin Plastic QFP (FPT-80P-M06) Remarks 94 MB90820 Series s PACKAGE DIMENSIONS 80-pin plastic QFP (FPT-80P-M06) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 23.900.40(.941.016) * 20.000.20(.787.008) 64 41 65 40 0.10(.004) 17.900.40 (.705.016) * 14.000.20 (.551.008) INDEX Details of "A" part 80 25 0.25(.010) +0.30 3.05 -0.20 +.012 .120 -.008 (Mounting height) 1 24 0.80(.031) 0~8 M 0.370.05 (.015.002) 0.16(.006) 0.170.06 (.007.002) 0.800.20 (.031.008) 0.880.15 (.035.006) 0.30 -0.25 +0.10 +.004 "A" .012 -.010 (Stand off) C 2002 FUJITSU LIMITED F80010S-c-6-5 Dimensions in mm (inches) Note : The values in parentheses are reference values. (Continued) 95 MB90820 Series 80-pin plastic LQFP (FPT-80P-M11) 16.000.20(.630.008)SQ Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. * 14.000.10(.551.004)SQ 60 41 0.1450.055 (.006.002) 61 40 0.10(.004) Details of "A" part 1.50 -0.10 .059 -.004 (Mounting height) 0.25(.010) INDEX 0~8 21 +0.20 +.008 80 1 20 "A" 0.13(.005) M 0.65(.026) 0.500.20 (.020.008) 0.600.15 (.024.006) 0.100.10 (.004.004) (Stand off) 0.320.05 (.013.002) C 2003 FUJITSU LIMITED F80016S-c-3-6 Dimensions in mm (inches) Note : The values in parentheses are reference values. (Continued) 96 MB90820 Series (Continued) 80-pin plastic LQFP (FPT-80P-M05) 14.000.20(.551.008)SQ * 12.000.10(.472.004)SQ 60 41 Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 0.1450.055 (.006.002) 61 40 0.08(.003) Details of "A" part 1.50 -0.10 .059 -.004 +0.20 +.008 (Mounting height) INDEX 80 21 0~8 0.100.10 (.004.004) (Stand off) "A" LEAD No. 1 20 0.50(.020) 0.500.20 (.020.008) 0.600.15 (.024.006) 0.25(.010) 0.200.05 (.008.002) 0.08(.003) M C 2003 FUJITSU LIMITED F80008S-c-4-8 Dimensions in mm (inches) Note : The values in parentheses are reference values. 97 MB90820 Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0410 (c) 2004 FUJITSU LIMITED Printed in Japan |
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