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TC5299J
TC5299J
FAST ETHERNET PCMCIA LAN CONTROLLER
4FL No. 106 Hsin-Tai Wu Road, Sec. 1, Hsichih, Taipei Hsien, Taiwan R.O.C. TEL: 886-2-2696-1669 FAX: 886-2-2696-2220 http:\\www.tmi.com.tw
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Ver. 0.1 07/04/01
TC5299J
TABLE OF CONTENTS
1 2 3 Introduction .................................................................................................................................3
1.1 General Description.............................................................................................................................................3 1.2 Features ...............................................................................................................................................................3
Block Diagram .............................................................................................................................3 Pin Description.............................................................................................................................4
3.1 Pin Out Diagram .................................................................................................................................................4 3.2 Signal Description ...............................................................................................................................................5 3.3 Power On Configuration .....................................................................................................................................8
4
I/O and Mapping .......................................................................................................................10
4.1 I/O Port Address Mapping ................................................................................................................................10 4.2 EEPROM/SRAM Memory Mapping ................................................................................................................10 4.3 Attribute Memory Mapping ..............................................................................................................................11 4.3.1 Attribute Memory Map ......................................................................................................................11
5
Configuration Registers ............................................................................................................13
Configuration Register A ..................................................................................................................................13 Configuration Register B ..................................................................................................................................13 Configuration Register C ..................................................................................................................................14 Hardware Configuration....................................................................................................................................14 MII/PHY Control Register ................................................................................................................................15 TC5299J Core Registers Assignment................................................................................................................15 Register Descriptions ........................................................................................................................................18 5.7.1 Command Register (CR) 00H (Read/Write) ......................................................................................18 5.7.2 Data Configure register (DCR) 0EH(Write) ....................................................................................19 5.7.3 Transmit configuration Register (TCR) 0DH(Write) ........................................................................19 5.7.4 Transmit Status Register (TSR) 04H(Read).....................................................................................20 5.7.5 Receive Configuration Register (RCR) 0CH(Write)........................................................................21 5.7.6 Receive Status Register (RSR) 0CH(Read)......................................................................................21 5.7.7 Interrupt Mask Register (IMR) 0FH(Write) ....................................................................................22 5.7.8 Interrupt Status Register (ISR) 07H(Read/Write)............................................................................23 5.8 Network Tally Counter Registers (CNTR)........................................................................................................23 5.9 Number of Collisions Register (NCR) ..............................................................................................................24 5.10 Physical Address Register (PAR0-PAR5).........................................................................................................24 5.11 Multicast Address Registers (MAR0-MAR7)...................................................................................................24 5.12 DMA Registers..................................................................................................................................................25 5.13 LOCAL DMA RECEIVE REGISTERS ...........................................................................................................25 5.14 REMOTE DMA REGISTERS..........................................................................................................................25 5.15 (i) Local DMA Transmit Registers ...................................................................................................................25 5.16 (ii) Local DMA Receive Registers ....................................................................................................................26 5.17 (iii) Remote DMA registers...............................................................................................................................26 5.1 5.2 5.3 5.4 5.5 5.6 5.7
6 Electrical Specification and Timing.........................................................................................28 7 Physical Dimension....................................................................................................................31 Notice .................................................................................................................................................32
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TC5299J
Fast Ethernet PCMCIA Controller
1 Introduction
1.1 General Description The TC5299J is a 10/100 PCMCIA Ethernet controller, include a standard MII interface. It provides an 8/16-bit PCMCIA interface to host CPU and buffer memory into single chip to minimize the chip gate count. The TC5299J supports both half-duplex and full-duplex (both 10BT or 100BTX) operation environment. Features !" PCMCIA 2.01 bus interface. !" Use serial EEPROM 93C56/66 to store CIS. !" Internal 5V to 3.3V regulator. Ethernet LAN features: !" Integrated Fast Ethernet MAC and SRAM in one chip. !" Supports both 10Mbps and 100Mbps operation. !" IEEE 802.3/802.3u compatible. !" Full-duplex or half-duplex operation supported for both 10Mbps and 100Mbps operation. !" NE2000 register definitions. !" Supports 3.3V or 5V signaling environment. !" The size of built-in Buffer RAM is 8k x 16 bits. It does not need the extra SRAM in the application circuit. !" Supports loop-back mode for self-testing. !" Supports 256/512 bytes EEPROM interface. !" LED interface supported. !" Supports MII bus interface. !" Flow control ability
1.2
2 Block Diagram
E EP R O M
E EP R O M C ontrol C ircuit
SRAM
P C M C IA Interface
P C M C IA C ommand D ecoder
F IFO s
MAC
PHY TW R
R J45
D M A B u ffer C ontrol Logic
F IFO C ontroller
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3 Pin Description
3.1 Pin Out Diagram
VV CC CC 5AN ARC G N D A R G NGG DNN ADD 1ADN 0PPC V CVV CCC ACC 1AD 0PP V G C N C D 3 3 NNN I N I CCCOCO G N D 3NN DCC G NM DD 3I DO V G LC N EECLLD ED3EE3 CL IDDIX SAOSFO2 G N D 3 I O
N C
X 1
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 NC NC GNDAT VCCAT VCC5A VCC5R NC VCC3IO RSTN GND3IO JMP0 GND3D GND3IO JMP1 NC VCC3D VCC3IO SD15 SD14 SD13 SD12 GND3IO SD11 SD10 VCC3D SD9 SD8 VCC3IO INT IOR OE GND3IO 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VCC3D VCC5A VCC5R VCC5A VCC3IO MDC RXD3 RXD2 GND3IO RXD1 RXD0 X25M RXDV RXC RXER GND3IO TXC TXEN TXD0 TXD1 GND3IO TXD2 TXD3 GND3D COL CRS VCC3IO EXLEDF EXLEDL CE1 WE NC
TC5299J 128pin LQFP
VIS COA CW9 3 I O
S A 8
S A 7
GS NA D6 3 D
S A 5
S A 4
S A 3
S A 2
S A 1
GS NA D0 3 I O
NRWIR CSANE TIPG TA C K
GISSSVSSVSS NODDDCDDCDD DI012C34C56 3 3 3S D I I1 O O6
SG DN 7D 3 I O
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3.2
Signal Description PCMCIA Bus Interface Pins Symbol SA[9:0] Pin # 3-5 7-12, 14 114-117, 119-120, 122-123, 31-29, 27-26, 24-22 16 I/O I Description The address signal lines of PCMCIA Bus are used to select a register to be read or written and attribute memory enabled. Register Access, with DMA inactive, SD0-SD7 are used to read/write register data. SD8-SD15 invalid during this state. Remote DMA Bus Cycle, SD0-SD15 contain packet data. Direction of transfer depends on Remote read/write.
SD[15:8]
I/O
SD[7:0]
RST
I/O
RSTZ WAIT* REG*
105 17 19
O O I
RST is active high and places the TC5299J in a reset mode immediately. During falling edge the TC5299J controller loads the configuration from JMP0 - JMP8. RSTZ is an active low signal. It is an inverted signal of RST. This pin is set low to insert wait states during Remote DMA transfer. REG is an active low input used to determine whether a host access is to Attribute memory or to common memory. If REG is low the access is to attribute memory, if REG* is high the access is to common memory. REG* is also asserted low for all accesses to the TC5299J IO Registers. Read Strobe: Strobe from host to read registers or Remote DMA read. Write Strobe: Strobe from host to read registers or Remote DMA write. Host memory read strobe, when OE* and REG* both low the attribute memory can be read. When OE* is low and REG* is high common memory can be read. Host memory write strobe, After Power reset if TC5299J is configured to memory write enable, then WE and REG* is both low, Attribute memory can be written. When WE is low and REG* is high common memory can be written. An active low signal. Asserted if the host access register or Remote DMA read cycle. IO16* is driven by TC5299J to support host 16 bits access cycle. While the TC5299J is configured as a memory device, this pin servers as RDY/BSY* pin, If the TC5299J is ready to perform a transfer, this pin is set high. When TC5299J is operated at I/O mode, this pin is used as an interrupt pin. It indicates that the TC5299J needs host service. RDY/BSY* state can be read from the pin Replacement Register (CCR2). While LAN and MODEM both functions are enabled and IntSel bit in control Register (CCR5) is zero. This pin output is logical OR of LAN and MODEM interrupt. Card enable 1, is active low signals driven by the host. This signal provides a card select based on the address decode (decode by the host).
IOR* IOW* OE*
126 2 127
I I I
WE*
34
I
INPACK* IO16* INT* (RDY/BSY*)
18 21 125
O O O
CE1*
35
I
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EEPROM/LED Interface Pins Symbol EECS EESK/LEDLA DO/LEDS DI/LEDF Pin # 73 72 70 69 I/O O O I/O O Description EEPROM chip select. It is asserted when to access EEPROM. Link (on/off) & Receive data (Blink) LED pin. It is also used as a serial clock for EEPROM data loading. Speed (100M:ON/10M:OFF) & transmit data (Blink) LED pin. It is also used as a signal for EEPROM data loading. Full-duplex (ON/OFF, Full/Half-duplex) & Collision (Blink) LED pin. It is a data output pin for EEPROM writing.
External PHY / MII Interface Pins Symbol TXD[3:0] Pin # 42-43, 45-46 47 I/O O Description Four parallel transmit data lines. This data is synchronized to the assertion of the TXC signal and is latched by the external PHY on the rising edge of the TXC signal. This pin function as transmit enable. It indicates that a transmission is active on the MII port to an external PHY device. Pull down this pin on power-on reset to select 50MHz-clock input from pin X1. Otherwise, use 25MHz-clock input. Supports the transmit clock supplied by the external PMD device. This clock should always be active. Four parallel receive data lines. This data is driven by an external PHY that attached the media and should be synchronized with the RXC signal. Supports receive clock from PHY. And is recovered by the PHY. Data valid is asserted by an external PHY when receive data is present on the RXD[3:0] lines and is deasserted at the end of the packet. This signal should be synchronized with the RXC signal. Data valid is asserted by an external PHY when receive data is present on the RXD[3:0] lines and is deasserted at the end of the packet. This signal should be synchronized with the RXC signal. This pin functions as the collision detect. When the external physical layer protocol (PHY) device detects a collision, it asserts this pin. In MII mode this pin functions as the carrier sense and is asserted by the PHY when the media is active. MII management data clock is sourced by the TC5299J to the external PHY devices as a timing reference for the transfer of information on the MDIO signal. MII management data input/output transfers control information and status between the external PHY and the TC5299J. Low active; presents the external PHY link status. Present the half/full duplex mode for external PHY.
TXEN
I/O
TXC RXD[3:0]
48 58-57, 55-54 51 52
I I
RXC RXDV
I I
RXER
50
I
COL
40
I
CRS MDC
39 59
I O
MDIO EXLEDL EXLEDF Clock Interface Pins Symbol X1 X2 X25M
74 36 37
I/O I I
Pin # 66 67 53
I/O I O O
Description CRYSTAL OR EXTERNAL OSCILLATOR INPUT: 50 MHz CRYSTAL FEEDBACK OUTPUT: used in crystal connection only. 25MHz clock output -6-
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TC5299J
Power Supply Pins Symbol VCCAR GNDAR VCCA10 GNDA10 VCCAP GNDAP VCCDP GNDDP VCCAT GNDAT VCC5A VCC5R VCC3D, GND3D VCC3IO Pin # 95 92 87 91 86 90 85 89 100 99 101, 96, 63, 61 102, 62 121, 112, 28, 64 6, 41, 75, 78, 108 1, 25, 38, 60, 71, 81, 104, 113, 124 13, 20, 32, 44, 49, 56, 65, 68, 79, 106, 118, 128 I/O PWR GND Description Power input for internal circuit.
PWR, GND PWR PWR PWR, GND PWR,
Power input for internal circuit. 5V power input pin. 5V power reference pin. 3.3V power input pin, for digital core circuit.
3.3V power input pin, for I/O PAD.
GND3IO
GND
JUMPER Interface Pins Symbol JMP0 Pin # 107 I/O I Description When power on setting, this bit directly locked to CCR0, bit5. 0: enable I/O. For embedded system use to enable I/O mode. 1: disable I/O. For PCMCIA system use only. Default setting is leaving this pin open. Power on setting: 0: separate address decode. Decode range from A0 to A5. 1: full address decode. Decode range from A0 to A9.
JMP1
110
I
No Connection Pins Symbol NC NC Pin # 15, 103, 111, 33 97, 98, 93, 94, 83, 77, 84, 82, 80, 76, 88 I/O Description No Connection No Connection. Reserved for future use for PHY is included in a single chip.
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TC5299J
3.3
Power On Configuration The TC5299J Controller configures itself after a RST signal is applied. When a Power-On-Reset occurs the TC5299J controller latches up the values on the configuration pins and uses these to configure the internal registers and options. Internally these pins contain pull-up resistance. If pins are unconnected they have default logic. The configuration registers are loaded JMP0 & JMP1 setting when RST goes inactive. A Power-On-Reset also causes the Controller to load the internal PROM from the EEPROM, which can take up to 3 ms. This occurs after "Config-Regs." has completed. If EECONFIG is high the configuration data loaded on the falling edge of RST will be overwritten with data read from the serial EEPROM. Regardless of the level on EECONFIG the PROM store will always be loaded with data from the serial EEPROM during the time specified as EELOAD.
Figure 1 shows how the RESET circuitry operates.
VCC
RESET
Regload
EEload
The TC5299J Controller use a 93C56/66 EEPROM, The programmed contents of the EEPROM is shown as following. D15 CIS byte n 13H 12H 11H 10H 0FH 0EH ::::: 08H 07H ::::: 04H 03H 02H 01H 00H ........ ........ CIS byte 3 CIS byte 1 Not Used Config. B Reserved 42H 57H Reserved Reserved Reserved D8 D7 CIS byte n-1 D0
........ ........ CIS byte 2 CIS byte 0 Config C Config. A Reserved 42H 57H Reserved Reserved bit [0]: 8-bit enable bit [7:1]: Reserved Enet Address 5 Enet Address 4 Enet Address 3 Enet Address 2 Enet Address 1 Enet Address 0 EEPROM Programming Map
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TC5299J
Storing and Loading Configuration from EEPROM: During boot up the TC5299J Controller's configuration is read from the EEPROM, before the PROM data is read. The configuration data is stored within the address 0EH, 0FH (as above table) of the EEPROM's address space. Configuration Register A, B and C are located in the address 0EH. To write this configuration into the EEPROM, the user can program register in TC5299J's address 02H of page 3. This operation will work regardless of the level on EECONFIG.
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4 I/O and Mapping
4.1 I/O Port Address Mapping This chip is register-liked with Novell's NE2000. The base I/O address of TC5299J Controller is configured by Configuration Register (either upon power up or by software writing to this register). At that address the following structure appears. Base+00H TC5299J Core Registers Base+0FH Base+10H Data Transfer Port Base+17H Base+18H Reset Port Base+1FH The registers within this area are 8 bits wide, but the data transfer port is 16 bits wide. By accessing the data transfer port (using I/O instructions) the user can transfer data to or from the TC5299J 's internal memory. 4.2 EEPROM/SRAM Memory Mapping The TC5299J Controller's internal memory map is as shown below. D15 0000H PROM 001FH Reserved 4000H 8K x 16 Buffer RAM 7FFFH TC5299J Core Memory Map PROM Location 00h 01h 02h 03h 04h 05h 06-0Dh 0E,0Fh 10-15h 16-1Dh 1E-1Fh Location Contents ETHERNET ADDRESS 0 ETHERNET ADDRESS 1 ETHERNET ADDRESS 2 ETHERNET ADDRESS 3 ETHERNET ADDRESS 4 ETHERNET ADDRESS 5 RESERVED 57h ETHERNET ADDRESS 0-5 RESERVED 42h Contents of PROM Map -10D7 D0
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TC5299J
TC5299J Controller actually has 32k-address range but only does partial decoding on these devices. 0000H - 001FH is PROM address and 4000H - 7FFFH is Buffer RAM address, otherwise is reserved. To access either the PROM or the RAM buffer which user must initiate a Remote DMA transfer between the I/O port and memory. Remote Read/Write Cache: The TC5299J Controller includes 4 words cache internally. On a remote read the TC5299J Controller moves data from memory buffer to the cache buffer; the TC5299J moves data continuously until the cache buffer is full. On a remote write the system can writes data into the cache buffer until the 4 words cache buffer is full. 4.3 Attribute Memory Mapping
PCMCIA CIS Structures & Decode Function: The TC5299J supports access to 1K of attribute Memory. Attribute memory is defined by the PCMCIA standard to be comprised of the card information structure and four 8-bits Card Configuration Registers. These four registers are contained in the TC5299J. 4.3.1 Attribute Memory Map
The attribute Memory map for a PCMCIA card is shown below. Address 00H-3E0H 3F0H (CCR4) 3F2H (CCR5) 3F4H-3F6H 3F8H(CCR0) 3FAH(CCR1) 3FCH(CCR2) 3FEH(CCR3) Description Attribute Memory I/O Event indication Register Control Register Reserved Configuration Option Register Card Configuration and Status Register Pin Replacement Register Reserved
Card Option Registers 0 (R/W): 3F8H (CCR0) D7 SRESET D6 XX D5 PCMIOEN D4 XX D3 XX D2 XX D1 PJ1 D0 PJ0
Name PJ0-PJ1 PCMIOEN SRESET XX
Description If JMP1 pulled low during power on reset and FUNC=0, The two bits select one of 4 I/O base address. (shows as below) To set high make the card enter I/O mode. The function also can be set by JMP0 (MCS) when Power On Reset. Setting this bit to high, place the card enter reset mode. Reserved
JMP1 does not pull-low during power on reset.
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Ethernet I/O address range PJ1 0 0 1 1 PJ0 0 1 0 1 Address Range 300H-31FH 320H-33FH 340H-35FH 360H-37FH
Card Configuration and Status Registers (R/W): 3FAH (CCR1) D7 XX Name Ireq D6 XX D5 XX Description Interrupt. This bit describes the interrupt signal of LAN or MODEM 1: LAN interrupt 0: Modem interrupt Reserved D4 XX D3 XX D2 XX D1 Ireq D0 XX
XX
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5 Configuration Registers
5.1 Configuration Register A To prevent any accidental writes of this register it is"hidden" behind a previously unused register. Register 0AH in the Controller's Page 0 of registers was previously reserved on a read. Now Configuration Register A can be read at that address and can be written to by following a read to 0AH with a write to 0AH. If any other Controller register accesses take place between the read and the write then the write to 0AH will access the Remote Byte Count Register 0. 7 XX 6 FREAD 5 FDUPLEX 4 3 2 IO16CON 1 MIISEL1 0 MIISEL0
LNK_CFG FULL_CFG
Name MIISEL[1:0] IO16CON FULL_CFG
R/W R/W R/W R/W
Description 10: Default value to active the MII bus. Other: reserved. When this bit is set high the Controller generates IO16* after REG* active. If low this output is generated only on address decode. The bit is described EXLEDF what the polarity is. 0: Low active/ Hi inactive 1: Hi active/ Low inactive The bit is described EXLEDL what the polarity is. 0: Low active/ Hi inactive 1: Hi active/ Low inactive The Full-Duplex setting bit. 1: Full-duplex mode, 0: Half-duplex mode The bit is indicated the decode-number of SA[9:0]. 0: Only decode 5 address-lines, SA[5:0]. 1: Full decode 10 address-lines, SA[9:0]. The TC5299J Controller supports 4 words Remote DMA read/write cache. When this bit is set high, Remote DMA cache control will be enabled. Reserved
LNK_CFG
R/W
FDUPLEX
R
PCMIOALL
EL
FREAD XX
R/W
PS. EL: The bit only set on EEPROM loading.
5.2
Configuration Register B To prevent any accidental writes of his register it is "hidden" behind a previously unused register. Register 0BH in the Controller's Page 0 of registers was previously reserved on a read. Now Configuration Register B can be read at that address and can be written to by following a read to 0BH with a write to 0BH. If any other Controller register accesses take place between the read and the write then the write to 0BH will access the Remote Byte Count Register 1. 7 XX 6 LINT R/W R/W 5 EXTRMII 4 MIICINT 3 MIICIM 2 LINK 1 LCINT 0 LCIM
Name LCIM
Description The interrupt mask bit for link status changed. When set to "1", the Interrupt will generate on link status changed. -13-
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LCINT LINK MIICIM MIICINT EXTRMII LINT XX
R/W R R/W R/W R R/W X
The Link-Changed interrupt report bit. 1: indicates the Link status changed. When this bit is high, link test integrity checking is good. Otherwise, indicate link signal lost. This bit should be set to 0. This bit should be set to 0. This bit should be set to 0. LAN interrupt status indicator. To write a one to this bit can reset it. Reserved
5.3
Configuration Register C
This register just set in EEPROM and it can't been read from user. 7 XX Name RBLO [1:0] R/W X 6 XX 5 XX 4 FE 3 RBHI1 2 RBHI0 1 RBLO1 0 RBLO0
Description This is low value of receive buffer setting on full-duplex flow-control. It means that are few data in Rx buffer. 00: Less than 1.5K data in Rx buffer. 01: Less than 3k data in Rx buffer. 10: Less than 4.5k data in Rx buffer. 11: Less than 6k data in Rx buffer. That is high value of receive buffer setting on full-duplex flow-control. It means that is few space in Rx buffer. 00: Less than 1.5K space in Rx buffer. 01: Less than 3k space in Rx buffer. 10: Less than 4.5k space in Rx buffer. 11: Less than 6k space in Rx buffer. Flow control enable bit in full-duplex mode. 0: Disable flow-control. 1: Enable flow-control. Reserved
RBHI [1:0]
X
FE
X
XX
X
PS. X: Can't read, just set these bit in the EEPROM.
5.4
Hardware Configuration These functions are configured during a power on RESET.
Symbol JMP0 JMP1
I/O I/O I/O
Description Power on setting: 0: Enter I/O mode (Same as CCR0, bit 5) Power on setting: 1: Full address decode(A9-A0) 0: Separate address decode(A5-A0)
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Programming Register (R/W) The Controller enable software (driver) programming EEPROM or testing interrupt signal through this register directly. It is located at core register Page3 base+02H. 7 EESEL Name EESEL, CS, SK, DI, DO FIRQ READ ATTRDIS 6 FIRQ Description The software can read or programming serial EEPROM directly through accesses these bits. EESEL should be set high before starting the EEPROM read/write. 5 XX 4 READ 3 CS 2 SK 1 DI 0 DO(r) ATTRDIS
This chip interrupt signal IRQ will be asserted when this bit is set high. TC5299J can reload CFGA, CFGB and internal PROM, if this bit is set high. When reload state is completed, READ will be cleared to low. Attribute and common memory access will be disable if it is programmed to high. NOTE: DO: read only ATTRDIS: write only
5.5
MII/PHY Control Register The controller can access PHYTER register via software driver. It is located at core register Page3 base+03H.
7 XX Name MDC MDO MDIR R/W W W W
6 FE
5 XX
4 XX
3 MDI
2 MDIR
1 MDO
0 MDC
Description MII Management Clock MII Management Write Data. MII Management Operation Mode Defines the operation of PHY. When set, the PHY is in read operation mode. When clear, the PHY is in write operation mode. MII Management Data In. Flow control enable bit in full-duplex mode. The bit can be set when EEPROM loading. 0: Disable flow-control. 1: Enable flow-control. Reserved
MDI FE
R R/W
XX
X
5.6
TC5299J Core Registers Assignment All registers are 8-bit wide and mapped into four pages, which are selected in the Command Register (PS0, PS1).
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Pins A0-A3 are used to address registers within each page. Page 0 register are those registers which are commonly accessed during TC5299J Controller operation while Page 1 registers are used primarily for initialization. The registers are partitioned to avoid having to perform two read/write cycles to access commonly used registers. Register Assignments: Page 0 Address Assignments (PS1=0,PS0=0) A0-A3 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH Command(CR) Current Local DMA Address 0 (CLDA0) Current Local DMA Address 1 (CLDA1) Boundary Pointer (BNRY) Transmit Status Register(TSR) Number of Collisions Register(NCR) FIFO(FIFO) Interrupt Status Register(ISR) Current Remote DMA Address 0(CRDA0) Current Remote DMA Address 1(CRDA1) Config. Register A (CFGA) Config. Register B (CFGB) Receive Status Register(RSR) Tally Counter 0(Frame alignment Errors) (CNTR0) Tally Counter 1 (CRC errors) (CNTR1) Tally Counter 2 (Missed Packet Errors) (CNTR2) RD Command(CR) Page Start Register (PSTART) Page Stop Register (PSTOP) Boundary Pointer (BNRY) Transmit Page Start Address (TPSR) Transmit Byte Count Register 0 (TBCR0) Transmit Byte Count Register 1 (TBCR1) Interrupt Status Register(ISR) Remote Start Address Register 0(RSAR0) Remote Start Address Register 1(RSAR1) Remote Byte Count Register 0(RBCR0) Remote Byte Count Register 1(RBCR1) Receive Configuration Register(RCR) Transmit Configuration Register(TCR) Data Configuration Register(DCR) Interrupt Mask Register(IMR) WR
Page 1 Address Assignments (PS1=0,PS0=1) A0-A3 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH Command(CR) Physical Address Register 0(PAR0) Physical Address Register 1(PAR1) Physical Address Register 2(PAR2) Physical Address Register 3(PAR3) Physical Address Register 4(PAR4) Physical Address Register 5(PAR5) Current Page Register(CURR) Multicast Address Register 0(MAR0) Multicast Address Register 1(MAR1) Multicast Address Register 2(MAR2) Multicast Address Register 3(MAR3) Multicast Address Register 4(MAR4) Multicast Address Register 5(MAR5) -16RD Command(CR) Physical Address Register 0(PAR0) Physical Address Register 1(PAR1) Physical Address Register 2(PAR2) Physical Address Register 3(PAR3) Physical Address Register 4(PAR4) Physical Address Register 5(PAR5) Current Page Register(CURR) Multicast Address Register 0(MAR0) Multicast Address Register 1(MAR1) Multicast Address Register 2(MAR2) Multicast Address Register 3(MAR3) Multicast Address Register 4(MAR4) Multicast Address Register 5(MAR5) WR
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Page 1 Address Assignments (PS1=0,PS0=1) A0-A3 0EH 0FH RD Multicast Address Register 6(MAR6) Multicast Address Register 7(MAR7) WR Multicast Address Register 6(MAR6) Multicast Address Register 7(MAR7)
Page 2 Address Assignments (PS1=1,PS0=0) A0-A3 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH Command(CR) Page Start Register (PSTART) Page Stop Register (PSTOP) Remote Next Packet Pointer Transmit Page Start Address(TPSR) Local Next Packet Pointer Address Counter (Upper) Address Counter (Lower) Reserved Reserved Reserved Reserved Receive Configuration Register(RCR) Transmit Configuration Register(TCR) Data Configuration Register(DCR) Interrupt mask Register(IMR) RD Command(CR) Current Local DMA Address 0(CLDA0) Current Local DMA Address 1(CLDA1) Remote Next Packet Pointer Reserved Local Next Packet Pointer Address Counter (Upper) Address Counter (Lower) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved WR
Note: Page 2 registers should only be accessed for diagnostic purposes. They should not be modified during normal operation. Page 3 Reserved should never be modified.
Page 3 Address Assignments (PS1=1,PS0=1) A0-A3 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH Command(CR) Reserved Programming Reg. MII Control Register Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RD Command(CR) Reserved Programming Reg. MII Control Register Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved WR
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TC5299J
Page 3 Address Assignments (PS1=1,PS0=1) A0-A3 0CH 0DH 0EH 0FH 5.7 Reserved Reserved Reserved Reserved RD Reserved Reserved Reserved Reserved WR
Register Descriptions 5.7.1 Command Register (CR) 00H (Read/Write)
The Command Register is used to initiate transmissions, enable or disable Remote DMA operations and to select register pages. To issue a command the microprocessor sets the corresponding bit(s) (RD2, RD1, RD0 and TXP). Further commands may be overlapped, but with the following rules: (1) if a transmit command overlaps with a remote DMA operation, bits RD0, RD1, and RD2 must be maintained for the remote DMA command when setting the TXP bit. Note, if a remote DMA command is re-issued when giving the transmit command, the DMA will complete immediately if the remote byte count register have not been reinitialized. (2) If a remote DMA operation overlaps a transmission, RD0, RD1, and RD2 may be written with the desired values and a "0"to this bit has no effect. (3) A remote write DMA may not overlap remote read operation or visa versa. Either of these operations must either complete or be aborted before the other operation may start. Bits PS1, PS0, RD2, and STP may be set any time. 7 PS1 Bit D0 Symbol STP 6 PS0 5 RD2 4 RD1 3 RD0 2 TXP 1 STA 0 STP
Description Stop: Software reset command, take the controller offline, no packets will be received or transmitted. Any reception of transmission in progress will continue to completion before entering the reset state. To exit this state, the STP bit must be reset. The software reset has executed only when indicated by the RST bit in the ISR being set to a 1. STP powers up high. Start: This bit is used to active the TC5299J core after either power up, or when the TC5299J core has been placed in a reset mode by software command. STA power up low. Transmit Packet: This bit must be set to initiate transmission of a packet. TXP is internally reset either after the transmission is completed or aborted. This bit should be set only after the Transmit Byte Count and Transmit Page Start registers have been programmed. TXP powers up low. Remote DMA Command: These three encoded bits control operation of the Remote DMA channel. RD2 can be set to about any Remote DMA command in progress. The Remote Start Addresses are not restored to the starting address if the Remote DMA is aborted. RD2 powers up high. RD2 RD1 RD0 0 0 0 Not Allowed 0 0 1 Remote Read 0 1 0 Remote Write (Note) 0 1 1 Send Packet 1 X X Abort/Complete Remote DMA (Note) Page Select: Three two encoded bits select which register page is to be accessed with addresses A0-3. PS1 PS0 0 0 Register Page 0 -18-
D1
STA
D2
TXP
D3-D5
RD0-RD2
D6,D7
PS0,PS1
Ver. 0.1 07/04/01
TC5299J
Bit
Symbol
Description 0 1 1 1 0 1 Register Page 1 Register Page 2 Register Page 3 0EH(Write)
5.7.2
Data Configure register (DCR)
This Register is used to program the TC5299J for 8 or 16-bit memory interface, select byte ordering in 16-bit applications and establish FIFO thresholds. The DCR must be initialized prior to loading the Remote Byte count Registers. 7 Bit D0 Symbol WTS 6 FT1 5 FT0 4 3 LS 2 1 0 WTS
Description Word Transfer Select 0: Selects byte-wide DMA transfers. 1: Selects word-wide DMA transfers Note: When word-wide mode is selected, up to 32k bytes are addressable; A0 remains low. Reserved Reserved Loopback Select 0: Loopback mode selected. Bits D1, D2 of the TCR must also be programmed for Loopback mode selected. 1: Normal Operation. Reserved FIFO Threshold Select: Encoded: FIFO threshold. During reception, the FIFO threshold indicates the number of bytes (or words) the FIFO has filled serially from the network before the FIFO is emptied onto memory bus. RECEIVE THRESHOLDS FT1 FT0 Word Wide Byte Wide 0 0 2 Word 4 Bytes 0 1 4 Word 8 Bytes 1 0 8 Word 16 Bytes 1 1 12 Word 24 Bytes During transmission, the FIFO threshold indicates the number of bytes (of words) the FIFO has filled from the Local DMA before being transferred to the memory. Thus, the transmission threshold is 16 bytes less the receive threshold.
D1 D2 D3
LS
D4 D5,D6
FT0,FT1
5.7.3
Transmit configuration Register (TCR)
0DH(Write)
The transmit configuration establishes the actions of the transmitter section of the TC5299J during transmission of a packet on the network, LB1 and LB0 power up as 0. 7 Bit D0 Symbol CRC 6 5 4 OFST 3 ATD 2 LB1 1 LB0 0 CRC
Description Inhibit CRC -19-
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TC5299J
D1,D2
LB0,LB1
D3 D4
OFST
0: CRC appended by transmitter 1: CRC inhibited by transmitter Encoded Loopback Control: These encoded configuration bits set the type of loopback that is to be performed. Note that loopback in mode 2 sets the LPBK pin high, this places the TC5299J in loopback mode and that D2 of the DCR must be set to zero for loopback operation. LB1 LB0 Mode0 0 0 Normal Operation (LPBK=0) Mode1 0 1 Internal Loopback (LPBK=0) Reserved 1 0 Reserved 1 1 Reserved Collision Offset Enable: This bit modifies the back off algorithm to allow prioritization of nodes. 0: Backoff Logic implements normal algorithm. 1: Forces Backoff algorithm modification to 0 to 2mim(3+n,10) slot times for first three collisions, Then follows standard backoff. (For first three collisions station has higher average backoff delay making a low priority mode.) Reserved Reserved Reserved
D5 D6 D7
-
5.7.4
Transmit Status Register (TSR)
04H(Read)
This register records events that occur on the media during transmission of a packet. It is cleared, when the next transmission is initiated by the host. All bits remain low unless the event that corresponds to a particular bit occurs during transmission. Each transmission should be followed by a read of this register. The contents of this register are not specified until after the first transmission. 7 OWC Bit D0 D1 D2 Symbol PTX COL 6 5 FU Description Packet Transmitted: Indicates transmission without error (No excessive collisions or FIFO underrun) (ABT="0", FU="0"). Reserved Transmit Collided: Indicates that the transmission collided at least once with another station on the network. The number of collisions is recorded in the Number of Collisions Registers. (NCR). Transmit Aborted: Indicates the TC5299J aborted transmission because of excessive collisions. (Total number of transmissions including original transmission attempt equals 16). Carrier Sense Lost: This bit is set when carrier is lost during transmission of the packet. Carrier Sense is monitored from the end of Preamble/Synch until TXE is dropped. Transmission is not aborted on loss of carrier. FIFO Underrun: If the TC5299J cannot gain access of the bus before the FIFO empties, this bit is set. Transmission of the packet will be aborted. Reserved Out of Window Collision: Indicates that a collision occurred after a slot time. Transmissions rescheduled as in normal collisions. 4 CRS 3 ABT 2 COL 1 0 PTX
D3
ABT
D4
CRS
D5 D6 D7
FU OWC
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TC5299J
5.7.5
Receive Configuration Register (RCR)
0CH(Write)
This register determines operation of the TC5299J during reception of a packet and is used to program what types of packets to accept. 7 Bit D0 Symbol SEP 6 5 MON 4 PRO 3 AM 2 AB 1 AR 0 SEP
Description Save Errored Packets 0: Packets with receive errors are rejected. 1: Packets with receive errors are accepted. Receive errors are CRC and Frame Alignment errors. Accept Runt Packets 0: Packets with fewer than 64 bytes rejected. 1: Packets with fewer than 64 bytes accepted. Accept Broadcast 0: Packets with all 1's broadcast destination address rejected. 1: Packets with all 1's broadcast destination address accepted. Accept Multicast 0: Packets with multicast destination address not checked. 1: Packets with multicast destination address checked. Promiscuous Physical 0: Physical address of node must match the station address programmed in PAR0-PAR5. (Physical address checked) 1: All packets with any physical address accepted. (physical address not checked) Monitor Mode: Enables the receiver to check addresses and CRC on incoming packets without buffering to memory. The missed packet Tally counter will be incremented for each recognized packet. 0: Packets buffered to memory. 1: Packets checked for address match, good CRC and frame Alignment but not buffered to memory. Reserved Reserved
D1
AR
D2
AB
D3
AM
D4
PRO
D5
MON
D6 D7
-
Note: D2 and D3 are "OR'd" together, i. e., if D2 and D3 are set the TC5299J will accept broadcast and multicast addresses as well as its own physical address. To establish full promiscuous mode, bits D2, D3 and D4 should be set. In addition the multicast hashing array must be set to all 1's in order to accept all multicast addresses. 5.7.6 Receive Status Register (RSR) 0CH(Read)
This register records status of the received packet, including information on errors and the type of address match, either physical or multicast. The contents of this register are written to buffer memory by the DMA after reception of a good packet. If packets with errors are to be saved the receive status is written to memory at the head of the erroneous packet if an erroneous packet is received. If packets with errors are to be rejected the RSR will not be written to memory. The contents will be cleared when the next packet arrives. CRC errors, frame Alignment errors and missed packets are counted internally by the TC5299J which relinquishes the Host from reading the RSR in real time to record errors for Network Management functions. The contents of this register are not specified until after the first reception. 7 6 5 4 3 2 1 0
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TC5299J
DFR Bit D0 D1 D2 Symbol PRX CRC FAE
DIS
PHY
MPA
FO
FAE
CRC
PRX
Description Packet Received Intact: Indicates packet received without error. (Bits CRC, FAE, FO and MPA are zero for the received packet.) CRC Error: Indicates packet received with CRC error. Increments Tally Counter (CNTR1). This bit will also be set for Frame Alignment errors. Frame Alignment Error: Indicates that the incoming packet did not end on a byte boundary and the CRC did not match at last byte boundary. Increments Tally counter (CNTR0). FIFO Overrun: This bit is set when the FIFO is not serviced causing overflow during reception. Reception of the packet will be aborted. Missed Packet: Set when packet intended for node cannot be accepted by TC5299J because of a lack of receive buffers of if the controller is in monitor mode and did not buffer the packet to memory. Increments Tally Counter (CNTR2). Physical/Multicast Address: Indicates whether received packet had a physical or multicast address type 0: Physical Address Match 1: Multicast/Broadcast Address Match Receiver Disabled: Set when receiver disabled by entering Monitor mode. Reset when receiver is re-enabled when exiting Monitor mode. Deferring: Set when CRS or COL inputs are active. If the transceiver has asserted the CD line as a result of the jabber, this bit will stay set indicating the jabber condition.
D3 D4
FO MPA
D5
PHY
D6 D7
DIS DFR
Note: Following coding applies to CRC and FAE bits FAE CRC Type of Error 0 0 1 1 5.7.7 0 1 0 1 No error (Good CRC and <6 Dribble Bits) CRC ERROR Legal, will not occur Frame Alignment Error and CRC Error Interrupt Mask Register (IMR) 0FH(Write)
The interrupt Mask Register is used to mask interrupts. Each interrupt mask bit corresponds to a bit in the Interrupt Status Register (ISR). If an interrupt mask bit is set, an interrupt will be issued whenever the corresponding bit in the ISR is set. If any bit in the IMR is set low, an interrupt will not occur when the bit in the ISR is set. The IMR powers up all zeroes. 7 Bit D0 D1 D2 D3 D4 D5 Symbol PRXE PTXE RXEE TXEE OVWE CNTE 6 RDCE 5 CNTE 4 OVWE 3 TXEE 2 RXEE 1 PTXE 0 PRXE
Description Packet Received Interrupt Enable: Enables Interrupt when packet received. Packet Transmitted Interrupt Enable: Enables Interrupt when packet is transmitted. Receive Error Interrupt Enable: Enables Interrupt when packet received with error. Transmit Error Interrupt Enable: Enables Interrupt when packet transmission results in error. Over Write Warning Interrupt Enable: Enables Interrupt when Buffer management Logic lacks sufficient buffers to store incoming packet. Counter Overflow Interrupt Enable: Enables Interrupt when MSB of one or more fh N k T ll hb -22-
Ver. 0.1 07/04/01
TC5299J
Bit D6 D7 5.7.8
Symbol RDCE -
Description of the Network Tally counters has been set. DMA Complete Interrupt Enable: Enables Interrupt when Remote DMA transfer has been completed. Reserved 07H(Read/Write)
Interrupt Status Register (ISR)
This register is accessed to determine the cause of an interrupt. Any interrupt can be masked in the interrupt Mask Register (IMR). Individual interrupt bits are cleared by writing a "1" into the corresponding bit of the ISR. The IRQ signal is active as long as any unmasked signal is set, and will not go low until all unmarked bits in this register have been cleared. The ISR must be cleared after power up by writing it with all 1's. 7 RST Bit D0 D1 D2 Symbol PRX PTX RXE 6 RDC 5 CNT 4 OVW 3 TXE 2 RXE 1 PTX 0 PRX
Description Packet Received: Indicates packet received with no errors. Packet Transmitted: Indicates packet transmitted with no errors. Receive Error: Indicates that a packet was received with one or more of the following errors: - CRC Error - Frame Alignment Error - FIFO Overrun - Missed Packet Transmit Error: Set when packet transmitted with one or more of the following errors: - Excessive Collisions - FIFO Underrun Over Write Warning: Set when receive buffer ring storage resources have been exhausted. (Local DMA has reached Boundary Pointer). Counter Over flow: Set when MSB of one or more of the Network Tally Counters has been set. Remote DMA Complete: Set when Remote DMA operation has been completed. Reset Status: A status indicator with no interrupt generated - Set when TC5299J enters reset state and is cleared when a start command is issued - Set when a Receive Buffer Ring overflows and is cleared when leaves overflow status. Writing to this bit has no effect and powers up high.
D3
TXE
D4 D5 D6 D7
OVW CNT RDC RST
5.8
Network Tally Counter Registers (CNTR) Three 8-bit counters are provided for monitoring the number of CRC errors, Frame Alignment Errors and missed packets, The maximum count reached by any counter is 192 (C0H). These registers will be cleared when read by the CPU. The count is recorded in binary in CT0-CT7 of each Tally Register.
CNTR0: Monitor the number of Frame Alignment error 7 6 5 4 CT7 CT6 CT5 CT4
3 CT3
2 CT2
1 CT1
0 CT0
CNTR1: Monitor the number of CRC error -23-
Ver. 0.1 07/04/01
TC5299J
7 CT7
6 CT6
5 CT5
4 CT4
3 CT3
2 CT2
1 CT1
0 CT0
CNTR2: Monitor the number of Missed Packets 7 6 5 CT7 5.9 CT6 CT5
4 CT4
3 CT3
2 CT2
1 CT1
0 CT0
Number of Collisions Register (NCR) This register contains the number of collisions a node experiences when attempting to transmit a packet. If no collisions are experienced during a transmission attempt, the COL bit of the TSR will not be set and the contents of NCR will be zero. If there are excessive collisions, the ABT bit in the TSR will be set and the contents of NCR will be zero. The NCR is cleared after the TXP bit in the CR is set. 7 6 5 4 3 NC3 2 NC2 1 NC1 0 NC0
5.10 Physical Address Register (PAR0-PAR5) The physical address registers are used to compare the destination address of incoming packets for rejecting or accepting packets. Comparisons are performed on a byte-wide basis. The bit assignment shown below relates the sequence in PAR0-PAR5 to the bit sequence of the received packet. .. Syn Syn DA0 |------D7 DA7 DA15 DA23 DA31 DA39 DA47 D6 DA6 DA14 DA22 DA30 DA38 DA46 D5 DA5 DA13 DA21 DA29 DA37 DA45 DA1 DA2 DA3 DA4 DA5 DA6 DA7 ..
Destination Address D4 DA4 DA12 DA20 DA28 DA36 DA44 D3 DA3 DA11 DA19 DA27 DA35 DA43 D2 DA2 DA10 DA18 DA26 DA34 DA42 D1 DA1 DA9 DA17 DA25 DA33 DA41
--------|--- Source D0 DA0 DA8 DA16 DA24 DA32 DA40
PAR0 PAR1 PAR2 PAR3 PAR4 PAR5
5.11 Multicast Address Registers (MAR0-MAR7) The Multicast address registers provide filtering of multicast addresses hashed by the CRC logic. All destination addresses are fed through the CRC logic and as the last bit of the destination address enters the CRC, the 6 most significant bits of the CRC generator are latched. These 6 bits are then decoded by a 1 of 64 decode to index a unique filter bit (FB0-63) in the multicast address register. If the filter bit selected is set, the multicast packet is accepted. The system designer would use a program to determine which filter bits to set in the multicast registers. For some address found to hash to the value 50 (32H), then FB50 in MAR6 should be initialized to "1" All multicast filter bits that correspond to multicast address accepted by the node are then set to one. To accept all multicast packets all of the registers are set to all ones.
D7 MAR0 MAR1 MAR2 MAR3 FB7 FB15 FB23 FB31
D6 FB6 FB14 FB22 FB30
D5 FB5 FB13 FB21 FB29
D4 FB4 FB12 FB20 FB28 -24-
D3 FB3 FB11 FB19 FB27
D2 FB2 FB10 FB18 FB26
D1 FB1 FB9 FB17 FB25
D0 FB0 FB8 FB16 FB24
Ver. 0.1 07/04/01
TC5299J
MAR4 MAR5 MAR6 MAR7 5.12 DMA Registers
FB39 FB47 FB55 FB63
FB38 FB46 FB54 FB62
FB37 FB45 FB53 FB61
FB36 FB44 FB52 FB60
FB35 FB43 FB51 FB59
FB34 FB42 FB50 FB58
FB33 FB41 FB49 FB57
FB32 FB40 FB48 FB56
LOCAL DMA TRANSMIT REGISTERS 15 8| 7 (TPSR) TRANSMIT PAGE START TRANSMIT BYTE COUNT
0
(TBCR0,1)
5.13 LOCAL DMA RECEIVE REGISTERS 15 8| 7 (PSTART) (PSTOP) (CURR) (BRNY) PAGE START PAGE STOP CURRENT BOUNDARY 15 (CLDA0,1) 8| 7
0
0
CURRENT LOCAL DMA ADDRESS
5.14 REMOTE DMA REGISTERS 15 8| 7 (RSAR0,1) (RBCR0,1) (CRDA0,1) START ADDRESS BYTE COUNT CURRENT REMOTE DMA ADDRESS
0
5.15 (i) Local DMA Transmit Registers Transmit page start register (TPSR): This register points to the assembled packet to be transmitted. Only the eight higher order addresses be specified since all transmit packets are assembled on 256-byte page boundaries. 7 A15 6 A14 5 A13 4 A12 3 A11 2 A10 1 A9 0 A8
Transmit byte count register0, 1 (TBCR0, TBCR1): These two registers indicate the length of the packet to be transmitted in bytes. The maximum number of transmit bytes allowed is 32k bytes. (4000H - 7FFFH) The TC5299J will not truncate transmissions longer than 1500 bytes. 7 L15 6 L14 5 L13 4 L12 3 L11 2 L10 1 L9 -250 L8
TBCR1
Ver. 0.1 07/04/01
TC5299J
TBCR0
7 L7
6 L6
5 L5
4 L4
3 L3
2 L2
1 L1
0 L0
5.16 (ii) Local DMA Receive Registers Page start, stop registers (PSTART, STOP): The Page Start and Page stop Registers program the starting and stopping page of the Receive Buffer Ring. Since the TC5299J uses fixed 256-byte buffers aligned on page boundaries only the upper eight bits of the start and stop address are specified. 7 PSTART PSTOP A15 6 A14 5 A13 4 A12 3 A11 2 A10 1 A9 0 A8
Boundary register (BNRY): This register is used to prevent overflow of the Receive Buffer Ring. Buffer management compares the contents of this register to the next buffer address when linking buffers together. If the contents of this register match the next buffer address the local DMA operation is aborted. 7 BNRY A15 6 A14 5 A13 4 A12 3 A11 2 A10 1 A9 0 A8
5.17 (iii) Remote DMA registers Remote Start Address Registers (RSAR0, 1): Remote Byte Count Registers (RBCR0, 1): Remote DMA operations are programmed via the Remote Start Address (RSAR0, 1) and Remote Byte Count (RBCR0, 1) registers. The Remote Start Address is used to point to the start of the block of data to be transferred and the Remote Byte Count is used to indicate the length of the block (in bytes). 7 RSAR1 A15 7 RSAR0 A7 7 RBCR1 BC15 7 RBCR0 BC7 6 BC6 6 A6 6 BC14 5 BC5 6 A14 5 A5 5 BC13 4 BC4 5 A13 4 A4 4 A12 3 A3 4 BC12 3 BC3 3 A11 2 A2 3 BC11 2 BC2 2 A10 1 A1 2 BC10 1 BC1 1 A9 0 A0 1 BC9 0 BC0 0 BC8 0 A8
Current Page Register: This register is used internally by the Buffer Management Logic as a backup register for reception. CURR contains the address of the first buffer to be used for a packet reception and is used to restore DMA pointers in the event of receive errors. This register is initialized to the same value as PSTART and should not be written to again unless the controller is reset. 7 6 5 4 3 2 1 0 CURR A15 A14 A13 A12 A11 A10 A9 -26A8
Ver. 0.1 07/04/01
TC5299J
Current local DMA register 0,1 (CLDA0, 1): These two registers can be accessed to determine the current Local DMA Address. 7 CLDA1 A15 7 CLDA0 A7 6 A14 6 A6 5 A13 5 A5 4 A12 4 A4 3 A11 3 A3 2 A10 2 A2 1 A9 1 A1 0 A8 0 A0
Current Remote DMA Address Registers: The Current Remote DMA Registers contain the current address of the Remote DMA. The bit assignment is shown as below: 7 CRDA1 A15 7 CRDA0 A7 6 A14 6 A6 5 A13 5 A5 4 A12 4 A4 3 A11 3 A3 2 A10 2 A2 1 A9 1 A1 0 A8 0 A0
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TC5299J
6 Electrical Specification and Timing
MII : RECEIVE TIMING
An example transfer a packet from PHY to MAC
RXC RXDV RXD[3:0] RXER Receive Data
TRANSMIT TIMINGS
An example transfer a packet from MAC to PHY
TXC TXEN TXD[3:0] CRS COL Transm it Data
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Ver. 0.1 07/04/01
TC5299J
ISA Slave Accesses
ISA Slave Accesses
T6c T16
ALE
T1 T15 T19 T18
AEN
T2
T6a
SA0-9
T13
T7
IOR*,IOW*
T14
IO16*
T5a T5c
IORDY
T3 T4 T17 T10
SD0-15 (Read)
T20 T11
T9
SD0-15 (Write)
Data Valid
T12
MR*
T21 MW * T22
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TC5299J
Symbol T1 T2 T3 T4 T5a T5c T6a T6c T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Description ALE Width (ISA Interface) AEN valid before Command Strobe Active SA0-9 Valid before IOR* , IOW* Asserted IOR*, Asserted to SD0-15 Driven SA0-9 Valid before IO16* Valid SA0-9 Valid and IOR* or IOW* Active before IO16* Valid IOR*, IOW* Asserted to IORDY Deasserted ALE Asserted and SA0-9 Valid to IORDY Deasserted IOR*, IOW* Deasserted before SA0-9 Invalid IOR*, Deasserted to SD0-15 Read Data Invalid IOR*, Deasserted to SD0-15 Floating SD0-15 Write Data Valid to IOW* Deasserted IOW*, Deasserted to SD0-15 Write Data Invalid IOR*, IOW* Active Width IOR*, IOW* Inactive Width ALE Asserted before IOR*, IOW* Asserted IOR*, IOW* Negated before Next ALE Asserted IORDY Asserted to SD0-15 I/O Read Data Valid IOR*, IOW* Deasserted before AEN Invalid AEN Valid before ALE Deasserted IOR* Asserted to SD0-15 Read Data Valid IORDY Invalid after MR* Deasserted IORDY Invalid after MW* Deasserted
8-Bit Transfers Min Max 20 60 40 0
16-Bit Transfers Min Max 20 60 20 0 60 50
Units ns ns ns ns ns ns ns ns ns ns
100 60 15 0 45 60 20 300 85 20 20 140 85 25 20 60 25 50 150 25 50 15 0
50 60
45
ns ns ns ns ns ns ns
60
ns ns ns
90 30 20
ns ns ns
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Ver. 0.1 07/04/01
TC5299J
7 Physical Dimension
D D1
1 2
65
4
2
1
96
97
64
R1 B R2
E1 E
GAGE PLANE
.25
2
1
S 3
128 PIN 1 IDENTIFIER 1 32 33
B L L1
DETAIL "A" e b
"A"
A A2 -C6 A1
WITH PLATING
0.08
C
b
5
3
PACKAGE LQFP 128
c
5 5
c1
BASE METAL
b1
5
SECTION B-B
Dimension in mm Symbol A A1 A2 b b1 c c1 D D1 E E1 Min -----0.05 1.35 0.13 0.13 0.09 0.09 15.85 13.90 15.85 13.90 Nom ----------1.40 0.18 0.16 ----------16.00 14.00 16.00 14.00 0.40 BSC 0.45 0.60 1.00 REF 0.08 0.08 0.20 --------------------0.20 -----0.75 Max 1.60 -----1.45 0.23 0.19 0.20 0.16 16.15 14.10 16.15 14.10
Dimension in inch Min -----0.002 0.053 0.005 0.005 0.004 0.004 0.624 0.547 0.624 0.547 Nom ----------0.055 0.007 0.006 ----------0.630 0.551 0.630 0.551 0.016 BSC 0.018 0.024 0.039 REF 0.003 0.003 0.008 --------------------0.008 ----0.030 Max 0.063 -----0.057 0.009 0.007 0.008 0.006 0.636 0.555 0.636 0.555
e
L L1 R1 R2 S
1 2 3
0 0
3 .5
------
7
------
0 0
3 .5
------
7
------
12 TYP 12 TYP
12 TYP 12 TYP
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TC5299J
Notice
This document contains information on product, which is in the development phase. TMI reserves the rights to change specifications, features, functions and availability of the product without notice. TMI devices are NOT designed, intended, authorized, or warranted to be suitable for use in Life-Supporting applications.
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Ver. 0.1 07/04/01

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