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Integrated Device Technology, Inc.
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY
IDT54/74FCT162511AT/CT
FEATURES:
* * * * * * * * * * * 0.5 MICRON CMOS Technology Typical tsk(o) (Output Skew) < 250ps, clocked mode Low input and output leakage 1A (max) ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack Extended commercial range of -40C to +85C VCC = 5V 10% Balanced Output Drivers: 24mA (commercial) 16mA (military) Series current limiting resistors Generate/Check, Check/Check modes Open drain parity error allows wire-OR
DESCRIPTION:
The FCT162511AT/CT 16-bit registered/latched transceiver with parity is built using advanced dual metal CMOS technology. This high-speed, low-power transceiver combines D-
type latches and D-type flip-flops to allow data flow in transparent, latched or clocked modes. The device has a parity generator/cheker in the A-to-B direction and a parity checker in the B-to-A direction. Error checking is done at the byte level with separate parity bits for each byte. Separate error flags exits for each direction with a single error flag indicating an error for either byte in the A-to-B direction and a second error flag indicating an error for either byte in the B-to-A direction. The parity error flags are open drain outputs which can be tied together and/or tied with flags from other devices to form a single error flag or interrupt. The parity error flags are enabled by the OExx control pins allowing the designer to disable the error flag during combinational transitions. The control pins LEAB, CLKAB and OEAB control operation in the A-to-B direction while LEBA, CLKBA and OEBA control the B-to-A direction. GEN/CHK is only for the selection of A-to-B operation, the B-to-A direction is always in checking mode. The ODD/EVEN select is common between the two directions. Except for the ODD/EVEN control, independent operation can be achieved between the two directions by using the corresponding control lines.
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM:
LEAB CLKAB Data 16 Parity GEN/CHK Byte Parity Generator/ Checker 2 Latch/ Register Parity, data 18 OEAB B0-15 PB1,2
PERB (Open Drain)
A0-15 PA1,2 ODD/EVEN
LEBA CLKBA Parity, data 18 OEBA PERA (Open Drain) Latch/ Register Byte Parity Checking Parity, Data 18
2916 drw 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1996 Integrated Device Technology, Inc.
AUGUST 1996
DSC-2916/5
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IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL BLOCK DIAGRAM
ODD/EVEN OEAB LEBA CLKBA CLKAB LEAB C A0 - A7 D C D OEBA C D B0 - B7
C D
P
O
C D
C D P C D C D
PB1
PA1
I
C A8 - A15 D C D
C D
B8 - B15
C D
P
O
C D
C D C D C D C D C
PA2
I
PB2
C GEN/CHK D
PERB (Open Drain) C D P
2916 drw 02
PERA (Open Drain)
D
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IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
OEAB LEAB PA1 GND A0 A1 VCC A2 A3 A4 A5 A6 A7 GND PERA A8 A9 A10 A11 A12 A13 VCC A14 A15 GND PA2 OEBA LEBA 1 2 3 4 5 6 7 8 9 10 11 12 13 56 55 54 53 52 51 50 49 48 47 46 45 44 GEN/CHK CLKAB PB1 GND B0 B1 VCC B2 B3 B4 B5 B6 B7 PERB GND B8 B9 B10 B11 B12 B13 VCC B14 B15 GND PB2 CLKBA ODD/EVEN
OEAB LEAB PA1 GND A0 A1 VCC A2 A3 A4 A5 A6 A7 GND PERA A8 A9 A10 A11 A12 A13 VCC A14 A15 GND PA2 OEBA LEBA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 E56-1
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
GEN/CHK CLKAB PB1 GND B0 B1 VCC B2 B3 B4 B5 B6 B7 PERB GND B8 B9 B10 B11 B12 B13 VCC B14 B15 GND PB2 CLKBA ODD/EVEN
14 SO56-1 43 SO56-2 15 SO56-3 42 16 17 18 19 20 21 22 23 24 25 26 27 28 41 40 39 38 37 36 35 34 33 32 31 30 29
SSOP/ TSSOP/TVSOP TOP VIEW
2916 drw 03
CERPACK TOP VIEW
2916 drw 04
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IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max. VTERM(2) Terminal Voltage with Respect to -0.5 to +7.0 GND VTERM(3) Terminal Voltage with Respect to -0.5 to GND VCC +0.5 TSTG Storage Temperature -65 to +150 IOUT DC Output Current -60 to +120 Unit V V C mA
PIN DESCRIPTION
Pin Names Description A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B Latch Enable Input B-to-A Latch Enable Input A-to-B Clock Input B-to-A Clock Input A-to-B Data Inputs or B-to-A 3-State Outputs B-to-A Data Inputs or A-to-B 3-State Outputs Parity Error (Open Drain) on A Outputs Parity Error (Open Drain) on B Outputs A-to-B Parity Input, B-to-A Parity Output B-to-A Parity Input, A-to-B Parity Output Parity Mode Selection Input A to B Port Generate or Check Mode Input
OEAB OEBA
LEAB LEBA CLKAB CLKBA Ax Bx
2916 lnk 01 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Open drain and all device terminals except FCT162XXXT Output and I/O terminals. 3. Output and I/O terminals for FCT162XXXT.
PERA PERB
PAx(1) PBx ODD/EVEN
GEN/CHK
FUNCTION TABLE
(1,4)
OEAB
H L L L L L L
Inputs LEAB CLKAB X H H L L L L X X X L H
Ax X L H L H X X
Outputs Bx Z L H L H B(2) B(3)
2916 tbl 03 NOTES: 1. The PAx pin input is internally disabled during parity generation. This means that when generating parity in the A to B direction there is no need to add a pull up resistor to guarantee state. The pin will still function properly as the parity output for the B to A direction.
NOTES: 2916 tbl 02 1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA. 2. Output level before the indicated steady-state input conditions were established. 3. Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. 4. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance = LOW-to-HIGH Transition
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IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol CIN Input Capacitance CI/O I/O Capacitance CO Open Drain Capacitance Parameter(1) Conditions VIN = 0V VOUT = 0V VOUT = 0V Typ. 3.5 3.5 3.5 Max. 6.0 8.0 6.0 Unit pF pF pF
2916 lnk 04
FUNCTION TABLE (PARITY GENERATION)(1, 2, 3, 4, 5)
A0 - A7, Total Number of inputs that are high 1, 3, 5 or 7 1, 3, 5 or 7 0, 2, 4, 6 or 8 0, 2, 4, 6 or 8 ODD/EVEN EVEN L H L H PB1 H L L H
NOTE: 1. This parameter is measured at characterization but not tested.
FUNCTION TABLE (PARITY CHECKING)(1, 2, 3, 4)
A0 - A7 and PA1 (5), Total Number of inputs that are high 1, 3, 5, 7 or 9 1, 3, 5, 7 or 9 0, 2, 4, 6 or 8 0, 2, 4, 6 or 8 ODD/EVEN EVEN L H L H
2916 tbl 06 NOTES: 1. Conditions shown are for GEN/CHK = L, OEAB = L, OEBA = H. 2. A-to-B parity checking is shown. B-to-A is capable of parity checking while A-to-B is performing generation. B-to-A will not generate parity. 3. The response shown is for LEAB = H. If LEAB = L then CLKAB will control as an edge triggered clock. 4. Conditions shown are for the byte A0-A7 . The byte A8-A15 is similiar but will output the parity on PB2. 5. The error flag PERB will remain in a high state during parity generation.
PERB
L H(6) H(6) L
2916 tbl 05 NOTES: 1. Conditions shown are for GEN/CHK = H, OEAB = L, OEBA = H. 2. A-to-B parity checking is shown. B-to-A parity checking is similar but uses OEBA = L, OEAB = H and errors will be indicated on PERA. 3. In parity checking mode the parity bits will be transmitted unchanged along with the corresponding data regardless of parity errors. (PB1 = PA1). 4. The response shown is for LEAB = H. If LEAB = L then CLKAB will control as an edge triggered clock. 5. Conditions shown are for the byte A0-A7 and PA1. The byte A8-A15 and PA2 is similiar. 6. The parity error flag PERB is a combined flag for both bytes A0-A7 and A8A15. If a parity error occurs on either byte PERB will go low. PERB is an open drain output which must be externally pulled up to achieve a logic HIGH.
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IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = -40C to +85C, VCC = 5.0V 10%; Military: TA = -55C to +125C, VCC = 5.0V 10%
Symbol VIH VIL II H II L IOZH IOZL VIK IOS VH ICCL ICCH ICCZ Parameter Input HIGH Level Input LOW Level Input HIGH Current (Input pins)(5) Input HIGH Current (I/O pins)(5) Input LOW Current (Input pins)(5) VCC = Max. VCC = Min., IIN = -18mA VCC = Max., VO = GND (3)
--
Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VI = VCC VI = GND VO = 2.7V VO = 0.5V
Min. 2.0 -- -- -- -- -- -- -- -- -80 -- --
Typ.(2) --
-- -- -- -- -- -- -- -0.7 -140
Max.
--
Unit V V A
0.8 1 1 1 1 1 1
-1.2 -225 --
Input LOW Current (I/O pins)(5) High Impedance Output Current (3-State Output pins) (5) Clamp Diode Voltage Short Circuit Current Input Hysteresis Quiescent Power Supply Current
A V mA mV A
100 5
VCC = Max., VIN = GND or VCC
500
2916 lnk 07
OUTPUT DRIVE CHARACTERISTICS FOR FCT162511T
Symbol IODL IODH IOFF VOH VOL Parameter Output LOW (I/O pins) Current (Open Drain) VCC = 5V, VIN = VIH or VIL, VOUT = VCC = 0, VO 5.5V VCC = Min. VIN = VIH or VIL VCC = Min. VIN = VIH or VIL IOH = -16mA MIL. IOH = -24mA COM'L. IOL = 16mA MIL. IOL = 24mA COM'L. IOL = 48mA MIL. IOL = 64mA COM'L. 1.5V (3) Output HIGH Current (I/O pins) Output Power Off Leakage Current (Open Drain)(5) Output HIGH Voltage (I/O pins) Output LOW Voltage (I/O pins) (Open Drain) Test Conditions(1) VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V (3) Min. 60 -- -60 -- 2.4 -- -- Typ.(2) 115 250 -115 -- 3.3 0.3 0.3 Max. 200 -- -200 1 -- 0.55 0.55 Unit
mA mA mA A V V V
2916 tbl 08
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. Duration of the condition can not exceed one second. 5. The test limit for this parameter is 5A at TA = -55C.
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IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Test Conditions(1) VCC = Max. VIN = 3.4V(3) All other Input Pins Parity Input Pins (PAx, PBx) VIN = VCC VIN = GND Min. -- -- -- Typ.(2) 0.5 1.0 75 Max. 1.5 2.5 120 Unit mA A/ MHz
OEAB = GND, OEBA = VCC
One Input Toggling 50% Duty Cycle VCC = Max., Outputs Open fCP = 10MHz (CLKAB) 50% Duty Cycle OEAB = GND, OEBA = VCC LEAB = GND One Bit Toggling fi = 5MHz 50% Duty Cycle VCC = Max., Outputs Open fCP = 10MHz (CLKAB) 50% Duty Cycle OEAB = GND, OEBA = VCC LEAB = GND Eighteen Bits Toggling fi = 2.5MHz 50% Duty Cycle
VCC = Max., Outputs Open
IC
Total Power Supply Current(6)
VIN = VCC VIN = GND
--
0.8
1.7
mA
VIN = 3.4V VIN = GND
--
1.3
3.2
VIN = VCC VIN = GND
--
3.8
6.5(5)
VIN = 3.4V VIN = GND
--
9.0
21.8(5)
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi
2916 tbl 09
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IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE (PROPAGATION DELAYS)
FCT162511AT Com'l. Symbol Parameter Condition(1) Min.(2) Max. Mil. Min.(2) Max. FCT162511CT Com'l. Min.(2) Max. Mil. Min.(2) Max. Unit
tPLH tPHL tPLH tPHL tPLH(3) tPHL tPLH(3) tPHL tPLH tPHL tPLH(3) tPHL tPLH tPHL tPLH(3) tPHL tPZH tPZL tPHZ tPLZ tPLZ(3) tPZL tPLH(3) tPHL tPLH tPHL
Propagation Delay, PAx to PBx CL = 50pF Ax to Bx or Bx to Ax, PBx to PAx RL = 500 Propagation Delay GEN/CHK LOW Ax to PBx Propagation Delay Ax to PERB, PAx to PERB Propagation Delay Bx to PERA, PBx to PERA Propagation Delay LEBA to Ax and PAx LEAB to Bx and PBx Propagation Delay LEBA to PERA, LEAB to PERB Propagation Delay CLKBA to Ax and PAx CLKAB to Bx and PBx Propagation Delay CLKBA to PERA CLKAB to PERB Output Enable Time OEBA to Ax and PAx OEAB to BX and PBx Output Disable Time OEBA to Ax and PAx OEAB to Bx and PBx Parity ERROR Enable OEBA to PERA, OEAB to PERB ODD/EVEN to PERx ODD/EVEN to PBx
1.5 1.5 1.5 1.5 1.5 1.5 1.5
5.0 7.5 9.0 8.0 9.0 8.0 5.6
1.5 1.5 1.5 1.5 1.5 1.5 1.5
5.3 8.0 9.0 8.0 9.0 8.0 6.0
1.5 1.5 1.5 1.5 1.5 1.5 1.5
4.2 6.5 7.5 6.5 7.5 6.5 5.3
1.5 1.5 1.5 1.5 1.5 1.5 1.5
4.5 6.8 7.8 6.8 7.8 6.8 5.5
ns ns ns ns ns
1.5 1.5 1.5
7.0 6.0 5.6
1.5 1.5 1.5
7.0 6.0 6.0
1.5 1.5 1.5
6.0 5.0 5.3
1.5 1.5 1.5
6.3 5.3 5.5
ns ns
1.5 1.5 1.5
7.0 6.0 6.0
1.5 1.5 1.5
7.0 6.0 6.5
1.5 1.5 1.5
6.0 5.0 5.6
1.5 1.5 1.5
6.3 5.3 5.8
ns
ns
1.5
5.6
1.5
6.0
1.5
5.2
1.5
5.5
ns
1.5 1.5 1.5 1.5 1.5
6.0 6.0 10.0 10.0 10.0
1.5 1.5 1.5 1.5 1.5
6.3 6.3 10.0 10.0 10.0
1.5 1.5 1.5 1.5 1.5
6.0 6.0 10.0 10.0 10.0
1.5 1.5 1.5 1.5 1.5
6.3 6.3 10.0 10.0 10.0
ns ns ns
2916 tbl 10
NOTES: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. On Open Drain Outputs tPLH is measured at VOUT = VOL + 0.3V.
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IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE (SET UP TIMES)
FCT162511AT Com'l. Symbol Parameter Mil. Min. Max. FCT162511CT Com'l. Min. Max. Mil. Min. Max. Unit
tSU
Set-up Time HIGH or LOW Ax to CLKAB
GEN/CHK LOW
Test Conditions(1,3)
Min.
Max.
PBx valid PBx not valid
CL = 50pF RL = 500
4 3 4 3 4 3 4 3 3.5 3 3.5 3 3.5 3 3.5 3 3.5 3 3.5 3 3.5 3 3.5 3 --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.5
4 3 4 3 4 3 4 4 3.5 3 3.5 3 3.5 3 3.5 3 3.5 3 3.5 3 3.5 3 3.5 3 --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.5
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.5
3.5 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
GEN/CHK HIGH GEN/CHK HIGH
tSU tSU
Set-up Time PAx to CLKAB Set-up Time Bx to CLKBA, PBx to CLKBA Set-up Time Ax to LEAB
PERB valid PERB not valid PERB valid PERB not valid PERA valid PERA not valid
PBx valid PBx not valid
tSU
CLKAB LOW
GEN/CHK LOW
CLKAB LOW
GEN/CHK HIGH
CLKAB HIGH
PERB valid PERB not valid
PBx valid PBx not valid
GEN/CHK LOW
CLKAB HIGH
GEN/CHK HIGH
tSU Set-up Time PAx to LEAB CLKAB LOW
GEN/CHK HIGH
CLKAB HIGH
GEN/CHK HIGH
tSU Set-up Time Bx to LEBA PBx to LEBA tSK(O) Output Skew (4) CLKBA HIGH CLKBA LOW
PERB valid PERB not valid PERB valid PERB not valid PERB valid PERB not valid PERA valid PERA not valid PERA valid PERA not valid
2916 tbl 11
SWITCHING CHARACTERISTICS OVER OPERATING RANGE (HOLD TIMES)
FCT162511AT Com'l. Symbol Parameter Condition(1) Min. Max. Mil. Min. Max. FCT162511CT Com'l. Min. Max. Mil. Min. Max. Unit
tH tH tH tH tH tW tW
Hold Time HIGH or LOW Ax to LEAB, Bx to LEBA Hold Time HIGH or LOW PAx to LEAB Hold Time HIGH or LOW PBx to LEBA Hold Time Ax to CLKAB, PAx to CLKAB Hold Time Bx to CLKBA, PBx to CLKBA LEAB or LEBA Pulse Width HIGH (2) LOW(2) CLKAB or CLKBA Pulse Width HIGH or
CL = 50pF RL = 500
1 1 1 1 1 3 3
-- -- -- -- -- -- --
1 1 1 1 1 3 3
-- -- -- -- -- -- --
1 1 1 0 0 3 3
-- -- -- -- -- -- --
1 1 1 0 0 3 3
-- -- -- -- -- -- --
ns ns ns ns ns ns ns
2916 tbl 12 NOTES: 1. See test circuits and waveforms. 2. This parameter is guaranteed but not tested. 3. "Not valid" means the set-up time indicated is not sufficient to assure proper functioning of this output; however, the set-up time indicated will assure proper functioning of the A to B or B to A port respective to the indicated direction. 4. Skew between any two outputs of the same package, switching in the same direction, excluding PERx in clocked mode, and Pxx (parity bits) and PERx in transparent/latched mode. This parameter is guaranteed by design.
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IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS
V CC 500 VIN Pulse Generator RT D.U.T. 50pF CL
2916 drw 05
SWITCH POSITION
7.0V
Test Open Drain Disable Low Enable Low All Other Tests
Switch
Closed
VOUT
Open
500
2916 lnk 13 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tSU
tH
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
2916 drw 06
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
1.5V
tREM
1.5V
tSU
tH
2916 drw 07
PROPAGATION DELAY
3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V
2916 drw 08
ENABLE AND DISABLE TIMES
ENABLE DISABLE 3V 1.5V 0V 3.5V 0.3V tPHZ 0.3V 1.5V 0V VOH 0V
2916 drw 09
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
CONTROL INPUT tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED tPZH SWITCH OPEN 3.5V 1.5V tPLZ
VOL
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns
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IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT FCT XXXX X Device Temperature Type Range X Package X Process
Blank B PV PA PF E 162511AT 162511CT 54 74
Commercial MIL-STD-883, Class B Shrink Small Outline Package (SO56-1) Thin Shrink Small Outline Package (SO56-2) Thin Very Small Outline Package (SO56-3) CERPACK (E56-1) 16-Bit Registered Transceiver with Parity
-55C to +125C -40C to +85C
2916 drw 10
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