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Data Sheet November 2001
LCK4950 Low-Voltage PLL Clock Driver
Features
s s s s s
Fully integrated phase-locked loop (PLL) Oscillator or crystal reference input Output frequency up to 180 MHz Outputs disable in high impedance Compatible with PowerPC(R), Intel (R), and highperformance RISC microprocessors TQFP packaging Output frequency configurable 35 ps typical cycle-to-cycle jitter Pin compatible with the Motorola(R) MPC950 clock driver
To provide input reference clock flexibility, two selectable division ratios are available on the LCK4950. The internal VCO runs at either 2x or 4x the high-speed output. The FBSEL pin is used to select between a divide by 8 or a divide by 16 of the VCO frequency to be compared with the input reference. These selections allow the input reference to be either one-half, one-fourth, or one-eighth of the high-speed output. The LCK4950 is capable of scan clock distribution or system diagnostics due to an external test clock input. The REF_SEL pin allows the selection between a crystal input to an on-chip oscillator for the reference or selection of a TTL level oscillator input directly. Only a parallel resonant crystal is required for the onboard crystal oscillator external components. The LCK4950 is fully 3.3 V compatible and requires no external loop filter components. All inputs accept LVCMOS or LVTTL compatible levels while the outputs provide LVCMOS levels with the capability to drive terminated 50 transmission lines. The LCK4950 can drive two traces, giving the device an effective fan out of 1:18 for series-terminated 50 lines. For optimum performance and board density, the device is packaged in a 7 mm x 7 mm 32-lead TQFP package.
s s s s
Description
The LCK4950 is a PLL-based clock driver device intended for high-performance clock tree designs. The LCK4950 is 3.3 V compatible with output frequencies of up to 180 MHz and output skews of 200 ps. The LCK4950 can accommodate the most demanding tree designs by employing a fully differential PLL design. This minimizes cycle-to-cycle jitter, which is critical when the device is acting as the reference clock for PLLs in today's microprocessors and ASICs. The device has nine low-skew configurable outputs for support of the clocking needs of the various high-performance microprocessors.
LCK4950 Low-Voltage PLL Clock Driver
Data Sheet November 2001
Description (continued)
fsela PLL_En Tclk Ref_Sel /2//4
PHASE DETECTOR xtal1 xtal2 xtal OSC LPF /8//16 (PULL-DOWN) FBsel fselb
(VCO) 200 MHz--480 MHz
Qa
/4//8
Qb
/4//8
Qc0 Qc1
fselc MR/OE POWER-ON RESET /4//8 Qd0 Qd1 fseld Qd2 Qd3 Qd4
5-9698 (F)
Figure 1. Logic Diagram
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Agere Systems Inc.
Data Sheet November 2001
LCK4950 Low-Voltage PLL Clock Driver
Pin Information
Qd0 Qd1 18 Qc0 Qc1 VDD VDD VSS VSS 17 16 15 14 13 LCK4950 VSS TCLK PLL_En Ref_Sel 29 30 31 32 1 2 3 4 5 6 7 8 12 11 10 9 Qd4 VDD MR/OE xtal2
24
23
22
21
20
VSS Qb VDD Qa
25 26 27 28
19
Qd2 VDD Qd3 VSS
fsela
fselb
fseld
FBsel
VDDA
xtal1
fselc
VSS
5-9699 (F)
Figure 2. Pin Diagram
Functional Description
Table 1. Function Tables Ref_Sel 1 0 PLL_En 1 0 FBsel 1 0 MR/OE 1 0 fseln 1 0 Function TCLK XTAL_OSC Function PLL Enabled PLL Bypass Function /8 /16 Function Outputs Disabled Outputs Enabled Function Qa = /4; Qb:d = /8 Qa = /2; Qb:d = /4
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LCK4950 Low-Voltage PLL Clock Driver
Data Sheet November 2001
Functional Description (continued)
Table 2. Function Table Inputs fsela 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 fselb 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 fselc 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 fseld 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Qa(1) 2x 2x 2x 2x 2x 2x 2x 2x x x x x x x x x Outputs Qb(1) x x x x x/2 x/2 x/2 x/2 x x x x x/2 x/2 x/2 x/2 Qc(2) x x x/2 x/2 x x x/2 x/2 x x x/2 x/2 x x x/2 x/2 Qd(5) x x/2 x x/2 x x/2 x x/2 x x/2 x x/2 x x/2 x x/2 Total 2x 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Totals Total x 8 3 6 1 7 2 3 0 9 4 7 2 8 3 6 1 Total x/2 0 5 2 7 1 6 5 8 0 5 2 7 1 6 3 8
Note: x = fVCO/4; 200 MHz < fVCO < 480 MHz.
Table 3. PLL Input Reference Characteristics Characteristic TCLK Input Rise/Falls Reference Input Frequency Crystal Oscillator Frequency Reference Input Duty Cycle Symbol tr, tf fref fXtal frefdc Min -- --* 12.5 25 Max 3.0 --* 25 75 Unit ns MHz MHz %
* Maximum and minimum input reference is limited by the VCO lock range and the feedback divider for the TCLK or xtal1 inputs. See the Applications section for more crystal information.
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Agere Systems Inc.
Data Sheet November 2001
LCK4950 Low-Voltage PLL Clock Driver
Applications
Programming the LCK4950S
Several frequency relationships are configurable by the LCK4950. Frequency ratios of 1:1, 2:1, 4:1, and 4:2:1 are possible from configuring the output dividers for the four output groups. To ensure that the output duty cycle is always 50%, the LCK4950 uses even dividers. Table 4 illustrates output configurations of the LCK4950, describing the outputs using the VCO frequency as a reference. For example, setting the Qa outputs to VCO/2, the Qb and Qc to VCO/4, and the Qd to VCO/8 would provide the output frequency relationship of 4:2:1. Table 4. Programmable Output Frequency Relationships Inputs FSELA 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FSELB 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FSELC 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FSELD 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Qa VCO/2 VCO/2 VCO/2 VCO/2 VCO/2 VCO/2 VCO/2 VCO/2 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 Qb VCO/4 VCO/4 VCO/4 VCO/4 VCO/8 VCO/8 VCO/8 VCO/8 VCO/4 VCO/4 VCO/4 VCO/4 VCO/8 VCO/8 VCO/8 VCO/8 Outputs Qc VCO/4 VCO/4 VCO/8 VCO/8 VCO/4 VCO/4 VCO/8 VCO/8 VCO/4 VCO/4 VCO/8 VCO/8 VCO/4 VCO/4 VCO/8 VCO/8 Qd VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8
The division settings establish the output relationship, but one must still ensure that the VCO will be stable given the frequency of the outputs desired. The feedback frequency should be used to situate the VCO into a frequency range in which the PLL will be stable. The design of the PLL is such that for output frequencies between 25 MHz and 180 MHz, the LCK4950 can generally be configured into a stable region.
Agere Systems Inc.
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LCK4950 Low-Voltage PLL Clock Driver
Data Sheet November 2001
Applications (continued)
Table 5. Input Reference vs. Output Frequency Relationships Config 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 fsela 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 fselb 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 fselc 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 fseld Qa 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 4x 4x 4x 4x 4x 4x 4x 4x 2x 2x 2x 2x 2x 2x 2x 2x FB_Sel = 1 Qb 2x 2x 2x 2x x x x x 2x 2x 2x 2x x x x x Qc 2x 2x x x 2x 2x x x 2x 2x x x 2x 2x x x Qd 2x x 2x x 2x x 2x x 2x x 2x x 2x x 2x x Qa 8x 8x 8x 8x 8x 8x 8x 8x 4x 4x 4x 4x 4x 4x 4x 4x FB_Sel = 0 Qb 4x 4x 4x 4x 2x 2x 2x 2x 4x 4x 4x 4x 2x 2x 2x 2x Qc 4x 4x 2x 2x 4x 4x 2x 2x 4x 4x 2x 2x 4x 4x 2x 2x Qd 4x 2x 4x 2x 4x 2x 4x 2x 4x 2x 4x 2x 4x 2x 4x 2x
The relationship between the input reference and the output frequency is very flexible. Table 5 shows the multiplication factors between the inputs and outputs for the LCK4950. Figure 3 through Figure 6 illustrate several programming possibilities. Note: The variations of the configurations shown are not complete, but do represent potential applications.
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Agere Systems Inc.
Data Sheet November 2001
LCK4950 Low-Voltage PLL Clock Driver
Applications (continued)
1 1 1 0 0
fsela fselb fselc fseld FBsel
Qa
1
66.66 MHz
1 1
fsela fselb fselc fseld FBsel
Qa
1
66.66 MHz
Qb
1
33.33 MHz
1 0
Qb
1
33.33 MHz
Qc
2
33.33 MHz
0
Qc
2
33.33 MHz
16.66 MHz
INPUT REF
Qd
5
66.66 MHz
16.66 MHz
INPUT REF
Qd
5
33.33 MHz
5-9700 (F)
5-9702 (F)
Figure 3. Dual-Frequency Configuration
Figure 5. Dual-Frequency Configuration
1 0 0 1 1
fsela fselb fselc fseld FBsel
Qa
1
66.66 MHz
0 0
fsela fselb fselc fseld FBsel
Qa
1
160 MHz
Qb
1
66.66 MHz
1 1
Qb
1
80 MHz
Qc
2
66.66 MHz
0
Qc
2
40 MHz
33.33 MHz
INPUT REF
Qd
5
33.33 MHz
20 MHz
INPUT REF
Qd
5
40 MHz
5-9701 (F)
5-9703 (F)
Figure 4. Dual-Frequency Configuration
Figure 6. Triple-Frequency Configuration
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Table 6. Absolute Maximum Ratings Parameter Supply Voltage Input Voltage Input Current Storage Temperature Range Symbol VDD, VDDA VI IIN TStor Min -0.3 -0.3 -- -40 Max 4.6 VDD + 0.3 20 125 Unit V V mA C
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LCK4950 Low-Voltage PLL Clock Driver
Data Sheet November 2001
Electrical Characteristics
Table 7. dc Characteristics TA = 0 C to 70 C, VCC = 3.3 V 5%. Characteristic Input High Voltage (LVCMOS inputs) Input Low Voltage (LVCMOS inputs) Output High Voltage Output Low Voltage Input Current Input Capacitance Power Dissipation Capacitance Maximum Quiescent Supply Current Non-PLL Maximum PLL Supply Current Symbol VIH VIL VOH VOL IIN CIN Cpd IDDQ IDDPLL Min 2.0 -- 2.4 -- -- -- -- -- -- Typ -- -- -- -- -- -- 25 -- -- Max 3.6 0.8 -- 0.5 120 4 -- 1 55 Unit V V V V A pF pF mA mA Condition -- -- IOH = -40 mA1 IOL = 40 mA1 -- -- Per Output All VDD Pins Except VDDA2 VDDA Pin Only
1. The LCK4950 outputs can drive series or parallel-terminated 50 (or 50 to VCC/2) transmission lines on the incident edge. 2. Total power = (IDDPLL + IDDQ) x V + (fQaCQa + fQbCQb + fQc0CQc0 + fQc1CQc1 + fQd0CQd0 + fQd1CQd1 + fQd2CQd2 + fQd3CQd3 + fQd4CQd4) x V2; where V = VDD, CQa = load capacitance on Qa, CQb = load capacitance on Qb, etc.
Table 8. ac Characteristics TA = 0 C to 70 C, VCC = 3.3 V 5%. Characteristic Output Rise/Fall Time Output Duty Cycle Same Frequencies Output-to-Output Skews Different Frequencies: Qafmax < 150 MHz Qafmax > 150 MHz PLL VCO (feedback = VCO/4) Lock (feedback = VCO/8) Range (feedback = VCO/16) Maximum Output Frequency: Qa(/2) Qa/Qb (/4) Qb (/8) Output Disable Time Output Enable Time Cycle-to-Cycle Jitter (peak-to-peak) Maximum PLL Clock Time
1.See Applications section for more information.
Symbol tr, tf tpw tsk(0)
Min 0.10 48.5 -- -- -- 200 200 200 -- -- -- -- -- -- --
Typ -- -- 150 200 -- -- -- -- -- -- -- -- -- 35 --
Max 1.0 52.5 300 400 400 480 480 480 180 120 60 7 6 50 10
Unit ns % ps ps ps MHz MHz MHz MHz MHz MHz ns ns ps ms
Condition 0.8 V to 2.0 V -- -- -- -- -- -- -- -- -- -- -- -- --1 --
fVCO
fmax
tPLZ,HZ tPZL tjitter tlock
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Agere Systems Inc.
Data Sheet November 2001
LCK4950 Low-Voltage PLL Clock Driver
Electrical Characteristics (continued)
Jitter Performance of the LCK4950S
More focus is given to clock distribution design and management today because of the continuing increase of today's digital system's clock rates. System-clock jitter and its effect on overall system timing budget is at the center of this focus. The LCK4950 is designed to utilize a differential CMOS PLL and incorporate multiple power and ground pins in the design to minimize clock jitter. The following text provides details on the jitter performance, illustrates measurement limitations, and provides guidelines to minimize the jitter of the LCK4950. The most commonly specified jitter parameter is cycle-to-cycle jitter. With today's high-performance measurement equipment, there is no way to measure this parameter for jitter performance in the class demonstrated by the LCK4950. As a result, different methods are used which approximate cycle-to-cycle jitter. The typical method of measuring the jitter is to accumulate a large number of cycles, create a histogram of the edge placements, and record peak-to-peak as well as standard deviations of the jitter. It is of great importance to measure the edge immediately following the trigger edge. If this is not the case, the measurement inaccuracy will add significantly to the measured jitter. The oscilloscope cannot collect adjacent pulses. It is safe to assume that collecting pulse information in this mode will produce jitter values somewhat larger than if consecutive cycles were measured; therefore, this measurement will represent an upper bound of cycle-to-cycle jitter. Most likely, this is a conservative estimate of the cycle-to-cycle jitter. There are two common sources of jitter for a PLL-based clock driver. The most common source of jitter is random jitter. Less commonly known is the jitter produced by different frequency outputs switching synchronously. If all of the outputs are switching at the same frequency, the PLL jitter is equal to the total jitter of the device. In the LCK4950, where a number of the outputs can be switching synchronously but at different frequencies, a multimodal jitter distribution can be seen on the highest frequency outputs. It is important to consider what is happening on the other outputs because the output being monitored is affected by the activity on the other outputs. From Figure 7, one can see that for each rising edge on the higher-frequency signal, the activity on the lowerfrequency signal is not consistent. The placement of the edge that is being monitored is displaced in time due to the activity on the other outputs altering the internal thresholds of the device. The relationship is periodic because the signals are synchronous. The resulting jitter is a superposition of the PLL jitter on the displaced edges. The multimodal distribution will appear to be a fat Gaussian distribution, or a truly multimodal distribution depending on the size of the PLL jitter and displacement of the edges. When all the outputs are switching at the same frequency, there is no edge displacement and the jitter is that of the PLL.
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LCK4950 Low-Voltage PLL Clock Driver
Data Sheet November 2001
Electrical Characteristics (continued)
1 2 1 2
1
2
PEAK-TO-PEAK PLL JITTER PEAK-TO-PEAK PERIOD JITTER
1
2
3
2
1
2
3
1
2
3
PEAK-TO-PEAK PLL JITTER PEAK-TO-PEAK PERIOD JITTER
5-9704 (F)
Figure 7. PLL Jitter and Edge Displacement
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Agere Systems Inc.
Data Sheet November 2001
LCK4950 Low-Voltage PLL Clock Driver
Power Supply Filtering
The LCK4950 exhibits some sensitivities that would not be seen on a fully digital product because the LCK4950 is a mixed analog/digital product. Analog circuitry is naturally sensitive to random noise, most noticeably when the noise is in the power supply pins. The LCK4950 provides a separate output buffer power supply (VDD) and phase-locked loop (VDDA) power supply pins. This design isolates the high switching noise digital outputs from the sensitive internal analog phase-locked loop. In a controlled setup (i.e., an evaluation board), this amount of isolation will suffice. In a digital system, where it is much more difficult to minimize noise on the power supplies, an additional level of isolation may be required. The easiest means of accomplishing this is by applying a power supply filter on the VDDA pin for the LCK4950. Figure 8 illustrates a typical power supply filter scheme for the LCK4950. The device is most greatly affected by spectral content in the 1 kHz to 1 MHz range, and therefore needs a filter to target this range. The most important aspect of this final filter design is the dc voltage drop between the VDD supply and VDDA pin. The IDDPLL current (current forced through the VDDA pin) is normally 45 mA (55 mA maximum), assuming that a minimum of 3.0 V must be maintained on the VDDA pin. Very little voltage drop can be tolerated when a 3.3 V VDD supply is used. The resistor shown in Figure 10 must have a resistance of 5 --10 to meet the voltage drop criteria. The RC filter shown provides a broadband filter with about 100:1 attenuation for noise, with a spectral content above 20 kHz. As the noise frequency crosses the series resonant point of an individual capacitor, its overall impedance begins to look inductive and therefore increases with increasing frequency. The parallel capacitor circuit shown in Figure 11 guarantees that a low- impedance path to ground exists for frequencies exceeding the bandwidth of the PLL. It is recommended that the user start with an 8 --10 resistor to avoid potential VDD drop problems and only use higher-value resistors when a higher level of attenuation is needed. The LCK4950 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL). Still, there may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noiserelated problems in most designs.
Electrical Characteristics (continued)
3.3 V
RS = 5 --10 PLL_VCC 0.01 F LCK4950 VCC 0.01 F 22 F
5-9707 (F)
Figure 8. Power Supply Filter PLL jitter can be measured for configurations where the outputs are switching at different frequencies by triggering the lowest-frequency output. PLL jitter is dependent on internal VCO frequency more so than output configuration. There are some general guidelines that will minimize the output jitter of the device. First, always configure the device so the VCO runs as fast as possible. This is the most important aspect in minimizing jitter of the LCK4950. Second, maintain the reference frequency at the highest possible frequency. These more frequent phase detector updates help to reduce jitter. There is a trade-off between higher reference frequencies and higher VCO frequency; always choose a higher VCO frequency to reduce jitter. Third, and the most difficult to follow, minimize the number of different frequencies sourced from a single chip. The fixed edge displacement associated with the switching noise, in most cases, nearly doubles the effective jitter of a highspeed output.
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LCK4950 Low-Voltage PLL Clock Driver
Data Sheet November 2001
Electrical Characteristics (continued)
Using the On-Chip Crystal Oscillator
The LCK4950 features an on-chip crystal oscillator buffer to allow for seed clock generation as well as final distribution. The only external component required is the crystal since the on-chip oscillator buffer is completely self-contained. The user is advised to mount the crystal as close to the LCK4950 as possible to avoid board-level parasitics since the oscillator is, to a degree, sensitive to loading at the inputs. To facilitate collocation, surfacemount crystals are recommended, but not required. The oscillator circuit is a parallel resonant circuit with on-chip shunt capacitors. A parallel resonant crystal is simply a crystal that has been characterized in its parallel resonant mode. Therefore, in the majority of cases, a parallel specified crystal or a series resonant crystal can be used with the LCK4950 with just a minor frequency error. Typically, a series crystal used in a parallel resonant mode will exhibit an oscillatory frequency a few hundred ppm different than the specified value. For most processor implementations, a few hundred ppm translates into kHz inaccuracies, a small enough level not to represent a major issue. The LCK4950 is a clock driver that was designed to generate outputs with programmable frequency relationships. As a result, the crystal input frequency is a function of the desired output frequency. To determine the crystal required to produce the desired output frequency for an application that utilizes internal feedback, the PLL block diagram (Figure 9) should be used. The P and the M values for the LCK4950 are also included in Figure 9. The M values can be found in Table 1 on page 3. Table 9. Crystal Specifications Parameter Crystal Cut Resonance Frequency Tolerance Frequency/Temperature Stability Operating Range Shunt Capacitors Equivalent Series Resistance (ESR) Correction Drive Level Aging Value Fundamental AT Cut Parallel Resonance 75 ppm at 25 C 150 ppm at 0 C to 70 C 0 C to 70 C 10 pF--40 pF 50 to 80 Max 100 W 5 ppm/yr (first three years)
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Data Sheet November 2001
LCK4950 Low-Voltage PLL Clock Driver
Electrical Characteristics (continued)
fref PHASE DETECTOR LPF
VCO
/P
/N
Qn
/m
5-9708 (F)
Figure 9. PLL Block Diagram Note: For computations refer to the following equations:
fVCO f = ------------- , fvco = fQ m fref = ----------------------------m = 8 (FBsel = 1), 16(FBsel = 0), P = 1 For the LCK4950 clock driver, the following will provide an example of how to determine the crystal frequency required for a given design. Given: Qa = 160 MHz Qb = 80 MHz Qc = 40 MHz Qd = 40 MHz FBSel = 0
fQn * N * P m
fQn * N * P fref = ----------------------------m
From Figure 3: fQd = VCO/8 then N = 8 or fQa = VCO/2 then N = 2 From Figure 9: m = 16 and P = 1
(eq. 1)
40 * 8 * 1 tref = ------------------------ = 20 MHz 16
or
160 * 2 * 1 tref = --------------------------- = 20 MHz 16 Agere Systems Inc. 13
LCK4950 Low-Voltage PLL Clock Driver
Data Sheet November 2001
Electrical Characteristics (continued)
Driving Transmission Lines
The LCK4950 clock driver was designed to drive high-speed signals in a terminated transmission line environment. The output drivers were designed to exhibit the lowest impedance possible to provide the optimum flexibility to the user. With an output impedance of less than 10 , the drivers can drive either parallel-terminated or seriesterminated transmission lines. Point-to-point distribution of signals is the method of choice in most high-performance clock networks. In a point-topoint scheme, either series-terminated or parallel-terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VDD/2. Only a single terminated line can be driven by each output of the LCK4950 clock driver because this technique draws a fairly high level of dc current. For the series driven case, however, there is no dc current draw and the outputs can drive multiple seriesterminated lines. Figure 10 illustrates an output driving a single series-terminated line.
OUTPUT BUFFER IN 7 RS = 43 ZO = 50 OutA
5-9709 (F)
Figure 10. Single Transmission Line The situation in Figure 11 should be used to better match the impedances when driving multiple lines. In this case, the series-terminating resistors are reduced so when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched.
RS = 36 OUTPUT BUFFER 7 RS = 36
ZO = 50
ZO = 50
5-9710 (F)
Figure 11. Optimized Dual Line Termination
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Agere Systems Inc.
Data Sheet November 2001
LCK4950 Low-Voltage PLL Clock Driver
Outline Diagram
Dimensions are in millimeters.
9.00 0.20 7.00 0.20 PIN #1 IDENTIFIER ZONE
32 25
1.00 REF
0.25 GAGE PLANE
1 24
SEATING PLANE 0.45/0.75 7.00 0.20 9.00 0.20
DETAIL A
8
17
9
16
0.09/0.200
DETAIL A
DETAIL B 1.40 0.05
0.30/0.45 0.20
M
1.60 MAX SEATING PLANE 0.10 0.80 TYP 0.05/0.15
DETAIL B
12-3076(F)
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PowerPC is a registered trademark of International Business Machines Corporation. Intel is a registered trademark of Intel Corporation. Motorola is a registerd trademark of Motorola, Inc.
For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
Copyright (c) 2001 Agere Systems Inc. All Rights Reserved
November 2001 DS02-033HSI (Replaces DS01-118ANET)

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