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RF AMP & SERVO SIGNAL PROCESSOR
S1L9225X
INTRODUCTION
As a pre-signal & servo signal processor for the DISC-MAN, S1L9225X is a low voltage, low consumption current IC that can read CD-RW, and CD-R discs and can be applied to various products, such as the CDP/VCD/CD-MP3 for the DISC-MAN. It is a hard-wired free-adjustment servo, which automatically controlled the control point of the pre-signal portion.
64-LQFP-1010
FEATURES
* * * * * * * * * * * * * * * * * * * * * * RF amplifier (CD, CD-R, CD-RW applicable) Gain setting & monitoring for the CD-R, CD-RW DISC Focus error amp & Febias adjustment Tracking error amp & balance, gain adjustment FOK, defect, mirror detect Center voltage amplifier APC (Automatic Power Control) APC laser controller (Controlled by Tracking Summing Signal) RF AGC & EQ control (AGC Level Control Compatible) Enhanced EFM slice (Double Asymmetry Method) Focus servo loop & offset adjustment Tracking servo loop & offset adjustment Sled servo loop Spindle servo loop Auto-sequence Fast search mode (1 - 36000 track jump) Interruption countermeasure Focus & Tracking servo muting controlled by EFM duty check RF peaking prevention system by EFM duty check Focus, tracking, spindle loop pole move option Operating voltage 2.7V 3.3V Power saving mode
LPC Control used by side beam signal, it related to pick-up assurance. When used pick-up, the specification is present extra.
ORDERING INFORMATION
Device S1L9225X01Q0R0 Package 64-LQFP-1414 Supply Voltage 2.7V 3.3V Operating Temperature -20C +75C
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S1L9225X
RF AMP & SERVO SIGNAL PROCESSOR
BLOCK DIAGRAM
60 TESO
61 RFM2
55 VREF
57 EQC
62 RFM
63 RFO
56 VCC
52 PDD
50 PDC
54 PDE
51 PDB
EQO EFMI DCC1 DCC2 MCP DCB VSSA/GND FRSH FSET
1 2 3 4 5 6 7 8 9
RF AGC & EQ Control Focus OK Detect Defect Detect Mirror Gen Focus Servo Loop - Gain & Phase Compensation - Focus Search - Offset Adjust - FZC Gen.
Center Voltage
Tracking Error (RW) I/V AMP
49 PDA
53 PDF
59 LPC
58 LPB
64 EQI
RF & Focus Error (CD-RW) I/V AMP
48 PD 47 LD 46 LPFT2 45 LPFT1 44 TEIO 43 TZC 42 ATSC 41 TEO 40 TEM
APC. Laser Control & LPC
Tracking Servo Loop - Gain & Phase Compensation - Track Jump - Offset Adjust - TZC Gen.
FLB 10 FGD 11 FDFCT 12 FSE0 13 FSI 14 ATSCO 15 TGU 16 VDDA 17 Micom Data Interface Logic Decoder
Hardware Logic - Auto-Sequencer - Fast Search - Febias, Focus Servo, Tracking Offset ADJ. - Tracking Balance & Gain Adjust - Interruption Detect - EFM Muting System
39 SLP Sled Servo & Kick Gen 38 SLO 37 SLM 36 FEO 35 FEM Spindle Servo LPF 34 SPDLO 33 SPDLM
EFM Comparator CLVI 25 LOCK 26 ASY 27 EFM2 28 EFM 29 SSTOP 30
ISTAT2 18
ISTAT1 19
MCK 20
MDATA 21
MLT 22
RESET 23
WDCK 24
VSS 31
2
VDD 32
RF AMP & SERVO SIGNAL PROCESSOR
S1L9225X
APPLICATION DIAGRAM
100uF
103
1K 3.6uF 500 100
120K
683
3V
1uF
22
3V
10uF
150K 333 103 103 222
15K
39K 474 100K
103 56K
381
120K
47K
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 A C B D F E 33uF 683 2.2uF SPDLM LD TEIO TZC SPDLO PD LPFT2 LPFT1 SLO SLM TEO ATSC TEM FEO SLP FEM
49 50 51 52 53 54 55 56 57 58 59
PDA PDC PDB PDD PDF PDE VREF VCC EQC LPB LPC TESO RFM2 RFM
VDD VSS SSTOP EFM EFM2 ASY LOCK CLVI
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 From DSP From Micom From Micom From Micom From Micom To Micom To Micom
103 474 10K
From_Pick-up To DSP
From DSP 333 474
20K 8.2K
SMDP SMDS FSW
S1L9225X
WDCK RESET MLT MDATA MCK ISTAT1
82pF 12pF 22K
8pF 153
60 61 62 63 64
ATSCO
FDFCT
EQI DCC1 DCC2 EFMI EQO MCP DCB
VSSA/GND
RFO
ISTAT2 VDDA TGU FSEO FRSH FSET FGD
FLB
1
821
2
3
333
4
5
6
7
8
9 10 11 12 13 14 15 16
103
103
4.7uF
104
104
102
FSI
47pF
104
104
1M
3
S1L9225X
RF AMP & SERVO SIGNAL PROCESSOR
PIN CONFIGURATION
60 TESO
61 RFM2
55 VREF
57 EQC
62 RFM
63 RFO
56 VCC
52 PDD
50 PDC
54 PDE
51 PDB
49 PDA
53 PDF
59 LPC
58 LPB
64 EQI
EQO EFMI DCC1 DCC2 MCP DCB VSSA/GND FRSH FSET
1 2 3 4 5 6 7 8 9
48 PD 47 LD 46 LPFT2 45 LPFT1 44 TEIO 43 TZC 42 ATSC 41 TEO 40 TEM 39 SLP 38 SLO 37 SLM 36 FEO 35 FEM 34 SPDLO 33 SPDLM VDDA 17 ISTAT2 18 ISTAT1 19 MCK 20 MDATA 21 MLT 22 RESET 23 WDCK 24 CLVI 25 LOCK 26 ASY 27 EFM2 28 EFM 29 SSTOP 30 VSS 31 VDD 32
S1L9225X
FLB 10 FGD 11 FDFCT 12 FSE0 13 FSI 14 ATSCO 15 TGU 16
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S1L9225X
PIN DESCRIPTION
Table 1. Pin Description Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Symbol EQO EFMI DCC1 DCC2 MCP DCB VSSA/GND FRSH FSET FLB FGD FDFCT FSEO FSI ATSCO TGU VDDA ISTAT2 ISTAT1 MCK MDATA MLT RESET WDCK CLVI LOCK ASY EFM2 EFM SSTOP VSS VDD I/O O I O I I I G I I I I I O I O I P O O I I I I I I I I O O I G P RF equalizer output EFM slice input. (input impedance 47K) Time constant connection output to detect defects Time constant connection input to detect defects CAP connection terminal for mirror hold CAP terminal to limit defect detection RF, servo ground CAP connection terminal for focus search Filter bias for focus, tracking, spindle CAP terminal to make focus loop rising low band Terminal to change the high frequency gain of the focus loop CAP connection terminal to integrate the focus error Focus error output Focus servo input Shock level detect output (shock: L: state) Time constant connection to change the high frequency gain of the tracking loop. Power supply for the servo Internal status output pin (FOK, TRCNT) Internal status output pin Micom clock pin Data input pin Data latch input pin Reset input pin 88.2kHz input terminal from DSP Control output input terminal of DSP spindle Sled run away prevention pin (L: sled off and tracking gain up) Auto asymmetry control input terminal Output for EFM pulse integration EFM output terminal for RFO slice (to DSP) PICK UP's maximum lead-in diameter position check pin Digital ground Digital power Description
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RF AMP & SERVO SIGNAL PROCESSOR
Table 1. Pin Description (Continued) Pin No 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Symbol SPDLM SPDLO FEM FEO SLM SLO SLP TEM TEO ATSC TZC TEIO LPFT1 LPFT2 LD PD PDA PDB PDC PDD PDF PDE VREF VCC EQC LPB LPC TESO RFM2 RFM RFO EQI I/O I O I O I O I I O I I B I I O I I I I I I I O P I I I O I I O I Spindle amp inverting input pin Spindle amp output pin Focus servo amp inverting input pin Focus servo amp output pin Sled servo inverting input Sled servo output Sled servo non inverting input Tracking servo amp inverting input pin Tracking servo amp output pin Anti-shock input pin Tracking zero crossing input pin Tracking error output & tracking servo input pin Tracking error integration input terminal 1 (automatic control) Tracking error integration input terminal 2 (automatic control) APC AMP output pin APC AMP input pin Photo-diode A/C RF I/V amp1 inverting input pin Photo-diode B/D RF I/V amp2 inverting input pin Photo-diode A/C RF I/V amp1 inverting input pin Photo-diode B/D RF I/V amp2 inverting input pin Photo-diode F with tracking (F) I/V amp inverting input pin Photo-diode E with tracking (E) I/V amp inverting input pin (VCC+GND)/2 voltage reference output pin RF part VCC power supply pin AGC_ equalize level control terminal and VCA input connection cap terminal Laser power level control resistance terminal Laser power control tracking summing signal integration terminal Tracking error summing signal RF summing amp 2x filter on/off RF summing amp inverting input terminal RF summing amp output terminal RFO dc control input terminal (use by MIRROR, FOK, AGC&EQ terminals) Description
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S1L9225X
MAXIMUM ABSOLUTE RATINGS
Item Power supply voltage Input supply voltage Operating temperature Storage temperature Symbol VDD VI TOPR TSTG Rating -0.3 5.5 -0.3 VDD + 0.3 -20 75 -40 125 Unit V V C C
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RF AMP & SERVO SIGNAL PROCESSOR
ELECTRICAL CHARACTERISTICS
Table 2. Electrical Characteristics
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Inspection Items Supply current 2.7V RF AMP offset voltage RF AMP oscillation voltage RF AMP voltage gain AC RF AMP voltage gain BD RF RHD characteristic RF AMP maximum output voltage RF AMP minimum output voltage RF CDRW gain AC1 RF CDRW gain AC2 RF CDRW gain AC3 RF CDRW gain BD1 RF CDRW gain BD2 RF CDRW gain BD3 RF IVSEL connection AC RF IVSEL connection BD RF AMP offset conversion 1 RF AMP offset conversion 2 Focus error offset voltage Focus error auto voltage ISTAT state after FEBIAS control Focus ERROR voltage gain 1 Focus ERROR voltage gain 2 Focus ERROR voltage gain difference Focus ERROR AC difference FERR maximum output voltage H FERR minimum output voltage L AGC max gain AGC EQ gain AGC normal gain AGC compress ratio AGC frequency Symbols ICCTY Vrfo Vrfosc Grfac Grfbd Rfthd Vrfh Vrfl GRWAC1 GRWAC2 GRWAC3 GRWBD1 GRWBD2 GRWBD3 RFSELAC RFSELBD Vrfoff1 Vrfoff2 VFEO1 VFEO2 VISTAT1 GFEAC GFEBD GFE VFEACP VFEPPH VFEPPL GAGC GEQ GAGC2 CAGC FAGC AGC_Equalize Focus Error Amplifier RF AMP Inspection Block 6 -85 0 16.2 16.2 2.35 5.5 11.0 18.0 5.5 11.0 18.0 24 24 0 -100 -525 -35 2.5 18 18 -3 0 2.3 16 0 3 0 -1.5 Spec 10 0 50 14.7 14.7 7.7 13.1 21.3 7.7 13.1 21.3 47 47 -100 -200 -250 0 21 21 0 50 19 1 6 2.5 0 14 +85 100 17.7 17.7 5 0.85 9.9 16.2 24.6 9.9 16.2 24.6 70 70 -200 -300 -50 +35 24 24 +3 100 0.4 22 2 9 5 2.5 Unit mA mV mV dB dB % V V k k mV mV mV mV V dB dB dB mV V V dB dB dB dB dB
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S1L9225X
Table 2. Electrical Characteristics (Continued)
No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 Inspection Items TERR sum voltage gain SF TERR sum voltage gain SE TERR sum voltage gain S2 TERR gain voltage gain 1 TERR gain voltage gain 2 TERR gain voltage gain 3 TERR gain voltage gain 4 TERR gain voltage gain 5 TERR gain voltage gain 6 TERR gain voltage gain 7 TERR balance gain TERR balance mode 1 TERR balance mode 2 TERR balance mode 3 TERR balance mode 4 TERR balance mode 5 TERR balance mode 6 TERR EF voltage gain difference TERR maximum output voltage H TERR maximum output voltage L APC PSUB voltage L APC PSUB voltage H APC PSUB LDOFF APC current drive H APC current drive L LPC RF differential 1 LPC RF differential 2 LPC TE differential MIRROR minimum operating frequency MIRROR maximum operating frequency MIRROR AM characteristic MIRROR minimum input voltage MIRROR maximum input voltage Symbols GTSF GTSE GTS2 GTEF1 GTEF2 GTEF3 GTEF4 GTEF5 GTEF6 GTEF7 GTEE TBE1 TBE2 TBE3 TBE4 TBE5 TBE6 GTEF VTPPH VTPPL APSL APSH APSLOF ACDH ACDL LPRF1 LPRF2 LPTE FMIRB FMIRP FMIRA VMIRL VMIRH MIRROR APC & Laser Control Inspection Block Tracking Error Amplifier 16.5 16.5 22.5 -1.5 1 1 1 1 1 1 10.5 1.0 1.0 1.0 1.0 1.0 1.0 10.0 2.0 2.0 2.2 1.35 0.4 0.4 0.4 30 1.8 Spec 19.5 19.5 25.5 0.5 1.7 1.3 1.45 1.55 1.45 1.45 13.5 1.05 1.05 1.05 1.25 1.20 1.3 13.0 0.5 0.5 0.5 550 75 400 0.1 22.5 22.5 28.5 2 2.4 1.6 1.9 2.1 1.9 1.9 16.5 1.1 1.1 1.1 1.5 1.4 1.75 16.0 0.7 1.0 1.35 0.6 0.6 0.6 900 600 0.2 Unit dB dB dB dB dB dB V V V V V V V V V V HZ kHz HZ V V
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RF AMP & SERVO SIGNAL PROCESSOR
Table 2. Electrical Characteristics (Continued)
No. 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 Inspection Items FOK threshold voltage FOK output voltage H FOK output voltage L FOK FEEQ. characteristic Defect bottom voltage Defect CUTOFF voltage Defect minimum input voltage Defect maximum input voltage Normal EFM duty voltage 1 Normal EFM duty symmetry Normal EFM duty voltage 3 Normal EFM duty voltage 4 Normal EFM minimum input voltage Normal EFM duty difference 1 Normal EFM duty difference 2 EFM2 duty voltage 1 EFM2 duty voltage 2 EFM2 duty symmetry EFM2 duty voltage 3 EFM2 duty voltage 4 EFM2 duty voltage 5 EFM2 duty voltage 6 EFM2 minimum input voltage FZC threshold voltage ANTI-shock detection H ANTI-shock detection L TZC threshold voltage SSTOP threshold voltage Tracking gain win T1 Tracking gain win T2 Tracking gain win I1 Tracking gain win l2 Tracking BAL win T1 Tracking BAL win T2 Symbols VFOKT VFOHH VFOKL FFOK FDFCTB FDFCTC VDFCTL VDFCTH NDEFMN NDEFMA NDEFMH NDEFML NDEFMV NDEFM1 NDEFM2 EDEFMN1 EDEFMN2 EDEFMA EDEFMH1 EDEFMH2 EDEFML1 EDEFML2 EDEFMV VFZC VATSCH VATSCL VTZC VSSTOP VTGWT1 VTGWT2 VTGWI1 VTGWI2 VTGW11 VTGW12 Interface Enhanced EFM Slicer EFM Slice Defect Inspection Block FOK -420 2.2 40 2.0 1.8 -50 0 0 -100 30 30 -50 -50 0 0 0 -100 -120 35 7 -67 -30 -100 200 100 250 150 -50 -40 Spec -360 45 670 4.7 0.3 0 5 +50 -50 50 50 0 0 5 +50 +60 -50 -60 69 32 -32 0 -65 250 150 300 200 0 0 -300 0.5 50 1000 0.5 +50 10 +100 0 0.12 70 70 +50 +50 10 +100 +120 0 0 0.12 100 67 -7 +30 -30 300 200 350 250 +50 +40 Unit mV V V kHz HZ kHz V V mV % mV mV V mV mV mV mV % mV mV mV mV V mV mV mV mV mV mV mV mV mV mV mV
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S1L9225X
Table 2. Electrical Characteristics (Continued)
No. 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 Inspection Items VFRSH voltage Reference voltage Reference current H Reference current L F. Servo off offset F. Servo DAC on offset F. Servo auto offset F. Servo auto ISTAT FERR FEBIAS status F. Servo loop gain F. Servo output voltage H F. Servo output voltage L F. Servo oscillation voltage F. Servo feed through F. Servo search voltage H F. Servo search voltage L2 F. Servo search voltage H2 F. Servo search voltage L Focus full gain F. Servo AC gain 1 F. Servo AC phase 1 F. Servo AC gain 1 F. Servo AC phase 1 F. Servo muting F. Servo AC characteristic 1 F. Servo AC characteristic 2 F. Servo AC characteristic 3 F. Servo AC characteristic 4 F. Servo AC characteristic 5 F. Servo AC characteristic 6 T. Servo DC gain T. Servo off offset T. Servo DAC offset T. Servo on offset Symbols VFRSH VREF IREFH IREFL VOSF1 VOSF2 VAOF VISTAT2 VFEBIAS GF VFOH VFOL VFOSC GFF VFSH VFSH2 VFSL2 VFSL GFSFG GFA1 PFA1 GFA2 PFA2 GMUTT GFAC1 GFAC2 GFAC3 GFAC4 GFAC5 GFAC6 GTO VOST1 VTDAC VOST2 Tracking Servo Focus Servo Inspection Block Interface 0.35 -100 -100 -100 -100 0 -65 2.3 -50 19 2.2 0 +0.35 +0.20 -0.30 -0.65 40.0 19.0 30 14.0 30 0.75 0.68 0.60 0.68 0.94 0.73 13.0 -100 150 -250 Spec 0.5 0 0 0 0 +250 0 0 21.5 +100 +0.50 +0.25 -0.50 -0.50 42.5 23.0 60 18.5 60 0.85 0.78 0.70 0.78 1.04 0.83 15.5 0 320 0 0.65 +100 +100 +100 +100 +550 +65 +50 24 0.5 +185 -35 +0.65 +0.30 -0.20 -0.35 45.0 27.0 90 23.0 90 -15 0.95 0.88 0.80 0.88 1.14 0.93 17.75 +100 550 +250 Unit V mV mV mV mV mV mV V mV dB V V mV dB V V V V dB dB deg dB deg dB dB mV mV mV
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RF AMP & SERVO SIGNAL PROCESSOR
Table 2. Electrical Characteristics (Continued)
No. 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 Inspection Items T. Servo auto offset T. Servo oscillation T. Servo atsc gain T. Servo lock gain T. Servo gain up T. Servo output voltage H T. Servo output voltage L T. Servo jump H T. Servo jump L T. Servo dirc H T. Servo DIRC L T. Servo output voltage L T. Servo AC gain 1 T. Servo AC phase 1 T. Servo AC gain 1 T. Servo AC phase 1 T. Servo full gain T. Servo AC characteristic1 T. Servo AC characteristic2 T. Servo AC characteristic3 T. Servo AC characteristic4 T. Servo AC characteristic5 T. Servo AC characteristic6 T. Servo loop mutt T. Servo loop mutt AC T. Servo int mutt M1 T. Servo int mutt M2 T. Servo int mutt M3 SL. Servo DC gain SL. Servo feed through SL. Servo offset Sled forward kick Sled reverse kick Sled output voltage H Symbols VTAOF VTOSC GATSC GLOCK GTUP VTSH VTSL VTJH VTJL VDIRCH VDIRCL GTFF GTA1 PTA1 GTA2 PTA2 GTFG GTAC1 GTAC2 GTAC3 GTAC4 GTAC5 GTAC6 TSMUTT TSMTAC TSMTM1 TSMTM2 TSMTM3 GSL GSLF VSLOFF VSKH VSKL VSLH Sled Servo Inspection Block Tracking Servo -50 0 17.5 17.5 17.5 2.2 0.35 -0.65 0.35 -0.65 9.0 -140 17.5 -195 29.5 0.59 0.75 0.65 1.30 1.15 1.01 -250 0 0 0 0 10.5 -100 0.45 -0.75 2.2 Spec 0 +100 20.5 20.5 20.5 0.5 -0.5 0.5 -0.5 12.5 -115 21.5 -150 32 0.69 0.85 0.75 1.35 1.25 1.11 0 +50 +50 +50 +50 12.5 0 0.60 -0.60 +50 +185 23.5 23.5 23.5 0.5 0.65 -0.35 0.65 -0.35 -39 16.5 -90 25.5 -100 34.75 0.90 0.95 0.85 1.50 1.35 1.21 +250 +100 +100 +100 +100 14.5 -34 +100 0.75 -0.45 Unit mV mV dB dB dB V V V V V V dB dB deg dB deg dB mV mV mV mV mV dB dB mV V V V
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Table 2. Electrical Characteristics (Continued)
No. 168 169 170 171 172 173 174 175 176 177 Inspection Items Sled output voltage L Sled lock off SP. Servo 1X gain SP. Servo 2X gain SP. Servo output voltage H SP. Servo output voltage L SP. Servo AC gain 1 SP. Servo AC phase 1 SP. Servo AC gain 2 SP. Servo AC phase 2 Symbols VSLL VSLOCK GSP GSP2 VSPH VSPL GSPA1 PSPA1 GSPA2 PSPA2 CLV Servo Inspection Block Sled Servo -100 14.0 19.5 2.2 -7.0 -120 5.5 -110 Spec 0 16.5 23.0 -3.5 -90 9.0 -80 0.5 100 19.0 27.0 0.5 0 -60 12.5 -50 Unit V mV dB dB V V dB deg dB deg
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RF AMP & SERVO SIGNAL PROCESSOR
OPERATION DESCRIPTION
MICOM COMMAND $0X, $1X
Item Address D7 D6 D5 D4 Focus control Tracking control 0 0 0 0 0 0 0 1 D3 FS4 Focus on Anti - shock D2 FS3 Gain down Brake - on Data D1 FS2 Search on TG2 Gain set D0 FS1 Search up TG1 Gain set FZC ATSC Istat Output
Tracking Gain Setting According to Anti-Shock
D7 D6 D5 D4 D3 ANTI - shock 0 0 0 0 1 ANTI shock off 1 ANTI shock on D2 Lens. Brake - on 0 1 D1 TG2 (D3 = 1) 0 1 High Freq. gain normal 0 Gain normal D0 TG1 1 Gain up Istat ATSC
Lens Lens High brake off brake on Freq. gain down
Item Tracking gain control TG1. TG2 = 1 gain up
Hex TG2 $10 $11 $12 $13 $14 $15 $16 $17 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
AS = 0 TG1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 TG2 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0
AS = 1 TG1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0
$13, $17, $1B, $1F (AS0) $13, $17, $18, $1C (AS1) MIRROR muting turns off when the tracking gain goes up
$18 $19 $1A $1B $1C $1D $1E $1F
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$2X
D7 0 D6 0 D5 1 D4 0 MODE $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A $2B $2C $2D $2E $2F D3 D2 D1 Sled Servo Mode TM5 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 0 TM4 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 TM3 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 TM2 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 TM1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 TZC D0 Istat
Tracking Servo Mode TM7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 TM6 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0
Operation of mode (TM1-TM7) TM1 0 1 Track. servo off Track. servo on TM2 0 1 TM4 0 0 1 TM6 0 0 1 Sled. servo on Sled. servo off TM3 Track. kick 0 1 1 Fwd. jump Jump off Rev. jump
TM5 Sled kick 0 1 1 Fwd kick Kick off Rev kick
TM7 (jump) 1 Lens brake on
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RF AMP & SERVO SIGNAL PROCESSOR
DIRC (DIRECT 1 Track Jump) Tracking Condition
Item Hex DIRC = 1 TM 654321 Tracking Mode $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A $2B $2C $2D $2E $2F 000000 000010 010000 100000 000001 000011 010001 100001 000100 000110 010100 100100 001000 001010 011000 101000 DIRC = 0 654321 001000 001010 011000 101000 000100 000110 010100 100100 001000 001010 011000 101000 000100 000100 000100 100100 DIRC = 1 654321 000011 000011 100001 100001 000011 000011 100001 100001 000011 000011 100001 100001 000011 000011 100001 100001
Register $3X
Address D15 - D12 0011 Focus Search D11 PS4 Search+2 D11 0 D10 0 D10 PS3 Search+1 Focus search 1X (5u) D9 PS2 Kick+2 D9 0 D8 0 Sled Kick D8 PS1 Kick+1 Sled Kick 1X (10u) D7 PS5 Jump+1 D7 0 0 0 1 2X (10u) 0 1 2X (20u) 0 0 1 0 3X (15u) 1 0 3X (30u) 1 1 1 1 4X (20u) 1 1 4X (40u) 1 1 Initial 0 0 0 0 1 D6 0 0 1 1 0 0 1 1 Tracking Jump D6 PS6 Jump 1/2 D5 0 1 0 1 0 1 0 1 0 D5 PS7 Jump 1/4 Tracking Jump 0X (0u) 0.25X (1.25u) 0.50X (2.50u) 0.75X (3.75u) 1.00X (5.00u) 1.25X (6.25u) 1.50X (7.50u) 1.75X (8.75u) 0
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Address D15-D12 0011 D4 0 0 1 1 Initial 0
Focus Servo Gain D4 Focus Gain 60K D3 0 1 0 1 $08 580K 460K 520K 400K 0 D3 Focus Gain 120K $0C 180K 60K 120K 0K D2 0 0 1 1 1 D2 Fset1 9K
FSET D1 Fset2 18K Equivalence Resistance 141K (535K) 122K (464K) 131K (498K) 113K (430K) 1 D1 0 1 0 1
OffCK D0 Febias, Focus servo Offset control clock 1: ON 0: off 1
Select (First 8 bits of 16 bits)
D15 D14 D13 D12 D11 D10 D9 D8 Istat
0
0
1
1
Focus Servo Search Level Control PS4 Search +2 PS3 Search +1 $30XX-$33XX
Sled Servo Kick Level Control PS2 Kick +2 Kick X1 PS1 Kick +1 $30XX, $34XX, $38XX, $3CXX
SSTOP
Data Mode (level)
Search X1
Search X2
$34XX-$37XX
Kick
X2
$31XX, $35XX, $39XX, $3DXX
Search X3
$38XX-$3BXX
Kick
X3
$32XX, $36XX, $3AXX, $3EXX
Search X4
$3CXX-$3FXX
Kick
X4
$33XX, $37XX, $3BXX, $3FXX
Data
S.X1, K.X1 $30XX
S.X2, K.X2 $35XX
S.X3, K.X3 $3AXX
S.X4, K.X4 $3FXX
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Auto-Sequence Mode
Address 0 1 0 0 D3 0 0 1 1 1 1 0 D2 0 1 0 0 1 1 1 Data D1 0 1 0 1 0 1 0 D0 0 1 0: FWD 1: REV
Auto-sequence cancel Auto-focus 1-track jump 10-track jump 2N-track jump M-track jump Fast search
Speed Related Command ($F00, F03)
Address D11 1 D10 1 D9 1 D8 1 D7 0 D6 0 D5 0 D4 0 x x x x 0 1 0 1 D3 D2 Data D1 D0
1X Speed ($F00, $F04, $08, $F0C) 2X Speed ($F03, $F07, $F0B, $F0F)
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RAM Register Set Table 1. RAM Register Set
Item Address Blind A, E Overflow. C BRAKE. B FAST FAST INI. Control Register $51XX F K 1 PS3X SSTOP on/off 0 PSTZC TZC on/off 0 OFFS T. Window on/off 0 FZCOFF FZC on/off 0.36ms 23.2ms 0.18ms 11.6ms 0.09ms 5.80ms 0.04ms 2.90ms 0.72ms 1 SBAD Terr sum gain 0.36ms 0 GSEL CDRWWin TGH 0 Off Off Off Off DivideX2
400mV 500 mV
Data D7 0.18ms D6 0.09ms D5 0.04ms D4 0.02ms D3 D2 D1 D0
$50XX
0.18ms 0 MCC1 Mirror bottom
0.09ms 0 MCC2 Mirror peak
1X
1X
1
On
On
On
On
Sum
200 mV 300 mV
2X (Recommend)
2X (Recommend)
INI. Control Register $52XX
1 MGA1 Mirror gain1.5X 0 1 Normal Up (recommend)
1 MGA2 Mirror gain2X Normal Up
1 MGA3 Mirror bias S. Off Bias
1 FGS1 F. Servo DC gain Up Normal
1 FGS2 F. Servo AC gain Up Normal
0 TGC1 T. Servo AC gain Up Normal
0 TGC2 T. Servo DC gain Normal Up
0 GEFM EFM. ASY gain sel 5X Normal 8X Up
INI. Control Register $53XX
1 TZCS1 Trcnt, TZC sel 0 1 Trcnt TZC 0 $54XX DSP3 FlagHold 46.4ms 0 0ms
1 EC9 Track I. setting 3 On Off 1 DSP2 FlagHold 23.2ms 0ms
0 LIMITS C1-Flag SSTOP SSTOP C1-Flag 1 DSP1 FlagHold 11.6ms 0ms
1 SPEAK 44K, 88K sel. 88K 44K 0 ALOCK Lock On/Off Lock = 1
1 IVSEL Voltage current sel Voltage Current 0 Complete TRCNT complete Duty repeat
1 On/Off EFM peaking Off On 0 TASY TES output
0 TOCD T. Servo offset C Reset Set 1 EFMMODE Double ASY meth.
0 TRSTS T. Bal & gain reset Reset Set 1 TZCRC TZC noise filter TZC Ori.
INI. Control Register
F0K
ASY compensation
1 INI.
46.4ms 1
23.2ms 0
11.6ms 0
Lock 0, 1 1
Complete 1
TES 1
VREF 1
TZC Fil. 0
19
S1L9225X
RF AMP & SERVO SIGNAL PROCESSOR
Table 1. RAM Register Set (Continued)
Item Address Control Register $55XX D7 FJTS Fast search TEO output 0 1 INI. T. Jump T. Mute 1 D6 TCNT Trcnt clock rate 1:1 16:1 0 MSB Off On 0 Positive Offset 10mv/step Off On 0 LSB Off On 0 MSB On Off 1 D5 D4 Data D3 D2 D1 D0
Febias Offset Control Negative Offset 10mv/step On Off 1 LSB On Off 1
Item D7 Function PS3X SSTOP ON/OFF 0 1 INI. OFF ON 1 * SSTOP comparator ON/OFF * OFF 0 output * SSTOP input 47K pull-up resistance $51XX Function SBAD Terr sum gain 0 1X SUM D3 * TES output Control GSEL CDRW-Win TGH 400mV 500 mV 1 1.25X SUM 200 mV 300 mV INI. 1 0 D5 PSTZC TZC ON/OFF OFF ON 1 D5 * TZC
DATA D5 OFFS T.Window ON/OFF OFF ON 1 * Tbal. Tgain comparator ON/OFF * Off 0 output FZCOFF FZC ON/OFF OFF ON 1 D4 * FZC comparator ON/OFF * Off 0 output
comparator ON/OFF * Off 0 output
D5 MCC1 Mirror Bottom 1X * 2X Mirror detect strengthen 2X MCC2 Mirror peak 1X
D4 * 2X Mirror detect strengthen 2X
* TGH window comparator input select
2X
(recommend)
2X
(recommend)
0
0
20
RF AMP & SERVO SIGNAL PROCESSOR
S1L9225X
Item D7 Function MGA1 Mirror Gain1. 5X 0 1 INI. $52XX Function FGS2 F.Servo AC Gain 0 1 INI. UP Normal 1 Normal Up 1 D3 * Focus servo DC Gain select MGA2 Mirror Gain2X UP Normal 1 * Mirror input voltage level select 1:recommend MGA2 Mirror Gain2X Normal UP 1 D5 D5
DATA D5 MGA3 Mirror Bias S. Off Bias 0 D5 TGC2 T.Servo DC Gain Normal UP 0 * Track servo DC Gain select GEFM EFM. ASY Gain Sel 5X Normal 8X UP 0 * Mirror input Voltage level bias select FGS1 F.Servo DC Gain UP Normal 1 D4 * EFM slice Asymmetry Loop gain select D4 * Focus servo DC Gain select
* Mirror input voltage level select 0: recommend
* Track servo DC Gain select
Item D7 Function TZCS1 Trcnt, TZC Sel 0 1 INI. $53XX Function IVSEL Current voltage sel 0 1 INI. Voltage Current 0 * Voltage, Current pick-up Type select mode setting ON/OFF EFM peaking Off ON 0 Trcnt TZC 0 * Track count clock select EC9 Track I. Setting3 ON Off 1 D5
DATA D5 *Tracking servo pole Freq. select LIMITS C1-Flag SSTOP SSTOP C1-Flag 1 0: SSTOP in 1: C1-Flag out * Pin 30 output select SPEAK 44K, 88K Sel. 88K 44K 0 D4 * F.Servo servo mute & EFM slice Hold judgment clock select
* F.Servo. T. servo mutt & EFM slice Hold using control
TOCD T.Servo Offset C Reset Set 1
* Tracking servo offset value reset control
TRSTS T.Bal & Gainreset Reset Set 1
* T.Bal & T.Gain DAC value reset control
21
S1L9225X
RF AMP & SERVO SIGNAL PROCESSOR
Item D7
Function DSP3 FlagHold 46.4ms
DATA D6
DSP2 FlagHold 23.2ms
D5
DSP1 FlagHold 11.6ms
Video-CD confrontation C1flag select signal Defect, Cpeak C1flag control signal generator cycle select H: C1point 1, L: C1point 0 ALOCK LOCK ON/OFF
D4
According to
0 1 2 3 4 5 $54XX 6 7 INI.
0 0 0 0 1 1 1 1 1 D3
0 0 1 1 0 0 1 1 0
0 1 0 1 0 1 0 1 0 D5
Only Defect Time Defect + 11.6ms Defect + 23.2ms Defect + 34.8ms Defect + 46.4ms Defect + 58.0ms Defect + 69.6ms Defect + 81.2ms 0: LOCK=1 1: LOCK 0,1 by DSP
Alock signal SSP lock control
D5 * Pin 60 Output select EFMMODE * EFM mode TZCRC
D4 * Control by TZC Filter at Using TZC of Trcnt
Function COMPLETE
* Trcnt
TASY TES output FOK TES 1
TRCNT count value complete for 0 1 INI. duty repeat complete 1 Micom move
Double Double ASY TZC noise ASY meth. mode filter ASY requital VREF 1 control TZC Ori. TZC Fil. 0
22
RF AMP & SERVO SIGNAL PROCESSOR
S1L9225X
Item D7 Function FJTS * Tracking TCNT Trcnt clock 1:1 16:1 0 D4 D3 D6
DATA
* Trcnt count clock rate at micom move
Fast search servo output TEO output at fast 0 1 $55XX INI. T.Jump T.Mutt 1 D5 Function search
D2 Febias Offset control
D1
D0
Positive Offset MSB 0 1 0 0 0 0 1 1 1 1 INI. 0 10mv/step 0 0 1 1 0 0 1 1 0 LSB 0 1 0 1 0 1 0 1 0 output offset 0mV +15mV +30mV +45mV +60mV +75mV +90mV +100mV MSB 0 0 0 0 1 1 1 1 1
Negative Offset 10mv/step 0 0 1 1 0 0 1 1 1 LSB 0 1 0 1 0 1 0 1 1 output offset -100mV -90mV -75mV -60mV -45mV -30mV -15mV 0mV
23
S1L9225X
RF AMP & SERVO SIGNAL PROCESSOR
Address KICK D FAST R PWM DUTY PD PWM WIDTH PW
HEX $6XXX
D11 11.6ms 23.2ms
D10 5.80ms 11.6ms
D9 2.90ms 5.80ms
D8 1.45ms 2.90ms
D7
D6
D5
D4
D3
D2
D1
D0
8
4
2
1
11.0ms
5.43ms
2.71ms
1.35ms
INI. 2N TRA. N M TRA. M Fast search T INI. Brake point P $CXXX $7XXX $7XXX
0 4096
1 2048
1 1024
1 512
1 256
0 128
1 64
0 32
0 16
0 8
1 4
0 2
16384
8192
4096
2048
1024
512
256
128
64
32
16
8
0 16384
0 8192
0 4096
0 2048
0 1024
0 512
1 256
1 128
1 64
1 32
1 16
1 8
INI. TRCNT count output comptlete $CXXX TCNT =0 $55XX TCNT =1 INI. CLV on/off register
0
0
0
0
0 128
0 64
1 32
1 16
1 8
0 4
0 2
0 1
2048
1024
512
256
128
64
32
16
1 CLV on, EFM on $99X1~$99XF CLV off, EFM off $99X0 X X 0 1 X
1 X X X
0 X X X
0 X X X
0 X 0 0
1 X 0 0
1 X 0 0
1 1 0 0
INI Notice.
1
0
The actual value many be slightly different from the set value. A set value + 4 - 5 WDCK B, D, E set value + 3 WDCK C set value + 5 WDCK N, M, T, P set value + 3 TRCNT Caution - Among the 16 settings of PWM WIDTH 'PW' only one from D3, D2, D1, and D0 can be selected. (not 4bit combination) - More than 512 tracks are not recommended when 2N track and M track are used. (algorithm possesses problem generation) - Because PWM DUTY 'PD' can have 1 - 2 errors, should be set to "set value + 2" - $5XXX's I/V SEL command is ( 0: Voltage pick-up configuration, 1: Current type only) - T.RST - 0: Tracking servo offset DAC value RESET cancel, 1: Tracking servo offset DAC value RESET
24
RF AMP & SERVO SIGNAL PROCESSOR
S1L9225X
AUTOMATIC CONTROL COMMAND Tracking Balance and Gain Control
Address D7 Tracking BAL. $800X - $801X Initial V. Tracking Gain. $810X - $811X Initial V. 0 0 0 0 Address D6 0 D5 0 D4 B4 0 G4 1 D3 B3 1 G3 0 D2 B2 1 G2 0 Data D1 B1 1 G1 0 D0 B0 1 G0 0 TGH TGL BAL TRCNT Istat Trcnt
Tracking Balance and Gain Control Window
Data Address D7 T. Gain
$84XX
D6 T. BAL
D5
D4
D3 INTC
D2 INTC2
D1 INTC3
D0 DSPMC
Istat
Trcnt
F.S.O.C F.E.O.C
Tracking gain control window
Tracking F. Servo FE. Bias T. Servo T. Servo F. Servo C1 Falg $841 balance offset offset cpeak mirror cpeak defect ref. (F.ERR) control control control mute mute mute $842 window (F.SER)
ISTAT
-10 - 15mV -20 20mV
TRCNT
TRCNT 0 1 INITIAL 250mV 150mV 0
ISTAT 200mV 300mV
Off On 0
Off On 0
Off On 0
Off On 1
Off On 1
0.54ms 0.73ms 1
0
APC (Automatic Power Control)
Address D7 LDON APC on/off $85XX D6 LPCOFF LPC laser control ON/OFF default
(recommend)
Data D5 ALPC1 Laser mediation control default
(recommend)
D4 ALPC2 Laser mediation control default
(recommend)
D3 APCL1 Laser range control default
(recommend)
D2 APCL2 Laser range control default
(recommend)
D1 AHOLD
D0 ASEL3
Laser Laser control control hold default gain default
(recommend) (recommend)
0 1 Initial
On Off 1
Off On 1
Off On 1
Off On 1
Off On 1
Off On 1
Hold Off 1
2X 1X 0
Recommend default value ( D6 D7)
25
S1L9225X
RF AMP & SERVO SIGNAL PROCESSOR
Additional Register Set 1
Data Address $86XX D7 F.Ser.Reset D6 FOKSEL D5 MONITOR Trcnt monitor select 1: FOK, TGL TRCNT 0:Test output ISTAT2 TEST FOK(TGL) TEST TRCNT(TGL) TEST 46ms/step 1/2 EQI 1/3 EQI 1 EQI TES 0 12uA 20uA 0 Up-13K Nor-7K 1 FOK, TRCNT, 5.8ms/step TGL 1 1 D4 FSOC D3 ASEL1 D2 ASEL2 Laser control source D1 EQB AGC EQ D0 EQR AGC gain up/normal
Focus servo Trcnt output sel offset control (monitor:1) except at reset gain control ($81XX) 0: FOK 1: TRCNT D6 0 0 1 1 D5 0 1 0 1
FERR. offset Laser Focus offset control control step source time setting 0:46.0ms 1:5.80ms
0 1 INITIAL
RESET SET 1
FOK TRCNT 1
TRCNT select is selected by the MONITOR (D1). With the tracking gain control command ($81XX), TGL is output, and the remaining becomes FOK if they are 0 from the FOKSEL bit. If they are 1, COUT is output to TRCNT. D5 bit priority over D6 bit, it related ISTAT2 output.
Additional Register Set 2
Address D7 DIRC $87XX DIRC control D6 RSTS Febias reset D5 AGCL2 AGC size control D5 D5, D4 0 0 1.6V 0 1 1.45V 1 0 1.25V 1 1 1.0V * Recom mend D5 D4 1 1 D4 AGCL1 Data D3 EFMBC EFM double ASY. revision D2 MT2 0 D1 MT1 0 D0 MT0 0 FSDFCT
0 0 0 1 1 1 1
0 1 1 0 0 1 1
1 0 1 0 1 0 1
Fecmpo Defect Mirror Cpeak Dfctint BALH BALL
0 1 Initial V.
Enable Disenable 1
Reset Set 1
On Off 0
On Off 0
Off On 0 1 1 1
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RF AMP & SERVO SIGNAL PROCESSOR
S1L9225X
$8EXX Focus & Tracking Servo Filter Control Command
Address D7 D6 D5 D4 F. Servo Phase shift 0: low frequency 1: high frequency On Off 1 On Off 1 On Off 0 On Off 1 Data D3 D2 D1 CLV Freq. movement 0: low frequency 1: high frequency On Off 1 On Off 0 D0
$8EXX 0 1 Initial V.
Track. S Freq. movement 0: low frequency 1: high frequency) On Off 1 On Off 0
$8FXX Tracking Servo Offset Control Command
Address D7 $8F00 $8F1F X D6 X D5 X D4 Data D3 D2 D1 D0
Tracking servo offset control command 8F(000XXXXX) $8F1F $8F00 (-160mV +160mV) Control window is used with the balance window and monitors the ISTAT output Because tracking offset of approximately +30mV - +50mV is ideal in the system, consider the control setting by raising to ($8F1F $8F00) 3 - 5 steps after controlling the offset to 0mV.
Consider the measure setting by $8010 command of tracking switch and $811F command of tracking gain switch after $24 command.
Initial V. 0 0 0 1 0 0 0 0
27
S1L9225X
RF AMP & SERVO SIGNAL PROCESSOR
Photo-Diode I/V AMP Gain Setting for CD-R and CD-RW
DATA Address D7 RWC1 1.0X $82XX D6 RWC2 1.5X D5 RWC3 2.0X D4 RWC4 1.25X RFO only RF & FERRGAIN I/V AMP Equivalence RFO ONLYGAIN RFO Feed resistance rate 22K ROF total compared with OF 0E 0F 06 07 0A 0B 02 03 0C 0D 04 05 08 09 00 01 0 1 INITIAL 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 up normal 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 up normal 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 up normal 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 normal up 0 58.5K 58.5K 91.5K 91.5K 121.75K 121.75K 154.75K 154.75K 154.75K 154.75K 187.75K 187.75K 218.00K 218.00K 251.00K 251.00K 1.06 1.06 1.66 1.66 2.21 2.21 2.81 2.81 2.81 2.81 3.41 3.41 3.96 3.96 4.56 4.56 10K 8K 10K 8K 10K 8K 10K 8K 10K 8K 10K 8K 10K 8K 10K 8K 22K/10K=2.2 22K/8K=2.75 22K/10K=2.2 22K/8K=2.75 22K/10K=2.2 22K/8K=2.75 22K/10K=2.2 22K/8K=2.75 22K/10K=2.2 22K/8K=2.75 22K/10K=2.2 22K/8K=2.75 22K/10K=2.2 22K/8K=2.75 22K/10K=2.2 22K/8K=2.75 9.33 11.66 14.61 18.26 19.45 24.31 24.73 30.91 24.73 30.91 30.00 37.51 34.84 43.56 40.33 50.16 1.00 1.25 1.56 1.96 2.08 2.60 2.65 3.31 2.65 3.31 3.21 4.02 3.73 4.66 4.32 5.37 RFO TOTAL RFO loop total
Input resistance RWC4 Summing at 55K GAIN resistance
RFO & Focus error gain
1 stage GAIN
2 stage GAIN
CD-RW mode set by 0, if more gain up set by 1 and gain value is more big set by 8.
28
RF AMP & SERVO SIGNAL PROCESSOR
S1L9225X
Tracking Error CD-RW Mode Gain
DATA Address D3 RWC6 1.0X D2 RWC7 1.5X D1 RWC8 2.0X D0 RWC9 1.5X I/V AMP Equivalence resistance $82XX Tracking Error Gain T.E difference 0F 0E 07 06 0B 0A 03 02 0D 0C 05 04 09 08 01 00 0 1 INITIAL 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 up normal 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 up normal 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 up normal 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 normal up 0 391K 391K 583K 583K 786K 786K 979K 979K 979K 979K 1171K 1171K 1374K 1374K 1567K 1567K 1.06 1.06 1.66 1.66 2.21 2.21 2.81 2.81 2.81 2.81 3.41 3.41 3.96 3.96 4.56 4.56 30K 15K 30K 15K 30K 15K 30K 15K 30K 15K 30K 15K 30K 15K 30K 15K 96K/30K=3.2 22K/15K=6.4 96K/30K=3.2 22K/15K=6.4 96K/30K=3.2 22K/15K=6.4 96K/30K=3.2 22K/15K=6.4 96K/30K=3.2 22K/15K=6.4 96K/30K=3.2 22K/15K=6.4 96K/30K=3.2 22K/15K=6.4 96K/30K=3.2 22K/15K=6.4 9.33 11.66 14.61 18.26 19.45 24.31 24.73 30.91 24.73 30.91 30.00 37.51 34.84 43.56 40.33 50.16 1 stage GAIN Tracking Error Input resistance at 82K gain RWC9 difference resistance 2 stage GAIN Terr total compared with OE 2.00 1.00 2.98 1.49 4.02 2.01 5.01 2.50 5.01 2.50 6.00 3.00 7.03 3.51 8.02 4.01 Tracking Feed resistance rate 22K RFO TOTAL TERR LOOP TOTAL
CD-RW mode set by 0 (4.01X) if gain value more big setting by 8
29
S1L9225X
RF AMP & SERVO SIGNAL PROCESSOR
Photo-Diode I/V AMP Gain Setting and RFO Offset Control for CD-R and CD-RW.
DATA ADDRESS D7 RWC5 $83XX 0 1 INITIAL D6 RWC10 D5 RFOC1 D4 RFOC2 D3 RFOC3 D2 RFOC4 D1 RFBC1 D0 RFBC2
Focus Error related Gain Down(0.5X) Normal(1X) 1 Normal(1X) UP(2X) 0
CD-RW related monitor output based on RFOC1 + RFOC2 + RFOC3 + RFOC4. Priority order: RFOC2>RFOC4>RFOC1,RFOC3
RFAMP Offset Control Normal Down 0 Normal Down 0
1/2 RFO EQI 0
RFOC4 TE GAIN 1 MODE Setting
Focus Error TES 0
RFOC3 RFOC1 0
DATA
DATA D7 0 0 1 1 D6 0 1 0 1
F.Error Gain D5 0.5 1.0 1.0 2.0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
DATA D4 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Monitor ISTAT Focus Error 1/2 RFO TES 1/2 RFO TGH TGH TGH TGH Focus Error EQI TES EQI TGH TGH TGH TGH
Output TRCNT Focus Error 1/2 RFO TES 1/2 RFO TGL TGL TGL TGL Focus Error EQI TES EQI TGL TGL TGL TGL D1 0 0 1 1
DATA D0 0 1 0 1
RFO Offset
0mV 0mV -100mV -200mV
CD-RW Detect Method
There are four types of source signals in the method used to read the CD-RW DISC. 1. Focus Error Signal 2. Tracking Error Summing Signal (TES) 3. RFO 4. EQI Tracking Gain Window outputs(TGH,TGL) are sent to ISTAT1 and ISTAT2 during focus search.
1
Focus Error
The monitor output in the table above is set as the focus error output and the focus error output level comparison $81XX is sent to ISTAT1 and ISTAT2 to allow the micom to monitor the focus error output. After $81XX is sent, it possible to monitor because the tracking gain window comparator are used commonly. With search command ($47), if the intensity of radiation set its target, focus search level is 1Vp-p, and peak value is 0.5V. As the table below, windows level transmit $84CX $513X command, ISTAT1 monitored at 500mV.
2 3 4
TES RFO EQI
Set the TES in the table above and read the CD-RW disc the same way as focus error detect. Set the RFO in the table above and read the CD-RW disc the same way as focus error detect. Set the EQI in the table above and read the CD-RW disc the same way as focus error detect. ISTAT Output Mode $844X $84CX 250mV 150mV ISTAT2 ISTAT1 $517X $513X 200mV 400mv A total of 6 Tracking Gain Windows use $84XX and $51XX to 300mV 500mv read the CD and CD-RW disc.
30
RF AMP & SERVO SIGNAL PROCESSOR
S1L9225X
AUTO-SEQUENCE This function executes the chain of commands that execute auto-focus, track jump, and move. MLT latches the data at time L, and ISTAT is L during auto-sequence. It output H upon. Auto Focus Flow-Chart
Auto Focus
Focus Search UP
FOK = H YES FZC = H YES FZC = L YES Focus Servo ON
NO
NO
During Blind "E" time set by register 5, FOK and FZC executions repeat until they become "H".
NO
END
Timing Chart Auto-focus receives the auto-focus command from the MICOM in the focus search down state and focus search up. The SSP becomes focus servo on when FZC changes to L after the internal FOK RZC satisfy 'H', all the time set blind 'E' (Register $5X). All the internal auto focus executes ended. And this status is sent to micom through the ISTAT output.
$47 Latch MLT FOK
Blind Time E FOK, FZC -> H
FZC
Focus Output ISTAT Internal STATUS
Search UP Search DOWN
Focus Servo ON
$02
$03
$03
$03
$08
31
S1L9225X
RF AMP & SERVO SIGNAL PROCESSOR
1 Track Jump {$48(FWD), $49(REV)} Flow-Chart
1 Track Jump
Track Jump Sled Servo OFF
Forward jump when $48 and reverse jump when $49 Wait using the WDCK reference clock for blind "A" time, set by register 5. (1 WDCK = 0.011mS)
NO
WAIT (Blind A)
Trcnt = YES Track REV Jump
WAIT Brake "B"
Repeat check of whether TRCNT is continuously in "H" state with the WDCK reference clock for the brake "B" time, set by register 5, at the TRCNT rising edge.
Track, Sled Servo On
END
1 Track Jump Timing Chart {$48(FWD), $49(REV) inside ( ) Reverse}
$47 ( $49) MLT TRCNT
Blind Time A WAIT Blind Time B Trcnt "H"
Tracking Farward Jump
Track Output Sled Output ISTAT Internal STATUS
Track Servo ON Sled Servo ON Sled Servo OFF
Track Servo ON Tracking Revrese Jump Sled Servo ON
$25
$28 ($2C)
$28 ($2C)
$2C ($28)
$25
Receives $48 ($49) for 1 track jump and sets the blind and brake times through register $5X.
32
RF AMP & SERVO SIGNAL PROCESSOR
S1L9225X
10 Track Jump {$4A(FWD), $4B(REV)} Flow-Chart
10 Track Jump
Track FWD Jump Sled FWD Kick
Foward jump & kick when $4A and reverse jump & kick when $4B. Wait using the WDCK reference clock for blind "A" time, set by register 5. (1 WDCK = 0.011mS)
NO
WAIT (Blind A)
Trcnt = 5 YES Track REV Jump, Sled FWD Kick
Tracking reverse jump & sled forward kick when $4A and tracking forward jump & reverse kick when &4B.
NO
C = Over Flow? YES Track, Sled Servo ON
Repeat check of TRCNT 1's cycle with the WDCK reference clock to determine if the cycle is long than the overflow "C" time, set by register 5.
END
10 Track Jump Timing Chart {$4A(FWD), $4B(REV) inside ( )Reverse }
$4A ( $4B) MLT TRCNT
Blind Time A WAIT Trcnt 5 Count Over Flow Time C Trcnt 1's Time Check Track Servo ON Tracking Revrese Jump Sled Forward Kick Sled Servo ON
FWD REV
Tracking Forward Jump
Track Output Sled Output ISTAT Internal STATUS
Track Servo ON Sled Servo ON
$25
$2A ($2F)
$2A ($2F)
$2E ($2B)
$25
10 track jump executes the tracking forward jump up to trcnt 5track count and turns on the tracking and sled servos after a tracking reverse jump until trcnt 1's cycle is longer than the overflow 'C' time. This operation checks whether the actuator speed is sufficient to turn on the servo.
33
S1L9225X
RF AMP & SERVO SIGNAL PROCESSOR
2N Track Jump Flow-Chart
2N Track Jump
Track FWD Jump, Sled FWD Kick
Foward jump & kick when $4C and reverse jump & kick when $4D. Wait using the WDCK reference clock for blind "A" time, set by register 5. (1 WDCK = 0.011mS)
NO
WAIT (Blind A)
Trcnt = N? YES Track REV Jump, Sled FWD Kick C = Over Flow? YES WAIT (Kick "D") Track Servo ON, Sled FWD Kick
Tracking reverse jump & sled forward kick when $4C and tracking forward jump & reverse kick when $4D.
NO
Repeat check of TRCNT 1's cycle with the WDCK reference clock to determine if the cycle is longer than the overflow "C" time, set by register 5. When $4C, the sled forward kick continues for KICK "D" time. When $4D, the sled reverse kick continues for KICK "D" time.
Tracking & Sled Servo ON
END
34
RF AMP & SERVO SIGNAL PROCESSOR
S1L9225X
2N Track Jump Timing Chart {$4C(FWD), $4D(REV) inside ( ) Reverse }
$4C ( $4D)
MLT TRCNT
Blind Time A WAIT Trcnt N Count Tracking Forward Jump C Over Flow Time C Trcnt 1's Cycle Time Check Track Servo ON Tracking Revrese Jump Sled Forward Kick Kick Time D Sled FWD Kick for D Time Sled Servo ON C Q Data Read Enable FWD REV
Track Output Sled Output
Track Servo ON
Sled Servo ON
ISTAT Internal STATUS $25+$17 $2A ($2F) $2A ($2B)
$2E ($2B)
$26($27)
$25+$18
Similar to 10 tracks and executes by adding sled kick by the amount of kick 'D' time and the servo turns on after lens brake starts.
35
S1L9225X
RF AMP & SERVO SIGNAL PROCESSOR
M Track Jump {$4E(FWD), $4F(REV)} Flow-Chart
M Track Jump
Track Servo OFF, Sled FWD Kick
Sled FWD kick when $4E and REV kick when $4F. Wait using the WDCK reference clock for blind "A" time, set by register 5. (1 WDCK = 0.011mS)
NO
WAIT (Blind A)
TRCNT = M? YES Tracking & Sled Servo ON
Count trcnt with the clock for M amount, set by register 7.
END
M Track Jump Timing Chart {$4E(FWD), $4F(REV) inside () Reverse}
$4E ( $4F) MLT TRCNT
Blind Time A WAIT Trcnt N Count
FWD REV
Track Output
Track Servo ON
Tracking Servo OFF
Treck Servo ON
Sled Output
Sled Servo ON
Sled Forward Kick
Sled Servo ON
ISTAT Internal STATUS $25 $22 ($23) $22 ($23) $22 ($23) $25
Makes Trcnt to clock and counts to the value of M count, set by register 7, to execute sled kick.
36
RF AMP & SERVO SIGNAL PROCESSOR
S1L9225X
Fast Search Flow-Chart
Fast Search Track Servo ON, Sled FWD Kick WAIT (Blind F)
Sled forward kick when $44 and sled reverse kick when $45.
Track FWD Jump, Sled FWD Kick WAIT (Blind K) NO
Tracking forward kick jump and sled forward kick when $44 and tracking reverse jump and sled reverse kick when $45 Execute the above conditions until TRCNT is the same as the brake point "P" count value, set by register 7. Repeat checks Trcnt, until Trcnt equals T set by register 7, like the PD and PW set by register 6, PWMs duty is decided with the PWs PWM1 period width used as the period, and PDs high. Low duty used as standard 4 bits (number selected from 0 - 15) When $44, the sled forward kick continues for kick "R" time. When $45, the sled reverse kick continues for kick "R" time.
Trcnt = P? YES Track FWD Jump, Sled FWD PWM Kick
Trcnt = T? YES Track Servo ON, Sled REV Kick WAIT (REV. Kick "R") Tracking & Sled Servo ON END
NO
37
S1L9225X
RF AMP & SERVO SIGNAL PROCESSOR
Fast Search Timing Chart {$44(FWD), $45(REV) inside () Reverse}
$44 ( $45) MLT TRCNT
Blind Time F WAIT Blind K WAIT
$5XX1 Tracking Servo Mutt
FWD REV
Trcnt P Count Trcnt T Count Kick "R" Walt
Track Output
Sled Servo ON
Tracking Forward Jump
Track Servo ON
Sled Output
Sled Servo ON
Sled Forward Kick
Sled servo Kick
Sled Servo ON Sled REV Kick
ISTAT Internal STATUS $25+$17 $26 ($27) $2A ($2F) $26 ($27) $25+$18
To Note During use of Auto-Sequence 1. Must send tracking gain up and brake on ($17) during 1, 10, 2N, track jump, and fast search. 2. Before the auto-sequence mode, MLT becomes 'L' and sequence operation executes at the initial WDCK falling edge after data latch. 3. During play, determine as FOK and GFS, not ISTAT. 4. Tracking gain up, brake, anti-shock and focus gain down are not executed in auto-sequence, and separate command must be provided. 5. If the Auto-sequence does not operate as Istat Max time over, apply $40 and use after clearing the SSP internal state. 6. The above indicated WDCK receives 88.2kHz from DSP. (2x 176kHz) 7. The auto-sequence internal trcnt and the actual trcnt are slightly different. 8. Problems can be generated in the algorithm for 2N and M tracks if jump of more than 512 tracks are attempted; therefore, use them for less than 512 track jumps, if at all possible. 9. Use the fast-search algorithm for more than 512 tracks, if possible. 10. When the track is moved by micom, the internal trcnt count setting is created by the $CXXX command, and complete and continuous complete signals are output to ISTAT.
38
RF AMP & SERVO SIGNAL PROCESSOR
S1L9225X
TRACKING BALANCE CONTROL CONCEPT In tracking balance control, the micom compares and monitors the previously set DC voltage window and the tracking error DC offset, extracted from the external LPF for automatic control.
F F Beam E E Beam FDL FT2 Gain adjust 5bit Arrary 5bit (B4-B0) from Micom I/V AMP
5 bit arrary Gain control RH
-
Vdc RH
+ + -
AND TBAL RLO Logic
RHO
ISTAT1
MIRROR D TZC TE1 LPF LPFT CK
Q
Trcnt ISTAT2
Summary of Operation When the focus and spindle servos are on, tracking balance control turns off the tracking and servo loops to open the tracking loop, extracts the DC offset by sending the error signal, passed through the optical pick-up and tracking error amp, through the external LPF, then this offset to the previously set window comparator level, and then informs of the completion the balance control to the micom through the ISTAT, when the dc offset of the tracking error amp in window is extracted. At this time, Tracking E beam-side I/V amps gain is selected by MICOM, and the 5-bit resistance arrays resistance value is selected by the 5-bit control signal. The values that MICOM applies are 00000 11111. If you select the switch, TESO DC offset increases the (2.5V-V) (2.5V + V) one step at a time, to enter the pre-selected DC window level. When it enters that level, the balance adjust is completed, and the switch condition is latched at this time Because the TESO signal frequency is distributed up to 2kHz, the DC offset that passed through the LPF is not a correct value, if a DC component exists, and therefore, micom monitors the window output when the TESO signal frequency is above 1kHz. At this time, the frequency check the Trcnt pin. When TBAL output is H, balance control is complete. Vdc < RLI 39
S1L9225X
RF AMP & SERVO SIGNAL PROCESSOR
RHI: High level threshold value RLI: Low level threshold value Vdc: Window comparator input voltage TBAL: And gate output value of the window comparator output An Example of Tracking Balance Control Out of $8000 $801F 32 steps, the upper and lower 32 steps are used. After receiving $8110 as the gain when the focus and tracking are on, the control flow checks TRCNT frequency to see if the more than 7 TRCNT entered during 10ms. If yes, it checks the ISTAT, if no, it checks the number of TRCNT three times and goes on to the ISTAT check. Repeats fail, it raises the balance switch by 1 step. If ISTAT does not immediately go to H, it for 10 ms during ISTAT check after which it check whether ISTAT is H continuously for 10ms, is repeated three times. If the three repeats fail, it raises the balance switch by 1 step. The above wait 10 ms while running the system. It finds the average of the values obtained the three repeated execution of the entire above balance control. If only the balance values are from two of the three repeats, these values are averaged. If only two out of the three tries were successful in getting a balance value, average the two values. Set as balance switch, this average value +2. This is because the balance for the system and the minus value for the DC is stable in the system. Precision is important in balance adjust, and about 1+2 sec is spent as adjust time, which is accounted for. Balance Control Flowchart 1
Balance ADJ. Start $8000 Other Method - Can balance adjust while moving tracks - $F03 easy to trcnt freq check in the 2X mode -10mV - +15mV $84 X0XX -20mV - +20mV $84 X1XX Almost 20mV
Start - Environment Setting Focus on $08 Spindle on CLV-S Tracking off $20 Sled off gain $8110 Balance Window Level Setting
Repeat 3 times Change switch if failure after 3 repeats
NO
Balance ADJ. Switch Incnease by 1 step $8000 -> $801F
Check to see if TRCNT is 7 for 10ms B0 to B4 Switch Control
NO YES
ISTAT = H?
YES
Is ISTAT = H? Check if ISTAT is H after waiting 10ms repeat 3 times Change switch if failure after 3 repeats
If finds the average of the values obtained the three repeated execution of the entire above bacance control. If only two out of the three tries ware successtial in getting a bacance value, average the two value.
Present Control Value +2 Step then, ADJ end.
40
RF AMP & SERVO SIGNAL PROCESSOR
S1L9225X
Balance Control Flowchart 2
Balance ADJ. Start $8000 Other Method - Can balance adjust while moving tracks - $F03 easy to trcnt freq. check in the 2X mode -10mV - +15mV $84 X0XX -20mV - +20mV $84 X1XX
Start Environment Setting - Focus on $08 - Spindle on CLV-S - Tracking off $20 - Sled off gain $8110 Balance Window Level Seting
Balance ADJ. Switch Incnease by 1 step $8000 -> $801F
TRCNT Freq is High Enough? B0 to B4 Switch Control
NO YES
NO
1kHz Check
ISTAT = H?
YES
End ADJ.
When Tracking Balance * The balance adjust is from $8000 to $801F, and the switch mode is changed one step at a time by 16-bit data transmission. After adjustment, a separate latch pulse is not necessary. If the Trcnt freq. is not high enough, the balance control can be adjusted at $F03 applied 2x mode . Here, we have suggested tracking off status for the balance adjust, but the same amount of flow can be balance adjusted while in track move. Among the 16 bit data, the tracking balance window setting level can be selected from 0: -10 mV +15mV 1: -20mV +20mV through the D6 bit. When the tracking balance adjust is complete, the tracking gain control starts.
* * * *
41
S1L9225X
RF AMP & SERVO SIGNAL PROCESSOR
Tracking Balance Equivalent Resistance
Tracking Balance Fixed Resistance and Parallel Resistance Data TSIO offset $8000 $8001 $8002 $8003 $8004 $8005 $8006 $8007 $8008 $8009 $800A $800B $800C $800D $800E $800F $8010 $8011 $8012 $8013 $8014 $8015 $8016 $8017 $8018 $8019 $801A $801B $801C $801D $801E $801F + F equivalent Res. 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K 391K E equivalent Res. 480K 475K 468K 463K 455K 451K 444K 439K 433K 426K 421K 415K 409K 403K 397K 391K 385K 380K 374K 368K 361K 357K 350K 344K 336K 332K 327K 321K 315K 309K 303K 298K 15.22K 15.6K 16.1K 16.5K 17.2K 17.6K 18.3K 18.9K 19.5K 20.4K 21.0K 21.9K 22.7K 23.7K 24.7K 25.9K 27.1K 28.5K 30.0K 31.7K 33.9K 35.8K 38.3K 41.1K 44.5K 48.4K 52.8K 58.3K 65.1K 73.6K 84.8K 100K 100K/ 5bit R 5bit equivalence 17.9K 18.6K 19.3K 19.7K 20.8K 21.5K 22.4K 23.3K 24.3K 25.5K 26.6K 28.0K 29.4K 31.1K 32.9K 35K 37.2K 39.9K 43.0K 46.6K 51.4K 56K 62.2K 70K 80.4K 93.9K 112K 140K 187K 280K 560K 0K 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 70K//35K = 23.3K 280K//140K = 93.3K 560K//280K = 186.6K 140K//35K = 28K 280K//35K = 31.1K 560K//35K = 32.9K 140K//70K = 46.6K 280K//70K = 56K 560K//70K = 62.2K 1//2 = 18.56K 10//560K = 17.96K 1 2 3 4 5 6 7 8 9 10
252K E Equivalence Resistance 13K 252K F Equivalence Resistance 13K
Variable Resistance (5bit)
35K
70K
140K
280K
560K
Comments
26K
5bit
42
RF AMP & SERVO SIGNAL PROCESSOR
S1L9225X
TRACKING GAIN CONTROL CONCEPT
F F Beam E E Beam I/V AMP 5bit (G4-G0) From Micom I/V AMP
-
Arrary Controlled by 5bit Switch
GHI Vac GLI
+ + -
TGH
AND TGO Logic TGL
ISTAT 1 To Micom
ISTAT 2 (Trcnt) TE1 LPF 1K, 103 LPFT TE2
Operation Summary Tracking gain control is executed by comparing the previously set gain set value of the window with the only the pure AC component of the signal TESO (DC+AC) , which was extracted the resistance divide of the tracking error amp output, passed through the LPF and DC offset . The resistance divide regulates the gain by changing the 5 bit resistance combination with micom command. The tracking gain control is executed under the balance control, the same of focus loop on, spindle servo on, tracking servo off and sled servo off and controls amount of optical pick-up reflection and tracking error amp gain. External LPF cut-off freq. Is 1o 10Hz - 100Hz. The window comparator comparison level can be selected between +150mV - +300mV and +250mV - 200mV using the micom command. TGL outputs the +150mV and +250mV comparator outputs to TRCNT. TGH outputs the +300mV and +200mV comparator outputs to ISTAT. Vac < GLI Gain control completes control when TGL output is H.
43
S1L9225X
RF AMP & SERVO SIGNAL PROCESSOR
1 Window Input GHI GLI
2
3
Vac
TGH (pin19)
TGL (pin18)
Tracking Gain Control * * * * * In balance control, 16 bit data transmission changes the switch mode by 1step from $811F $8100, and , after adjustment, a separate latch pulse is not needed. The H duty check reference of TGL output of Trcnt output is above 0.1ms. The most appropriate method is chosen among the 4 control modes listed besides the ones above for control. Among the 16 bit data, the tracking balance window setting level can be selected from 0: +250mV (TGL) - +200mV (TGH), 1: +150mV (TGL) - +300mV (TGH) through the D7 bit. When the tracking gain adjust is complete, it enters the tracking & sled servo loop and TOC read.
44
RF AMP & SERVO SIGNAL PROCESSOR
S1L9225X
Gain Control Flowchart 1
Gain ADJ. Start $83F Start - Environment Setting Focus on $08 Spindle on Tracking off $20 Sled off Gain Window Level Setting
Separate environment setting is not required when controlling the gain after controlling balance +150mV - +300mV $84 1XXX +250mV - +200mV $84 0XXX
32 TEP reduction of gain ADJ. Switch from $811F -> $8100
G0 to G4 Switch Control
NO
Trcnt = H?
YES
End ADJ.
In gain control, the micom command from $811F $8100 successively executes the down command and goes status 1 to 2 3. If it reaches status 2, control ends. * Gain Control Method 1 The micom monitors the TGL output of Trcnt and, when it detects the output's H duty (0.1ms), ends. The window comparator level at this time is +150mV - +300mV. Gain Control Method 2 The micom monitors the TGO output of Istat and, when it detects the output's H duty (0.1ms), ends. The window comparator level at this time is +150mV - +300mV. Gain Control Method 3 The micom monitors the TGL output of Trcnt and, when it detects the output's H duty (0.1ms), ends. It changes the window comparator level at this time from +150mV - +300mV to +250mV - +200mV. Then it remonitors the TGL output of Trcnt, and, if it detects the output's H duty (0.1ms), control ends. If it latches the middle command between the previous micom command value and latter command value, +200mV gain control becomes possible. Gain Control Method 4 The micom monitors the TGL output of Trcnt and, when it detects the output's H duty (0.1ms), it down the micom command by 1 and control ends. The window comparator level at this time is +150mV - +300mV. Gain Control Method 5 Gain control is set to 32 steps in total and gain window is set to +250mV. (That is, start from $811F and head toward $8110) after setting $811F, it monitors the Trcnt to check whether five Trcnts were detected for 10ms. If yes, control ends, and, if not, it as gain switch is lowered by 1 step. The above process is repeated three times and the average value obtained from this repetition set as the gain control switch.
*
*
*
*
45
S1L9225X
RF AMP & SERVO SIGNAL PROCESSOR
GAIN CONTROL FLOWCHART 2
Gain ADJ. Start $811F
Start - Environment Setting Focus on $08 Spindle on Tracking off $20 Sled off Balance Window Level Setting
Separate environment setting is not required when controlling the gain after controlling balance +150mV - +300mV $84 1XXX +250mV - +200mV $84 0XXX
32 TEP reduction of gain ADJ. Switch from $811F -> $8110
G0 to G4 Switch Control
NO
Are there 5 Trcnt for 100ms?
YES
Gain switch seting after averaging the 3 repeats
End ADJ.
46
RF AMP & SERVO SIGNAL PROCESSOR
S1L9225X
Tracking Gain Equivalent Resistance
Tracking Gain Data TERR Gain $811F $811E $811D $811C $811B $811A $8119 $8118 $8117 $8116 $8115 $8114 $8113 $8112 $8111 $8110 $810F $810E $810D $810C $810B $810A $8109 $8108 $8107 $8106 $8105 $8104 $8103 $8102 $8101 $8100 0.096 0.272 0.428 0.567 0.662 0.777 0.882 0.977 1.043 1.144 1.200 1.269 1.317 1.378 1.434 1.487 1.548 1.636 1.714 1.783 1.860 1.888 1.941 1.988 2.021 2.0625 2.100 2.134 2.158 2.189 2.217 2.243 TERR Gain 96K/32K x 3.0 5Bit Gain Ratio 0.032 0.090 0.142 0.189 0.220 0.259 0.294 0.325 0.347 0.381 0.400 0.423 0.439 0.459 0.478 0.495 0.516 0.545 0.571 0.594 0.620 0.629 0.647 0.662 0.673 0.6875 0.700 0.711 0.719 0.729 0.739 0.747 Proportional Resistance 15.0K 15.0K 15.0K 15.0K 15.0K 15.0K 15.0K 15.0K 15.0K 15.0K 15.0K 15.0K 15.0K 15.0K 15.0K 15.0K 7.5K 7.5K 7.5K 7.5K 7.5K 7.5K 7.5K 7.5K 7.5K 7.5K 7.5K 7.5K 7.5K 7.5K 7.5K 7.5K Combined Resistance 0.5K 1.5K 2.5K 3.5K 4.25K 5.25K 6.25K 7.25K 8.0K 9.25K 10.0K 11.0K 11.75K 12.75K 13.75K 14.75K 8.0K 9.0K 10.0K 11.0K 12.25K 12.75K 13.75K 14.75K 15.50K 16.50K 17.50K 18.50K 19.25K 20.25K 21.25K 22.25K 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 The gain at ratio is calculated in the TSIO terminal. 7.5K 7.5K 3.75K 2.0K 1K Comments
47
S1L9225X
RF AMP & SERVO SIGNAL PROCESSOR
EXAMPLE OF SYSTAM CONTROL
Disc Change
Power ON CLOSE
Disc Tray Check OPEN Replay TIME Loading
100ms Maximum
Focus Error Febias Automatic Control Start $8780+$87F0+$841 transfer
100ms ISTAT L -> H?
100ms Maximum
Focus Offset Cancel Automatic Control Start $08+$867+(200ms wait)+ $86F+$842 transfer
100ms ISTAT L -> H?
Tracking Offset Cancel Start $8F1F -> $8F00 (ISTAT->H) Laser Diode ON LD ON, P-SUB $8560 Transmission Limit SW Check
2s Maximum
Focusing Auto-Focusing $47 Transmission NO Focus OK? FOK H? NO TRY Count 3? YES Laser OFF $85C0 Transmission Display (no disc) Tracking Balance Adjust Standby Tracking Gain Adjust
YES Spindle Servo Loop ON Tracking & Sled Loop OFF $20 Transmission
300ms Maximum
TOC Read OK? PASS Disc 8/12Cm Check Play Back
FAIL
Laser OFF $85C0 Transmission Display (error), TRAY Open Standby
48
RF AMP & SERVO SIGNAL PROCESSOR
S1L9225X
FEBIAS OFFSET CONTROL
164K vb va 32K 32K + 160K 4K X1 X2 X4 X8 3K + vc + fcmpo
13 FSEO
Febias offset control starts when it receives the febias offset control start command $841X from the micom. Febias offset control ends when the focus error amp output above 1/2 VDD after the focus output with 1/2 VDD at the focus error amp final output terminal. The voltage per 1 step of the focus offset control is approximately 17mV. The 5bit resistance DAC changes from 112mV up to - 112mV in 1 step, after which 1/2 step, approximately -8mV offset, is applied. The offset dispersion after febias offset control exists between -8mV - +8mV. The time per 1 step is 5.8ms; for 5 bits and total of 32 steps, the maximum required time is 256ms. Hardware performs the control from minus offset to plus offset. The febias offset re-control is when 4bit DAC is reset by $8780. And Reset can be canceled only when the $87F0 applied D2 bit is changed from 0 1. The Febias DAC latch block reset for electrostatics and system operation is reset by Micom DATA and not by RESET terminal, the system reset.
49
S1L9225X
RF AMP & SERVO SIGNAL PROCESSOR
FOCUS OFFSET CONTROL
FSET 09 VC 3.6K 60K
+ +
to Digital
FSI 14 470K FDFCT 12 DFCTI FS3 FGD 26 580K
FZC I 20K
+
36 FEO
48K
Focus Phase Compensation FS2B
82K 40K
+
FS4B 470K 40K
35 FEM 10K 50K
+ -
PS 4 X1 X2 X3 X4 25 FLB 0 0 1 1 3 0 1 0 1
5K FS1
08 FRCH
Focus Offset control starts when it receives the Focus Offset control start command $842X from micom. Focus Offset control ends when the focus error amp output below 1.2 VDD after the focus output with 1/2 VDD at the focus error amp final output terminal. The voltage per 1 step of the focus offset control is approximately 40mV. The 4 bit resistance DAC changes from 320mV up to -320mV in 1 step, after which 1/2 step, approximately 20ms offset, is applied. The offset dispersion after Focus offset control exists between -20mV - +20mV. The Febias Offset can be changed in 10mV step within the micom's 100mV range after focus offset control. The required per 1 step is 5.8ms; for 4 bits and total of 16 steps, the maximum required time is 128ms. Also, lens-collision-sounds can be generated when adjusting the pick-up with a sensitive focus actuator, so the Time division that uses 46 ms per step, spending a total of 736 ms, is used. The adjustment is carried out by Hardware, and it goes from plus offset to minus offset. For focus offset readjust, 4-bit DAC is reset by $867, and reset can be canceled only when the $86FX applied D2 bit is changed from 0 1. The Febias DAC latch block reset for electrostatics and operation error is reset by micom DATA and not by RESET terminal, the system reset.
50
RF AMP & SERVO SIGNAL PROCESSOR
S1L9225X
Febias Offset Setting Febias Control The FEBIAS offset control is automatically controlled to 0mV and can be controlled to 100mV. After the focus offset automatic control ends after FEBIAS offset automatic control, the command sets the internal positive and negative offsets in 10mV units to the micom. RF SUMMING AMPLIFIER APPICATION The internal switch for the 1x and 2x filter select turns on when it is 1x and off, when 2x. The time constant to fit the set. The RF 1/V AMP can be controlled to 0.5X 16Step up to 1X - 8X CD-R and CDRW. The information related to CDR, CDRW disc detector is output as RFO level through the ISTAT. The RFO offset control is installed to prevent RF level clipping during low RFO voltage and the RFO offset information is output to ISTAT so that micom can know the RFO information.
33pF RFM2 CDRW Gain Sel PDA 49 PDC 50 47K 47K
+
33pF
61 62 RFM 22K 2pF
10K
+
79
RFO
VC CDRW Gain Sel PDB 51 PDD 52 47K 47K
+
10K
RF Offset Control
IV AMP
51
S1L9225X
RF AMP & SERVO SIGNAL PROCESSOR
RF EQUALIZE & AGC
Vin (t) Vcagc (t)
Modulator
Vo(t) =
Vo (t)
3x Gain AMP
HPF (3dB: 50kHz)
R5 (7.5K) Vcagc(t) Vin (t) tanh ( R6 (5.5K) 2Vt
)
Vin(t) = 0.73x (RFO)
EQO-AGC Output Iout = 2gm (Vid/2) = gm * Vid = (Iref) * (Vid/Vt) = Iref * (Vp-Vn)/Vt
V = I/C (115pF) Vp + Vn
if Vn > Vp Vcagc Increment (tanh (1-X)) if Vn < Vp Vcagc Decrement (tanh (1+X))
I/V Converter Control Range I * 10K
Full Wave Rectifier (RF Peak Envelope)
tanh tanh tanh tanh 0.1 = 0.5 = 0.1 = 2.0 = 0.1 0.462 0.7 0.964
Vref
The modulator output, which had the Veqc's Tanh term multiplied at the input, passes through the approximately 3X gain terminal to the ARF pad. On the one hand, the output is - rectified as it passes through the HPF having 50kHz pole frequency and follows the peak envelope the RF level. At this time, the pole frequency of the HPF is set to 50kHz so that the 3T - 11T component can pass through without attenuation. The RF level peak value is integrated at the 's CAP node after wave rectification. If this peak value is less than the already set voltage comparison, sinking current is output and, if not, sourcing current is output. The maximum peak value at this time is 10uA, which is I/V converted and applied as the modulator control voltage. Under the sinking condition, the Vcagc increases to 1outx10K and multiplied by Tanh (1-X); the sourcing condition, Vcagc decreases to Iout x10K and multiplied by Tanh (1+X), where X is (Veqc/2Vt). Overall, after detecting the 3T and 11T levels by full-wave rectification, it is compared to Tanh using the modulator and multiplied to the gain to realize the wave-form equalize. The above is related to the AGC concept, which means that a specific RF level is always taken
52
RF AMP & SERVO SIGNAL PROCESSOR
S1L9225X
OTHER BLOCK Tracking Error Amplifier The side spot photo diode current input to terminals E and F passes through the E Loop I-V and F Loop I-V Amps. It is then converted into voltage, in order to gain the difference signal in the Tracking Error Amp. This portion can perform 0.5X 16 step gain control up to 1X-8X for CD-R and CD-RW. Has the micom programming, which controls the balance by controlling gain at the E terminal and controls the gain at TEIO.
TEIO 44
LPFT2 46
PDF 53
CD-RW, CD Gain Sel CD-RW, CD Gain Sel
+
Win Comp B_REF_CN Win Comp 18 ISTAT2
PDE 54
16R8R 4R2R R Gain_UP/D Gain < 4:
G_REF_CNTR
BAL < 4:0 >
Focus OK circuit Focus Ok circuit makes the timing window, which turns on the focus in the focus search state by "output" FOK as L H if the RF level is above the reference after the difference in DC between and RFO terminals extracted and compared to the reference DC value.
40K RFO 63 EQI 64 40K 40K
+
57K 90K VC + 0.625V
+
FOKB
53
S1L9225X
RF AMP & SERVO SIGNAL PROCESSOR
MIRROR CIRCUIT After amplifying the RFI signal, the mirror signal peak and bottom holds. Peak hold can follow even at defect type traverse and bottom hold counts the tracks by following RF envelop at a jump. The mirror output is "L" on the disc track and "H" between tracks. Even if above 1.4 ms is detected, it outputs "H".
+
1.5K
05 MCP
38K EQI 64 17K
+
80K Peak and Bottom Hold 17K
+
96K
19K
+ -
MIRROR
EFM Comparator The EFM Comparator makes the Rf signal into a secondary signal. The Asymmetry generated by a fault during Disc production cannot be eliminated by only AC coupling, so control the standard voltage of the EFM Comparator to eliminate it.
- RF Double Asymmetry Conection - EFMI Peak Prevention System - Asymmetry Hold System - Asymmetry Gain Control
x5
27 ASY 28 EFM2
EFMI 02 40K
+
29 EFM
54
RF AMP & SERVO SIGNAL PROCESSOR
S1L9225X
Defect Circuit After RFO signal inversion, bottom hold is carried out using only 2. Except, the bottom hold of holds the coupling level just before the coupling. Differentiate this with the coupling, then level shift it. Compare the signals to either direction to generate the defect detect signal.
DCC1 DCC2 03 04 75K RFO 63 37.5K
+
DEFECT Bottom Envelope Bottom Envelope 43K
+
28K 75K VC+0.6254V VC
06 DCB
APC Circuit When the laser diode operates in electrostatic field, the laser output temperature highly negative so the monitor photo diode controls the laser output at a fixed level. The laser control system is installed to absorb the deviation of the disc reflection. System controls the laser power using the tracking summing signal of the side beam to a fixed laser output.
LDON PD 48
+ -
5K 5K
55K
+ -
0.25K
47 LD
55K 5K
55K Laser Control
55
S1L9225X
RF AMP & SERVO SIGNAL PROCESSOR
Center Voltage Generation Circuit The center voltage is made by using the resistance divide.
30K 30K
+
55 VREF
RF Equalize Circuit The AGC block, which maintains the RF peak to peak level, possess the 3T gain boost. It detects the RF envelop and compares it to the reference voltage to control the gain. Receives the RF output to stabilize the RF level to 1Vpeak-peak, which is applied to the EFM slice input.
EQC 37
EQI 64
VCA
Equalize
01 EQO
ATSC The detection circuit for shock tracking gain up is composed of the window comparator.
+ -
ATSC 42
BPF
Tracking Gain UP
+ -
56
RF AMP & SERVO SIGNAL PROCESSOR
S1L9225X
Focus Servo If the focus servo loop phase has been compensated, the focus servo loop mutts if the defect is. The focus error signal at this time is differentiated by the 0.1uF capacitor to be connected to the terminal and the 470kohms resistance and is output es through the servo loop. Therefore, the focus output is held to value before the defect error during defect. The FSET terminal changes the at which the focus loop compensation is at its maximum. If the resistance to VDDA connected to the terminal, the phase compensation frequency is changed 1.2kHz below, and GND connected to the terminal, the frequency is changed 1.2kHz above. During focus search, Fs4 turns on to cutoff the error signal and to output the focus search signal through the FEO. When the focus is on, FS2 turns on, and the focus error signal input through the FSI is output through the loop to the output pin.
FSET 09 VC 3.6K 60K
+ +
to Digital
FSI 14 470K FDFCT 12
FZC I 20K
+
36 FEO
48K
Focus Phase Compensation FS2B
82K 40K
+
DFCTI FS4B FS3 470K 40K
35 FEM PS 10K 50K
+ -
5K FS1
FGD 26 580K X1 X2 X3 X4 25 FLB
4 0 0 1 1
3 0 1 0 1
08 FRCH
57
S1L9225X
RF AMP & SERVO SIGNAL PROCESSOR
Tracking Servo The tracking servo phase compensate the tracking servo loop and differentiates the tracking error signal, after which it outputs the signal through the servo loop. TGU exchanges the tracking gain up/down time constant. As in the focus loop, the phase compensation peak frequency is varied by the Fset terminal. If the resistance connected to the FSET terminal changes, the OP Amp dynamic range offeset changes also.
TM4 TEIO 53 TM3 TLPFI DFCTI 680K TG1B 10K TM1 110K 82K 680K 40 TEM
68P F
TGU 16 TG2B
470K
Tracking Phase Compensation
10K
90K TM7
+
41 TEO
09 FSET
The TM7 switch is a brake switch which turns the tracking loop on/off when the actuator is unstable after a jump. After the servo jumps 10 tracks, the servo circuit leaves the linear range and the actuator sometimes pursues the unstable track, preventing unnecessary jumps from undesired tracking errors. As the terminal which controls the tracking servo loop's high frequency gain, the Tgu terminal controls the desired frequency range of the gain through the external cap.
58
RF AMP & SERVO SIGNAL PROCESSOR
S1L9225X
Sled Servo This servo differentiates the tracking servo and moves the pick-up. It also outputs the sled kick voltage to make a track jump in the sled axis during track movement.
TM6
38 SLO
TM7 PS 2 X1 X2 X3 X4 0 0 1 1 1 0 1 0 1
+ -
37 SLM 39 SLP
TM2
Spindle Servo & Low Pass Filter The 200Hz LPF, composed of an external 20kohms resistance and 0.33uF cap, eliminiates the high frequency carrier component.
22K
22K 220K 220K
+ + -
50K 100K
34 SPDLO
220K 220K
FVCO Double Speed
33 SPDLM
25 CLVI
09 FSET
59
S1L9225X
RF AMP & SERVO SIGNAL PROCESSOR
Mirror & Cpeak Mute (use only for tracking mute ) Used against ABEX-725A, this circuit processes the tracking mutting when mirror is detected. (No recommend) the tracking mutting when EFM duty is above 22T after it is checked. Mute does not operate in the following four cases. * * * * Micom tracking gain up command transmission (TG1, TG2 = 1) Anti-shock detection (ATSC) Lock falls to L Defect detection
TRCNT Output TRCNT is output of mirror and TZC. Mirror is the track movement detection output of the main beam; TZC is the track movement detection output of the side beam. TRCNT receives these two inputs to determine whether the present pick-up is moving from the inside to the outside or from the outside to the inside. It is used at $17 tracking brake operation.
MIRROR TZC Inverter Delay TZC EDGE Detection.
D
Q
Trcnt Output TZC Rising, Falling EDGE Mirror Output.
CK
60

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