View ICS670M-01_866177.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ICS670-01 Low Phase Noise Zero Delay Buffer and Multiplier
Description
The ICS670-01 is a high speed, low phase noise Zero Delay Buffer (ZDB) which integrates ICS' proprietary analog/digital Phase Locked Loop (PLL) techniques. Part of ICS' ClockBlocksTM family, the zero delay feature means that the rising edge of the input clock aligns with the rising edges of the outputs, giving the appearance of no delay through the device. There are two identical outputs on the chip. The FBCLK should be used to connect to the FBIN. Each output has its own output enable pin. The chip is ideal for synchronizing outputs in a large variety of systems, from personal computers to data communications to video. By allowing offchip feedback paths, the ICS670-01 can eliminate the delay through other devices. The 15 different on-chip multipliers work in a variety of applications. For other multipliers, including fractional multipliers, see the ICS527.
Features
* Packaged in 16 pin SOIC * Clock inputs from 5 to 160 MHz (see page 2) * Patented PLL with the lowest phase noise * Output clocks up to 160 MHz at 3.3 V * 15 selectable on-chip multipliers * Power down mode available * Low phase noise: -124 dBc/Hz at 10 kHz * Output Enable function tri-states outputs * Low jitter 15 ps one sigma * Full swing CMOS outputs with 25 mA drive capability at TTL levels * Advanced, low power, sub-micron CMOS process * Industrial temperature version available * 3.3 V or 5 V operation
Block Diagram
OE1
ICLK
FBIN S3:S0
Phase Detector, Charge Pump, and Loop Filter
Voltage Controlled Oscillator 4
ROMBased Multipliers
Output Buffer
FBCLK
Output Buffer
CLK2
External feedback from FBCLK is recommended.
OE2
1 Revision 100900 Printed 11/15/00 Integrated Circuit Systems * 525 Race Street * San Jose *CA*95126*(408) 295-9800tel*http://www.icst.com
MDS 670-01 B
ICS670-01 Low Phase Noise Zero Delay Buffer and Multiplier
Pin Assignment
VDD VDD VDD CLK2 OE2 FBCLK OE1 FBIN 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 GND GND GND S0 S1 S2 S3 ICLK Multiplier Select Table
S3 S2 S1 S0 CLK2 (and FBCLK) 0 0 0 0 Low (Power down entire chip) 0 0 0 1 Input x1.333 0 0 1 0 Input x6 0 0 1 1 Input x1.5 0 1 0 0 Input x3.333 0 1 0 1 Input x2.50 0 1 1 0 Input x4 0 1 1 1 Input x1 1 0 0 0 Input x2.333 1 0 0 1 Input x2.666 1 0 1 0 Input x12 1 0 1 1 Input x3 1 1 0 0 Input x10 1 1 0 1 Input x5 1 1 1 0 Input x8 1 1 1 1 Input x2 0=connect directly to ground 1=connect directl to VDD Input Range (MHz) 18 - 120 5 - 26.67 16.67 - 107 7.5 - 48 10 - 64 6 - 40 25 - 160 11 - 69 10 - 60 5 - 13.33 8 - 53.33 5 - 16 6 - 32 5 - 20 12 - 80
ICS670-01
Pin Descriptions
Number 1 2 3 4 5 6
7
8 9 10 11 12 13 14 15 16
Name VDD VDD VDD CLK2 OE2 FBCLK OE1 FBIN ICLK S3 S2 S1 S0 GND GND GND
Type P P P O I O I CI CI I I I I P P P
Description Connect to +3.3V or +5V. Must match other VDDs. Connect to +3.3V or +5V. Must match other VDDs. Connect to +3.3V or +5V. Must match other VDDs. Clock output from VCO. Output frequency equals the input frequency times multiplier. Output clock enable 2. Tri-states the clock 2 output when low. Clock ouput from VCO. Output frequency equals the input frequency times multiplier. Output clock enable 1. Tri-states the feedback clock output when low. Feedback clock input. Clock input. Connect to a 5 - 160 MHz clock. Multiplier select pin 3. Determines outputs per table above. Internal pull-up. Multiplier select pin 2. Determines outputs per table above. Internal pull-up. Multiplier select pin 1. Determines outputs per table above. Internal pull-up. Multiplier select pin 0. Determines outputs per table above. Internal pull-up. Connect to ground. Connect to ground. Connect to ground.
Key: I = Input with internal pull-up resistor; O = output; P = power supply connection; CI = clock input.
2 Revision 100900 Printed 11/15/00 Integrated Circuit Systems * 525 Race Street * San Jose *CA*95126*(408) 295-9800tel*http://www.icst.com
MDS 670-01 B
ICS670-01 Low Phase Noise Zero Delay Buffer and Multiplier
Electrical Specifications
Parameter Conditions Minimum Typical Maximum 7 VDD+0.5 70 85 260 150 5.5 0.8 IOH=-4mA IOH=-12mA IOL=12mA No Load Each output OE, select pins OE, select pins Depends on multiplier at 3.3V or 5V 0.8 to 2.0V, no load 0.8 to 2.0V, no load At VDD/2 Note 2 VDD-0.4 2.4 0.4 35 50 200 5 5 160 160 1.5 1.5 55 Units V V C C C C V V V V V V mA mA k pF MHz MHz ns ns % ps ps ps dBc/Hz dBc/Hz dBc/Hz dBc/Hz
ABSOLUTE MAXIMUM RATINGS (note 1) n
Supply voltage, VDD Referenced to GND Inputs and Clock Outputs Referenced to GND Ambient Operating Temperature Ambient Operating Temperature, ICS670M-01I Industrial temperature Soldering Temperature Max of 10 seconds Storage temperature -0.5 0 -40 -65 3.0 2
DC CHARACTERISTICS (VDD = 3.3 V unless noted)
Operating Voltage, VDD Input High Voltage, VIH Input Low Voltage, VIL Output High Voltage, VOH, CMOS level Output High Voltage, VOH Output Low Voltage, VOL Operating Supply Current, IDD Short Circuit Current Internal Pull-up Resistor Input Capacitance Input Frequency (see table on page 2) Output Frequency Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle Input to output skew, rising edges Maximum Absolute Jitter, short term Maximum Jitter, one sigma Phase Noise, relative to carrier, 125 MHz (x5) Phase Noise, relative to carrier, 125 MHz (x5) Phase Noise, relative to carrier, 125 MHz (x5) Phase Noise, relative to carrier, 125 MHz (x5) Notes:
AC CHARACTERISTICS (VDD = 3.3 V unless noted)
45
100 Hz offset 1 kHz offset 10 kHz offset 100 kHz offset
50 100 45 15 -110 -122 -121 -117
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability. 2. Rising edge of ICLK compared with rising edge of CLK2, with FBCLK connected to FBIN, and 15 pF load on CLK2. See the graph on page 4 for skew versus frequency and loading.
3 Revision 100900 Printed 11/15/00 Integrated Circuit Systems * 525 Race Street * San Jose *CA*95126*(408) 295-9800tel*http://www.icst.com
MDS 670-01 B
ICS670-01 Low Phase Noise Zero Delay Buffer and Multiplier
300 200 100
(ps)
CL = 20 pF
0 0 -100 -200 -300 -400 CLK2 Frequency (MHz) 25 50 75 100 125 150
Skew
CL = 10 pF
Figure 1.
ICS670-01 skew from ICLK to CLK2, with change in load capacitance. VDD = 3.3 V.
Adjusting Input/Output Skew
The data in Figure 1 can be used to adjust individual circuit characteristics and achieve the minimum possible skew between ICLK and CLK2. With a 125 MHz output, for example, having a total load capacitance of 15 pF will result in nearly zero skew between ICLK and CLK2. Note that the load capacitance includes board trace capacitance, input capacitance of the load being driven by the ICS670-01, and any additional capacitors connected to CLK2.
0
-20
Phase Noise (dBc/Hz)
-40
-60
-80
-100
-120
-140
10.0E+0
100.0E+0
1.0E+3
10.0E+3
100.0E+3
1.0E+6
10.0E+6
Offset from Carrier (Hz)
Figure 2.
Phase Noise of ICS670-01 at 125 MHz out, 25 MHz clock input. VDD = 3.3 V.
4 Revision 100900 Printed 11/15/00 Integrated Circuit Systems * 525 Race Street * San Jose *CA*95126*(408) 295-9800tel*http://www.icst.com
MDS 670-01 B
ICS670-01 Low Phase Noise Zero Delay Buffer and Multiplier
External Components Selection
The ICS670-01 requires a minimum number of external components for proper operation. Decoupling capacitors of 0.01 F should be connected between VDD and GND, as close to the part as possible. A series termination resistor of 33 may be used for each clock output.
Package Outline and Package Dimensions (For current dimensional specifications, see JEDEC Publication No. 95.)
16 pin SOIC narrow
Symbol A Inches h Min Max 0.0532 0.0688 0.0040 0.0098 0.0130 0.0200 0.0075 0.0098 0.3859 0.3937 0.1497 0.1574 .050 BSC S 0.2284 0.2440 0.0099 0.0195 0.0160 0.0500 Millimeters m Min Max 1.35 1.75 0.10 0.24 0.33 0.51 0.19 0.24 9.80 10.00 3.80 4.00 1.27 BSC S 5.80 6.20 0.25 0.50 0.41 1.27
E
INDEX AREA
H
A1
B
C
1
D A1 e Ordering Information
Part/Order Number ICS670M-01 ICS670M-01T ICS670M-01I ICS670M-01IT
h x 45
D E e H h L
B
C
A L
Marking ICS670M-01 ICS670M-01 ICS670M-01I ICS670M-01I
Shipping packaging tubes tape and reel tubes tape and reel
Package Temperature 16 pin narrow SOIC 0 to 70 C 16 pin narrow SOIC 0 to 70 C 16 pin narrow SOIC -40 to 85 C 16 pin narrow SOIC -40 to 85 C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
5 Revision 100900 Printed 11/15/00 Integrated Circuit Systems * 525 Race Street * San Jose *CA*95126*(408) 295-9800tel*http://www.icst.com
MDS 670-01 B

▲Up To Search▲

Price & Availability of ICS670M-01

	To Download ICS670M-01 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .