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OKI Semiconductor ML60841
USB Host + Device controller LSI
PEDL60841-01
Issue Date: Oct. 2, 2002
Preliminary
GENERAL DESCRIPTION
The ML60841 is a controller LSI with a device controller and a host controller that conform to the Universal Serial Bus (USB) 1.1. implemented on a single chip. By setting an external pin, the ML60841 can be used interchangeably as either a host controller or a device controller. The host controller section and device controller section support data transfer modes such as a control transfer mode, an interrupt transfer mode, a bulk transfer mode, and an isochronous transfer mode. The host controller section supports one USB port transceiver, can be connected to a USB transceiver LSI, and conforms to the OpenHCI Specification 1.0a.
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FEATURES
[Common Section] * USB 1.1 compliant * Maximum bus clock (BUS_CLK) frequency: 33 MHz * Allows host/device selection by an external terminal * 16-/32-bit bus width selectable * Little/Big endian can be selected * Common connector use/no use can be selected * Occupies 0000h to 1FFFh 8K byte space (registers: 0xxxh, internal RAM: 1000h to 1FFFh) * DMA control of high flexibility. - Supports host mode: 1 channel, device mode: 2 channels - Supports the following DMA transfer mode Transfer size: 32 bits (need to specify the same transfer size as that of the microcontroller side DMA controller) [Host Controller Section] * OpenHCI (Open Host Controller Interface) 1.0a compliant * Supports 4 data transfer types (control transfer, bulk transfer, interrupt transfer, and isochronous transfer) * Built-in 4-Kbyte RAM * DMA slave function (1 channel) reduces software load * Supports 1 USB port (supports full speed (12 Mbps) and low speed (1.5 Mbps)) * Supports SOF generation and CRC5/16 bit generation function [Device Controller Section] * Supports full speed (12 Mbps) * Supports 4 data transfer types (control transfer, bulk transfer, interrupt transfer, and isochronous transfer) * End points: 5 or 6 - Control EP : 1 (EP0) - Bulk/interrupt EP : 3 (EP1, EP2, and EP3) - Isochronous/bulk/interrupt EP : 1 or 2 (EP4 and/or EP5) * Built-in FIFO for storing data * Double-layer configuration FIFO of EP1, EP2, EP4, and EP5 * Supports 2-channel DMA slave function (EP1, EP2, EP4, and EP5) * Supports Suspend and Wakeup functions. [Others] * USB port can be connected to a USB transceiver LSI * 48 MHz crystal oscillator * 3.3 V single power supply * Package: 120-pin TQFP (TQFP120-P-1414-0.40-K) 120-pin BGA (P-TFBGA120-0909-0.65)
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XIN
OKI Semiconductor
BLOCK DIAGRAM
XOUT Register set for host D31:D00 RD/WR, CS, RD, RESET INTR DREQ0, 1 DACK0, 1 DRAK0, 1 BS Protocol engine for device Register set for device WAIT TEST1-21 Microcontroller A12:A01
Protocol engine for host BUS_CLK
ExtBuffENB OE, VPO, RCV, MODE VMO/FSEO, VP, VM, SUSPEND, SPEED Microcontroller interface FIFO
Over_Current
PCONT
USB transceiver for host/device
HD+
HD-
S.W PDCTL
SVBUS
S.W PUCTL
32/16SEL, D/H, Little/Big
DD+
DD-
USB transceiver for device
PEDL60841-01
ML60841
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PIN CONFIGURATION
120-pin TQFP (Top View)
90 61
91
60
120
31
123
30
120-pin TQFP
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Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I/O I/O I/O I/O I I/O I/O I I I/O I/O I I I I I I I I I I I I I/O I/O I/O I/O I/O I/O O I I/O I I/O I I/O I I/O Type *3 *3 *3 *1 *6 *6 *2 *2 *6 *6 *4 *4 *4 *4 *4 *4 *4 *4 *4 *4 *4 *4 *6 *6 Signal Code D2 D1 D0 GND VCC RESET TIO00 TIO01 Little/Big 32/16SEL TIO02 TIO03 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 TIO04 TIO05 GND VCC DD- DD+ TIO06 TIO07 PUCTL SVBUS TIO08 RCV TIO09 VP TIO10 VM Pin No 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 I/O I O O O I O I O I O I/O I I I/O I/O O I O I/O I/O I/O I/O I O I/O I/O I/O O O I I O I I O I I I I/O Type *2 *5 *5 *5 *2 *5 *2 *5 *2 *5 *6 *2 *2 *6 *6 *5 *4 *5 *6 *6 Signal Code TMD0 SUSPEND SPEED MODE TMD1 VPO TMD2 VMO/FSEO TMD3 OE TIO11 D/H ExtBuffENB TIO12 TIO13 PCONT
Over_Current
Pin No 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
I/O I I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
I/O Type *4 *6 *4 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3
Signal Code BS TIO19 BUS_CLK GND VCC D31 D30 D29 D28 D27 D26 D25 D24 GND VCC D23 D22 D21 D20 D19 D18 D17 D16 GND VCC D15 D14 D13 D12 D11 D10 D9 D8 GND VCC D7 D6 D5 D4 D3

*6 *6 *5 *4 *6 *4 *6 *4 *6 *4
*6 *6 *6 *5 *5 *4 *4 *5 *4 *4 *5 *4 *4 *4
PDCTL TIO14 TIO15 HD- HD+ GND VCC XIN XOUT TIO16 TIO17 TIO18 INTR DREQ0 DACK0 DRAK0 DREQ1 DACK1 DRAK1 WAIT CS RD/WR RD
Note: I/O types *1: TTL Schmitt Input Buffer with 4X Drive, *2: TTL Input Buffer with 4X Drive/50K Pull Up, *3: I/O Buffer with TTL Input/4mA Output, *4: TTL Input Buffer with 4X Drive, *5: Push Pull Output Buffer with 4mA Drive, *6: I/O Buffer with TTL Input/4mA Output 50K Pull Up
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120-pin BGA (Top View)
13 D2 D1 VCC TIO0 1 TIO0 2 A11 A8 A5 A2 TIO0 5 VCC DD+ TIO0 6 A D3 D4 D0 TIO0 0
32/16 SEL
D7 D6 GND RES ET Little/ Big TIO0 3 A10 A7 A4 A1 RCV SVB US PUC TL C
GND D8 D5
D10 D9 VCC
D13 D12 D11
VCC D15 D14
D17 D16 GND
D20 D19 D18
D23 D22 D21
D24 GND VCC D28 D31
BUS _CLK
D26 D27 D30 GND BS CS DAC K1 DAC K0 TIO1 8 XOU T VCC HD+ TIO1 4 M
D25 D29 VCC TIO1 9 RD/ WR DRA K1 DRA K0 INTR TIO1 6 XIN 03 GND 02 HD- TIO1 5 N 01 10 09 08 07 06 05 04 12 11
A12 A9 A6 A3 TIO0 4 GND DD- TIO0 7 B
RD WAI T 1-pin mark DRE Q1 DRE Q0 TIO1 0 TIO0 9 TIO0 8 D SUS PEN D VM VP E TMD 1 SPE ED TMD 0 F VMO/ FSEO VPO MO DE G TIO1 1 TMD 3 TMD 2 H TIO1 2 D/H OE J Over_C urrent TIO1 3
ExtBu ffENB
TIO7 PDC TL PCO NT L
K
120-pin BGA
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Pin No A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 D01 I/O I/O I/O I/O I I I I I/O I/O I/O I/O I/O I/O I/O I I I I I I/O I/O I/O I/O O I I I I I I I/O I I I/O I/O I/O I/O Type *6 *6 *4 *4 *4 *4 *6 *6 *3 *3 *6 *6 *4 *4 *4 *4 *2 *6 *3 *3 *3 *5 *4 *4 *4 *4 *4 *4 *6 *2 *1 *3 *3 *6 Signal Code TIO06 DD+ VCC TIO05 A2 A5 A8 A11 TIO02 TIO01 VCC D1 D2 TIO07 DD- GND TIO04 A3 A6 A9 A12 32/16SEL TIO00 D0 D4 D3 PUCTL SVBUS RCV A1 A4 A7 A10 TIO03 Little/Big RESET GND D6 D7 TIO08 Pin No D02 D03 D11 D12 D13 E01 E02 E03 E11 E12 E13 F01 F02 F03 F11 F12 F13 G01 G02 G03 G11 G12 G13 H01 H02 H03 H11 H12 H13 J01 J02 J03 J11 J12 J13 K01 K02 K03 K11 K12 I/O I/O I/O I/O I/O I I O I/O I/O I O I I/O I/O I/O O O O I/O I/O I I I/O I/O I/O O I I/O I/O I/O I/O I I/O I I/O I/O I/O Type *6 *6 *3 *3 *4 *4 *5 *3 *3 *2 *5 *2 *3 *3 *3 *5 *5 *5 *3 *3 *2 *2 *6 *3 *3 *5 *2 *6 *3 *3 *3 *2 *6 *4 *3 *3 Signal Code TIO09 TIO10 D5 D8 GND VP VM SUSPEND VCC D9 D10 TMD0 SPEED TMD1 D11 D12 D13 MODE VPO VMO/FSEO D14 D15 VCC TMD2 TMD3 TIO11 GND D16 D17 OE D/H TIO12 D18 D19 D20 ExtBuffENB TIO13
Over_Current
Pin No K13 L01 L02 L03 L04 L05 L06 L07 L08 L09 L10 L11 L12 L13 M01 M02 M03 M04 M05 M06 M07 M08 M09 M10 M11 M12 M13 N01 N02 N03 N04 N05 N06 N07 N08 N09 N10 N11 N12 N13
I/O I/O O O I/O O O O I I I/O I/O I/O I/O I/O O I/O I I I I I/O I/O I/O I/O I/O I I/O O I I I I/O I/O I/O
I/O Type *3 *5 *5 *6 *5 *5 *6 *4 *4 *3 *3 *3 *6 *6 *4 *4 *4 *4 *3 *3 *3 *6 *6 *5 *4 *4 *4 *6 *3 *3
Signal Code D23 PCONT PDCTL TIO17 DREQ0 DREQ1 WAIT RD BUS_CLK D31 D28 VCC GND D24 TIO14 HD+ VCC XOUT TIO18 DACK0 DACK1 CS BS GND D30 D27 D26 TIO15 HD- GND XIN TIO16 INTR DRAK0 DRAK1 RD/WR TIO19 VCC D29 D25
D21 D22
Note: I/O types *1: TTL Schmitt Input Buffer with 4X Drive, *2: TTL Input Buffer with 4X Drive/50K Pull Up, *3: I/O Buffer with TTL Input/4mA Output, *4: TTL Input Buffer with 4X Drive, *5: Push Pull Output Buffer with 4mA Drive, *6: I/O Buffer with TTL Input/4mA Output 50K Pull Up
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PIN DESCRIPTIONS
Description of each pin is given below. Pins having "-" attached to their symbols are "active low" pins and those having nothing attached are "active high" pins.
Symbol XIN, XOUT BUS_CLK Little/Big Pin Count 2 1 1 I/O -- I I Description Input/output pins for externally connecting a crystal oscillator. Input pin for synchronizing clock from a microcontroller. Maximum frequency: 33 MHz Input pin for specifying data bus specification of microcontroller interface. With an internal 50 k pull-up resistor. "L": Big endian, "H": Little endian Input pin for selecting host/device function. With an internal 50 k pull-up resistor. "L": Host, "H": Device Enabled only after the RESET signal is active (this signal is disabled after setting by an internal register). USB bus power supply control (ON/OFF) output pin in host mode. "L": ON, "H": OFF USB bus power supply trouble (overcurrent etc.) informing input pin in host mode. "L": abnormal, "H": normal External USB transceiver enable control input pin. With an internal 50 k pull-up resistor. "L": External USB transceiver disable (not used) "H": External USB transceiver enable (used) When using this LSI in the device controller mode with this pin in the enabled state ("H"), set the bit 00 of the common connector used/not used select register (address: 04h) to common connector used "1" state. The operation cannot be guaranteed if the common connector not used setting "0" is made. See the descriptions of the ConSel register for details. USB bus power supply sense input pin. It is necessary to provide an input to this pin that disables the USB power supply sense except only when the power supply of the USB interface is truly valid. "L": USB Interface VBUS disabled, "H": USB interface VBUS enabled USB bus input/output pins for host/device. Since this pin will be in the input state during the device controller mode when the common connector not used setting (bit 00 is "0" in the common connector used/not used select register (address: 04h) and when the external USB transceiver used setting (ExtBuffEN = "H") is made, tie the input level of this pin to "H" or "L". USB bus input/output pins exclusively for device. When the host controller mode has been set, or when the external USB transceiver used setting (ExtBuffEN = "H") has been made, tie the input level of this pin to "H" or "L" since this pin will be in the input state. Output pin for pull-up control of USB bus input/output pins in device mode. "L": pull-up enable, "H": pull-up disable Output pin for pull-down control of USB bus input/output pins in host mode. "H": pull-down enable, "L": pull-down disable Input/output pins for data bus. An invalid data will be output when read out in the 16-bit mode. Also, since these pins will be in the input state at all times other than reading out, keep the input levels of these pins tied to "H" or "L". Input/output pins for data bus. Enabled in 16-bit mode.
D/H
1
I
PCONT
Over_Current
1 1
O I
ExtBuffENB
1
I
SVBUS
1
I
HD+, HD-
2
I/O
DD+, DD-
2
I/O
PUCTL PDCTL D31:D16 D15:D0
1 1 16 16
O O I/O I/O
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Symbol 32/16SEL A12:A1 CS RD/WR RD INTR (*) WAIT RESET DREQ0 (*) DACK0 (*)
Pin Count 1 12 1 1 1 1 1 1 1 1
I/O I I I I I O O I O I
Description Input pin for selecting 32-bit/16-bit data bus width. With an internal 50 k pull-up resistor. "L": 16-bit, "H": 32-bit Input pins for address from microcontroller. (For accessing an internal 4 KB RAM and an internal register) Input pin for chip select signal from microcontroller. Input pin for RD/WR signal from microcontroller. Input pin for RD signal from microcontroller. Output pin for interrupt request to microcontroller. Output pin for wait request to microcontroller. Set the microcomputer so that this signal is sampled on the falling edge of the "BUS_CLK" signal. Reset input pin. Output pin for DMA request to microcontroller (used when HOST and Device are operating). Input pin used to indicate that DMA cycling is in progress (used when HOST and Device are operating). When not used, tie the input level of this pin to the inactive level. Input pin used to indicate that DMA has received the "DREQ0 signal" (used when HOST and Device are operating). When connecting to a microcontroller without the "DRAK" pin, connect to the "DACK" pin. When not used, tie the input level of this pin to the inactive level. Output pin for DMA request to microcontroller (used when Device is operating). Input pin used to indicate that DMA cycling is in progress (used when Device is operating). When not used, tie the input level of this pin to the inactive level. Input pin used to indicate that DMA has received the "DREQ0 signal" (used when Device is operating). When connecting to a microcontroller having no "DRAK" pin, connect to the "DACK" pin. When not used, tie the input level of this pin to the inactive level. Input pin for bus start (BS) signal from microcontroller. External USB transceiver input/output selector output pin. "L": transmit mode (ML60841 to USB), "H": receive mode (USB to ML60841) Pins for output to an external USB transceiver. The ML60841 outputs the status shown in the following Result column in combinations of 3 signal lines, as shown below. MODE VPO VMO/FSEO Result 0 0 0 Logic "0" 0 0 1 SE0# 0 1 0 Logic "1" 0 1 1 SE0# 1 0 0 SE0# 1 0 1 Logic "0" 1 1 0 Logic "1" 1 1 1 Illegal code Input pin for receive data from an external USB transceiver. When not used, tie the input level of this pin to "H" or "L".
DRAK0 (*) DREQ1 (*) DACK1 (*) DRAK1 (*) BS OE (**)
1 1 1
I O I
1 1 1
I I O
MODE (**), VPO (**), VMO/FSEO (**)
3
O
RCV (**)
1
I
(*) Active level can be changed by setting register. (**) Signal lines for connecting the host/device common USB ports to an external USB transceiver.
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Symbol
Pin Count
I/O
Description Input pins for external USB transceiver. The ML60841 operates by judging the status shown in the following Result column in combinations of 2 signal lines, as shown below. VP VM Result 0 0 SE0# 0 1 Low speed 1 0 Full speed 1 1 Error When not used, tie the input level of this pin to "H" or "L". Output pin used to notify an external USB transceiver that the SUSPEND status will be entered when the USB bus is not used. "L": specify non-SUSPEND, "H": specify SUSPEND Output pin used to notify an external USB transceiver of the USB bus speed. "L": low speed, "H": full speed Input/output pins for testing (normally left unconnected). Input pins for testing. With an internal 50 k pull-up resistor (normally left unconnected). VCC GND
VP (**), VM (**)
2
I
SUSPEND (**) SPEED (**) TIO00 to 19 TMD0 to 3 VCC GND Total
1 1 20 4 7 7 120
O O I/O I -- --
(**) Signal lines for connecting the host/device common USB ports to external USB transceiver.
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REGISTER
The registers of the ML60841 are divided mainly into common registers, host controller registers and device controller registers. Approximate categorywise map of addresses is as follows.
Category Common register Host controller register Device controller register Host controller memory Offset 000h-0FFh 100h-2FFh 200h-3FFh 1000h-1FFFh Internal 4 KB RAM OpenHCI control register included Remarks
Mapping of each register is shown on next page onward. The meanings of "R", "W", and "R/W" are the following in the register descriptions given hereafter. R: Only read operation is valid. Unless specifically described in the descriptions of the different registers, there will be no effect on the operations even when a "0" or a "1" is written to the concerned part. W: Only write operation is valid. Unless specifically described in the descriptions of the different registers, an uncertain data will be returned when the concerned part is read out. R/W: Both read and write operations are valid. In the following description of registers, operation cannot be guaranteed when an unspecified address is accessed. Therefore, control the LSI operation so that such an address will not be accessed. Moreover, since operation cannot be guaranteed when a "1" is written in an unspecified field of specified registers, write a "0" in an unspecified field when writing in other fields. Also, if the device controller registers (registers 300h to 3FFh) are accessed during operations as a host controller, or if the host controller registers (registers 100h to 2FFh) and host controller memories (1000h to 1FFFh) are accessed during operations as a device controller, the operations of the function being executed currently (host controller function in the former case and device controller function in the latter case) cannot be guaranteed and hence controls should be implemented so as not to make such access. The meaning of "Don't Care" and "X" is as follows. When writing: There is no affect on the operation of the ML60841 by writing either "0" or "1". When reading: Undefined data is read. In the ML60841, it is possible to specify combinations of big-endian or little-endian and 16-bit bus width or 32-bit bus width as the data bus specifications. Depending on these combinations, there are some restrictions on the register (memory) accesses of different blocks. Implement controls to observe the following restrictions. The operations cannot be guaranteed if these restrictions are not observed. When using a 16-bit bus width, carry out one set of the two accesses to the offset address and offset address +2 when accessing the host controller registers (including the OpenHCI operation register) and the host controller memories. The data is written to the concerned register or memory when the 32-bit data becomes ready within the ML60841. When using a 16-bit bus width, write data of bits 15:0 to the offset address of a common register in the case of both the big-endian and the little-endian modes. In other words, when using a 16-bit bus width, carry out writes using instructions that handle 16-bit data.
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Types and Mapping of Common Registers
Offset 000h 004h 008h 00Ch 010h 014h 018h 01Ch Symbol HostDevSel ConSel PolModeSel DmaMode0 DmaMode1 HdVbusIntStt HdVbusIntMask SrstPDownCtl Host/Device select register Common connector use/no use select register Pin polarity and USB transceiver mode select register DMA0 mode setting register DAM1 mode setting register Interrupt status register for a status change in the D/H pin and VBUS Interrupt mask register for a status change in the D/H pin and VBUS Software reset/Power down control register Name
* HostDevSel Register (000h)
Bits 31:02 01 Don't care Indicates that the ML60841 is under internal processing when changing the D/H pin setting or bit 00 set value. 0: Not under internal processing, 00 Specifies Host or Device function. 0: Host, 1: Device 1: Under internal processing Note R/W Field Reset X 0b R/W X R
Note) Depends on the status of the D/H pin. [Description] By writing in bit 00, host/device selection is possible irrespective of the D/H pin status. For example even if D/H pin is at device setting, it is possible to operate as host by writing "0000h" in this register. However, after writing in this register, change of D/H pin setting is ignored. (An interrupt is generated due to a change in the state of the D/H pin the status changes.) When change occurs in value set in bit 00, the ML60841 resets both the host block and the device block internal to the LSI. During reset, bit 01 gets set at "1" and then becomes "0" when reset is completed and operation becomes possible. Therefore, after change in setting, it is necessary for the microcontroller to execute initialization. Start initialization after bit 01 has become "0". See "Precautions in control of ML60841" for details related to the timing of starting the initialization processing. * ConSel Register (004h)
Bits 31:01 00 Don't care Specifies common connector use/no use. 0: Common connector not used 1: Common connector used 0b R/W Field Reset X R/W X
[Description] When common connector is used, the operation becomes as follows. * In Host mode: the HD+ and HD- pins are designated for host. * In Device mode: the HD+ and HD- pins are designated for device.
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When common connector is not sued, the operation becomes as follows. * In Host mode: the HD+ and HD- pins are designated for host. * In Device mode: the DD+ and DD- pins are designated for device. Set this bit to "1" to select the common connector used state when the external transceiver used setting has been made (ExtBuffEN= "H") when using the device controller operations. The operations cannot be guaranteed when the common connector not used setting "0" is made here. The relationship between the setting of this bit and the USB buffer status is shown below.
Operating mode Pin name HD+/HD- DD+/DD- Host controller OE, VMO/FSEO, VPO, RCV, VM, VP, SUSPEND (External USB buffer pins) HD+/HD- DD+/DD- Device controller OE, VMO/FSEO, VPO, RCV, VM, VP, SUSPEND (External USB buffer pins) This bit = "0" (Common connector not used) ExtBuffENB="L" ExtBuffENB="H" Power down Valid state Power down Power down state state Unused state* Power down state Valid Valid Illegal specification Illegal specification Illegal specification This bit = "1" (Common connector used) ExtBuffENB="L" ExtBuffENB="H" Power down Valid state Power down Power down state state Unused state* Valid Power down state Power down state Valid
Valid Power down state Unused state*
Unused state*
* The unused state is the following: * Input pin: Tied to "H" or "L" level * Output pin: Inactive level output (excepting the MODE, SPEED and SUSPEND pins) * SUSPEND pin: "H" level output
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* PolModeSel register (008h)
Bits 31:08 07 06:04 03 02 01 00 Don't care Field Reset X 1: MODE1 0b X 0b 0b 0b 0b R/W X R/W X R/W R/W R/W R/W
Specifies the mode signal to an external USB transceiver.
0: MODE0, Don't care
Specifies the polarity of the INTR signal.
0: Active Low, 1: Active High
Specifies the polarity of the DACK signal.
0: Active Low, 1: Active High
Specifies the polarity of the DRAK signal.
0: Active Low, 1: Active High
Specifies the polarity of the DREQ signal.
0: Active Low, 1: Active High
[Description] Bit 07 sets the value ("0" = "L" or "1" = "H") output to the MODE pin. Bits 03 to 00 set active level of each pin (INTR; DACK0, DACK1; DRAK0, DRAK1; DREQ0, DREQ1). Setting "0" makes the level active low and setting "1" makes it active high. Two each of "DACK0/1", "DRAK0/1" and "DREQ0/1" are provided for each DMA channel, but by setting this register the two get set to the same active level. * DmaMode0 Register (00Ch), DmaMode1 Register (010h)
Bits 31:04 Don't care Specifies the data bit length for one time of "DREQ". 11: Illegal specification 10: 32 bits 03:02 1 transfer/32 bits, 2 transfers/16 bits 01: Illegal specification 00: Illegal specification Set "10" in this field. Operation is not guaranteed if a value other than "10" is set. 01 00 Don't care. Don't care. X X X X 10b R/W Field Reset X R/W X
[Description] The settings of bits 03:02 and the operations are as follows: * When the data bus width is 32 bits ("32/16 SEL" pin is "H") In one DMA transfer, 32 bits of data are transferred by asserting "DREQ" once. * When the data bus width is 16 bits ("32/16 SEL" pin is "L") 16 bits of data are transferred twice by asserting "DREQ" once in one DMA transfer. The address in this case will have to be made `n+2' during the second transfer if the address during the first transfer was `n' (which should be a multiple of 4). For example, when transferring data to or from the host controller register FIFO ACC (20Ch), it is necessary to specify the addresses repeatedly in the sequence 20Ch 20Eh 20Ch 20Eh ..... 20Eh 20Ch 20Eh (the starting address is 20Ch and the ending address is 20Eh). Similarly, when transferring data to or from the device controller EP1 transmit/receive FIFO register (388h), it is necessary to specify the addresses
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repeatedly in the sequence 388h 38Ah 388h 38Ah .... 388h 38Ah (the starting address is 388h and the ending address is 38Ah). * HdVbusIntStt Register (014h)
Bits 31:10 09 08 07:02 01 Don't care Indicates the status of the SVBUS pin. 0: VBUS inactive, 1: VBUS active Indicates the status of the D/H pin. 0: Host, Don't care Indicates the status change of the SVBUS pin. 0: No change, 1: Change Clear this bit by writing a "1" in it. Indicates the status change of the D/H pin. 00 0: No change, 1: Change Clear this bit by writing a "1" in it. 0b R/W 0b R/W 1: Device Field Reset X Note 1 Note 2 X R/W X R R X
(Note 1) (Note 2)
Goes into the status of the SVBUS pin. Goes into the status of the D/H pin.
[Description] Bit 09 reflects the status of the SVBUS pin. Bit 08 reflects the status of the D/H pin. The status may not agree with the current operating mode (Host/Device), because this bit only reflects the D/H pin status even if setting is changed by the HostDevSel register. For example, when the D/H pin is at "H" level (Device setting) and "0 (Host function specified)" is written in bit 00, this bit 08 indicates "1 (Device)", but the ML60841 is in the Host operating mode. To know the current operating mode, read the HostDevSel register. Bit 01 gets set to "1" when the status of the SVBUS pin changes. At this time, if the bit corresponding to the HdVbusIntMask register is interrupt enable, an interrupt occurs. This bit can be cleared by writing a "1" in it. Bit 01 gets set to "1" when the D/H pin status changes. At this time, if the bit corresponding to the HdVbusIntMask register is interrupt enable, an interrupt occurs. This bit can be cleared by writing a "1". When a change occurs in the state of the SVBUS pin before this bit is cleared (that is, multiple causes of this interrupt are present), all the interrupt causes will be cleared when a "1" is written to this bit (the causes are not queued). For example, if the state of the SVBUS pin has changed several times before this bit has been cleared, the value of bit 09 after the interrupt may become the same as the value of bit 09 before the interrupt. Therefore, it is necessary that the microcomputer reads the value of bit 09 and confirms the status of SVBUS. Bit 00 will be set to "1" when there is a change in the state of the D/H pin. An interrupt is generated at this time if the interrupt has been enabled in the corresponding bit of the HdVbusIntMask register. When a "1" has been set in this bit, this bit can be cleared by writing a "1". When a change occurs in the state of the D/H pin before this bit is cleared (that is, multiple causes of this interrupt are present), all the interrupt causes will be cleared (the causes are not queued) when a "1" is written to this bit. For example, if the state of the D/H pin has changed several times before this bit has been cleared, the value of bit 08 after the interrupt may become the same as the value of bit 08 before the interrupt. Therefore, it is necessary that the microcomputer reads the value of bit 08 and confirms the status of D/H.
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* HdVbusIntMask Register (018h)
Bits 31:02 Don't care Specifies whether to generate an interrupt or not when the SVBUS pin status changes. 0: Interrupt disable 1: Interrupt enable Specifies whether to generate an interrupt or not when the D/H pin status changes. 0: Interrupt disable 1: Interrupt enable Field Reset X R/W X
01
0b
R/W
00
0b
R/W
[Description] Bits 00 and 01 set whether or not to generate an interrupt when the status of bits 01 and 00 of the HdVbusIntStt register changes to "1".
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* SRstPDownCtl Register (01Ch)
Bits 31:02 Field Don't care When a "1'" is written to this bit, internal processings are executed and the power down state is entered into within a maximum of 3 s. Writing a "0" in this bit has no meaning (that is, has no effect on the operation). It is necessary to give an input of the "RESET" signal in order to recover from the power down mode. A reset of the host controller is instructed by writing a "1" to this bit. Writing a "0" in this bit has no meaning (that is, has no effort on the operation). Reset X R/W X
01
0b
W
00
0b
W
[Description] When a "1" is written to bit 01, after the completion of the write access cycle, power down processings are executed within the ML60841 and the power down state is entered into within a maximum of 3 s after writing the "1". In concrete terms, the power down state is the following: * The oscillator circuit ("XIN" and "XOUT" pins) has stopped operating and the clock signal is not supplied to the internal circuits of the ML60841. * The clock signal supplied to the microcomputer ("BUS_CLK" pin) is not supplied to the internal circuits of the ML60841. * The receiver part of the USB transceiver ("HD+", "HD-", "DD+", and "DD-" pins) goes into the inactive state. In this state, the ML60841 does not detect even when there is any change in the status of the USB bus. * The suspend output (an "H" level output at the "SUSPEND" pin) is given to the external USB transceiver. In the power down state, since the USB transceiver will be in the disabled state, it will not be possible to verify changes in the status of the USB bus. Therefore, it is possible that no matching is made with the operations of the other equipment connected to the USB interface bus. Carry out the writing of a "1" in this bit when no other devices have been connected to the USB interface, and it is permissible to stop the operations completely. In concrete terms, write a "1" to this bit only when the power down mode has been instructed intentionally upon an operator intervention. Regarding all pins other than the above, the input or output states are not being controlled after the completion of the access cycle in which a "1" was written to this bit. Give a definite level input "H" or "L" to the input pins (including input/output pins in the input state). All subsequent operations cannot be guaranteed if a "1" is written to this bit while the ML60841 is operating (during USB communication, DMA transfer, etc.) After writing a "1" in this bit, it is necessary to input the "RESET" signal in order to return from the power down state. The operations cannot be guaranteed if the ML60841 is accessed during the period immediately after writing a "1" in this bit until a "RESET" input is given. See the section on the "Precautions in Control of the ML60841" for details of the processing after the "RESET" input is given. When a "1" is written in the bit 00, the ML60841 resets the host controller section within the LSI. In concrete terms, all the registers in the host controller section will be cleared to their initial values. The common section and the device controller section will not be reset. (It is possible to carry out a software reset of the device controller section by writing a "1" in bit 00 of the system control register.) During this reset operation, the bit 01 of the HostDevSel register is set to "1" and is reset to "0" when the resetting has been completed and normal operations can be started. Therefore, it is necessary for the microcomputer to execute the initialization processing after bit 01 has become "0". In addition, upon this resetting, the ML60841 resets the USB bus. Therefore, the microcomputer will also have to carry out initializations of all the devices connected to the USB bus.
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Types and Mapping of Host Controller Registers - 1
Offset 200h 204h 208h 20Ch 210h Symbol HOST CTL STT/TRNS CNT Host data transfer REQ FIFO ACC RAM ADR Host Control register Status, RD/WR FIFO transfer length register Host data transfer request register FIFO access register Internal RAM address setting register Name
For details concerning the registers mentioned below, refer to the section of NOTES ON THE ML60841 CONTROL. * HOST CTL Register (200h)
HC HCD (Host (Host Controller Controller) Driver) X X R/W R/W R/W X R R R X
Bits 31:04 03 02 01 00
Field Don't care Specifies DMA transfer. 0: Enables DMA transfer, 1: Disables DMA transfer Host data transfer interrupt mask 0: No mask, 1: Mask OpenHCI core interrupt mask 0: No mask, 1: Mask Don't care
Reset X 1b 1b 1b X
* STT/TRNS CNT Register (204h)
HC HCD (Host (Host Controller Controller) Driver) X X R R/W X X R R/W X X R/W R/W R/W R/W
Bits 31:27 26:24 23:19 18:16 15:02 01 (*) 00 (*) (**)
Field Don't care Don't care Don't care Don't care Don't care Indicates an interrupt request from the host core. 0: No interrupt request, 1: Interrupt request Indicates an interrupt request relating to host data transfer. 0: No interrupt request, 1: Interrupt request
Reset X 0b X 0b X 0b 0b
(*) Cleared by writing a "1" from the microcontroller. (**) DREQ is generated when interrupt clear is triggered and the HOST CTL register bit 03 is "0 (DMA)".
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* Host Data Transfer REQ Register (208h)
HCD (Host Controller Driver) R X HC (Host Controller) R/W X
Bits 31:02 01
Field Indicates the transfer start address when an interrupt relating to host data transfer is generated. Don't care Indicates the direction of transfer when an interrupt relating to host data transfer is generated. 1: MCU (MEM) to ML60841 0: ML60841 to MCU (MEM)
Reset 0h X
00
0b
R
R/W
* FIFO ACC Register (20Ch)
HCD (Host Controller Driver) R/W HC (Host Controller) R/W
Bits 31:00 FIFO access data
Field
Reset X
Specify the address of this register as the target address during DMA transfer. The operations cannot be guaranteed if there is an access from the microcomputer to the FIFO ACC register during DMA transfer. * RAM ADR Register (210h)
HCD Bits Field Sets the leading address for the internal RAM of the system. Don't care Reset (Host Controller Driver) R/W X HC (Host Controller) R X
31:12 11:00
0 X
[Description] This register is activated by write from a microcontroller. If write from the microcontroller is not executed, all transfer request addresses from the host core are judged to be outside the internal RAM address range (becomes an interrupt factor with regard to host data transfer). Therefore, even when it is used as the same value as the initial value "0", it is necessary to write a "0".
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Types and Mapping of Host Controller Registers - 2 Conforming to OpenHCI specifications, the registers control the Host controller functions of the ML60841. - USB HOST Operational Registers Summary
Offset 100h 104h 108h 10Ch 110h 114h 118h 11Ch 120h 124h 128h Register Name HcRevision HcControl HcCommandStatus HcInterruptStatus HcInterruptEnable HcInterruptDisable HcHCCA HcPeriodCurrentED HcControlHeadED HcControlCurrentED HcBulkHeadED Offset 12Ch 130h 134h 138h 13Ch 140h 144h 148h 14Ch 150h 154h Register Name HcBulkCurrentED HcDoneHead HcFmInterval HcFmRemaining HcFmNumber HcPeriodicStart HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus
The outline is given below.
See "OpenHCI (Release: 1.0a)" for details..
* HcRevision Register (100h)
HCD Bits 7:0 Revision (REV) Field Reset 10h (Host Controller Driver) R HC (Host Controller) R
* HcControl Register (104h)
HCD (Host Controller Driver) R/W R/W R/W R/W R/W R/W R/W R/W R/W HC (Host Controller) R R/W R R/W R R R R R
Bits 10 9 8 7:6 5 4 3 2 1:0
Field Remote Wakeup Enable (RWE) Remote Wakeup Connected (WC) Interrupt Routing (IR) Host Controller Functional State (HCFS) Bulk List Enable (BLE) Control List Enable (CLE) Isochronous Enable (IE) Periodic List Enable (PLE) Control Bulk Service Ratio (CBSR)
Reset 0b 0b 0b 00b 0b 0b 0b 0b 00b
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* HcCommandStatus Register (108h)
Bits 17:16 3 2 1 0 Field Scheduling Overrun Count (SOC) Ownership Change Request (OCR) Bulk List Filled (BLF) Control List Filled (CLF) Host Controller Reset (HCR) Reset 00b 0b 0b 0b 0b HCD (Host Controller Driver) R R/W R/W R/W R/W HC (Host Controller) R/W R/W R/W R/W R/W
Note:
Always set the HCR bit of bit 0 to "0". Operation is not guaranteed if set to "1". To execute software reset, use the SRstPDownCtl register.
* HcInterruptStatus Register (10Ch)
Bits 30 6 5 4 3 2 1 0 Field Ownership Change (OC) Root Hub Status Change (RHSC) Frame Number Overflow (FNO) Unrecoverable Error (UE) Resume Detected (RD) Start of Frame (SF) Writeback Done Head (WDH) Scheduling Overrun (SO) Reset 0b 0b 0b 0b 0b 0b 0b 0b HCD (Host Controller Driver) R R/W R/W R/W R/W R/W R/W R/W HC (Host Controller) R R/W R/W R/W R/W R/W R/W R/W
Note:
The OC bit of bit 30 is a read only bit fixed to "0". Therefore this bit does not change even when bit 3 (OCR bit) of the HcCommand Status register is set to "1". Moreover, no interrupt is generated even when bit 8 (IR bit) of the HcControl register is set to "1".
* HcInterruptEnable Register (110h)
Bits 31 30 6 5 4 3 2 1 0 Field Master Interrupt Enable (MIE) Ownership Change (OC) Root Hub Status Change (RHSC) Frame Number Overflow (FNO) Unrecoverable Error (UE) Resume Detected (RD) Start of Frame (SF) Writeback Done Head (WDH) Scheduling Overrun (SO) Reset 0b 0b 0b 0b 0b 0b 0b 0b 0b HCD (Host Controller Driver) R/W R/W R/W R/W R/W R/W R/W R/W R/W HC (Host Controller) R R R R R R R R R
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* HcInterruptDisable Register (114h)
Bits 31 30 6 5 4 3 2 1 0 Field Master Interrupt Enable (MIE) Ownership Change (OC) Root Hub Status Change (RHSC) Frame Number Overflow (FNO) Unrecoverable Error (UE) Resume Detected (RD) Start of Frame (SF) Writeback Done Head (WDH) Scheduling Overrun (SO) Reset 0b 0b 0b 0b 0b 0b 0b 0b 0b HCD (Host Controller Driver) R/W R/W R/W R/W R/W R/W R/W R/W R/W HC (Host Controller) R R R R R R R R R
* HcHCCA Register (118h)
Bits 31:8 Field Host Controller Communications Area (HCCA) Base Address Reset 0h HCD (Host Controller Driver) R/W HC (Host Controller) R
* HcPeriodCurrentED Register (11Ch)
Bits 31:4 Field Period Current ED (PCED) Base Address Reset 0h HCD (Host Controller Driver) R HC (Host Controller) R/W
* HcControlHeadED Register (120h)
Bits 31:4 Field Control Head ED (CHED) Base Address Reset 0h HCD (Host Controller Driver) R/W HC (Host Controller) R
* HcControlCurrentED Register (124h)
HCD (Host Controller Driver) R/W HC (Host Controller) R/W
Bits 31:4
Field Control Current ED (CCED) Base Address
Reset 0h
* HcBulkHeadED Register (128h)
HCD (Host Controller Driver) R/W HC (Host Controller) R
Bits 31:4
Field Bulk Head ED (BHED) Base Address
Reset 0h
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* HcBulkCurrentED Register (12Ch)
HCD (Host Controller Driver) R/W HC (Host Controller) R/W
Bits 31:4
Field Bulk Current ED (BCED) Base Address
Reset 0h
* HcDoneHead Register (130h)
HCD (Host Controller Driver) R HC (Host Controller) R/W
Bits 31:4
Field Done Head ED (DH) Base Address
Reset 0h
* HcFmInterval Register (134h)
HCD (Host Controller Driver) R/W R/W R/W HC (Host Controller) R R R
Bits 31 30:16 13:0
Field Frame Interval Toggle (FIT) FS Largest Data Packet (FSMPS) Frame Interval (FI)
Reset 0b 0h 2EDFh
* HcFmRemaining Register (138h)
HCD (Host Controller Driver) R R HC (Host Controller) R/W R/W
Bits 31 13:0
Field Frame Remaining Toggle (FRT) Frame Remaining (FR)
Reset 0b 0h
Note:
Writing in this register is enabled. If written in this register, the operation is not guaranteed.
* HcFmNumber Register (13Ch)
HCD (Host Controller Driver) R HC (Host Controller) R/W
Bits 15:0 Frame Number (FN)
Field
Reset 0h
Note:
Writing in this register is enabled. If written in this register, the operation is not guaranteed.
* HcPeriodicStart Register (140h)
HCD (Host Controller Driver) R/W HC (Host Controller) R
Bits 13:0 Periodic Start (PS)
Field
Reset 0h
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* HcLSThreshold (144h)
HCD (Host Controller Driver) R/W HC (Host Controller) R
Bits 11:0 LS Threshold
Field
Reset 628h
* HcRhDescriptorA Register (148h)
HCD (Host Controller Driver) R/W R/W R/W R R/W R/W R HC (Host Controller) R R R R R R R
Bits 31:24 12 11 10 9 8 7:0
Field Power On to Power Good Time (POTPGT) No Overcurrent Protection (NOCP) Overcurrent Protection Mode (OCPM) Device Type (DT) No Power Switching (NPS) Power Switching Mode (PSM) Number Downstream Ports (NDP)
Reset 32h 0b 0b 0b 0b 0b 1h
* HcRhDescriptorB Register (14Ch)
HCD (Host Controller Driver) R/W R/W HC (Host Controller) R R
Bits 17 1
Field Port Power Control Mask (PPCM) Device Removable (DR)
Reset 0b 0b
* HcRhStatus Register (150h)
HCD (Host Controller Driver) W R/W R/W R/W R R/W HC (Host Controller) R R/W R R R/W R
Bits 31 17 16 15 1 0
Field Clear Remote Wakeup Enable (CRWE) Overcurrent Indicator Change (OCIC) Local Power Status Change (LPSC) Device Remote Wakeup Enable (DRWE) Overcurrent Indicator (OCI) Local Power Status (LPS)
Reset 0b 0b 0b 0b 0b 0b
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* HcRhPortStatus Register (154h)
HCD (Host Controller Driver) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W HC (Host Controller) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bits 20 19 18 17 16 9 8 4 3 2 1 0
Field Port Reset Status Change (PRSC) Port Overcurrent Indicator Change (OCIC) Port Suspend Status Change (PSSC) Port Enable Status Change (PESC) Connect Status Change (CSC) Low-speed Device Attached (LSDA) Port Power Status (PPS) Port Reset Status (PRS) Port Overcurrent Indicator (POCI) Port Suspend Status (PSS) Port Enable Status (PES) Current Connect Status (CCS)
Reset 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b
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Memory for Host Controller
HCD Offset 1000h -1FFFh Description 4 KB (1K double word) HCCA, ED/TD buffer memory Reset (Host Controller Driver) R/W HC (Host Controller) R/W
X
This RAM must be accessed in 32 bits unit. When accessing this RAM by a 16-bit wide bus, it is necessary, for example, to continuously access two accesses of 1000h and 1002h as one set.
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Types and Mapping of Device Controller Registers - 1
Category Offset 380h 384h 388h FIFO 38Ch 390h 394h 398h 300h 304h 308h Common 30Ch 310h 314h 318h 320h DMA 324h R/W R/W W R R/W R/W R/W R/W R/W R R R/W R R/W R/W R/W R/W Offset Address Low-Order 2 Bits 11 10 01 00 EP0 transmit FIFO (EP0TXFIFO) EP0 receive FIFO (EP0RXFIFO) EP1 transmit/receive FIFO (EP1FIFO) EP2 transmit/receive FIFO (EP2FIFO) EP3 transmit/receive FIFO (EP3FIFO) EP4 transmit/receive FIFO (EP4FIFO) EP5 transmit/receive FIFO (EP5FIFO) wValue*bRequest*BmRequest Type setup register (SETUP0) wLengtht*wIndex setup register (SETUP1) Device address register (DVCADR) Frame number register (FRAME MSB) Interrupt status register (INTSTAT) Interrupt enable register (INTENBL) System control register (SYSCON) DMA0 control register (DMA0CON) DMA1 control register (DMA1CON)
Notes: 1. Access to unspecified address sections is meaningless. 2. Regarding access to FIFO/registers: In the case of 32 bits: Access to address specified in the above table with 32-bit width. For example 388h for EP1. In the case of 16 bits: Access to address specified in the above table with 16-bit width. By making the second access to the first access address +2h, the operation becomes the same as in the case of 32 bits. For example, in the case of EP1, by making the first access to 388h and second to 38Ah the operation becomes the same as accessing once 388h in the case of 32-bit address.
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Types and Mapping of Device Controller Registers - 2
Category Offset 330h 334h 338h 33Ch 340h 344h 348h 34Ch 350h EP support 354h 358h 35Ch 360h 364h 368h 36Ch 370h 374h 378h R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Offset Address Low-Order 2 Bits 10 01
11
00
EP1 payload register (EP1PLD) EP1 configuration register (EP1CONF) EP1 payload configuration register (EP1PLDCONF) EP2 payload configuration register (EP2PLDCONF) EP3 payload configuration register (EP3PLDCONF) EP4 payload configuration register (EP4PLDCONF) EP5 payload configuration register (EP5PLDCONF) EP0 receive byte count status register (EP0RXCNTSTAT) EP1 receive byte count status register (EP1RXCNTSTAT) EP2 receive byte count status register (EP2RXCNTSTAT) EP3 receive byte count status register (EP3RXCNTSTAT) EP4 receive byte count status register (EP4RXCNSTAT) EP5 receive byte count status register (EP5RXCNSTAT) EP0 transmit data byte count register (EP0TXCNT) EP1 transmit data byte count register (EP1TXCNT) EP2 transmit data byte count register (EP2TXCNT) EP3 transmit data byte count register (EP3TXCNT) EP4 transmit data byte count register (EP4TXCNT) EP5 transmit data byte count register (EP5TXCNT) ISO mode select register (ISO MODE)
Note: Access to unspecified address sections is meaningless.
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Types and Mapping of Device Controller Registers - 3
Category Offset 39Ch 3A0h 3A4h EP support 3A8h 3ACh 3B0h R/W R/W R/W R/W R/W R/W R/W Offset Address 2 Lower Bits 11 10 01 (EP0CONT) EP1 control register (EP1CONT) EP2 control register (EP2CONT) EP3 control register (EP3CONT) EP4 control register (EP4CONT) EP5 control register (EP5CONT) 00 EP0 control register
Note: Access to unspecified address sections is meaningless.
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* EP0 Transmit FIFO Register (380h)
Bits 31:00 Field EP0 Transmit data (EP0TXFIFO) Reset X USB Reset X R/W W
[Description] The EP0 send (transmit) data can be written by writing into this register. The send data to be transmitted to the host is stored in EP0TXFIFO in the data stage during a control read transfer. When the ML60841 requests an EP0 transmit packet ready interrupt, the microcomputer writes the send data in the EP0 transmit FIFO register. It is possible to write packets of data successively by executing a series of write operations. The EP0 transmit FIFO gets cleared under the following conditions. * When an ACK is received from the host in response to data transmission from EP0. * When a setup packet is received. * EP0 Receive FIFO Register (384h)
Bits 31:00 Field EP0 Receive data (EP0RXFIFO) Reset X USB Reset X R/W R
[Description] The receive data from the host is stored in EP0RXFIFO in the data stage during a control write transfer. When the ML60841 requests an EP0 receive packet ready interrupt, the microcomputer reads the receive data by reading the EP0 receive FIFO register. The data within a packet can be read out successively by executing a series of read operations. The EP0 receive FIFO gets cleared under the following conditions. * When the microcomputer resets the EP0 receive packet ready status. * When a setup packet is received. * When the microcomputer writes a "0" in the stall bit. * EP1 Transmit/Receive FIFO Register (388h)
Bits 31:00 Field EP1 Transmit/receive data (EP1FIFO) Reset X USB Reset X R/W R/W
[Description] The EP1 transfer direction is specified by the setting made in the EP1 configuration register EP1CONF. The FIFO address of EP1 is the same in the transmit direction as in the receive direction. When EP1CONF (bit 07) = 0, EP1 has the receive direction and EP1FIFO becomes a read only register. When EP1CONF (bit 07) = 1, EP1 has the transmit direction and EP1FIFO becomes a write only register.
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* EP2 Transmit/Receive FIFO Register (38Ch)
Bits 31:00 Field EP2 Transmit/receive data (EP2FIFO) Reset X USB Reset X R/W R/W
[Description] The EP2 transfer direction is specified by the setting made in the EP2 configuration register EP2CONF. The FIFO address of EP2 is the same in the transmit direction as in the receive direction. When EP2CONF (bit 07) = 0, EP2 has the receive direction and EP2FIFO becomes a read only register. When EP2CONF (bit 07) = 1, EP2 has the transmit direction and EP2FIFO becomes a write only register. * EP3 Transmit/Receive FIFO Register (390h)
Bits 31:00 Field EP3 Transmit/receive data (EP3FIFO) Reset X USB Reset X R/W R/W
[Description] The EP3 transfer direction is specified by the setting made in the EP3 configuration register EP3CONF. The FIFO address of EP3 is the same in the transmit direction as in the receive direction. When EP3CONF (bit 07) = 0, EP3 has the receive direction and EP3FIFO becomes a read only register. When EP3CONF (bit 07) = 1, EP3 has the transmit direction and EP3FIFO becomes a write only register. * EP4 Transmit/Receive FIFO Register (394h)
Bits 31:00 Field EP4 Transmit/receive data (EP4FIFO) Reset X USB Reset X R/W R/W
[Description] The EP4 transfer direction is specified by the setting made in the EP4 configuration register EP4CONF. The FIFO address of EP4 is the same in the transmit direction as in the receive direction. When EP4CONF (bit 07) = 0, EP4 has the receive direction and EP4FIFO becomes a read only register. When EP4CONF (bit 07) = 1, EP4 has the transmit direction and EP4FIFO becomes a write only register. * EP5 Transmit/Receive FIFO Register (398h)
Bits 31:00 Field EP5 Transmit/receive data (EP5FIFO) Reset X USB Reset X R/W R/W
[Description] In the ML60841, depending on the setting in the system control register (SYSCON), it is possible to select the 5EP mode, with the number of EP's being five or the 6EP mode in which the number of EP's is six. In the 5EP mode, EP0 to EP4 will be present but EP5 will not be present. All of EP0 to EP5 will be present in the 6EP mode. The EP5 transfer direction is specified by the setting made in the EP5 configuration register EP5CONF. The FIFO address of EP5 is the same in the transmit direction as in the receive direction. When EP5CONF (bit 07) = 0, EP5 has the receive direction and EP5FIFO becomes a read only register. When EP5CONF (bit 07) = 1, EP5 has the transmit direction and EP5FIFO becomes a write only register.
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* wValue*bRequest*BmRequest Type Setup Register (300h)
Bits Field wValueMSB setup data During the setup stage of a control transfer, the 8 bytes of setup data sent from the host are received automatically by the ML60841 and the fourth byte of that setup data is stored in this register. This is the higher order byte of a two-byte data. wValueLSB setup data During the setup stage of a control transfer, the 8 bytes of setup data sent from the host are received automatically by the ML60841 and the third byte of that setup data is stored in this register. This is the lower order byte of a two-byte data. bRequest setup data During the setup stage of a control transfer, the 8 bytes of setup data sent from the host are received automatically by the ML60841 and the second byte of that setup data is stored in this register. The content of the request code has been stipulated in section 9.3 of the USB standard as well as in other related standards. bmRequest Type setup data During the setup stage of a control transfer based on a request from the host, the 8 bytes of setup data sent from the host are received automatically by the ML60841 and stored in eight registers including this register. The formats of these data bytes have been defined in Section 9.3 of the USB standard. 07: Data transfer direction (1: Device Host, 0: Host Device) 06, 05: Type (00: Standard, 01: Class, 10: Vendor, 11: Reserved) 04:00: Receive side definition (00: Device, 01: Interface, 02: End point, 03: Others, 04-31: Reserved) Reset USB Reset R/W
31:24
0
0
R
23:16
0
0
R
15:08
0
0
R
07:00
0
0
R
* wLength*wIndex Setup Register (304h)
Bits Field wLengthMSB data During the setup stage of a control transfer, the 8 bytes of setup data sent from the host are received automatically by the ML60841 and the eighth byte of that setup data is stored in this register. This is the higher order byte of a two-byte data. wLengthLSB data During the setup stage of a control transfer, the 8 bytes of setup data sent from the host are received automatically by the ML60841 and the seventh byte of that setup data is stored in this register. This is the lower order byte of a two-byte data. wIndexMSB data During the setup stage of a control transfer, the 8 bytes of setup data sent from the host are received automatically by the ML60841 and the sixth byte of that setup data is stored in this register. This is the higher order byte of a two-byte data. wIndexLSB data During the setup stage of a control transfer, the 8 bytes of setup data sent from the host are received automatically by the ML60841 and the fifth byte of that setup data is stored in this register. This is the lower order byte of a two-byte data. Reset USB Reset R/W
31:24
0
0
R
23:16
0
0
R
15:08
0
0
R
07:00
0
0
R
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PEDL60841-01
OKI Semiconductor
ML60841
* Device Address Register (308h)
Bits 31:07 Don't care The microcomputer writes in this register the device address specified by the host in the SET_ADDRESS request. Thereafter, the specified address of the token from the host is judged by the ML60841, and operates so that only the token packets transmitted to this device address are processed by the device. The bit D7 is fixed at "0" and even if a "1" is written to it, it will have no validity. Field Reset X USB Reset X R/W X
06:00
0
0
R/W
* Frame Number Register (30Ch)
Bits 31:11 10:00 Don't care The ML60841 writes this automatically when the start of frame (SOF) packet is sent from the host. Field Reset X 0 USB Reset X 0 R/W X R
* Interrupt Status Register (310h)
Bits 31:16 15 14 13 12 11 10 09 08 07:05 04 03 02 01 00 Don't care EP0 Transmit packet ready interrupt status (ep0tx_pry) EP0 Receive packet ready interrupt status (ep0rx_pry) EP5 Packet ready interrupt status (ep5_pry) EP4 Packet ready interrupt status (ep4_pry) EP3 Packet ready interrupt status (ep3_pry) EP2 Packet ready interrupt status (ep2_pry) EP1 Packet ready interrupt status (ep1_pry) Setup ready interrupt status (stup_ry) Don't care Device awake state interrupt status (awake) Device suspend state interrupt status (suspend) USB Bus reset deassert interrupt status (busrst_des) USB Bus reset assert interrupt status (busrst_ass) SOF Interrupt status (sof) Field Reset X 0b 0b 0b 0b 0b 0b 0b 0b X 0b 0b 0b 0b 0b USB Reset X 0b 0b 0b 0b 0b 0b 0b 0b X 0b 0b 0b 0b 0b R/W X R R R R R R R R X R/Reset R/Reset R/Reset R/Reset R/Reset
Note 1: When the EP4 and EP5 configuration registers have been set for isochronous transfer, the EP4 and EP5 packet ready interrupt statuses will always be kept fixed at "0". Note 2: The status bit becomes "1" when an interrupt corresponding to the bits 04 to 00 occurs. This status will be cleared when a "1" is written to that status bit itself.
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PEDL60841-01
OKI Semiconductor
ML60841
* Interrupt Enable Register (314h)
Bits 31:16 15 14 13 12 11 10 09 08 07:05 04 03 02 01 00 Don't care EP0 Transmit packet ready interrupt enable EP0 Receive packet ready interrupt enable EP5 Packet ready interrupt enable EP4 Packet ready interrupt enable EP3 Packet ready interrupt enable EP2 Packet ready interrupt enable EP1 Packet ready interrupt enable Setup ready interrupt enable Don't care Device awake state interrupt enable Device suspend status interrupt enable USB Bus reset deassert interrupt enable USB Bus reset assert interrupt enable SOF Interrupt enable Field Reset X 0b 0b 0b 0b 0b 0b 0b 1b 000b 0b 0b 0b 0b 0b State before reset is maintained USB Reset X R/W X R/W R/W R/W R/W R/W R/W R/W R/W X R/W R/W R/W R/W R/W
[Description] When the 5EP mode has been selected (bit 02 is "1" in the system control register), the EP5 packet ready interrupt will not be generated irrespective of the value of bit 13 (EP5 packet ready interrupt enable). Similarly, in this case, even bit 13 of the interrupt status register (EP5 Packet ready interrupt status) will always be "0".
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PEDL60841-01
OKI Semiconductor
ML60841
* System Control Register (318h)
Bits 31:08 07 06:05 04 Don't care Instructs a clock stop of the device controller section 0: clock not stopped, 1: clock stopped. Don't care A remote wake-up is executed by writing a "1" to this bit. This bit itself will remain "0". Specifies the status of the PUCTL pin. 03 0: PUCTL pin invalid (the pin is at "H" level) 1: PUCTL pin valid (the pin is at "L" level) 02 Specifies the EP mode 0: 6EP mode, 1: 5EP mode Specifies the power down mode 01 0: Power not saved by suspending, 1: Power saved by suspending A software reset of the device controller section can be executed by writing a "1" to this bit. This bit itself will remain "0". 0b R/W 0b 0b
State before reset is maintained
Field
Reset X 0b X 0b
USB Reset X
State before reset is maintained
R/W X R/W X W
X
R/W
R/W
00
0b
W
[Description] When a "1" is written to bit 07, the clock of the device control section stops after the write access cycle has been completed. In addition, the USB buffer goes into the power down mode. Therefore, it may not be possible to achieve matching with the host side since it will not be possible to recognize any changes in the USB bus status (such as a token from the USB host, etc.). Make the clock stop specification when it is permissible to stop all the operations of a device controller such as when the host has not been connected, and in concrete terms, only when an operator intervenes and explicitly gives instruction to stop the clock. When transition to the suspend mode is specified while the ML60841 is operating (during DMA transfer or during USB communication), the operations thereafter cannot be guaranteed. It is necessary to input the "RESET" signal in order to recover from the clock stop state initiated due to writing a "1" in this bit. The operation cannot be guaranteed if the ML60841 is accessed during the period immediately after writing a "1" in this bit until the "RESET" signal is input. See the section "Precautions in Control of ML60841" for details of the processing after the "RESET" signal has been input. The difference between bit 07 and bit 01 is the following. As has been explained above, bit 07 instructs the stop of the clock supply to the device controller block. When this bit is set to "1", the ML60841 immediately starts the clock stop processing. On the other hand, bit 01 specifies whether or not to go into the power saving mode when the suspend state of the USB bus is detected. When this bit has been set to "1", the processing for transition to the power saving mode (*) will be started when the suspend state of the USB bus is detected. Even when this bit has been set to "1", the processing for transition to the power saving mode will not be started as long as the suspend state of the USB bus has not been detected. When this bit has been reset to "0", the processing for transition to the power saving mode will not be made even when the suspend state of the USB bus has been detected. *: The power save mode is equivalent to the clock stopped state that is initiated by writing a "1" to bit 07 excepting that some of the circuits in the device controller section for detecting a resume command from the USB host and some of the circuits in the USB transceiver will be operating. Therefore, the power consumption will be reduced more when a "1" is set in bit 07.
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PEDL60841-01
OKI Semiconductor
ML60841
* DMA0 Control Register (320h),
Bits 31:08 07 06:05 04:03 Don't care Don't care
DMA1 Control Register (324h)
Field Reset X X 00b X USB Reset X X
State before reset is maintained
R/W X X R/W X
Specifies the EP that is a target of DMA transfer. *1, *2 0: EP1, 1: EP2, 2: EP4, 3: EP5 Don't care When the EP that is specified as the target of DMA transfer is configured as bulk transfer or interrupt transfer, insertion or no insertion of DMA byte count is specified. *1, *3 0: No insertion of byte count 1: Insertion of byte count at the top of transfer data Don't care DMA enable *1 0: DMA disable, 1: DMA enable
X
State before
02
0b
reset is maintained
R/W
01 00
X 0b
X
State before reset is maintained
X R/W
*1) Complete setting of bits 06, 05, 02, 00 before arrival of token packet to EP1 to EP5 and do not change after that. Operation is not guaranteed if the setting is changed. *2) If the EP setting values for DMA channels 0 and 1 are the same, DREQ0, DRACK0 and DACK0 become equivalent to DREQ1, DRACK1 and DACK1 respectively. *3): Although DMA transfers can be made in the bulk, interrupt, and isochronous transfer modes, the DMA byte count insertion function using this bit is only valid in the bulk and interrupt transfer modes. The operations cannot be guaranteed when this bit is set to "1" for isochronous transfers. * EP0 Payload & Configuration Register (330h)
Bits 31:16 Don't care EP0 Payload data (EP0PLD) Write "20h" to the bMaxPacketSize byte of the device descriptor since the FIFO of the EP0 in the ML60841 is of 32 bytes. The maximum packet size of the EP0PLD is fixed to 32 bytes. If a packet exceeding 32 bytes is received, the stall bit of the EP0 status register is asserted and the stall is returned to the Host. Don't care Configuration bit: The configuration bit of the EP0 becomes "1" at USB bus reset. When this bit is "1", the data transmitted from the Host to this endpoint is received and it becomes possible to transmit data from this endpoint to the Host. When this bit is "0", no response is made to the transaction with this EP as target. The microcontroller cannot write to this bit. Don't care These bits indicate D transfer type, and fixed to "00b" since in the ML60841 the EP0 is determined as control transfer. The microcontroller cannot write in these bits. Field Reset X USB Reset X R/W X
15:07
20h
20h
R
07:05
X
X
X
04
0
1
R
03:02 01:00
X 0
X 0
X R
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PEDL60841-01
OKI Semiconductor
ML60841
* EP1/2/3 Payload & Configuration Registers (334h/338h/33Ch)
Bits 31:15 Don't care Maximum packet size: Make the microcomputer write in this register the value of wMaxPacketSize in the end point descriptor selected by the Set_Configuration request from the host. This specifies the packet size in bytes for all packets other than short packets. When the EP is being used for reception, if a data packet with a number of bytes exceeding the maximum packet size set in this register is received, the receive packet ready status will not be asserted, but a stall handshake is returned to the host by setting the stall bit in the EOP. When the EP is being used for transmission, the transmit packet ready status bit will be set automatically at the completion of writing data by the DMA controller equal to the maximum packet size set in this register. The content of this register is "Don't care" during transmissions that do not use DMA transfer. Transfer direction (0: Receive, 1: Transmit) Don't care Configuration bit: Write a "1" in this bit from the microcomputer during the status stage of control transfer when a Set Configuration request is received from the host requesting to make that EP active. Data transmission and reception can be made between the host and the EP when this bit is "1". When this bit is "0", there will be no responses to the transactions made targeting that EP. Don't care These are bits indicating the type of transfer, and are fixed at 00b since control transfer is the only type of transfer allowed for EP0 in the ML60841. The microcomputer cannot write to these bits. Field Reset X USB Reset X R/W X
14:07
0
0
R/W
07 06:05
0 X
0 X
R/W X
04
0
1
R
03:02 01:00
X 0
X 0
X R
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PEDL60841-01
OKI Semiconductor
ML60841
* EP4 Payload & Configuration Register (340h)
Bits 31:24 23:16 05:08 07 06:05 04 03:02 01:00 Don't care EP4 Packet maximum size MSB EP4 Packet maximum size LSB EP4 Transfer direction Don't care EP4 Configuration Don't care EP4 Transfer type Field Reset X 00h 00h 0b 00b 0b 00b 00b USB Reset X 00h 00h 0b 00b 0b 00b 00b R/W X R/W R/W R/W X R/W X R/W
[Description] Make the microcomputer write a "1" in bit 04 (EP4 Configuration) during the status stage of control transfer when a Set Configuration request is received from the host requesting that EP4 be made active. When this bit 04 is "1", data transmission and reception can be made between the host and EP4. When this bit is "0", there will be no responses to the transactions made targeting EP4. However, when the 5EP mode has been selected (bit 02 = 1 in the system control register), there will be no responses to the transactions made targeting EP4 irrespective of the value set in bit 04 (EP4 Configuration). In other words, in this case, the operations will be the same as when a "0" has been set in this bit even if a "1" has been written in this bit. * EP5 Payload & Configuration Register (344h)
Bits 31:24 23:16 05:08 07 06:05 04 03:02 01:00 Don't care EP5 Packet maximum size MSB EP5 Packet maximum size LSB EP5 Transfer direction Don't care EP5 Configuration Don't care EP5 Transfer type Field Reset X 00h 00h 0b 00b 0b 00b 00b USB Reset X 00h 00h 0b 00b 0b 00b 00b R/W X R/W R/W R/W X R/W X R/W
[Description] Make the microcomputer write a "1" in bit 04 (EP5 Configuration) during the status stage of control transfer when a Set Configuration request is received from the host requesting that EP5 be made active. When this bit 04 is "1", data transmission and reception can be made between the host and EP5. When this bit is "0", there will be no responses to the transactions made targeting EP5. However, when the 5EP mode has been selected (bit 02 = 1 in the system control register), there will be no responses to the transactions made targeting EP5 irrespective of the value set in bit 04 (EP5 Configuration). In other words, in this case, the operations will be the same as when a "0" has been set in this bit even if a "1" has been written in this bit.
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PEDL60841-01
OKI Semiconductor
ML60841
* EP0 Received Byte Count & Status Register (348h)
Bits 31:16 Field Don't care The ML60841 automatically counts the number of bytes in the packet being received. While the counting is made up to the number of bytes equal to the maximum packet size specified in the payload register in the case of full packets, the byte count will fall short of that maximum packet size in the case of short packets. The microcomputer refers to this value and reads the data of one packet from the EP0 Receive FIFO. EP0RXCNT is cleared under the following conditions: 1. When the microcontroller resets the EP packet ready bit. 2. When a setup packet is received. 3. When the microcontroller writes a "0" in the stall bit. Don't care EP0 stage 00: Default stage 01: Data stage 10: Data stage completed state Don't care Setup ready: This bit is set automatically when a setup packet for storing 8 bytes of setup data in the setup registers arrives correctly, and the EP0 Receive FIFO gets locked. If INTENBL1 (0) has been asserted, the INTR signal is asserted automatically when this bit is set. Write a "1" in this bit when the microcomputer completes reading the 8 bytes of setup data. By doing so, the setup ready will be reset and also the INTR pin will be deasserted. In the case of a control write transfer, the EP0 packet ready bit is reset at the same time thereby releasing the lock on the EP0 Receive FIFO so that packet reception can be made by EP0 during the data stage. Note that the value of this register will not change even if a "0" is written in this bit. EP0 Transmit pocket ready EP0 Receive packet ready Reset X USB Reset X R/W X
15:08
00h
00h
R
07:06 05:04 03
X 0b X
X 0b X
X R X
02
0b
0b
R/Reset
01 00
0b 0b
0b 0b
R/Set R/Reset
[Description] * EP0 Transmit packet ready bit (bit 01) This bit can be read by the microcontroller. In addition, this bit can be set to "1" by writing a "1" in this bit 01. The conditions of asserting and deasserting this bit are as follows.
Bit name Assert condition EP0 Transmit packet ready When the microcontroller sets this bit (bit 01) Bit name EP0 Transmit packet ready (bit 01) Operation when asserted Data transmission can be made from EP0.
Deassert condition Operation when deasserted 1. When an ACK is received from the EP0 is locked. That is, an NAK is host in response to data transmission returned automatically when an IN from EP0. token arrives from the host. 2. When a setup packet is received.
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PEDL60841-01
OKI Semiconductor
ML60841
* EP0 Receive packet ready bit (bit 00) This bit can be read by the microcontroller. In addition, this bit can be reset to "0" by writing a "1" to this bit 00. The assert and deassert conditions of this bit are as follows.
Bit name EP0 Receive packet ready (bit 01) Assert condition Operation when asserted 1. When data is received in EP0 and is EP0 is locked. That is, an NAK is stored in the FIFO. 2. When a setup packet is received returned automatically when a data during a control read or a control packet arrives from the host. write transfer. Deassert condition Operation when deasserted 1. When the microcontroller resets this bit (by writing a "1" in it). 2. When the microcontroller rests the Can be received by EP0. setup ready bit during a control write transfer.
Bit name EP0 Receive packet ready (bit 01)
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PEDL60841-01
OKI Semiconductor
ML60841
* EP1, 2 Receive Byte Count Registers / EP1, 2 Status Registers (34Ch, 350h)
Bits 31:16 Field Don't care The number of bytes in the packets received at EP1 and EP2 is counted and the value is indicated in these bits. Although the counting is made only up to the number of bytes equal to the maximum packet size specified in the payload register in the case of full packets, the count will be short of that maximum packet size in the case of short packets. The microcontroller refers to this value and reads one packet of data from the EP1/2 Receive FIFOs. This register will not be valid when the transfer direction of the EPs is set to transmission. EP1, 2 RXCNT are cleared under the following conditions. 1. When an OUT token for the EP is received. 2. When the microcontroller resets the EP receive packet ready bit. 3. When the microcontroller writes a "0" in the stall bit. Reserved. (For write, write a "0".) This bit is valid only when EP1 and EP2 are set to bulk or INT transfer. It indicates whether valid data is stored in the internal FIFO of this LSI or not. For details, refer to the description below. This bit is valid only when EP1 and EP2 are set to bulk or INT transfer. It indicates whether valid data is stored in the internal FIFO of this LSI or not. For details, refer to the description 2 below. Reset X USB Reset X R/W X
15:08
00h
00h
R
07:02 01 00
00h 0b 0b
00h 0b 0b
R/W R/SET R/RST
Note:
Write a "0" in bit 00 when writing in bit 01, and write a "0" in bit 01 when writing in bit 00. Operation is not guaranteed if a value other than "0" is written.
[Description 1] Bit 01 (transmit packet ready) can be read and set. By writing a "1", this bit can be set to "1". The assert/deassert conditions of this bit are shown below. EP1 and EP2 have FIFO of two layers (layers A and B). The transmit packet ready bit also individually exists in layer A and layer B and this LSI automatically executes switching of these two layers.
Condition Assert Deassert When the microcontroller sets bits of both layer A and layer B. When ACK is received from the host with regard to the transmit data of either layer A or layer B. Operation Transmitting from EP1 and EP2 are possible when either layer A or layer B is asserted. (Data is transmitted with regard to IN token.) Lock EP1 and EP2 when transmit data is not ready in either layer A or layer B. (NACK reply for IN token.)
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OKI Semiconductor
ML60841
Detailed example is shown below.
Layer A FIFO (64B) 1 2 3 4 5a 5b 6 7 Layers A and B FIFO both empty Microcontroller writes data in layer A FIFO. Data write for 1 packet is completed. Transmit layer A FIFO data to USB bus and write next packet data to layer B FIFO. When data write to layer B FIFO is completed before layer A FIFO becomes empty. When layer A FIFO becomes empty before data write to layer B FIFO is completed. From 5a : layer A FIFO became empty. From 5b : layer B FIFO became full. Start transmitting layer B FIFO data to USB bus. Layer B FIFO (64B) Layer A FIFO Packet Ready x x O O O x x x Layer B FIFO Packet Ready x x x x O x O O EP1, 2 Transmit Packet Ready Bit x x x x O x x x
O: Assert
x: Deassert
[Description 2] Bit 00 (Receive packet ready bit) can be read by the microcontroller. Further, it is possible to reset this bit to "0" by writing a "1" to it. The conditions of asserting and deasserting this bit are as follows. EP1 and EP2 have two separate layers of FIFOs, and even the receive packet ready bits are provided independently for layer A and layer B. The switching between these two layers is done automatically by the ML60841.
Condition Assert Deassert When an error-free packet is received in either layer A or layer B. When the microcontroller resets (by writing a "1") the bits of both layer A and layer B. Operation The microcontroller can read the EP1, 2 receive FIFOs. EP1 and EP2 are locked if packets of data have been received in both layer A and layer B. EP1 and EP2 can receive data when one of the bits of layer A and layer B has been reset.
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PEDL60841-01
OKI Semiconductor
ML60841
* EP3 Receive Byte Count & Status Register (354h)
Bits 31:14 Field Don't care The ML60841 automatically counts the number of packets being received. While the counting is made up to the number of bytes equal to the maximum packet size specified in the payload register in the case of full packets, the byte count will fall short of that maximum packet size in the case of short packets. The microcontroller refers to this value and reads the data of one packet from the EP3 Receive FIFO. This register will not be valid when the EP3 transfer direction is set to transmission. EP3RXCNT is cleared under the following conditions: 1. When an OUT token is received for EP3. 2. When the microcontroller resets the EP3 receive packet ready bit. 3. When the microcontroller writes a "0" in the stall bit. Don't care Receive packet ready Transmit packet ready Reset X USB Reset X R/W X
13:08
00h
00h
R
07:02 01 00
X 0b 0b
X 0b 0b
X R/SET R/RST
[Description] This register becomes valid only when the corresponding EP has been set to bulk or interrupt transfer. * EP3 Receive packet ready bit (bit 00) This bit can be read by the microcontroller. In addition, this bit can be set to "0" by writing a "1" to this bit 00. The conditions of asserting and deasserting this bit are as follows:
Bit name EP3 Receive packet ready (bit 00) Bit name EP3 Receive packet ready (bit 00) Assert condition When an error-free packet is received. Operation when asserted EP3 is locked.
Deassert condition Operation when deasserted When the microcontroller resets this bit EP3 can receive packets. (by writing a "1" to it).
* EP3 Transmit packet ready bit (bit 01) This bit can be read by the microcontroller. In addition, this bit can be set to "1" by writing a "1" in this bit 01. The conditions of asserting and deasserting this bit are as follows.
Bit name Assert condition EP3 Transmit packet ready When the microcontroller sets this bit (bit 01) Bit name EP3 Transmit packet ready (bit 01) Operation when asserted EP3 can transmit packets.
Deassert condition Operation when deasserted When an ACK is received from the host in response to data transmission from EP3 is locked. EP3.
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PEDL60841-01
OKI Semiconductor
ML60841
* EP4, 5 Receive Byte Count & Status Registers (358h, 35Ch)
Bits 31:24 Field Don't care The number of bytes in the packets received at EP4 and EP5 is counted and the value is indicated in these bits. Although the counting is made only up to the number of bytes equal to the maximum packet size specified in the payload register in the case of full packets, the count will be short of that maximum packet size in the case of short packets. The microcontroller refers to this value and reads one packet of data from the EP4/5 Receive FIFOs. The lower order 8 bits of the received byte count are stored in this register and the higher order bits are stored in the EP Receive byte counter MSB register. This register will not be valid when the transfer direction of the EPs is set to transmission. EP4, 5 RXCNT are cleared under the following conditions. 1. When an OUT token for the EP is received. 2. When the microcontroller resets the EP Receive packet ready bit. 3. When the microcontroller writes a "0" in the shall bit. This bit becomes valid only when EP4, 5 have been set to ISO IN transfer. This bit indicates whether or not an IN token for this EP was sent by the host in the immediately previous frame. 0: An IN token has not been sent for this EP in the immediately previous frame. 1: An IN token has been sent for this EP in the immediately previous frame. For details, see "Description 1" below. Reserved (Write "0" when writing to these bits) This bit becomes valid only when EP4 and EP 5 have been set to either bulk or interrupt transfer mode. This bit indicates whether or not valid data has been stored in the internal FIFO of the ML60841. For details, see "Description 2" below. This bit becomes valid only when EP4 and EP 5 have been set to either bulk or interrupt transfer mode. This bit indicates whether or not valid data has been stored in the internal FIFO of the ML60841. For details, see "Description 3" below. Reset X USB Reset X R/W X
23:08
00h
00h
R
07
00h
00h
R
06:02 01
00h 0b
00h 0b
R/W R/SET
00
0b
0b
R/RST
Note:
Write "0" to bit 00 when writing to bit 01 and also write "0" to bit 01 when writing to bit 00. The operation cannot be guaranteed when a value other than "0" is written.
[Description 1] The bit 07 (previous frame IN token bit) is valid only when EP4 and EP5 have been configured to the ISO IN mode. The value of this bit will be indeterminate when the configuration is other than ISO IN. The ML60841 judges whether or not an IN token to this EP was sent by the host during the immediately previous frame at the timing of detecting SOF, and updates the value of this bit at that timing. * This bit is updated to "1" when an IN token has been sent to this EP. * This bit is updated to "0" when an IN token has not been sent to this EP. Therefore, the microcontroller can know the correct status concerning the immediately previous frame by reading this bit after an SOF interrupt. See the diagram below for the detailed timings.
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PEDL60841-01
OKI Semiconductor
ML60841
1ms
1ms
1ms
USB Bus
S O F
IN
Token
S O F
IN
Token
S O F
S O F
Update
Update
Update
Update
Bit 07
"1" or "0" based on immediately previous state
"1"
"1"
"0"
See "Precautions in Control of ML60841" for the method of using this bit 07.
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PEDL60841-01
OKI Semiconductor
ML60841
[Description 2] Bit 01 (transmit packet ready) can be read and set. This bit can be set to "1" by writing a "1". The assert/deassert conditions of this bit are shown below. EP4 and EP5 have FIFO of two layers (layer A and B). The transmit packet ready bit also individually exists for layer A and layer B and this LSI automatically executes switching of these two layers.
Condition Assert Deassert When microcontroller sets both layer A bit and layer B bit. When ACK is received from the host with regard to transmit data of either layer A or layer B. Operation Transmitting from EP4 and EP5 is possible when asserted either from layer A or layer B. (Data is transmitted with regard to INT token.) Lock EP4 and EP5 when send data can not be prepared in both layer A and layer B. (NACL reply to IN token.)
Detailed example is shown below.
Layer A FIFO (64B) 1 2 3 Layers A and B FIFO both empty. Microcontroller writes data in layer A FIFO. Layer B FIFO (64B) Layer A FIFO Packet Ready x x O O O x x x Layer B FIFO Packet Ready x x x x O x O O O: Assert EP4, 5 Transmit Packet Ready Bit x x x x O x x x
Data write of 1 packet is completed. Transmits layer A FIFO data to USB bus 4 and writes next packet data to layer B FIFO. When data write to layer B FIFO is 5a completed before layer A FIFO becomes empty. When layer A FIFO becomes empty before 5b data write to layer B FIFO is completed. From 5a: Layer A FIFO became empty. 6 From 5b: Layer B FIFO became full. Starts transmitting layer B FIFO data to USB 7 bus.
x: Deassert
[Description 3] Bit 00 (Receive packet ready bit) can be read out by the microcontroller. In addition, it is possible to reset this bit to "0" by writing a "1". The conditions of asserting and deasserting this bit are as given below. EP4 and EP5 each have two separate layers of FIFOs, and also the receive packet ready bit is provided independently for layer A and layer B. The switching between these two layers is made automatically by the ML60841.
Condition Assert Deassert When an error-free packet is received in either layer A or layer B. When the microcontroller resets (by writing a "1") the bits of both layer A and layer B. Operation The microcontroller can read the EP4, 5 receive FIFOs. EP4 and EP5 are locked if packets of data have been received in both layer A and layer B. EP4 and EP5 can receive packet data when one of the bits of layer A and layer B has been reset.
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PEDL60841-01
OKI Semiconductor
ML60841
* EP0 Transmit Data Byte Count Register (360h)
Bits 31:06 05:00 Don't care EP0TFCnt[5:0] Field Reset X 0h USB Reset X 0h R/W X R/W
It is possible to suppress the transmission of invalid data by setting the number of bytes to be transmitted per packet in this register ("01h" for one-byte transmission). When sending successive packets with the same number of bytes, it is not necessary to set the value in this register each time (since the value set immediately before is retained). In the PIO mode, write the data in the FIFO for packet data transmission after first writing the number of bytes of transmit data in this register, and then set the transmit PKTRDY bit to "1". * EP1 Transmit Data Byte Count Register (364h)
Bits 31:07 06:00 Don't care EP1TFCnt[6:0] Field Reset X 0h USB Reset X 0h R/W X R/W
It is possible to suppress the transmission of invalid data by setting the number of bytes to be transmitted per packet in this register ("01h" for one-byte transmission). When sending successive packets with the same number of bytes, it is not necessary to set the value in this register each time (since the value set immediately before is retained). In the PIO mode, write the data in the FIFO for packet data transmission after first writing the number of bytes of transmit data in this register, and then set the transmit PKTRDY bit to "1". In the DMA mode, write the data in the FIFO after first writing the number of bytes of transmit data in this register. See the section "Precautions in Control of ML60841" for details on the method of using this register. * EP2 Transmit Data Byte Count Register (368h)
Bits 31:07 06:00 Don't care EP2TFCnt[6:0] Field Reset X 0h USB Reset X 0h R/W X R/W
It is possible to suppress the transmission of invalid data by setting the number of bytes to be transmitted per packet in this register ("01h" for one-byte transmission). When sending successive packets with the same number of bytes, it is not necessary to set the value in this register each time (since the value set immediately before is retained). In the PIO mode, write the data in the FIFO for packet data transmission after first writing the number of bytes of transmit data in this register, and then set the transmit PKTRDY bit to "1". In the DMA mode, write the data in the FIFO after first writing the number of bytes of transmit data in this register. See the section "Precautions in Control of ML60841" for details on the method of using this register.
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* EP3 Transmit Data Byte Count Register (36Ch)
Bits 31:06 05:00 Don't care EP3TFCnt[5:0] Field Reset X 0h USB Reset X 0h R/W X R/W
It is possible to suppress the transmission of invalid data by setting the number of bytes to be transmitted per packet in this register ("01h" for one-byte transmission). When sending successive packets with the same number of bytes, it is not necessary to set the value in this register each time (since the value set immediately before is retained). In the PIO mode, write the data in the FIFO for packet data transmission after first writing the number of bytes of transmit data in this register, and then set the transmit PKTRDY bit to "1". * EP4 Transmit Data Byte Count Register (370h)
Bits 31:10 09:08 07:00 Don't care EP4TFCntMSB[1:0] EP4TFCnt[7:0] Field Reset X 0h 0h USB Reset X 0h 0h R/W X R/W R/W
It is possible to suppress the transmission of invalid data by setting the number of bytes to be transmitted per packet in this register ("01h" for one-byte transmission). When sending successive packets with the same number of bytes, it is not necessary to set the value in this register each time (since the value set immediately before is retained). In the PIO mode, write the data in the FIFO for packet data transmission after first writing the number of bytes of transmit data in this register, and then set the transmit PKTRDY bit to "1". In the DMA mode, write the data in the FIFO after first writing the number of bytes of transmit data in this register. See the section "Precautions in Control of ML60841" for details on the method of using this register. * EP5 Transmit Data Byte Count Register (374h)
Bits 31:09 08 07:00 Don't care EP5TFCntMSB[0] EP5TFCnt[7:0] Field Reset X 0b 0h USB Reset X 0b 0h R/W X R/W R/W
It is possible to suppress the transmission of invalid data by setting the number of bytes to be transmitted per packet in this register ("01h" for one-byte transmission). When sending successive packets with the same number of bytes, it is not necessary to set the value in this register each time (since the value set immediately before is retained). In the PIO mode, write the data in the FIFO for packet data transmission after first writing the number of bytes of transmit data in this register, and then set the transmit PKTRDY bit to "1". In the DMA mode, write the data in the FIFO after first writing the number of bytes of transmit data in this register. See the section "Precautions in Control of ML60841" for details on the method of using this register.
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ML60841
* ISO Mode Select Register (378h)
Bits 31:06 Field Don't care This bit will be valid only when EP5 has been configured for ISO IN transfer. This bit specifies timing of layer switching and clearing of the two-layer FIFO for EP5. 0: The FIFO layer switching and clearing are made every time an SOF is received. 1: The FIFO layer switching and clearing are made only when an IN token for EP5 has been sent by the host during the immediately preceding frame. The ML60841 checks this bit and carries out the corresponding operation at the timing when an SOF is received. This bit will be valid only when EP4 has been configured for ISO IN transfer. This bit specifies the timing of layer switching and clearing of the two-layer FIFO for EP4. 0: The FIFO layer switching and clearing are made every time an SOF is received. 1: The FIFO layer switching and clearing are made only when an IN token for EP4 has been sent by the host during the immediately preceding frame. The ML60841 checks this bit and carries out the corresponding operation at the timing when an SOF is received. Don't care Reset X USB Reset X R/W X
05
0b
0b
R/W
04
0b
0b
R/W
03:00
X
X
X
[Description] Bits 05 and 04 are valid only when EP4 and EP5 have respectively been configured for ISO IN transfer. These bits specify the timing of switching between the two layers of the 2-layer FIFO and the timing of clearing the FIFO during ISO IN transfers. The settings of these bits are ignored (that is, they have no effect on the operations) when EP5 and EP4 have been configured for a transfer mode other than the ISO IN transfer mode. See the section "Precautions in Control of ML60841" for details on the method of using these bits.
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ML60841
* EP0 Control Register (39Ch)
Bits 31:05 Field Don't care Data sequence toggle bit (Transmit): The ML60841 carries out automatically the synchronization based on the data sequence toggle mechanism. Further, write operations to these bits (bit 04 and bit 01) are not valid. Don't care Data sequence toggle bit (Receive): The ML60841 carries out automatically the synchronization based on the data sequence toggle mechanism. Further, write operations to these bits (bit 04 and bit 01) are not valid. Stall bit: The ML60841 automatically sets this bit to "1" during EP0 reception (data stage of a control write transfer) when a packet having a number of bytes exceeding the maximum packet size specified in EP0PLD (or a packet with missing EOP) is received. This bit is cleared to "0" automatically when a setup packet is received, in order to conform to the protocol stall of USB Rev. 1.1. Reset X USB Reset X R/W X
04
X
X
X
03:02 01
X 0b
X 0b
X R/W
00
0h
0h
R/W
* EP1/2/3/4/5 Control Registers (3A0/3A4/3A8/3AC/3B0h)
Bits 31:05 03 Field Don't care Rate feed back: Valid only in the case of EP3. This bit will remain fixed at "0" in the case of all other EPs. FIFO Clear: Set this bit at the same time as setting the data sequence toggle bit. Do not set this bit at any other time. This bit is valid only when the EP has been configured for transmission in the EP control register. When a "1" is written to this bit, the transmit FIFO of the corresponding EP will be cleared. (This bit itself will remain "0".) Data sequence toggle bit: A reset is made when a "1" is written in this bit. When initializing the EP, a "1" is written in this bit thereby resetting the data packet toggle bit, and the PID of DATA0 is specified. (This bit too becomes "0".) The synchronization operation thereafter based on the data sequence toggle mechanism will be made automatically. Stall bit: The ML60841 automatically sets this bit to "1" during EP0 reception (data stage of a control write transfer) when a packet having a number of bytes exceeding the maximum packet size specified in EP0PLD (or a packet with missing EOP) is received. Reset X 0b USB Reset X 0b R/W X R/W
02
0b
0b
R/Reset
01
0b
0b
R/Reset
00
0b
0b
R/W
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NOTES ON THE ML60841 CONTROL
Host/Device Setting and Select Control This ML60841 selects Host or Device operation mode according to the status of the D/H pin after reset. Therefore, it is necessary for the microcontroller to wait until the setting is over (*). After setting of the operation mode, only write to a register corresponding to the operation mode is guaranteed. (*) By setting the HOST/DEV SEL register, operation mode can also be set actively from the microcontroller side. Supply current is reduced by stopping clock to the device control section in the case of Host operation mode setting and clock to the host control section in the case of Device mode setting. The Host/Device operation mode settings and the software control method upon mode switching are described below. (1) Operation Mode Setting
Processing by ML60841 Hardware reset
Software control
Wait for 50 s after releasing hardware reset. Monitor HOST/DEV SEL register until operation mode setting by ML60841 is over
D/H pin D (High) H (Low) PDCTL pin High (pulled down) 1b HOST/DEV SEL register setting
HOST/DEV SEL [01] 0b Release HdVbusIntMask
Device block operation
Host block operation
0b
HOST/DEV SEL [00] 1b
Host controller control
Device controller control
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(2) Shifting to Device operation mode in Host operation
Processing by ML60841
Software control
D/H pin change Host controller control HD/VBUS INT interrupt HdVbusIntStt [00] 0b Execution of internal processing (When starting the processing, bit 01 of HOST/DEV SEL register is set to "1" and then reset to "0" at completion of processing.) 1b
HOST/DEV SEL [01] 0b
1b
Device block operation
HOST/DEV SEL [00] 1b
0b Trouble processing
Proceed to ML60841 operation mode setting
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(3) Shifting to Host operation mode in Device operation
Processing by ML60841
Software control
D/H pin change Device controller control HD/VBUS INT interrupt HdVbusIntStt [00] 0b Execution of internal processing (When starting the processing, bit 01 of HOST/DEV SEL register is set to "1" and then reset to "0" at completion of processing.) 1b
HOST/DEV SEL [01] 0b
1b
Host block operation
HOST/DEV SEL [00] 0b
1b Trouble processing
Proceed to ML60841 operation mode setting
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Notes on DMA Data Transfer Address The data bus width in the ML60841 can be set to 16 bits or 32 bits. In addition, it is possible to specify 16 bits or 32 bits as the transfer size per one DREQ in the DMA function. The method of inputting the address is given below for the different combinations of the data bus width and the transfer size per one DREQ. (1) Bus width = 32 bits & Transfer size per DREQ = 32 bits
DREQx DACKx BS A12:1 Input values that are integer multiples of 4
For example, when carrying out data transfer with the FIFO ACC register (20Ch) of the host controller section, it is necessary to repeat the address specification in the sequence 20Ch 20Ch .... 20Ch 20Ch (the starting address is 20Ch and the ending address is also 20Ch). Further, when carrying out data transfer with the EP1 transmit/receive FIFO register (388h) of the device controller section, it is necessary to repeat the address specification in the sequence 388h 388h .... 388h 388h (the starting address is 388h and ending address is also 388h).
(2) Bus width = 16 bits & Transfer size per DREQ =32 bits
DREQx DACKx BS A12:1
Input values that are integer multiples of 4
Input a value equal to (immediately preceding address +2)
For example, when carrying out data transfer with the FIFO ACC register (20Ch) of the host controller section, it is necessary to repeat the address specification in the sequence 20Ch 20Eh 20Ch 20Eh .... 20Eh 20Ch 20Eh (the starting address is 20Ch and the ending address is 20Eh). Further, when carrying out data transfer with the EP1 transmit/receive FIFO register (388h) of the device controller section, it is necessary to repeat the address specification in the sequence 388h 38Ah 388h 38Ah .... 38Ah 388h 38Ah (the starting address is 388h and the ending address is 38Ah).
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ML60841
Notes on the Host Control As to its host function, the ML60841 complies with OHCI, but possesses special settings and functions apart from OHCI. The special part is described below. (1) DMA mode 0 register, DMA mode 1 register These are the setting registers to cope with DMA transfer of microcontroller. They must be set as described below. As host, only the channel 0 of DMA can be used. Therefore, set the following contents in the DMA mode 0 register. Operation is not guaranteed if DMA channel 1 is used. * Bits 03, 02 Specifies data bit length for one time of data transfer (DREQ). Since in this LSI the length is fixed at 32 bits, always set "10". Operation is not guaranteed if a value other than "10" is set. These bits correspond to bits TS1 and TS0 of the DMA channel control register of the microcontroller and it is necessary to set the same bit length as the microcontroller. (2) Host control register Set DMA/PIO transfer (bit 03) and interrupt factor mask (bits 02, 01) from the host section. By setting DMA/PIO transfer (bit 03) = 1 (PIO transfer), interrupt is generated if the transfer request address from host core is outside the range of internal RAM address. At this time it is necessary to process the data of double word count indicated in bits 18:16 (write) or bits 26:24 (read) of the STT/TRANS CNT register. (3) Locations of Descriptor, Data Buffer, etc. It is necessary to place the end point descriptor (ED), transfer descriptor (TD) and interrupt table (HCCA) required for transfer by OHCI in the internal RAM (4 KB) of the ML60841. Moreover it is also necessary to locate ED and TD at 16-byte boundary (at 32-byte boundary for TD of isochronous transfer) and HCCA at 256-byte boundary. The buffer for data to be transferred can be located either in the internal RAM of the ML60841 or in external memory area, but the top address should be set on 4-byte boundary. The ML60841 always compares the address set in the RAM ADR register and transfer request address. If they are the same, they are treated as transfer to the internal RAM of the ML60841; therefore, interrupt for host data transfer is not requested to microcontroller. Therefore by locating the data buffer in the internal RAM of the ML60841, interrupt requests etc. to microcontroller are minimized and thus burden on the CPU can be considerably reduced. However, it does not limit the use of the ML60841. It is necessary to suitably locate considering system configuration restraints and burden of microcontroller, etc. (4) Interrupt Processing Two types of interrupts, namely interrupt relating to host data transfer and interrupt from host core exist in the host section of the ML60841. As regards the interrupt relating to host data transfer, the generation conditions are as follows according to the value (DMA/PIO) of bit 03 of the HOST CTL register. (a) In the case of bit 03 of the HOST CTL register = "0" (DMA) * When the transfer address is outside the internal RAM address range of the ML60841. * When either of the following conditions occurs within the internal RAM address range of the ML60841: - When continuity (*) of transfer addresses is lost. The ML60841 monitors continuity of addresses and generates interrupt when continuity is lost. Therefore, interrupt is always generated at the time of first transfer. - When direction of transfer has changed. When direction of transfer has changed with regard to the transfer executed just before, that is, when the value of bit 00 of the host data transfer request register has changed.
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In such case it is necessary to again set the transfer length (basically the maximum value) and transfer start address with regard to the DMA controller in interrupt processing. Moreover, it is necessary to clear this interrupt factor after completing the setting with regard to the DMA controller. (b) In the case of bit 03 of the HOST CTL register = "1" (PIO) When the transfer address is outside the internal RAM address range of the ML60841, interrupt is generated every time a transfer request is generated. However, interrupt is not generated with regard to transfer of double word shown in bits 26:24 (read)/bits 18:16 (write) of the ST/TRANS CTN register at the time of interrupt generation. (Execution of transfer of double word count shown in the said bit in one time of interrupt is possible.) In interrupt processing it is necessary to write/read data to and from the FIFO ACC register by PIO after clearing of the interrupt factor. (*) Regarding continuity of addresses Continuity of addresses means existence of "+4h" address with regard to the just preceding transfer address. For example when doing 32-bit access by dividing the data of 20h byte up to addresses 00h to 1Fh into 12h byte and Eh byte, since address changes as 00h 04h 08h 0Ch 10h, 10h 14h 18h 1Ch and 10h appears twice in succession, the continuity is lost at this part. Therefore interrupt is generated when starting data transfer of Eh byte.
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ML60841
Notes on Device Control (1) Packet Data Transmission (ML60841 USB Host) In the ML60841, it is possible to select a 16-bit or 32-bit data bus width for the microcontroller interface. In addition, data transfer can be made only in the PIO mode with the FIFO for EP0 and EP3 packet data transfer, but can be made in either the PIO mode or the DMA mode with the FIFO for EP1, 2, 4, 5 packet data transfer. For example, when an 11-byte packet data is written by PIO transfer into a FIFO for packet data transfer using a 16-bit data bus width, the number of bytes written to the FIFO will be 12 bytes. In other words, valid packet data (11 bytes) + invalid packet data (1 byte) will be written in the FIFO. In the ML60841, the invalid packet data can be suppressed and only valid packet data can be transmitted over the USB bus by setting the number of valid packet data bytes per packet in the EPn transmit data byte count register. This is explained below using some concrete examples of data transfer using a 16-bit data bus width. Example 1: When 11 bytes of valid data + 1 byte of invalid data are written to EP1 by PIO transfer.
Initialization processing (EP1 Configuration, DMA control register setting, etc.)
Setting EP1 transmit data byte count register 11 bytes
Writing data to EP1FIFO by PIO transfer (Valid data 11 bytes + invalid data 1 byte = 12 bytes in total)
Setting transmit packet ready bit
Transmission over USB bus of 11-byte packet data
In Example 1 above, data writes to EP1FIFO are executed six times (12 bytes) with a data bus width of 16 bits. However, since there are only 11 bytes of valid data, one byte written will be invalid data. Because the number of valid data bytes (11 bytes) is set in the EP1 transmit data byte count register, only the 11 bytes of valid data are transmitted over the USB bus after discarding the one byte of invalid data within the ML60841 after the transmit packet ready bit has been set. Further, PIO transfer is one in which the target EP for DMA transfer has not been specified in bits 06:05 of the DMA control register, or DMA has been disabled in bit 00 although the target EP for DMA transfer has been specified.
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ML60841
Example 2:
When 11 bytes of valid data + 1 byte of invalid data are written to EP1 by DMA transfer
Initialization processing (EP1 Configuration, DMA control register setting, etc.)
Setting EP1 transmit data byte count register 11 bytes
Writing data in EP1FIFO by DMA transfer (Valid data 11 bytes + invalid data 1 byte = 12 bytes in total)
Transmission over USB bus of 11-byte packet data
In Example 2 above, data writes to EP1FIFO are executed six times (12 bytes) with a data bus width of 16 bits. However, since there are only 11 bytes of valid data, one byte in the written data will be invalid data. Because the number of valid data bytes (11 bytes) is written in the EP1 transmit data byte count register, after the DMA transfer of 12 bytes has been completed, the one invalid data byte is discarded within the ML60841, and only 11 bytes of valid data are transmitted over the USB bus. Further, DMA transfer is one in which the target EP for DMA transfer has been specified in bits 06:05 of the DMA control register and also DMA transfer has been enabled in bit 00 of the DMA control register for the EP that has been specified as the target for DMA transfer. The relationship among the value set in the transmit data byte count register during DMA transfer or PIO transfer, the number of bytes written to the FIFO for transferring packet data, and the number of bytes of packet data transmitted over the USB bus is shown in the table below.
Number of bytes written to FIFO for packet data transfer *1 *2 Value set in the transmit data byte count register M N Number of bytes in the packet data transmitted over USB bus M N Remarks
DMA Transfer PIO Transfer
*1: Data transfer is requested by outputting DREQ until completion of the transfer of data including the number of bytes set in the transmit data byte count register (for example, 12 bytes of DMA transfer when the data bus width is 16 bits and M=11, 6 bytes of DMA transfer when M=6 and the data bus width is 16 bits, 12 bytes of DMA transfer when the data bus width is 32 bits and M=11, 8 bytes of DMA transfer when M=6 and the data bus width is 32 bits), the DREQ output is stopped as soon as the required number of bytes has been reached, and packet data containing M bytes of valid data is transmitted over the USB bus. *2: Packet data is transmitted with N bytes, irrespective of the number of bytes written into the FIFO for packet data transfer, at the time when the packet ready bit is set, where N is the value set in the transmit data byte count register. In other words, if the number of bytes written into the FIFO for packet data transfer is less than N bytes, indeterminate data will be added to make up for the insufficient number of bytes and a packet data with N bytes is transmitted over the USB bus. If the number of data bytes written to the FIFO for packet data transfer is more than N bytes, the excess number of data bytes will be discarded and only N bytes of packet data are transmitted over the USB bus.
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ML60841
(2) ISO IN Transfer Control In the ML60841, when an EP has been configured for the ISO IN transfer mode, it is possible to specify the following two types of operation modes: In order to transfer data without breaks, the mode in which switching between the two FIFO layers is made every time an SOF is received (Mode 0) In order to avoid loss of data, the mode in which the switching between the two FIFO layers is made after the data written in the FIFO has been transmitted over the USB bus (when the SOF detection is made subsequent to receiving the IN token) (Mode 1) These operating modes can be specified using the ISO mode select register (378h). The operations by the LSI in these two modes are shown below. Operation equivalent to ML60852A (Corresponding bit is "0" in the ISO mode select register)
1 Frame (1 ms) USB Bus S S S S IN P3 S IN P4
Layer switching
Layer switching
Layer switching
Layer switching
Layer switching
USB side
FIFO
A
B
P1
A
P2
B
P3
A
P4
MCU side
B
P1
A
P2
B
P3
A
P4
B
P5
Write P1
Write P2
Write P3
Write P4
Write P5
ISO Mode Select Register
"0"
Write Mode 0
Note:
S
denotes an SOF, IN
denotes an IN token, and
Pn
denotes data of packet No. n.
The above figure shows the case in which the packet data are written from the MCU side successively in the order P1 P2 ... P5, and an IN token arrives from the USB host during the frame following the completion of writing packet P3. The ISO mode select register is set to "0" after the first SOF interrupt, and there is no need to change the setting thereafter. In this mode (Mode 0), since the layer is switched every time an SOF is received, the packet data prior to the packet data (P3 in the above figure) written during the frame period immediately preceding the IN token reception are not transmitted. The latest data P3 at the time an IN token is received will be transmitted in real time.
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ML60841
Operation of FIFO layer switching after transmitting FIFO data (Corresponding bit is "1" in the ISO mode select register)
1 Frame (1 ms) USB Bus
S S S S IN P1 S IN P2
Layer switching
Layer switching
USB side FIFO MCU side
A
B
P1
B
P1
B
P1
A
P2
B
P1
A
P2
A
P2
A
P2
B
P3
Write P1
Write P2
Write P3
ISO Mode Select Regist
"0"
"1"
Write Mode 0
Write Mode 1 & read immediately preceding frame IN token bit
Read immediately preceding frame IN token bit
Read immediately preceding frame IN token bit
Read immediately preceding frame IN token bit
Note:
S
denotes an SOF,
IN
denotes an IN token, and
Pn
denotes data of packet No. n.
The above figure shows the case in which the packet data are written from the MCU side successively in the order P1 P2 P3, and an IN token arrives from the USB host during the second frame after the completion of writing packet P2. The ISO mode select register is set to "0" after the first SOF interrupt. By setting to Mode 0 at this time, the ML60841 automatically carries out FIFO layer switching at the next SOF. Mode 1 is set after the SOF interrupt next to the completion of writing the data of packet P1, and thereafter the operation in Mode 1 is specified. After the specification of Mode 1, the bit 07 (immediately preceding frame IN token bit) of the EPn status register is read out at every SOF interrupt, and since packet data would have been transferred to the USB bus during the preceding frame if this bit has been set to "1", the ML60841 automatically switches the FIFO layer. Therefore, since one of the FIFO layer would be in the free state, the microcontroller writes packet data to the FIFO. Writing packet data to the FIFO will be suspended if this bit has been set to "0". In this mode (Mode 1), since the FIFO layer is switched at the time of an SOF detection immediately after receiving an IN token from the USB host, the packet data written earlier by the microcontroller in the FIFO (the packet data P1 and P2 in the above figure) will not be lost. However, depending on the relationship between the timings of data writing by the microcontroller and IN token transmission from the USB host, it is possible that the latest data is not transmitted. Therefore, change to Mode 0 in applications that request for the transmission of the latest data.
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ABSOLUTE MAXIMUM RATINGS
Parameter Supply voltage Input voltage Output current Power dissipation (BGA) Power dissipation (TQFP) Storage temperature Symbol VCC VI IO Pb Pt TSTG Ta = 70C -- Ta = 25C, VSS = 0 V Condition Rating -0.3 to +4.6 -0.3 to + VCC + 0.3 -12 to +12 330 300 -55 to +150 Unit V V mA mW C
RECOMMENDED OPERATING CONDITIONS
Parameter Supply voltage Operating temperature Crystal frequency Symbol VCC Ta fOSC Condition -- -- -- Range 3.0 to 3.6 0 to 70 48 0.12 Unit V C MHz
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ELECTRICAL CHARACTERISTICS
DC Characteristics (1)
(VCC = 3.0 to 3.6 V, VSS = 0 V, Ta = 0 to +70C) Parameter "H" input voltage "L" input voltage "H" input voltage "L" input voltage Schmitt trigger input voltage "H" output voltage "L" output voltage "H" input current "L" input current "H" input current "L" input current 3-state output leakage current Dynamic supply current Symbo l VIH VIL VIH VIL Vt+ Vt- Vt VOH VOL IIH IIL IIH IIL IOZH IOZL IDDO (Vt+) - (Vt-) IOH = -100 A IOH = -4 mA IOL = 100 A IOL = 4 mA VIH = VCC VIL = VSS VIH = VCC VIL = VSS VOH = VCC VOL = VSS VIH = VDD VIL = GND Output open Ta = 0 to 50C, Note 7 Ta = 50 to 70C, Note 7 -- -- -- -- 100 A 200 VCC -- -- 50 mA Condition Min. VCC x 0.7 -- VCC x 0.8 -- -- 0.8 -- VCC - 0.2 2.2 -- -- -- -10 -- -200 -- -10 Typ. -- -- -- -- -- -- 0.4 -- -- -- -- -- -- -- Max. -- 0.8 -- VCC x 0.2 VCC x 0.7 -- -- -- -- 0.2 0.45 10 -- 10 -10 10 -- Unit V V V V V V V V V V V A A A A A A Note 2 Note 3 Note 4 Note 5 Note 6 RESET Pin Note 1 Xin
-- -- --
Static supply current
IDDS
(Note 1) (Note 2) (Note 3) (Note 4) (Note 5) (Note 6) (Note 7)
Applicable to pins corresponding to I/O Type "*2, *3, *4" of list of parameters of PIN CONFIGURATION. Applicable to pins corresponding to I/O Type "*3, *5" of list of parameters of PIN CONFIGURATION. Applicable to pins corresponding to I/O Type "*3, *5, *6" of list of parameters of PIN CONFIGURATION. Applicable to pins corresponding to I/O Type "*4" of list of parameters of PIN CONFIGURATION. Applicable to pins corresponding to I/O Type "*2" of list of parameters of PIN CONFIGURATION. Applicable to pins corresponding to I/O Type "*3" of list of parameters of PIN CONFIGURATION. The condition when 3 s have elapsed after writing a "1" in bit 01 of the SOFT RESET/POWER DOWN Control Register. All output pins open.
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DC Characteristics (2) - USB Port
(VCC = 3.0 to 3.6 V, VSS = 0 V, Top = 0 to +70C) Parameter Differential input sensitivity Differential common mode range Single-ended receiver threshold "H" output voltage "L" output voltage Output leakage current Symbol VDI VCM VSE VOH VOL ILO 15 k to GND 1.5 k to 3.6 V 0 V < VIN < VCC Condition |(D+) - (D-)| Including VDI Min. 0.2 0.8 0.8 2.8 -- -10 Typ. -- -- -- -- -- -- Max. -- 2.5 2.0 3.6 0.3 +10 Unit V V V V V A D+, D- Pin
AC Characteristics - USB Port Section (Full-Speed)
(VCC = 3.0 to 3.6 V, VSS = 0 V, Top = 0 to +70C) Parameter Rise time Fall time Output signal crossover voltage Driver output resistance Data rate Symbol TR TF VCRS ZDRV TDRATE In normally operating state Average bit rate (12 Mbps 0.25%) Condition (Note 1) CL = 50 pF CL = 50 pF Min. 4 4 1.3 28 11.97 Typ. -- -- -- -- -- Max. 20 20 2 44 12.03 Unit ns ns V Mbps D+, D- Pin
(Note 1) TR and TF are transition times of 10% point and 90% point of amplitude.
AC Characteristics - USB Port Section (Low-Speed)
(VCC = 3.0 to 3.6 V, VSS = 0 V, Top = 0 to +70C) Parameter Rise time Fall time Output signal crossover voltage Data rate Symbol TR TF VCRS TDRATE Average bit rate (1.5 Mbps 0.25%) Condition (Note 1) CL = 150 pF CL = 150 pF Min. 75 75 1.3 1.4775 Typ. -- -- -- -- Max. 300 300 2 1.5225 Unit ns ns V Mbps D+, D- Pin
(Note 1) TR and TF are transition time of 10% point and 90% point of amplitude.
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AC Characteristics - Microcontroller Interface Section
(VCC = 3.0 to 3.6V, VSS = 0 V, Ta = 0 to +70C, Load capacitance 20 pF) Parameter High level time of BUS_CLK Low level time of BUS_CLK BUS CLK period CS setup time for rise of BUS_CLK CS hold time for rise of BUS_CLK A12:A1 setup time for rise of BUS_CLK A12:A1 hold time for rise of BUS_CLK RD/WR setup time for rise of BUS_CLK RD/WR hold time for rise of BUS_CLK BS setup time for rise of BUS_CLK BS hold time for rise of BUS_CLK Delay time from rise of BUS_CLK till WAIT becomes valid Delay time from rise of BUS_CLK till WAIT becomes invalid DACKn setup time for rise of BUS_CLK DACKn hold time for rise of BUS_CLK Delay time from rise of BUS_CLK till D31:D0 (at the time of read) are set up Delay time from rise of BUS_CLK till D31:D0 (at the time of read) become Hi-Z D31:D0 (at the time of write) setup time for rise of BUS_CLK D31:D0 (at the time of write) hold time for rise of BUS_CLK DRAKn setup time for rise of BUS_CLK DRAKn hold time for rise of BUS_CLK Delay time from rise of BUS_CLK till INTR becomes valid Delay time from rise of BUS_CLK till DREQn becomes valid Delay time from both CS and RD being enabled until D31:D0 are output Delay time from falling edge of BUS_CLK until WAIT becomes disabled (When reading the Host HCI register) Delay time from rising edge of BUS_CLK until valid data is output in D31:D0 (during read) (When reading the Host HCI register) Delay time from DRAK being enabled until DREQn becomes disabled Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 0 4 18 26 19 0 13 10 15 0 18 18 4 15 10 44 10 ns Min. 8 8 30 15 10 15 t1 + 10 15 10 15 0 18 18 Max. Unit
Note 1: The maximum delay time is 10 ns for the delay time (t17) from either CS or RD becoming disabled until D31:D0 (during read) become high impedance. If CS and RD disable timings become after the trailing clock rising edge of T2 cycle and if also the access cycle following the read access cycle is a write access cycle, then a bus collision may be caused by this delay time. Therefore, when the above condition occurs, it is necessary to introduce between the access cycles an idle cycle that is one clock cycle or longer. Note 2: The maximum delay time is 44 ns for the delay time (+16) from the rising edge of BUS_CLK until valid data is output in D31:D0 (during read). Introduce a software wait (minimum 3 waits) if the setup time cannot be satisfied at the time of taking in the read data. The timing specification diagram shown in the next page is the case when 3 wait states are introduced by software.
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T1
t1 t2
ML60841
Tw1 Tw2 Tw3 T2
BUS_CLK
t3
CS
t4
t5
A12 to A1
t6 t7
RD/WR
t8 t9
BS
Broken line: In the case of a Host HCI register read Full line: Cases other than the above Note: One or more waits will be introduced depending on the internal operating conditions of this LSI during an HCI register access immediately following an HCI register write.
t10
t11
WAIT
t12 t13 t25
DACK
t14 t15
RD
t24
DATA (ML60841 MCU)
t16 (When reading a register (including theRAM) other than a Host HCI register)
DATA (ML60841 MCU)
t26 (During a Host HCI register read) t17
DATA (MCU ML60841)
t18 t19
BUS_CLK
DRAK
t20 t21
INTR
t22
DREQ
t23
t27
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TIMING DIAGRAM
Basic Bus Cycle (1) Reset
VCC OSC & BUS_CLK
RESET
50 s
50 s

VCC rises and the RESET signal is asserted. Oscillation (48 MHz) of a crystal oscillator becomes stable and BUS_CLK is input. Since oscillation stabilization time ( to ) of a crystal oscillator differs depending on the crystal oscillator used, take suitable time. RESET signal is deasserted. Hold the RESET signal active for at least 50 s ( to ) for the ML60841 to be initialized. Internal setup of the ML60841 is completed and access from microcontroller becomes possible. Do not access the ML60841 before step .
Supply the BUS_CLK (bus clock) signal to the ML60841 not later than step .
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(2) PIO Read (ML60841 to Microcontroller)
Host HCI Register Read
T1 BUS_CLK TW TW TW T2 T1
Register Read other than Host HCI Register
TW TW T2
CS
A12:1
RD/WR
BS
RD
D31:0 (RD Data) WAIT
(Note) Regarding access to the HCI register immediately after HCI register write, one or more waits are additionally inserted according to the internal operation status of the ML60841.
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(3) PIO Write (Microcontroller to ML60841)
Register Write (Including Host HCI Register)
T1 BUS_CLK CS A12:1 TW TW T2 T1
Host HCI Register Write #2
TW TW TW T2
RD/WR BS RD
("H" level)
D31:0 (WR Data) WAIT
(Note) Regarding access to the HCI register immediately after HCI register write, one or more waits are additionally inserted according to the internal operation status of the ML60841. The Host HCI Reg Write #1 shown in the above diagram represents the case when the wait is not additionally inserted and Host HCI Rer Write #2 represents the case when the wait is additionally inserted.
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(4) Dual Address DMA Read (ML60841 to Memory)
T1 BUS_CLK TW TW T2 T1 TW TW T2
CS
A12:1
RD/WR
BS
RD
D31:0 (RD Data) WAIT
DACK
(Note) Insert three or more waits at the time of OHCI register read and insert two or more waits when reading a register other than OHCI (including the device controller).
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(5) Dual Address DMA Write (Memory to ML60841)
T1 BUS_CLK TW TW T2 T1 TW TW T2
CS A12:1
RD/WR BS RD ("H" level)
D31:0 (WR Data) WAIT
DACK
(Note)
Insert two or more waits.
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PACKAGE DIMENSIONS
(Unit: mm)
TQFP120-P-1414-0.40-K
Mirror finish
5
Notes for Mounting the Surface Mount Type Package
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5m) 0.55 TYP. 3/Nov. 12, 1998
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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(Unit: mm)
P-TFBGA120-0909-0.65
5
Notes for Mounting the Surface Mount Type Package
Package material Ball material Package weight (g) Rev. No./Last Revised
Epoxy resin Sn/Pb 0.16 TYP. 1/Mar. 11, 2002
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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REVISION HISTORY
Document No.
PEDL60841-01
Date
Oct. 2, 2002
Page Previous Current Edition Edition
- -
Description
Preliminary first edition
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NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2002 Oki Electric Industry Co., Ltd.
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