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SPLC782A
16COM/80SEG Controller/Driver
FEB. 15, 2005 Version 1.7
Sunplus Technology reserves the right to change this documentation without prior notice. Information provided by Sunplus Technology is believed to be accurate and reliable. However, Sunplus Technology makes no warranty for any errors which may appear in this document. Contact Sunplus Technology to obtain the latest version of device specifications before placing your order. No responsibility is assumed by Sunplus Technology for any infringement of patent
or other rights of third parties which may result from its use. In addition, Sunplus products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus.
SPLC782A
Table of Contents
PAGE
1. GENERAL DESCRIPTION .......................................................................................................................................................................... 4 2. FEATURES .................................................................................................................................................................................................. 4 3. BLOCK DIAGRAM ...................................................................................................................................................................................... 4 4. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 5 5. FUNCTIONAL DESCRIPTIONS.................................................................................................................................................................. 6 5.1. OSCILLATOR .......................................................................................................................................................................................... 6 5.2. CONTROL AND DISPLAY INSTRUCTIONS ................................................................................................................................................... 6 5.3. INSTRUCTION TABLE............................................................................................................................................................................... 8
5.4. 8-BIT OPERATION AND 16-DIGIT 1-LINE DISPLAY (USING INTERNAL RESET).............................................................................................. 9 5.5. 4-BIT OPERATION AND 16-DIGIT 1-LINE DISPLAY (USING INTERNAL RESET)............................................................................................ 10 5.6. 8-BIT OPERATION AND 16-DIGIT 2-LINE DISPLAY (USING INTERNAL RESET)............................................................................................ 10 5.7. RESET FUNCTION .................................................................................................................................................................................11 5.8. DISPLAY DATA RAM (DD RAM)............................................................................................................................................................ 13 5.9. TIMING GENERATION CIRCUIT............................................................................................................................................................... 13 5.10. LCD DRIVER CIRCUIT ....................................................................................................................................................................... 13 5.11. CHARACTER GENERATOR ROM (CG ROM)....................................................................................................................................... 13 5.12. CHARACTER GENERATOR RAM (CG RAM)........................................................................................................................................ 13 5.13. CURSOR/BLINK CONTROL CIRCUIT .................................................................................................................................................... 17 5.14. INTERFACING TO MPU....................................................................................................................................................................... 18 5.15. SUPPLY VOLTAGE FOR LCD DRIVE..................................................................................................................................................... 20 5.16. REGISTER --- IR (INSTRUCTION REGISTER) AND DR (DATA REGISTER) ................................................................................................ 22 5.17. BUSY FLAG (BF) ............................................................................................................................................................................... 22 5.18. ADDRESS COUNTER (AC).................................................................................................................................................................. 22 5.19. SEGMENT DATA DIRECTION ............................................................................................................................................................... 22 5.20. COMMON DATA DIRECTION ................................................................................................................................................................ 22 5.21. I/O PORT CONFIGURATION ................................................................................................................................................................ 22 6. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 24 6.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................. 24 6.2. DC CHARACTERISTICS (VDD = 2.4V TO 4.5V, TA = -20 TO +75) .................................................................................................... 24 6.3. DC CHARACTERISTICS (VDD = 4.5V TO 5.5V, TA = -20 TO +75) .................................................................................................... 25 6.4. AC CHARACTERISTICS (VDD = 4.5V TO 5.5V, TA = -20 TO +75) .................................................................................................... 25 6.5. AC CHARACTERISTICS (VDD = 2.4V TO 4.5V, TA = -20 TO +75) .................................................................................................... 26 6.6. WRITE MODE TIMING DIAGRAM (WRITING DATA FROM MPU TO SPLC782A).......................................................................................... 27 6.7. READ MODE TIMING DIAGRAM (READING DATA FROM SPLC782A TO MPU)........................................................................................... 27 6.8. THE FOLLOWING GRAPS SHOW THE RELATIONSHIP BETWEEN FOSC AND TEMPERATURE ......................................................................... 27 7. APPLICATION CIRCUITS ......................................................................................................................................................................... 28 7.1. INTERFACE TO MPU............................................................................................................................................................................. 28 7.2. APPLICATIONS FOR LCD ...................................................................................................................................................................... 29 8. CHARACTER GENERATOR ROM ........................................................................................................................................................... 35 8.1. SPLC782A - 016 ................................................................................................................................................................................ 35 8.2. SPLC782A - 022 ................................................................................................................................................................................ 36
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9. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 37 9.1. PAD ASSIGNMENT AND LOCATIONS....................................................................................................................................................... 37 9.2. ORDERING INFORMATION ..................................................................................................................................................................... 37 10. DISCLAIMER............................................................................................................................................................................................. 38 11. REVISION HISTORY ................................................................................................................................................................................. 39
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SPLC782A
16COM/80SEG CONTROLLER/DRIVER
1. GENERAL DESCRIPTION
The SPLC782A, a dot-matrix LCD controller and driver, is a low-power CMOS integrated circuit. for designing the low-cost products. The SPLC782A is capable of connecting with MPU for LCD application and easily to be used Provide connecting to 4-bit or 8-bit MPU Direct driver for LCD: 16 COMs x 80 SEGs 80-channel Bi-Direction segment driver 16-channel Bi-direction common driver Duty factor (selected by program): 1/8 duty: 1 line of 5 x 8 dots
2. FEATURES
Character generator ROM: 10880 bits Character font 5 x 8 dots: 192 characters Character font 5 x 10 dots: 64 characters 4 type CGROM mode, Max. 256 characters can be used. Character generator RAM: 512 bits Character font 5 x 8 dots: 8 characters
1/11 duty: 1 line of 5 x 10 dots
1/16 duty: 2 lines of 5 x 8 dots / line
LCD type-A, type-B waveform can be selected. Built-in power on automatic reset circuit Built-in Bias resistor Built-in oscillator circuit (with internal resistor)
Character font 5 x 10 dots: 4 characters
3. BLOCK DIAGRAM
OSC1 MOD0 MOD1 VDD VSS V2 V3 VPP DB0-DB3 DB4-DB7 RS R/W E
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Support external clock operation Package form: Au bump chip
Timing Generation Circuit Parallel to Serial Data Conversion Circuit 5 5 Character Generator ROM 8 Character Generator RAM 8 Busy Flag Cursor Blink Control Circuit 80-bit Bi-Direction Shift Register 80 8 I/O Data Register Latch Circuit 80 8 7 Buffer 7 8 Instruction Register 8 Instruction Decorder 7 Display Data RAM 80 Bytes 16-bit 16 Shift Register 7 LCD Driver Address Counter
Figure 3-1: Block Diagram
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CL2 SHL D
80 Segments x 16 Commons
TYPE DIRC COM1COM16
SEG1SEG80
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4. SIGNAL DESCRIPTIONS
Mnemonic VDD VSS VPP V2 V3 E R/W RS PIN No. 19, 20, 28 11, 12, 37 23, 24 22 21 27 26 25 I I I Type I I I I Logic Power input Ground LCD Voltage; VLCD = VPP - VSS LCD Bias Voltage Control. Open for 1/5 Bias, Short for 1/4 Bias It is a start signal to read data or write data. It is a signal to select read or write. 1: Read, 0: Write. It is a signal to select register. 1: Data register (for read and write) 0: Instruction register (for write), DB3 - DB0 DB7 - DB4 SEG80 - SEG1 32 - 29 36 - 33 I/O I/O O O Low-order 4 data bits Description
COM16 - COM9 COM8 - COM1 TYPE
DIRC
SHL
MOD1 MOD0
OSC1 CL2 D
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High-order 4 data bits 46 - 125 45 - 38 1-8 14 Segment signals for LCD. Common signals for LCD. O I Common signals for LCD. LCD Alternate Signals. TYPE = 0: Type-A TYPE = 1: Type-B 15 I Common Scan Direction DIRC = 0: COM1 COM2 Segment Shift Direction ... COM15 COM16 COM2 COM1 DIRC = 1: COM16 COM15 ... 16 I SHL = 0: SEG1 SEG2 ... SEG79 SEG80 SHL = 1: SEG80 SEG79 ... SEG2 SEG1 18 17 I CGROM / CGRAM Mode Select
MOD1 1 1 0 0 MOD0 1 0 1 0 Function $00 - $0F as CGRAM $00 - $07 as CGRAM, $08 - $0F as CGROM $00 - $03 as CGRAM, $04 - $0F as CGROM $00 - $0F as CGROM
Busy flag -- address counter (for read).
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For internal clock operation, leave this pin open.
For external clock operation, the clock is input to OSC1. 10 9 O O Test Mode Clock Output; Open for normally use. Test Mode Data Output; Open for normally use.
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5. FUNCTIONAL DESCRIPTIONS
5.1. Oscillator
The built-in RC oscillator generates suitable clock for SPLC782A operation. S=1 S=1 I/D=1 I/D=0 It shifts the display to the left It shifts the display to the right
5.2. Control and Display Instructions
Control and display instructions is shown as follows:
Figure 5-4: Shift Direction Patterns According to S and I/D Bits
5.2.4. Display ON/OFF control
RS Code 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0
5.2.1. Clear display
RS Code 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 1
Figure 5-5: Display ON/OFF Control Instruction Code
Figure 5-1: Clear Display Instruction Code
D = 1: Display on, D = 0: Display off C = 1: Cursor on, C = 0: Cursor off B = 1: Blinks on, B = 0: Blinks off
It clears the whole display and sets display data RAMs address 0 in address counter.
5.2.2. Return home
RS Code 0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 X
Figure 5-2: Return Home Instruction Code
X: Do not care (0 or 1)
It sets display data RAMs address 0 in address counter and display returns to its original position. The cursor or blink goes to the left edge of the display (to the 1st line if 2 lines are displayed). The content of the Display Data RAM does not change.
5.2.3. Entry mode set
shifts the display.
RS Code 0
During writing and reading data, it sets cursor move direction and
Figure 5-3: Entry Mode Instruction Code
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5 x 8 dot character font 8th line
Cursor
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1
D
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C
B
5 x 10 dot character font
11th line
Blink display alternately
Figure 5-6: Cursor and Blinking
5.2.5. Cursor or display shift
display.
Without changing DD RAMs data, it can move cursor and shift
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 I/D S
RS 0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 S/C R/L X X
Code
Figure 5-7: Cursor or Display Shift Instruction Code
I / D = 1: Increment, I / D = 0: Decrement. S = 1: The display shift, S = 0: The display does not shift.
S/C 0 0 1 1
R/L 0 1 0 1 Shift cursor to the left Shift cursor to the right Shift display to the left. Shift display to the right.
Description
Address Counter AC = AC - 1 AC = AC + 1
Cursor follows the display shift Cursor follows the display shift
AC = AC AC = AC
Figure 5-8: Shift Patterns According to S/C and R/L Bits
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5.2.6. Function set
RS Code 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 DL N F X X
Display data RAM can read or write after this setting. In one-line display (N = 0),
Figure 5-9: Function Set Instruction Code
(aaaaaaa)2: (00)16 - (4F)16. In two-line display (N = 1), (aaaaaaa)2: (00)16 - (27)16 for the first line, (aaaaaaa)2: (40)16 - (67)16 for the second line.
X: Do not care (0 or 1) DL: It sets interface data length. DL = 1: Datas are transferred with 8-bit lengths (DB0 - DB7). DL = 0: Datas are transferred with 4-bit lengths (DB4 - DB7). (It requires two times to transfer data) N: It sets the number of the display line. N = 0: One-line display. N = 1: Two-line display. F: It sets the character font. F = 0: 5 x 8 dots character font.
5.2.9. Read busy flag and address
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Code 0 1
F = 1: 5 x 10 dots character font.
N 0 0 1
F 0 1 X
No. of Display Lines Character Font Duty Factor 1 1 2 5 x 8 dots 1/8
Figure 5-10: Function Set Description
It cannot display two lines with 5 x 10 dot character font.
5.2.7. Set character generator RAM address
RS Code 0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 a a a a a a
Figure 5-11: Set CGRAM address Instruction Code
It sets character generator RAM address (aaaaaa)2 to the address counter. Character generator RAM data can read or write after this setting.
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5 x 10 dots 5 x 8 dots 1 / 11 1 / 16
Figure 5-13: Read busy flag and address Instruction Code
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When (BF = 1) indicates that the system is busy now; it will not accept any instruction until no busy (BF = 0). At the same time, the address counter contents (aaaaaaa)2 is read out.
5.2.10. Write data to character generator RAM or display data RAM
RS 1
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 d d d d d
Code
Figure 5-14: Write Data to CGRAM/DDRAM Instruction Code
It writes data (dddddddd)2 to character generator RAM or display
data RAM.
5.2.11. Read data from character generator RAM or display data RAM
RS 1
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 d d d d d d d d
Code
Figure 5-15: Read Data from CGRAM/DDRAM Instruction Code
5.2.8. Set display data RAM address
RS Code 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 a a a a a a a
It reads data (dddddddd)2 from character generator RAM or display data RAM. To get the correct data readout is shown belows: 1). Set the address of the character generator RAM or display data RAM or shift the cursor instruction. 2). Send the "Read" instruction.
Figure 5-12: Set DDRAM address Instruction Code
It sets display data RAM address (aaaaaaa)2 to the address counter.
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5.3. Instruction Table
Instruction Instruction Code RS 0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 1 Description Write "20H" to DDRAM Clear Display and set DDRAM address to "00H" from AC Set DDRAM address to "00H" Return Home 0 0 0 0 0 0 0 0 1 return from cursor AC to and its 4.1ms Max. Execution time (Temp = -20 ~ +75)
original position if shifted. The contents of DDRAM are not changed. Assign cursor
Entry Mode Set
0
0
0
0
0
0
0
1
I/D
S
direction and enable the shift of entire display Set display
Display ON/ OFF Control
Cursor or Display Shift
Function Set
Set CGRAM Address Set DDRAM Address
Read Busy Flag and Address Counter
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(D), 0 0 0 0 0 0 1 D C B cursor(C), and blinking of cursor(B) on/off control bit. Set cursor moving and display shift control bit, and the direction, without changing data. of 0 0 0 0 0 1 S/C R/L DDRAM Set interface data length (DL: 8-bit/4-bit), numbers display line (N: 0 0 0 0 1 DL N F of 2-line/1-line) and, display font type (F:5x10 dots/5x8 dots) 0 0 0 0 0 1 1 AC5 AC4 AC3 AC2 AC1 AC0 Set CGRAM address in address counter. address counter AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address in Whether during internal operation or not can be The contents of address counter read. can also 0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 known by reading BF. be 1 1 0 1 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Write data into internal RAM (DDRAM/CGRAM). Read data from internal RAM (DDRAM/CGRAM).
Figure 5-16: Instruction Table
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100s
100s
100s 100s
0s
Write Data to RAM Read Data from RAM
Note: "-" don't care
100s 100s
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5.4. 8-Bit Operation and 16-Digit 1-Line Display (Using Internal Reset)
NO. Instruction Display Power on reset. No display. Set to 8-bit operation and select 1-line display line and character font.
0 1 1 0 0 X X
Operation
1 Power on. (SPLC782A starts initializing) 2 Function set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0
3
Display on / off control
0 0 0 0 0 0 1 1 1 0
_
Display on. Cursor appear. Increase address by one.
4
Entry mode set
0 0 0 0 0 0 0 1 1 0
_
It will shift the cursor to the right when writing to the DD RAM/CG RAM. Now the display has no shift. Write " W ".
5
Write data to CG RAM / DD RAM
1 0 0 1 0 1 0 1 1 1
W_
The cursor is incremented by one and shifted to the right. Write " E ".
6
Write data to CG RAM / DD RAM
1 0 0 1 0 0 0 1
7 8
1 0 0
Write data to CG RAM / DD RAM
1 0 0 0 1
9
Entry mode set
0 0 0
0
10 Write data to CG RAM / DD RAM
1 0 0 0 1 0 0 0
11 Write data to CG RAM / DD RAM
1 0 0 1 0 0 0 0
12
1 0 0
13 Write data to CG RAM / DD RAM
1 0 1 1 0
14 Cursor or display shift
0 0 0 0 0
15 Cursor or display shift
0 0 0 0 0
16 Write data to CG RAM / DD RAM
1 0 0 1 0 0 1 1
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0 1
WE_
The cursor is incremented by one and shifted to the right.
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0
1
WELCOME_
Write " E ".
The cursor is incremented by one and shifted to the right. Set mode for display shift when writing
0
0
0
1
1
1
WELCOME_
0
0
ELCOME
_
Write "
"(space).
The cursor is incremented by one and shifted to the right.
1
1
LCOME C_
Write " C ".
The cursor is incremented by one and shifted to the right.
:
:
0
1
COMPAMY
_
Write " Y ".
The cursor is incremented by one and shifted to the right. Only shift the cursor's position to the left (Y).
1
0
0
X
X
COMPAMY _
COMPAMY _
Only shift the cursor's position to the left (M).
1
0
0
X
X
COMPANY _
Write " N ".
1
0
The display moves to the left.
17 Cursor or display shift
0 0 0 0 0 1 1 1 X X
COMPANY _
Shift the display and the cursor's position to the right.
18 Cursor or display shift
0 0 0 0 0 1 0 1 X X
COMPANY_
Shift the display and the cursor's position to the right.
19 Write data to CG RAM / DD RAM
1 0 0 1 0 0 0 0 0 0
COMPANY _
Write "
" (space).
The cursor is incremented by one and shifted to the right. :
20 21 Return home
0 0 0 0 0
:
0 0 0 1 0
WELCOME
Both the display and the cursor return to the original position (address 0).
Figure 5-17: 8-Bit Operation and 16-Digit 1-Line Display
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5.5. 4-Bit Operation and 16-Digit 1-Line Display (Using Internal Reset)
NO. 1 2 Power initializing) Function set
RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 0
Instruction on. (SPLC782A starts
Display Power on reset. No display. Set to 4-bit operation.
Operation
3
Function set
0 0 0 0 0 0 0 0 1 X 0 X
Set to 4-bit operation and select 1-line display line and character font.
4
Display on / off control
0 0 0 0 0 1 0 1 0 1 0 0
Display on.
_
Cursor appears.
5
Entry mode set
0 0 0 0 0 0
6
Write data to CG RAM / DD RAM
1 1 0 0 0 0 1 1 0 1 1 1
5.6. 8-Bit Operation and 16-Digit 2-Line Display (Using Internal Reset)
NO. 1 2 Instruction Display
Power on. (SPLC782A starts initializing) Function set
0 0 0
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 1 1 0 X X
3
Display on / off control
0 0 0 0 0 0
4
Entry mode set
0 0 0 0
5
Write data to CG RAM / DD RAM
1 0 0 1 0 1 0 1
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0 1 0 1 0 0
Increase address by one.
_
It will shift the cursor to the right when writing to the DD RAM/CG RAM. Now the display has no shift. Write " W ".
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The cursor is incremented by one and shifted to the right.
Figure 5-18: 4-Bit Operation and 16-Digit 1-Line Display
Operation
Power on reset. No display.
Set to 8-bit operation and select 2-line display line and 5 x 7 dot character font. Display on.
_
1
1
1
0
Cursor appear.
0
0
0
1
1
0
_
Increase address by one.
It will shift the cursor to the right when writing to the DD RAM/CG RAM. Now the display has no shift. Write " W ".
W_
1
1
The cursor is incremented by one and shifted to the right.
6 7
1 0 0 1 0
: Write data to CG RAM / DD RAM
0 0 1 0 1
:
WELCOME_
Write " E ". The cursor is incremented by one and shifted to the right.
8
Set DD RAM address
0 0 1 1 0 0 0 0 0 0
WELCOME _
It sets DD RAM's address. The cursor is moved to the beginning position of the 2nd line. Write " T ". The cursor is incremented by one and shifted to the right.
9
Write data to CG RAM / DD RAM
1 0 0 1 0 1 0 1 0 0
WELCOME T_
10 11
1 0 0 1 0
: Write data to CG RAM / DD RAM
1 0 1 0 0
:
WELCOME TO PART_
Write " T ". The cursor is incremented by one and shifted to the right.
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NO. 12
1 0 0
Instruction Write data to CG RAM / DD RAM
1 0 1 0 1 0 0
Display
WELCOME TO PART_
Operation Write " T ". The cursor is incremented by one and shifted to the right. When writing, it sets mode for the display shift.
13
Entry mode set
0 0 0 0 0 0 0 1 1 1
WELCOME TO PART_ ELCOME O PARTY_
14
Write data to CG RAM / DD RAM
1 0 0 1 0 1 1 0 0 1
Write " Y ". The cursor is incremented by one and shifted to the right.
15 16 Return home
0 0 0 0 0
:
0 0 0 1 0
:
WELCOME TO PARTY
Both the display and the cursor return to the original position (address 0).
Figure 5-19: 8-Bit Operation and 16-Digit 2-Line Display
5.7. Reset Function
At power on, it starts the internal auto-reset circuit and executes the initial instructions.
Power On
Wait time > 15 ms after Vdd > 4.5V
RS R/W DB7 DB6 DB5 DB4 DB3 DB3 DB1 DB0 00 0 0 11 X X XX
Wait time > 4.1 ms
RS R/W DB7 DB6 DB5 DB4 DB3 DB3 DB1 DB0 00 0 0 11 X X XX
Wait time > 100 us
RS R/W DB7 DB6 DB5 DB4 DB3 DB3 DB1 DB0 00 0 0 11 X X XX
RS R/W DB7 DB6 DB5 DB4 DB3 DB3 DB1 DB0 000 0 11 N F XX 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 I/D
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[ 8-Bit Interface ] Wait time > 40ms After VDD > 2.7V BF cannot be checked before this instruction . Function set ( Interface is 8 bits length . ) BF cannot be checked before this instruction . Function set ( Interface is 8 bits length . ) BF cannot be checked before this instruction . Function set ( Interface is 8 bits length . ) BF can be checked after the following instructions .
0 1 S
There are the initial procedures shown as belows:
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Function set ( Interface is 8 bits length . Specify the number of display lines and character font . ) The number of display lines and character font cannot be changed afterwards . Display off
Display clear Entry mode set
Figure 5-20: Reset Function (8-bit Interface)
Initialization Ends
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[ 4-Bit Interface ] Power On Wait time > 15 ms after Vdd > 4.5V RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 1 Wait time > 4.1 ms RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 1 Wait time > 100 us RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 1 BF cannot be checked before this instruction . Function set ( Interface is 8 bits length . ) Wait time > 40ms After VDD > 2.7V BF cannot be checked before this instruction . Function set ( Interface is 8 bits length . )
BF cannot be checked before this instruction . Function set ( Interface is 8 bits length . ) BF can be checked after the following instructions .
RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 N 0 0 0 F 0 X 0 X
Initialization Ends
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Function set ( Set interface to be 4 bits length) Interface is 8 bits length . Function set ( Interface is 4 bits length . Specify the number of the display lines and character font . ) 1 0 0 0 0 0 0 0 1 0 0 0 Display off 0 1 I/D S Display clear Entry mode set
Figure 5-21: Reset Function (4-bit Interface)
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The number of display lines and character font cannot be changed afterwards .
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5.8. Display Data RAM (DD RAM)
The DD RAM stores display data and its RAM size is 80 bytes. The area in DD RAM that is not used for display can be used as a general data RAM. Its address is set in the address counter. There are the relations between the display data RAMs address and the LCDs position shown belows.
1-line display , 80 display characters 1 2 3 4 5 6 00 01 02 03 04 05
79 4E
80 4F
Display position Display data RAM address
( Example ) 1-line display , 8 display characters 1 2 3 4 5 6 7 8 00 01 02 03 04 05 06 07
Display position Display data RAM address
When the display shift operation is performed , the display data RAM's address moves as : ( i ) Left shift 01 ( ii ) Right shift 4F 00
5.9. Timing Generation Circuit
to the internal circuits. generated.
The timing generation circuit can generate needed timing signals
the MPU access timing and the RAM access timing are separately
5.10. LCD Driver Circuit
There are 16 commons x 80 segments signal drivers in the LCD
driver circuit. When a program specifies the character fonts and
line numbers, the corresponding common signals will output drive waveforms and the others still output unselected waveforms.
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02 03 04 05 06 06 07 08 01 02 03 04
Figure 5-22: Relations Between Display Data Ram's Address and the LCD's Position
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It also can
06
5.11. Character Generator ROM (CG ROM)
Using 8-bit character code, the character generator ROM generates 5 x 8 dot or 5 x 10 dot character patterns. character patterns. generate 192 5 x 8 dot character patterns and 64 5 x 10 dot
To prevent the internal timing interface,
5.12. Character Generator RAM (CG RAM)
Using the programs, users can easily change the character patterns in the character generator RAM. character patterns. It can be written with 5 x 8 dots, 8 character patterns or written with 5 x 10 dots, 4
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Here are the SPLC782As character patterns shown as belows: Correspondence between Character Codes and Character Patterns.
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Figure 5-23: Character Code and Character Patterns
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The relations between character generator RAM addresses, character generator RAM data (character patterns) and character codes are shown as belows:
5.12.1. 5 x 8 dot character patterns
Character Code ( DD RAM Data ) b7 b6 b5 b4 b3 b2 b1 b0
CG RAM Address b5 b4 b3 b2 b1 b0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X
Character Patterns ( CG RAM Data ) b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 X X 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0
0
0
X
0
0
0
0
0
0
0
0
0
Note1: Note2:
It means that the bit0~2 of the character code correspond to the bit3~5 of the CG RAM address. These areas are not used for display, but can be used for the general data RAM.
Note3: When all of the bit4-7 of the character code are 0, CG RAM character patterns are selected. Note4: " 1 ": Selected, " 0 " : No selected , " X " : Do not care (0 or 1). display " T " character. with the cursor.
Note5: For example (1), set character code (b2 = b1 = b0 = 0, b3 = 0 or 1, b7-b4 = 0) to display " T ". Note6: The bits 0-2 of the character code RAM is the character pattern line position.
nU o C ER sN lu I pM nT uR SA P r o F
0 X 0 0 1 0 0 1 X X X
Figure 5-24: 5 x 8 Dot Character Patterns
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Character Pattern Example (1)
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Cursor Position
Character Pattern Example (2)
That means character code (00) 16,and (08) 16 can
The 8th line is the cursor position and display is formed by logical OR
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5.12.2. 5 X 10 dot character patterns
Character Code ( DD RAM Data ) b7 b6 b5 b4 b3 b2 b1 b0
CG RAM Address b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X
Character Patterns ( CG RAM Data ) b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 1 1 X X 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 0 Character Pattern Example (1)
0
0
0
0
X
0
0
X
0
0
0 0 0 1 1 1 1 1 1 1 1
Note1: Note2:
It means that the bit1~2 of the character code correspond to the bit4~5 of the CG RAM address.
These areas are not used for display, but can be used for the general data RAM.
Note3: When all of the bit4-7 of the character code are 0, CG RAM character patterns are selected. Note4: " 1 ": Selected, " 0 ": No selected, " X ": Do not care (0 or 1). (08) 16,and (09) 16 can display " U " character. with the cursor.
Note5: For example (1), set character code (b2 = b1 = 0, b3 = b0 = 0 or 1, b7-b4 = 0) to display " U ". That means all of the character codes (00) 16, (01) 16, Note6: The bits 0-3 of the character code RAM is the character pattern line position. The 11th line is the cursor position and display is formed by logical OR
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X X X X X X X X
Figure 5-25: 5 x 10 Dot Character Patterns
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Cursor Position
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5.13. Cursor/Blink Control Circuit
It can generate the cursor or blink in the cursor / blink control circuit. address set in the address counter. When the address counter is (07) 16, the cursor's position is shown as follows: The cursor or the blink appears in the digit at the display data RAM
b6 AC 0
b5 0
b4 0
b3 0
b2 1
b1 1
b0 1
In a 1-line display digit 1 00 In a 2-line display digit 1st line 2nd line 1 2 3 4 5 6 2 01 3 02 4 03 5 04 6 05 7 06 8 07 9 08 10 09 Display position
Display data RAM address ( Hexadecimal )
the cursor position 7 8 9 10
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Display position 00 40 01 41 02 42 03 43 04 44 05 45 06 46 07 47 08 48 09 49 the cursor position
Figure 5-26: Cursor/Blink Control
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Display data RAM address ( Hexadecimal )
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5.14. Interfacing to MPU
There are two types of data operations: 4-bit operation and 8-bit operation. Using 4-bit MPU, the interfacing 4-bit data is The Using 4-bit MPU to transferred by 4 bus lines (for 8-bit operation, DB7 to DB4). bus lines of DB0 - DB3 are not used. interface 8-bit data needs two times. transferred by 4-busline (for 8-bit operation, DB7 to DB4). Secondly, the lower 4-bit data is transferred by 4 bus lines (for 8-bit operation, DB3 to DB0). Using 8-bit MPU, the interfacing 8-bit data is transferred by 8 bus lines (DB0 - DB7).
First, the higher 4-bit data is
RS
R/W
E
Internal operation
DB7
DB6
DB5
DB4
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Functioning IR7 IR3 Busy AC3 Not busy AC3 D7 IR6 IR2 AC6 AC2 AC6 AC2 D6 IR5 IR1 AC5 AC1 AC5 AC1 D5 IR4 IR0 AC4 AC0 AC4 AC0 D4 Instruction Write Busy flag check Busy flag check
Figure 5-27: Example of 4-bit Data Transfer Timing Sequence
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D1
D0
Data Write
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RS
R/W
E
Internal operation
Functioning
DB7
IR7
Busy
Busy
Not Busy
DB6
IR6
AC6
AC6
DB5
IR5
AC5
AC5
DB4
IR4
AC4
AC4
DB3
DB2
DB1
DB0
nU o C ER sN lu I pM nT uR SA P r o F
IR3 AC3 AC3 AC3 IR2 AC2 AC2 AC2 IR1 AC1 AC1 AC1 IR0 AC0 AC0 AC0 Instruction Write Busy flag check Busy flag check Busy flag check
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AC6
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D6
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Data Write
Figure 5-28: Example of 8-bit Data Transfer Timing Sequence
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5.15. Supply Voltage for LCD Drive
LCD bias can be selected by open/short V2 and V3 pins. Duty Factor Supply Voltage V2, V3 1/8, 1/11 1/4 Short 1/16 1/5 Open
1/4 Bias (1/8, 1/11 Duty) 1/5 Bias (1/16 Duty) SPLC782A V2 V3 SPLC782A
short
V2 V3
open
Figure 5-29: Supply Voltage for LCD Drive
5.15.1. The relations between LCD frames frequency and oscillators frequency
(Assume the oscillation frequency is 250KHz, 1 clock cycle time = 4.0s)
5.15.2. 1/8 Duty, type-A waveform
COM1
1 frame = 4 (s) x 400 x 8 = 12800 (s) = 12.8 ms 1 Frame frequency = = 78.1 (Hz) 12.8 (ms)
5.15.3. 1/11 Duty, type-A waveform
COM1
1 frame = 4 (s) x 400 x 11 = 17600 (s) = 17.6 ms 1 Frame frequency = = 56.8 (Hz) 17.6 (ms)
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400 clocks
1 VPP 2 3 4 8 1 2 V1 V2(V3) V4 VSS 1 frame
Figure 5-30: 1/8 Duty type-A waveform
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400 clocks
1
VPP
2
3
4
11
1
2
V1
V2(V3) V4
VSS
1 frame
Figure 5-31: 1/11 Duty type-A waveform
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5.15.4. 1/16 Duty, type-A waveform
200 clocks
VPP COM1 V1 V2 V3 V4 VSS 1 frame 1 frame = 4 (s) x 200 x 16 = 12800 (s) = 12.8 ms 1 = 78.1 (Hz) Frame frequency = 12.8 (ms)
Figure 5-32: 1/16 Duty type-A waveform
1
2
3
4
16
1
2
5.15.5. 1/8 Duty, type-B waveform
VPP V1 COM1 V2(V3) V4 VSS
5.15.6. 1/11 Duty, type-B waveform
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400 clocks 12 7812 7812 7812 78 1 Frame 1 Frame 1 frame = 4(s) x 400 x 8 = 12800(s) = 12.8ms 1 Framefrequ ency 78.1(Hz) 12.8(ms)
Figure 5-33: 1/8 Duty type-B waveform
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400 clocks
12
10 11 1 2
10 11 1 2
VPP V1 COM1 V2(V3) V4 VSS
1 Frame 1 frame = 4(s) x 400 x 11 = 17600(s) = 17.6ms Framefrequency 1 17.6(ms) 56.8(Hz)
1 Frame
Figure 5-34: 1/11 Duty type-B waveform
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5.15.7. 1/16 Duty, type-B waveform
200 clocks 12 VPP V1 COM1 V2 V3 V4 VSS 1 Frame 1 frame = 4(s) x 200 x 16 = 12800(s) = 12.8ms 1 Framefrequ ency 78.1(Hz) 12.8(ms)
Figure 5-35: 1/16 Duty type-B waveform
15 16 1 2
15 16 1 2
1 Frame
5.16. Register --- IR (Instruction Register) and DR (Data Register)
SPLC782A has two 8-bit registers - IR (instruction register) and DR (data register). DR. In the followings, we can use the combinations of the RS pin and the R/W pin to select the IR and
RS 0 0 1 1
R/W 0 1 0 1
IR write (Display clear, etc.) (DB0 - DB6)
Read busy flag (DB7) and address counter
DR write (DR to Display data RAM or Character generator RAM)
DR read (Display data RAM or Character generator RAM to DR)
5.17. Busy Flag (BF)
When RS = 0 and R/W = 1, the busy flag is output to DB7. any instructions until the busy flag = 0.
the busy flag = 1, SPLC782A is in busy state and does not accept
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5.19. Segment Data Direction 5.20. Common Data Direction
Operation VDD.
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SHL is the segment data shift direction control pin. LCD data is shifted from SEG1 to SEG80 by connecting SHL to VSS, and is reversed by connecting SHL to VDD.
DIRC is the common data shift direction control pin.
LCD common scan sequence from COM1 to COM16 by
connecting DIRC to VSS, and is reversed by connecting DIRC to
5.21. I/O Port Configuration 5.21.1. Input port: E
VDD
PMOS
As
NMOS
Figure 5-36: Input port: E Configuration
5.18. Address Counter (AC)
The address counter assigns addresses to display data RAM and character generator RAM. When an instruction for address is After
PMOS PMOS
5.21.2. Input port: R/W, RS
VDD VDD
written in IR, the address information is sent from IR to AC.
writing into (or reading from)display data RAM or character generator RAM, AC is automatically incremented by +1 (or decremented by -1). RS = 0 and R/W = 1. AC contents are output to DB0 - DB6 when
NMOS
Figure 5-37: Input port: RW, RS Configuration
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5.21.3. Output port: CL2, D
VDD
PMOS
NMOS
Figure 5-38: Output port: CL2, D Configuration
5.21.4. Input / Output port: DB0 - DB7
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PMOS PMOS NMOS
Figure 5-39: Input/Output port: DB0-DB7 Configuration
VDD
VDD
VDD
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6. ELECTRICAL SPECIFICATIONS
6.1. Absolute Maximum Ratings
Characteristics Operating Voltage Driver Supply Voltage Input Voltage Range Operating Temperature Storage Temperature
conditions see AC/DC Electrical Characteristics.
Symbol VDD VPP VIN TA TSTO
Ratings -0.3V to +7.0V -0.3V to +7.0V -0.3V to VDD +0.3V -20 to +75 -55 to +125
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device.
6.2. DC Characteristics (VDD = 2.4V to 4.5V, TA = -20 to +75)
Characteristics Operating Voltage Symbol VDD IDD1 IDD2 Limit Min. 2.4 Typ. Max. 4.5
Unit V
Operating Current
Input High Voltage Input Low Voltage
Input High Current Input Low Current
Output High Voltage Output Low Voltage Voltage Drop
Operating Current LCD Voltage
Note1: Typ. condition VDD = 3.0V @ 25, Max. condition VDD = 4.5V @ -20 Note2: Typ. condition VPP = 6.0V @ 25, Max. condition VPP = 6.0V @ -20
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0.15 0.18 0.25 0.48 mA mA V VIH1 VIL1 IIH IIL 0.7VDD -0.3 VDD 0.55 2.0 V A A V -5.0 -30 -100 VOH1 VOL1 0.75VDD VDD 0.2VDD 1.0 1.0 V VDCOM VDSEG IPP V V 0.35 0.45 6.0 mA V VPP 4.0
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For normal operational
Test Condition
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No access from MPU (Note1)
Access operation from MPU (FCYC = 500KHz)(Note1) Pins:(E, RS, R/W, DB0 - DB7)
Pins: (RS, R/W, DB0 - DB7)
IOH = - 0.1mA, Pins: DB0 - DB7 IOL = 0.1mA, Pins: DB0 - DB7
IO = 0.1mA, Pins: COM1 - COM16 IO = 0.1mA, Pins: SEG1 - SEG80
VPP = 6.0V (Note2) 1/4 bias or 1/5 bias
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6.3. DC Characteristics (VDD = 4.5V to 5.5V, TA = -20 to +75)
Characteristics Operating Voltage Operating Current Symbol VDD IDD1 IDD2 VIH1 VIL1 IIH IIL VOH1 VOL1 VDCOM VDSEG IPP VPP Limit Min. 4.5 0.7VDD -0.3 -30 2.4 Typ. 0.25 0.45 -80 Max. 5.5 0.35 0.7 VDD 0.6 2.0 -150 VDD 0.4 1.0 1.0 Unit V mA mA V V A A V V V V No access from MPU (Note1) Access operation from MPU (FCYC = 500KHz)(Note1) Pins:(E, RS, R/W, DB0 - DB7) Pins: (RS, R/W, DB0 - DB7) Test Condition
Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage (TTL) Output Low Voltage (TTL) Voltage Drop
Operating Current LCD Voltage
Note1: Typ. condition VDD = 5.0V @ 25, Max. condition VDD = 5.5V @ -20 Note2: Typ. condition VPP = 6.0V @ 25, Max. condition VPP = 6.0V @ -20
6.4. AC Characteristics (VDD = 4.5V to 5.5V, TA = -20 to +75)
6.4.1. Internal clock operation (TA = 25, the oscillator frequency chart can be reference on Figure 6-3)
Characteristics OSC Frequency Symbol FOSC1 Limit Typ. 270 Unit KHz
6.4.2. LCD bias resistor (TA = 25)
Characteristics Bias Resistor
6.4.3. Write mode (Writing data from MPU to SPLC782A)
Characteristics E Cycle Time E Pulse Width E Rise/Fall Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Symbol tC
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0.35 0.45 6.0 mA V 4.0 Min. 190 Max. 350 Symbol R1 - R5 Limit Typ. 5.0 Min. 3.0 Max. 7.0 Limit Min. 500 230 40 10 80 10 Typ. Max. 20 Unit ns ns ns ns ns ns ns tPW t R, t F tSP1 tHD1 tSP2 tHD2
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IOH = - 0.1mA, Pins: DB0 - DB7
IOL = 0.1mA, Pins: DB0 - DB7
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IO = 0.1mA, Pins: COM1 - COM16 IO = 0.1mA, Pins: SEG1 - SEG80 1/4 bias or 1/5 bias
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VPP = 6.0V (Note2)
Unit K-ohm
Test Condition
Pin E Pin E
Pin E Pins: RS, R/W, E Pins: RS, R/W, E Pins: DB0 - DB7 Pins: DB0 - DB7
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6.4.4. Read mode (Reading Data from SPLC782A to MPU)
Characteristics E Cycle Time E Pulse Width E Rise/Fall Time Address Setup Time Address Hold Time Data Output Delay Time Data hold time Symbol tC tW t R, t F tSP1 tHD1 tD tHD2 Limit Min. 500 230 40 10 5.0 Typ. Max. 20 160 Unit ns ns ns ns ns ns ns Test Condition Pin E Pin E Pin E Pins: RS, R/W, E Pins: RS, R/W, E
6.5. AC Characteristics (VDD = 2.4V to 4.5V, TA = -20 to +75)
6.5.1. Internal clock operation (TA = 25, the oscillator frequency chart can be reference on Figure 6-3)
Characteristics OSC Frequency
6.5.2. LCD bias resistor (TA = 25)
Characteristics Bias Resistor
6.5.3. Write mode (Writing data from MPU to SPLC782A)
Characteristics E Cycle Time Symbol tC
E Pulse Width
E Rise/Fall Time
Address Setup Time Address Hold Time Data Setup Time Data Hold Time
6.5.4. Read mode (Reading data from SPLC782A to MPU)
Characteristics E Cycle Time E Pulse Width E Rise/Fall Time Address Setup Time Address Hold Time Data Output Delay Time Data hold time Symbol tC tW t R, t F tSP1 tHD1 tD tHD2
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Symbol FOSC1 Limit Typ. 270 Min. 190 Max. 350 Symbol R1 - R5 Limit Typ. 5.0 Min. 3.0 Max. 7.0 Limit Min. Typ. Max. Unit ns 1250 600 tPW ns t R, t F tSP1 25 ns ns ns 60 20 tHD1 tSP2 195 10 ns tHD2 ns Limit Typ. Min. 1250 600 60 20 5.0 Max. 25 360 Unit ns ns ns ns ns ns ns
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Pins: DB0 - DB7 Pins: DB0 - DB7
O
Unit KHz Unit
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K-ohm
Test Condition
Pin E Pin E
Pin E Pins: RS, R/W, E Pins: RS, R/W, E Pins: DB0 - DB7
Pins: DB0 - DB7
Test Condition Pin E Pin E Pin E Pins: RS, R/W, E Pins: RS, R/W, E Pins: DB0 - DB7 Pin DB0 - DB7
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6.6. Write Mode Timing Diagram (Writing Data from MPU to SPLC782A)
VIH1 VIL1 tSP1 VIL1 tPW E tR DB0 - DB7 VIH1 VIL1 VIH1 VIL1 VIH1 VIL1 tSP2 tF tHD1 VIH1 VIL1 tHD1 VIL1
RS
R/W
tHD2
Valid Data tC
VIH1 VIL1
Figure 6-1: Write Mode Timing Diagram
6.7. Read Mode Timing Diagram (Reading Data from SPLC782A to MPU)
VIH1 VIL1 tSP1 VIH1 VIL1
6.8. The Following Graps Show the Relationship Between FOSC and Temperature
SPLC782A Fosc Frequency (VDD = 2.4V ~ 5.5V)
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RS tHD1 R/W VIH1 VIH1 tPW E VIH1 VIL1 VIH1 VIL1 tF tHD1 VIL1 tR DB0 - DB7 tD VIH1 VIL1 tHD2 Valid Data tC VIH1 VIL1
Figure 6-2: Read Mode Timing Diagram
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550 500 450 400 350 300 250 200 150 100
Min. Typ. Max.
KHz
-20
-10
0
10
20
30 Temp
40
50
60
70
80
FOSC (Max.) = 515KHz @ VDD = 5.5V, Temp = -20 FOSC (Min.) = 114KHz @ VDD = 2.4V, Temp = 80 Figure 6-3: The Relationship Between Fosc and Temperature
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7. APPLICATION CIRCUITS
7.1. Interface to MPU 7.1.1. Interface to 8-bit MPU (6805)
PA0 | PA7 6805 PB0 PB1 PB2
8
DB0 | DB7
COM1 | COM16 SEG1 | SEG80
16
LCD PANEL 16 COMMONS X
SPLC782A E RS R/W 80
80 SEGMENTS
7.1.2. Interface to 8-bit MPU (Z80)
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Figure 7-1: Interface to 8-bit MPU (6805)
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D0 | D7
8
DB0 | DB7 E
Z80
COM1 | COM16
16
LCD PANEL
A1 | A7
7
SPLC782A
16 COMMONS X
A0
RS
IORQ WR
R/W
SEG1 | SEG80
80
80 SEGMENTS
Figure 7-2: Interface to 8-bit MPU (Z80)
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7.2. Applications for LCD 7.2.1. Chip bottom & lower view (DIRC = "0", SHL = "0")
LCD Panel 16 characters x 1 line
COM8 COM1
SPLC782A BOTTOM VIEW
DIRC SHL V2 V3
( Example 1 ) : 5 x 8 dots , 16 characters x 1 line [ 1 / 4 Bias , 1 / 8 Duty ]
Figure 7-3: Chip Bottom & Lower View (Example 1)
( Example 2 ) : 5 x 10 dots , 16 characters x 1 line [ 1 / 4 Bias , 1 / 11 Duty ]
Figure 7-4: Chip Bottom & Lower View (Example 2)]
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LCD Panel SEG80 SEG1 COM8 COM1
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SEG1
DIRC
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16 characters x 1 line
SPLC782A BOTTOM VIEW
SHL V2
COM11 COM9
V3
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LCD Panel 16 characters x 2 line
COM8 COM1
SPLC782A BOTTOM VIEW
DIRC SHL V2 V3
COM16 COM9
7.2.2. Chip bottom & upper view (DIRC = "1", SHL = "1")
LCD Panel
16 characters x 1 line
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( Example 3 ) : 5 x 8 dots , 16 characters x 2 lines [ 1 / 5 Bias , 1 / 16 Duty ]
Figure 7-5: Chip Bottom & Lower View (Example 3)
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SEG80
( Example 4 ) : 5 x 8 dots , 16 characters x 1 line [ 1 / 4 Bias , 1 / 8 Duty ]
Figure 7-6: Chip Bottom & Upper View (Example 4)
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SEG1
SEG1
VDD
SEG80
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V3
V2
SHL
DIRC
COM1 COM8
SPLC782A BOTTOM VIEW
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SPLC782A
VDD VDD COM1 COM8 SEG1
COM9 COM11 SEG80
V3
V2
SHL
DIRC
SPLC782A BOTTOM VIEW
LCD Panel 16 characters x 1 line
16 characters x 2 line
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( Example 5 ) : 5 x 10 dots , 16 characters x 1 line [ 1 / 4 Bias , 1 / 11 Duty ]
Figure 7-7: Chip Bottom & Upper View (Example 5)
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COM9
V3
V2
SHL
DIRC
COM1 COM8 SEG1
COM16
LCD Panel
( Example 6 ) : 5 x 8 dots , 16 characters x 2 lines [ 1 / 5 Bias , 1 / 16 Duty ]
Figure 7-8: Chip Bottom & Upper View (Example 6)
(c) Sunplus Technology Co., Ltd. Proprietary & Confidential
SEG80
SPLC782A BOTTOM VIEW
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7.2.3. Chip top & lower view (DIRC = "0", SHL = "1")
LCD Panel 16 characters x 1 line
LCD Panel 16 characters x 1 line
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VDD ( Example 7 ) : 5 x 8 dots , 16 characters x 1 line [ 1 / 4 Bias , 1 / 8 Duty ]
Figure 7-9: Chip Top & Lower View (Example 7)
SEG80 V3
SEG80 COM11 COM9 V3 V2
SPLC782A TOP VIEW
V2 SHL
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SEG1
SPLC782A TOP VIEW
SHL
COM8 COM1
DIRC
VDD
( Example 8 ) : 5 x 10 dots , 16 characters x 1 line [ 1 / 4 Bias , 1 / 11 Duty ]
Figure 7-10: Chip Top & Lower View (Example 8)
(c) Sunplus Technology Co., Ltd. Proprietary & Confidential
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LCD Panel 16 characters x 2 line
COM16 COM9 V3
SPLC782A TOP VIEW
V2
VDD
7.2.4. Chip top & upper view (DIRC = "1", SHL = "0")
VDD
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Figure 7-11: Chip Top & Lower View (Example 9)
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( Example 9 ) : 5 x 8 dots , 16 characters x 2 lines [ 1 / 5 Bias , 1 / 16 Duty ]
COM1 COM8
DIRC
SEG80
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V2
V3
SPLC782A TOP VIEW
SEG80
(c) Sunplus Technology Co., Ltd. Proprietary & Confidential
SEG1
LCD Panel
16 characters x 1 line
( Example 10 ) : 5 x 8 dots , 16 characters x 1 line [ 1 / 4 Bias , 1 / 8 Duty ]
Figure 7-12: Chip Top & Upper View (Example 10)
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VDD COM1 COM8 SEG1
COM1 COM8 SEG1 DIRC
(c) Sunplus Technology Co., Ltd. Proprietary & Confidential
DIRC
SHL
V2
V3
COM9 COM11 SEG80
SPLC782A TOP VIEW
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( Example 11 ) : 5 x 10 dots , 16 characters x 1 line [ 1 / 4 Bias , 1 / 11 Duty ]
Figure 7-13: Chip Top & Upper View (Example 11)
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16 characters x 1 line
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SHL
V2
V3
COM9
SPLC782A TOP VIEW
COM16
( Example 12 ) : 5 x 8 dots , 16 characters x 2 lines [ 1 / 5 Bias , 1 / 16 Duty ]
Figure 7-14: Chip Top & Upper View (Example 12)
SEG80
LCD Panel
16 characters x 2 line
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FEB. 15, 2005 Version: 1.7
SPLC782A
8. CHARACTER GENERATOR ROM
8.1. SPLC782A - 016
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Figure 8-1: CGROM (SPLC782A-016)
(c) Sunplus Technology Co., Ltd. Proprietary & Confidential
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8.2. SPLC782A - 022
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Figure 8-2: CGROM (SPLC782A-022)
(c) Sunplus Technology Co., Ltd. Proprietary & Confidential
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SPLC782A
9. PACKAGE/PAD LOCATIONS
9.1. PAD Assignment and Locations
Please contact Sunplus sales representatives for more information.
9.2. Ordering Information
Product Number SPLC782A-NnnnV-C
Note1: Code number is assigned for customer. Note2: Code number (N = A - Z or 0 - 9, nnn = 000 - 999); version (V = A - Z).
Package Type Chip form with gold bump
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10. DISCLAIMER
The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or FURTHER, SUNPLUS MAKES NO WARRANTY OF SUNPLUS reserves the right to halt production or alter the specifications and regarding the freedom of the described chip(s) from patent infringement. MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. prices at any time without notice. publication are current before placing orders.
Accordingly, the reader is cautioned to verify that the data sheets and other information in this Products described herein are intended for use in normal commercial applications.
Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. Please note that application circuits illustrated in this document are for reference purposes only.
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SPLC782A
11. REVISION HISTORY
Date FEB. 15, 2005 Revision # 1.7 Description 1. Modify from TYPE to DIRC in section 5.20 Common data Direction 2. Add description(TA=25) in section 6.5.1 and 6.5.2 3. Correct the description of Figure 5-4 4. Correct the code of 5.2.9 Read busy flag and address 5. Modify the execution time of 5.3 Instruction table 6. Remove the note of Figure 5-16 7. Correct the display of 14~21 of Figure 5-17 8. Insert the display of 10 of Figure 5-19 9. Modify the Driver Supply voltage of 6.1 absolute maximum ratings Characteristics Page 22 26 6 7 8
10. Modify the operation current of IDD1 and IDD2 of 6.2 DC Characteristics and 6.3 DC
DEC. 24, 2004
APR. 23, 2004
APR. 01, 2004
JUN. 20, 2003
MAY. 09, 2002
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12. Add the description of max. and min. of Fosc of Figure 6-3 1. Add figure number for all figure 1.6 2. Modify 6.2 IIL max. Value to -100uA 3. Modify 6.3 IIL max. Value to -150uA 4. Modify 6.3 VIH1 min. Value to 0.7VDD 5. Modify TA of all DC/AC Characteristics to TA=-20 to +75 6. Modify 6.5.3 and 6.5.4 E Cycle time to 1250ns 7. Modify 6.5.3 and 6.5.4 E Pulse Width to 600ns 1.5 1. Modify description: "Execution time" to "Execution time (Temp = 25)" 2. Modify Note2: from 2.3ms to 4.1ms 1.4 1. Add min. and max. value in Instruction Table 2. Add 8-bit/4-bit data transfer timing sequence example 4. Add Note2 in Instruction Table 1.3 1. Add "8.3 SPLC782A - 22" 2. Remove "9. PACKAGE/PAD LOCATIONS" 1.2 1. Correct PIN No. error V2 pin: 21 to 22 V3 pin: 22 to 21 R/W pin: 25 to 26 RS pin: 26 to 25 MOD1 pin: 17 to 18 MOD0 pin: 18 to 17 2. Correct ROM size: 160 5*8 dot -> 192 5*8 dot character patterns 32 5*10 dot -> 64 5*10 dot character patterns 1.1 2. Modify pins "CL2" and "D" description: "normal mode" to "normally use" in the "4. SIGNAL DESCRIPTIONS" 3. Modify pin OSC1 description in the "4. SIGNAL DESCRIPTIONS" 4. Modify DC Characteristics in the "6. ELECTRICAL SPECIFICATIONS"
11. Add the operation current of Ipp of of 6.2 DC Characteristics and 6.3 DC Characteristics
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3. Add "6.8 The Following Graps Show the Relationship Between FOSC and Temperature"
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NOV. 26, 2001
1. Modify "MODE1" to "MOD1", "MODE2" to "MOD0" in the "4. SIGNAL DESCRIPTIONS"
5 5 5 21
(c) Sunplus Technology Co., Ltd. Proprietary & Confidential
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SPLC782A
Date JUL. 27, 2001 Revision # 1.0 1. Delete "PRELIMINARY" 2. Add "with gold bump" in the "9.3 Ordering Information" 3. Renew to a new document format MAY. 04, 2001 0.1 Original 33 Description Page
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