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TFBS5607
Vishay Semiconductors
Integrated Low Profile Transceiver Module for Telekom Applications 9.6 kbit/s to 1.152 Mbit/s Data Transmission Rate
Description
The miniaturized TFBS5607 is an ideal transceiver for applications in telecommunications like mobile phones, pagers, and PDAs of all kinds. The devices are both designed for optimum performance and minimum package size. These devices cover the latest IrDA(R) physical layer for Low Power SIR and MIR 1.152 Mbit/s IrDA(R) mode. The transceivers is in a very low profile package, allowing to replace and upgrade a variety of common SIR devices to MIR functionality with the additional feature of variable logic voltage swing. The TFBS5607 is using the Vishay Semiconductors, IBM(R) and Infineon(R) order of the pinning. The new features The devices are modifications of the TFDU5107 devices. An additional new feature as in TFDU5107 is the adjustable logic voltage Vddlogic swing. It can be set externally between 1.5 V and 5.5 V. The device covers the supply voltage range from 5.5 V down to 2.7 V and with its low current consumption it is optimum suited for battery powered applications. Double eye safety protection by pulse duration and current limitation is integrated. The device is defined to operate over an extended low power IrDA range close to 1 m. A custom modification of current control for MIR low power standard is available on request.
Features
D Package: TFBS5607 Vishay Legacy Pinning Order D Compatible to IrDA Low Power Standard (MIR and SIR with Lowest Current Consumption) D Wide Supply Voltage Range (2.7 V to 5.5 V) D Logic Input and Output Voltage 1.5 V to 5.5 V D Tri - State - Receiver Output with weak pull-up efficient in shut down mode D Lowest Power Consumption, typically 500 A (900 A max.) in Receive Mode, <1 A in Shutdown Mode D Fewest External Components D Vishay's well known High EMI Immunity D Eye Safety Protection Integrated
Applications
D Mobile Phones, Pagers, Hand-held Battery Operated Equipment D Computers (WinCE, PalmPC, PDAs) D Digital Still and Video Cameras D Extended IR Adapters D Medical and Industrial Data Collection
Document Number 82553 Rev. A1.3, 17-Jul-02
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TFBS5607
Vishay Semiconductors Packages
TFBS5607
Ordering Information
Part Number TFBS5607-TR3 Qty / Reel 2500 pcs Description
Functional Block Diagram
Vdd1 Vlogic
Driver Amplifier Comparator Rxd
SD Txd Mode
AGC Logic Current controlled driver
IRED Anode
IRED Cathode
GND Figure 1. Functional Block Diagram (mode input is for internal current selection of customized version for low power or full IrDA range)
Definitions:
In the Vishay transceiver data sheets the following nomenclature is used for defining the IrDA operating modes: SIR: 2.4 kbit/s to 115.2 kbit/s, equivalent to the basic serial infrared standard with the physical layer version IrPhy 1.0 MIR 576 kbit/s to 1152 kbit/s FIR 4 Mbit/s VFIR 16 Mbit/s MIR and FIR were implemented with IrPhy 1.1, followed by IrPhy 1.2, adding the SIR Low Power Standard. IrPhy 1.3 extended the Low Power Option to MIR and FIR and VFIR was added with IrPhy 1.4. A new version of the standard in any obsoletes the former version.
Document Number 82553 Rev. A1.3, 17-Jul-02
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TFBS5607
Vishay Semiconductors Pin Description
Pin TFBS560 7 1 IRED Anode IRED Anode to be externally connected to VCC through a current control resistor. This pin is allowed to be supplied from an uncontrolled power supply separated from the controlled VCC supply. IRED Cathode, internally connected to driver transistor Transmit Data Input Received Data Output, push-pull CMOS driver output capable of driving a standard CMOS or TTL load. No external pull-up or pull-down resistor is required. Pin is connected to Vlogic with a weak pull-up (500 k) when device is in shutdown mode. Rxd output is quiet during transmission. Shutdown, will switch the device into shutdown after a delay of 1 ms Supply Voltage Defines the input and output logic swing voltage Ground I I O HIGH LOW Function Description I/O Active
2 3 4
IRED Cathode Txd Rxd
5 6 7 8
SD Vdd Vlogic GND
I
HIGH
TFBS5607
1
Pin order: IREDA IRED C Txd Rxd SD Vdd Vlogic GND
Figure 2. Pinning
Document Number 82553 Rev. A1.3, 17-Jul-02
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TFBS5607
Vishay Semiconductors Absolute Maximum Ratings
Reference Point Ground, Pin 8, unless otherwise noted Parameters Supply Voltage Range y g g Test Conditions 0 V < Vdd2 < 6 V 0 V < Vdd1 < 6 V 0 V < Vdd1 < 6 V 0 V < Vdd2 < 6 V all pins (IRED Anode excluded) Rxd IRED Anode, ton< 20%, < 20 s Symbol Vdd1 Vdd2 Vlogic Min. -0.5 -0.5 -0.5 Typ. Max. 6 6 6 10 25 500 125 450 125 85 85 240 6 Vlogic+0.5 2.8 500*) save in all modes Unit V V V mA mA mA mA mW C C C C V V mm mW/sr
Input Current Output Sink Current, Rxd Rep. Pulsed IRED Current
IIRED(RP) IIRED(DC) Ptot TJ Tamb Tstg VTxd, VSD VRxd d Ie
Average IRED Current Power Dissipation Junction Temperature Ambient Temperature Range (Operating) Storage Temperature Range Soldering Temperature t = 20 s @215C Transmitter Data and 2.7 V < Vdd1 < 5.5 V Shutdown Input Voltage Receiver Data Output Voltage Virtual source size Method: (1-1/e) encircled energy Max. Intensity for Class 1 EN60825, 1.1.2001 operation of IEC 60825 or Worst case IrDA pulse EN60825 pattern, lab. conditions. *)
-25 -25 215 -0.5 -0.5 2.5
The Jan. 2001 edition of the IEC825-1 or EN60825-1 gives no limitation below the IrDA standard maximum. IrDA max. limit is 500 mW/sr. The device is protected against Txd short by an internal shut-off when the pulse duration is exceeding maximum IrDA specification value of pulse duration. In addition the max. current is limited.
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Document Number 82553 Rev. A1.3, 17-Jul-02
TFBS5607
Vishay Semiconductors Optoelectronic Characteristics
Tamb = 25C, Vdd1 = 2.4 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameters Transceiver Supported Data Rates Rxd pulse duration 400 ns Base band SIR mode Base band 1.152 Mbit/s Supply Voltage Range Supply Voltage Supply Current shutdown mode Average Supply Current *) specified operation Vdd2 = 2.4 V to 5.5 V Vdd1 = 2.4 V to 5.5 V Vdd1 = 2.4 V to 5.5 V Vdd1 Vdd2 IS ISSD IS 9.6 9.6 2.4 2.4 500 0.1 60 1152 152 5.5 5.5 900 1 110 kbit/s kbit/s V V A A mA Test Conditions Symbol Min. Typ. Max. Unit
Supply Current receive mode Vdd1 = 2.4 V to 5.5 V
Standard MIR transmit mode above Vdd1 = 3.3 V Ie > 100 mW/sr a serial resistor for reducing the internal power dissipation should be implemented, e.g. RL = 2.7 Logic Voltage Range Shutdown/ Mode clock pulse duration Shutdown delay "Receive off" Shutdown delay "Receive on" Transceiver "Power on" Settling Time *) Time from switching on Vdd1 to established specified operation Vdd2 = 2.4 V to 5.5 V Vlogic tprog tprog tprog 1.5 0.2 1 40 50 5.5 20 1.5 100 V s ms s s
Max. data is for 20% (25%) duty cycle for SIr (MIR) 1.152 Mbit/s low power mode. The typical value is given for the case of normal operation with statistical equal distribution of "0" and "1" states.
Document Number 82553 Rev. A1.3, 17-Jul-02
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TFBS5607
Vishay Semiconductors Optoelectronic Characteristics
Tamb = 25C, Vdd1 = 2.4 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameters Receiver Min. Detection Threshold Irradiance SIR 9.6 kbit/s to 1.152 Mbit/s *) Min. Detection Threshold Irradiance SIR 576 kbit/s to 1.152 Mbit/s *) Maximum Detection Threshold Irradiance || 15 Vdd1 = 2.4 V to 5.5 V || 15 Vdd1 = 2.4 V to 5.5 V || 90 Vdd1 = 3 V || 90 Vdd1 = 5 V Logic Low Receiver Input Irradiance Output Voltage Rxd active C = 15 pF, R = 2.2 k non active C = 15 pF, R = 2.2 k Output Current Rxd VOL < 0.8 V Rise Time @Load C = 15 pF Fall Time @Load C = 15 pF Rise Time @Load: C = 15 pF, R = 2.2 k Fall Time @Load: C = 15 pF, R = 2.2 k 1.5 V Vlogic < 1.8 V 1.5 V Vlogic < 1.8 V 1.8 V Vlogic < 5.5 V 1.8 V Vlogic < 5.5 V tr tf tr tf tp tL 20 20 250 30 30 25 25 400 50 70 70 550 200 4 mA ns ns ns ns ns s VOH Vdd1-0.5 V Ee, min 40 80 mW/m 2 Test Conditions Symbol Min. Typ. Max. Unit
Ee, min
70
150
mW/m 2
Ee, max Ee, max Ee,max,low VOL
8000
15000 5000
W/m 2 W/m 2 mW/m 2
4 0.5 0.8
V
Rxd Signal Electrical Output 1.5 V Vlogic < 5.5 V Pulse Width Latency *) MIR mode Rxd output pulse duration 400 ns
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Document Number 82553 Rev. A1.3, 17-Jul-02
TFBS5607
Vishay Semiconductors Optoelectronic Characteristics
Tamb = 25 C, Vdd1 = 2.4 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameters Transmitter Logic CMOS High/Low Decision Threshold Logic Low Transmitter Input Voltage Logic High Transmitter Input Voltage Output Radiant Intensity, || 15 1.5 V < Vlogic < 5.5 V Vdd2 = 3 V VIL(Txd) VIL(Txd) VIH(Txd) Ie IIRED PWOmin PWO PWO tr, tf p Txd logic low level Ie tj 850 40 0.04 25 0.2 23 1.45 210 0 0.8 x Vlogic 40 90 450 80 1.75 226 40 900 1/2 x Vlogic 0.2 x Vlogic Vlogic + 0.5 V V V mW/ sr mA s s ns ns nm nm W/sr % s Test Conditions Symbol Min. Typ. Max. Unit
Controlled IRED drive peak current *) Vdd1 = 2.7 V to 5.5 V Maximum Output Pulse width (eye safety protection) Optical Pulse width Optical Rise/Falltime Peak Wavelength of Emission Spectral Optical Radiation Bandwidth Output Radiant Intensity Overshoot, Optical Rising Edge Peak to Peak Jitter *) PWI > 23 s PWI > 1.6 s PWI > 217 ns
The current through the IRED can be reduced and defined by an external resistor, the internal current limitation is set to 450 mA peak, nominal. For operating above VIRED = 4 V an external resistor is to be used for internal power dissipation reduction
Document Number 82553 Rev. A1.3, 17-Jul-02
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TFBS5607
Vishay Semiconductors Identification
The identification of the device can be recalled by setting the SD active followed by activating Txd for a short period. With the low going edge of Txd a single pulse is generated at Rxd. The SD is indendet to activate the shutdown function after a delay of 1 ms. Therefore the full sequence should be run with that 1 ms time limitation, see drawing.
tSD: > 5 ms for "real" shutdown > 1 ms
SD
tTxd: > 0.5 ms to 2 ms
Txd
tdelTxd: 1 ms tdelRxd: 10 ns
tRxd = 400 ns
Rxd
Figure 3. Timing for self identification
Current Derating Diagram
600 Peak Operating Current ( mA ) 500
Recommended Solder Profile
240 210 Temperature ( C )
2 - 4C/s
10 s max. @ 230C
400 300 200 100 0 -40 -20 0
Current derating as a function of the maximum forward current of IRED. Maximum duty cycle: 25%.
180 150 120 90 60 30 0
120 - 180 s 90 s max.
2 - 4C/s
14875
20 40 60 80 100 120 140 Temperature ( C )
0
14874
50
100
150 200 250 Time ( s )
300
350
Figure 4. Current Derating as a Function of Ambient Temperature and Duty Cycle, see Absolute Maximum Ratings
Figure 5. Recommended Solder Profile
Vlogic Setting
The logic voltage swing is set by applying an external voltage to the Vlogic pin.
Table 1. Truth table
Inputs SD Txd Optical input Irradiance mW/ m2 x Rxd
Outputs LED drive current resulting intensity Ie in mW/ sr 0
high < 1 ms
pulse
low going Txd triggers monostable to edit a 400 ns (nominal) low pulse floating (500 k to Vdd) high high high low, edge triggered pulse of 400 ns durating
high > 1 ms low low low low
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x high high > 80 s low low
x x x <4 40
0 > 40 0 0 0
Document Number 82553 Rev. A1.3, 17-Jul-02
TFBS5607
Vishay Semiconductors TFBS5607 (Mechanical Dimensions)
Dimensions in mm
16503
Document Number 82553 Rev. A1.3, 17-Jul-02
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TFBS5607
Vishay Semiconductors Pad Layout
The leads of the device should be soldered in the center position of the pads.
Mounting center 1.35 Shield solder pad
1.25 0.1 0.6 2.05
1.75
Fiducial 0.95 7 x 0.95 = 6.65 Unit: mm
15250
Figure 6. Recommended Land Pattern
8.2
0.2 3.2
2.6 Solder Mask
16505
Figure 7. Adjacent Land Keep-out and Solder Mask Areas
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Document Number 82553 Rev. A1.3, 17-Jul-02
TFBS5607
Vishay Semiconductors
Tape and Reel Dimensions
16525
Trailer
no devices devices
Leader
no devices
End
min. 200 min. 400
Start
96 11818
W1
N
A
Reel Hub
W2
16515
Version B
Document Number 82553 Rev. A1.3, 17-Jul-02
Tape Width 16
A 330 1
N 60 + 2.5
W1 16.4 + 2
W2 max 22.4
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TFBS5607
Vishay Semiconductors Appendix
Application Hints Recommended Circuit Diagram TFBS5607
The TFBS5607 doesn't need any external components when operated at a "clean" power supply. In a more noisy ambient it is recommended to add a combination of a resistor and capacitor (R1, C1, C2) for noise suppression as shown in the figure below. A combination of a electrolytic for the low frequency range and a ceramic capacitor for suppressing the high frequency disturbance will be most effective. The capacitor C3 is only necessary when inductive wiring is used or the power supply cannot deliver the operating peak pulse current. However, a low impedance layout is the better and more cost efficient solution. The inputs TXD and SD are high impedance CMOS inputs. Therefore, the lines from the I/O to those inputs should be carefully designed not to pick up ambient noise. If long lines are used, loads at the Txd input of the TFBS5607 and at the Rxd input of the controller (!) are recommended. At the IRED Anode voltage supply line an additional capacitor might be necessary when inductive wiring is used. For adjusting the intensity depending on the application, a serial resistor in the Vcc2 supply to the IRED Anode pin can be used.
Shut Down
To shut down the TFBS5600 into a standby mode the SD pin has to be set active. After a delay of < 1 ms it will switch to the standby mode.
Latency
The receiver is in specified conditions after the defined latency. In a UART related application after that time (typically 50 s) the receiver buffer of the UART must be cleared. Therefore, the transceiver has to wait at least the specified latency after receiving the last bit before starting the transmission to be sure that the corresponding receiver is in a defined state.
C1, (C3): 4.7 F, see text C2: 470 nF R1 VCC1 GND Rxd VCC2 Txd SD Vlog C3 4 1 3 5 7 Rxd Vdd2, IRED Anode Txd SD Vlogic C1 C2 6 8 Vdd1 GND
TFBS5607
Figure 8. Recommended Application Circuit
Table 2. Recommended Application Circuit Components
Component Recommended Value C1, C3 4.7 mF, 16 V C2 0.47 F, Ceramic R1 47 , 0.125 W
Vishay Part Number 293D 475X9 016B 2T VJ 1206 Y 104 J XXMT CRCW-1206-47R0-F-RT1
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Document Number 82553 Rev. A1.3, 17-Jul-02
TFBS5607
Vishay Semiconductors Revision History:
A1.2, 18/02/2002: A1.3, 17/07/2002: Final new revision Typos corrected, operating voltage range adjusted to 2.7 V to 5.5 V, wavelength range of transmitter adapted to full IrDA(R) range.
Document Number 82553 Rev. A1.3, 17-Jul-02
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TFBS5607
Vishay Semiconductors Ozone Depleting Substances Policy Statement
It is the policy of Vishay Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. Vishay Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. Vishay Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use Vishay Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify Vishay Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Vishay Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2831, Fax number: 49 (0)7131 67 2423
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Document Number 82553 Rev. A1.3, 17-Jul-02

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