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19-0378; Rev 1; 6/95
Octal, 2-Wire Serial 8-Bit DAC with Rail-to-Rail Outputs
_______________General Description
The MAX521 is an octal, 8-bit voltage-output digital-toanalog converter (DAC) with a simple 2-wire serial interface that allows communication between multiple devices. It operates from a single 5V supply and its internal precision buffers allow the DAC outputs to swing rail-to-rail. The reference input range includes both supply rails. The MAX521 has five reference inputs. The first four DACs (DAC0-DAC3) each have a separate reference input (REF0-REF3), allowing each DAC's full-scale range to be set independently. The remaining four DACs (DAC4-DAC7) share the remaining reference input, REF4. The MAX521 features a serial interface and internal software protocol, allowing communication at data rates up to 400kbps. The interface, combined with the double-buffered input configuration, allows the DAC registers to be updated individually or simultaneously. In addition, the device can be put into a low-power shutdown mode that reduces supply current to 4A. Poweron reset ensures the DAC outputs are at 0V when power is initially applied. The MAX521 is available in 20-pin DIP and 24-pin SO package as well as a space-saving 24-pin SSOP package.
____________________________Features
o o o o o o o Single +5V Supply Simple 2-Wire Serial Interface I2C Compatible Output Buffer Amplifiers Swing Rail-to-Rail Reference Input Range Includes Both Supply Rails Power-On Reset Clears All Latches 4A Power-Down Mode
MAX521
______________Ordering Information
PART MAX521ACPP MAX521BCPP MAX521ACWG MAX521BCWG TEMP. RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C PIN-PACKAGE 20 Plastic DIP 20 Plastic DIP 24 Wide SO 24 Wide SO TUE (LSB) 1 2 1 2 1 2 2
________________________Applications
Minimum Component Analog Systems Digital Offset/Gain Adjustment Industrial Process Control Automatic Test Equipment Programmable Attenuators
MAX521ACAG 0C to +70C 24 SSOP MAX521BCAG 0C to +70C 24 SSOP MAX521BC/D 0C to +70C Dice* Ordering Information continued at end of data sheet. *Dice are specified at TA = +25C, DC parameters only.
________________Functional Diagram
SDA SCL REF2 REF1 REF0 OUT0 8
MAX521
8 8-BIT SHIFT REGISTER
INPUT LATCH 0 1 INPUT LATCH 1 1 INPUT LATCH 2 1 INPUT LATCH 3 1 1
OUTPUT LATCH 0
DAC0 OUT1
_________________Pin Configurations
TOP VIEW
OUT1 1 OUT0 2 REF1 3 REF0 4 DGND 5 AGND 6 SCL 7 SDA 8 OUT4 9 OUT5 10 20 OUT2 19 OUT3 18 REF2
ADDRESS COMPARATOR START/STOP DETECTOR
OUTPUT LATCH 1
DAC1 OUT2
8
OUTPUT LATCH 2
DAC2
OUT3 8 OUTPUT LATCH 3 DAC3
MAX521
17 REF3 16 REF4 15 VDD 14 AD1 13 AD0 12 OUT7 11 OUT6
8 8 DECODE 8 8 8 8
OUT4 OUTPUT LATCH 4 DAC4 OUT5 OUTPUT LATCH 5 DAC5 OUT6 OUTPUT LATCH 6 DAC6 OUT7 OUTPUT LATCH 7 REF3 DAC7
INPUT LATCH 4 1 INPUT LATCH 5 1 INPUT LATCH 6 1 INPUT LATCH 7
DIP
Pin Configurations continued at end of data sheet.
AD0
AD1
REF4
________________________________________________________________ Maxim Integrated Products
1
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Octal, 2-Wire Serial 8-Bit DAC with Rail-to-Rail Outputs MAX521
ABSOLUTE MAXIMUM RATINGS
VDD to DGND ...........................................................-0.3V to +6V VDD to AGND............................................................-0.3V to +6V OUT0-OUT7 ...............................................-0.3V to (VDD + 0.3V) REF0-REF4.................................................-0.3V to (VDD + 0.3V) AD0, AD1....................................................-0.3V to (VDD + 0.3V) SCL, SDA to DGND ..................................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) 20-Pin Plastic DIP (derate 11.11mW/C above +70C)....889mW 24-Pin Wide SO (derate 11.76mW/C above +70C) ....941mW 24-Pin SSOP (derate 8.00mW/C above +70C) .........640mW 20-Pin CERDIP (derate 11.11mW/C above +70C)....889mW Operating Temperature Ranges MAX521_C_ _ .....................................................0C to +70C MAX521_E_ _...................................................-40C to +85C MAX521BMJP ................................................-55C to +125C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec).............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 5V 10%, VREF_ = 4V, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25C.) PARAMETER STATIC ACCURACY Resolution Total Unadjusted Error Differential Nonlinearity Zero-Code-Error TUE DNL ZCE MAX521A MAX521B Guaranteed monotonic MAX521_C Code = 00 hex MAX521_E MAX521BM MAX521_C Zero-Code-Error Supply Rejection Zero-Code-Error Temperature Coefficient Full-Scale Error Code = 00 hex Code = 00 hex MAX521_C Code = FF hex MAX521_E MAX521BM MAX521_C Full-Scale-Error Supply Rejection Full-Scale-Error Temperature Coefficient REFERENCE INPUTS Input Voltage Range Input Resistance Input Current Input Capacitance Channel-to-Channel Isolation AC Feedthrough RIN Code = 55 hex (Note 1) PD = 1 Code = FF hex (Note 2) (Note 3) (Note 4) REF4 REF0-REF3 120 30 -60 -70 REF4 REF0-REF3 0 4 16 6 24 10 VDD V k A pF dB dB Code = FF hex VDD = 5V 10% MAX521_E MAX521BM 1 1 1 10 V/C mV MAX521_E MAX521BM 1 1 1 10 18 20 20 mV V/C mV 8 1.5 2.0 1.0 18 20 20 mV Bits LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
Note 1: Input resistance is code dependent. The lowest input resistance occurs at code = 55 hex. Note 2: Input capacitance is code dependent. The highest input capacitance occurs at code = FF hex. Note 3: VREF = 4Vp-p, 10kHz. Channel-to-channel isolation is measured by setting the code of one DAC to FF hex and setting the code of all other DACs to 00 hex. Note 4: VREF = 4Vp-p, 10kHz, DAC code = 00 hex. 2 _______________________________________________________________________________________
Octal, 2-Wire Serial 8-Bit DAC with Rail-to-Rail Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V 10%, VREF_ = 4V, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25C.) PARAMETER DAC OUTPUTS Full-Scale Output Voltage OUT_ = 4V, 0mA to 2.5mA Output Load Regulation Output Leakage Current DIGITAL INPUTS SCL, SDA Input High Voltage Input Current Input Hysteresis Input Capacitance DIGITAL INPUTS AD0, AD1 Input High Voltage Input Low Voltage Input Leakage DIGITAL OUTPUT SDA (Note 6) Output Low Voltage Three-State Leakage Current Three-State Output Capacitance DYNAMIC PERFORMANCE Voltage Output Slew Rate Output Settling Time Digital Feedthrough Digital-Analog Glitch Impulse Signal to Noise + Distortion Ratio Multiplying Bandwidth Wideband Amplifier Noise POWER REQUIREMENTS Supply Voltage VDD Normal mode, output unloaded, all digital inputs 0V or VDD Power-down mode (PD = 1) Note 5: Guaranteed by design. Note 6: I2C compatible mode. Note 7: Output settling time is measured by taking the code from 00 hex to FF hex, and from FF hex to 00 hex. MAX521_C MAX521_E/BM 4.5 10 10 4 5.5 20 mA 24 20 A V Positive and negative MAX521_C MAX521_E MAX521BM 1.0 0.7 0.5 6 5 12 87 1 60 V/s s nV-s nV-s dB MHz VRMS VOL IL COUT ISINK = 3mA ISINK = 6mA VIN = 0V to VDD (Note 5) 0.4 0.6 10 10 V A pF VIN VIL IIN VIN = 0V to VDD 2.4 0.8 10 V V A VIH VIL IIN VHYST CIN 0V VIN VDD (Note 5) (Note 5) 0.05VDD 10 0.7VDD 0.3VDD 10 V A V pF VREF_ = VDD, code = FF hex, 0A to 500A, MAX521_C/E VREF_ = VDD, code = FF hex, 0A to 500A, MAX521BM OUT_ = 0V to VDD, PD = 1 0 0.25 1.5 2.0 10 A LSB VDD V SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX521
SINAD
To 1/2 LSB, 10k and 100pF load (Note 7) Code = 00 hex, all digital inputs from 0V to VDD Code 128 to 127 VREF_ = 4Vp-p at 1kHz, VDD = 5V, Code = FF hex VREF_ = 4Vp-p, 3dB bandwidth
Supply Current
IDD
_______________________________________________________________________________________
3
Octal, 2-Wire Serial 8-Bit DAC with Rail-to-Rail Outputs MAX521
TIMING CHARACTERISTICS
(VDD = 5V 10%, TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25C.) PARAMETER Serial Clock Frequency Bus Free Time Between a STOP and a START Condition Hold Time, (Repeated) Start Condition LOW Period of the SCL Clock High Period of the SCL Clock Setup Time for a Repeated START Condition Data Hold Time Data Setup Time Rise Time of Both SDA and SCL Signals, Receiving Fall Time of Both SDA and SCL Signals, Receiving Fall Time of SDA Transmitting (Note 6) Setup Time for STOP Condition Capacitive Load for Each Bus Line Pulse Width of Spike Suppressed SYMBOL fSCL tBUF tHD, STA tLOW tHIGH tSU, STA tHD, DAT tSU, DAT tR tF tF tSU, STO Cb tSP (Notes 10, 11) 0 (Note 9) (Note 9) ISINK 6mA (Note 9) (Note 8) CONDITIONS MIN 0 1.3 0.6 1.3 0.6 0.6 0 100 20 + 0.1Cb 20 + 0.1Cb 20 + 0.1Cb 0.6 400 50 300 300 250 0.9 TYP MAX 400 UNITS kHz s s s s s s ns ns ns ns s pF ns
Note 8: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to bridge the undefined region of SCL's falling edge. Note 9: Cb = total capacitance of one bus line in pF. tR and tf measured between 0.3VDD and 0.7VDD. Note 10: An input filter on the SDA and SCL input suppresses noise spikes less than 50ns. Note 11: Guaranteed by design.
__________________________________________Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
DAC OUTPUT HIGH VOLTAGE vs. OUTPUT SOURCE CURRENT
MAX521-1
DAC OUTPUT LOW VOLTAGE vs. OUTPUT SINK CURRENT
MAX521-2
SUPPLY CURRENT vs. TEMPERATURE
VDD = 5.5V ALL REF INPUTS = 0.6V ALL DIGITAL INPUTS to VDD ALL DAC CODES FF HEX
MAX521-3
1.0
SUPPLY CURRENT (mA)
0.8 VDD - VOUT (V)
VDD = 5V VREF = 5V DAC CODE = FF HEX LOAD to AGND
1.0
0.8
VDD = 5V VREF = 5V DAC CODE = 00 HEX LOAD to VDD
12 10 8 6 4
0.4
VOUT (V)
0.6
0.6
0.4
0.2 VOUT = VREF = (255/256) 0 2 4 6 8 10 12 14 16
0.2
ALL DAC CODES 00 HEX 2 0
0
0 0 2 4 6 8 10 OUTPUT SINK CURRENT (mA)
-60
-20
20
60
100
140
OUTPUT SOURCE CURRENT (mA)
TEMPERATURE (C)
4
_______________________________________________________________________________________
Octal, 2-Wire Serial 8-Bit DAC with Rail-to-Rail Outputs
______________________________Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE
SHUTDOWN SUPPLY CURRENT (A) VDD = 5.5V ALL REF INPUTS = 0.6V ALL DIGITAL INPUTS to VDD
MAX521-4
MAX521
SUPPLY CURRENT vs. REFERENCE VOLTAGE
VDD = 5V ALL REFERENCE INPUTS DRIVEN
MAX521-5
REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE
0 RELATIVE OUTPUT (dB) -2 -4 -6 -8 -10 -12 -14 -16 4VP-P SINE 2VP-P SINE 1VP-P SINE 0.5VP-P SINE VDD = 5V VREF = SINE WAVE CENTERED AT 2.5V 1k 10k 100k FREQUENCY (Hz) 1M 10M
MAX521-6
6 5 4 3 2 1 0 -60 -20
10
-2
SUPPLY CURRENT (mA)
8
6 ALL DAC CODES = FF HEX
4
2
ALL DAC CODES = 00 HEX
0 20 60 100 140 0 1 2 3 4 5 TEMPERATURE (C) REFERENCE VOLTAGE (V)
-18
POSITIVE SETTLING TIME
NEGATIVE SETTLING TIME
OUT1 1V/div
OUT1 1V/div
1s/div OUT1 LOADED WITH 10k II 100pF REF1 = 4V DAC CODE = 00 HEX to FF HEX
1s/div OUT1 LOADED WITH 10k II 100pF REF1 = 4V DAC CODE = FF HEX to 00 HEX
WORST-CASE 1LSB DIGITAL STEP CHANGE
OUT1 20mV/div AC COUPLED
500ns/div REF1 = 5V DAC CODE = 80 HEX to 7F HEX
_______________________________________________________________________________________
5
Octal, 2-Wire Serial 8-Bit DAC with Rail-to-Rail Outputs MAX521
______________________________Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
CLOCK FEEDTHROUGH REFERENCE FEEDTHROUGH AT 1kHz
A
A
B B
A = SCL, 400kHz, 5V/div B = OUT1, 5mV/div DAC CODE = 7F HEX REF1 = 5V
A = REF1, 1V/div (4VP-P) B = OUT1, 50V/div, UNLOADED FILTER PASSBAND = 100Hz to 10kHz DAC CODE = 00 HEX
REFERENCE FEEDTHROUGH AT 10kHz
REFERENCE FEEDTHROUGH AT 100kHz
A
A
B
B
A = REF1, 1V/div (4VP-P) B = OUT1, 50V/div, UNLOADED FILTER PASSBAND = 1kHz to 100kHz DAC CODE = 00 HEX
A = REF1, 1V/div (4VP-P) B = OUT1, 50V/div, UNLOADED FILTER PASSBAND = 10kHz to 1MHz DAC CODE = 00 HEX
6
_______________________________________________________________________________________
Octal, 2-Wire Serial 8-Bit DAC with Rail-to-Rail Outputs
_____________________Pin Description
PIN NAME DIP 1 2 3 4 -- 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SO/SSOP 1 2 3 4 7, 9, 16, 20 5 6 8 10 11 12 13 14 15 17 18 19 21 22 23 24 OUT1 OUT0 REF1 REF0 N.C. DGND AGND SCL SDA OUT4 OUT5 OUT6 OUT7 AD0 AD1 VDD REF4 REF3 REF2 OUT3 OUT2 DAC1 Voltage Output DAC0 Voltage Output Reference Voltage Input for DAC1 Reference Voltage Input for DAC0 No Connect--not internally connected. Digital Ground Analog Ground Serial Clock Input Serial Data Input DAC4 Voltage Output DAC5 Voltage Output DAC6 Voltage Output DAC7 Voltage Output Address Input 0; sets IC's slave address Address Input 1; sets IC's slave address Power Supply, +5V Reference Voltage Input for DACs 4, 5, 6, and 7 Reference Voltage Input for DAC3 Reference Voltage Input for DAC2 DAC3 Voltage Output DAC2 Voltage Output FUNCTION
_______________Detailed Description
Serial Interface
The MAX521 uses a simple two-wire serial interface requiring only two I/O lines (2-wire bus) of a standard microprocessor port. Figure 1 shows the timing diagram for signals on the wire bus. Figure 2 shows the typical application of the MAX521. The 2-wire bus can have several devices (in addition to the MAX521) attached. The two bus lines (SDA and SCL) must be high when the bus is not in use. When in use, the port bits are toggled to generate the appropriate signals for SDA and SCL. External pull-up resistors are not required on these lines. The MAX521 can be used in applications where pull-up resistors are required (such as in I2C systems) to maintain compatibility with the existing circuitry. The MAX521 is a receive-only device and must be controlled by a bus master device. The MAX521 operates at SCL rates up to 400kHz. A master device sends information to the MAX521 by transmitting the MAX521's address over the bus and then transmitting the desired information. Each transmission consists of a START condition, the MAX521's programmable slaveaddress, one or more command-byte/output-byte pairs (or a command byte alone, if it is the last byte in the transmission), and finally, a STOP condition (Figure 3). The address byte and pairs of command and output bytes are transmitted between the START and STOP conditions. The SDA state is allowed to change only while SCL is low. The only exceptions to this are the START and STOP conditions. SDA's state is sampled, and therefore must remain stable while SCL is high. Data is transmitted in 8-bit bytes. Nine clock cycles are required to transfer the data bits to the MAX521. Set SDA low during the 9th clock cycle as the MAX521 pulls SDA low during this time. RC (see Figure 2) limits the current that flows during this time if SDA stays high for short periods of time.
MAX521
SDA tSU, DAT tLOW SCL tHD, STA tR START CONDITION tHIGH tF REPEATED START CONDITION STOP CONDITION START CONDITION tHD, DAT tSU, STA tHD, STA tSU, STO tBUF
Figure 1. Two-Wire Serial Interface Timing Diagram
_______________________________________________________________________________________ 7
Octal, 2-Wire Serial 8-Bit DAC with Rail-to-Rail Outputs
The START and STOP Conditions When the bus is not in use, both SCL and SDA must be high. A bus master signals the beginning of a transmission with a START condition by transitioning SDA from high to low while SCL is high (Figure 4). When the master has finished communicating with the slave, it issues a STOP condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission. The Slave Address The MAX521's slave address is seven bits long (Figure 5). The first five bits (MSBs) of the slave address have been factory programmed and are always 01010. The state of the MAX521 inputs AD0 and AD1 determine the final two bits of the 7-bit slave address. These input pins may be connected to VDD or DGND, or they may be actively driven by TTL or CMOS logic levels. There are four possible slave addresses for the MAX521, and therefore a maximum of four such devices may be on the bus at one time. The eighth bit (LSB) in the slave address byte should be low when writing to the MAX521. The MAX521 watches the bus continuously, waiting for a START condition followed by its slave address. When it recognizes its slave address, it is ready to accept data.
MAX521
C
SDA SCL
RC 1k
REF0 REF1 REF2 OCTAL REF3 DAC REF4 OUT0 MAX521 OUT1 OUT2 . SCL . . SDA . AD0 OUT7 AD1
+1V +4V +5V
OFFSET ADJUSTMENT OFFSET ADJUSTMENT
GAIN ADJUSTMENTS
+5V REF0 . . . OCTAL . DAC REF4 OUT0 MAX521 OUT1 OUT2 . SCL . . SDA AD0 OUT6 OUT7 AD1
BRIGHTNESS ADJUSTMENT CONTRAST ADJUSTMENT THRESHOLD ADJUSTMENTS +5V
+5V
MOTOR +12V SDA
SCL START CONDITION STOP CONDITION
Figure 2. MAX521 Typical Application Circuit
Figure 4. All communications begin with a START condition and end with a STOP condition, both generated by a bus master.
SLAVE ADDRESS BYTE (0, 1, 0, 1, 0, AD1, AD0) SDA MSB SCL START CONDITION LSB ACK MSB
COMMAND BYTE
OUTPUT BYTE
LSB
ACK
MSB
LSB
ACK
STOP CONDITION
Figure 3. A Complete Serial Transmission
8 _______________________________________________________________________________________
Octal, 2-Wire Serial 8-Bit DAC with Rail-to-Rail Outputs
The Command Byte and Output Byte A command byte follows the slave address. Figure 6 shows the format for the command byte. A command byte is usually followed by an output byte unless it is the last byte in the transmission. If it is the last byte, all bits except PD and RST are ignored. If an output byte
SLAVE ADDRESS 0 SDA LSB SCL SLAVE ADDRESS BITS AD1 AND AD0 CORRESPOND TO THE LOGIC STATE OF MAX521 INPUT PINS AD1 AND AD0. 1 0 1 0 AD1 AD0 0 ACK
Figure 5. Address Byte
R2 SDA MSB SCL R2, R1, R0: RESERVED BITS. SET TO 0. RST: PD: RESET BIT, SET TO 1 TO RESET ALL DAC REGISTERS. POWER-DOWN BIT. SET TO 1 TO PLACE THE MAX521 IN THE 10A SHUTDOWN MODE. SET TO 0 TO RETURN THE MAX521 TO THE NORMAL OPERATIONAL STATE. LSB R1 R0 RST PD A2 A1 A0 ACK
A2, A1, A0: ADDRESS BITS. DIGITAL ADDRESS FOR DAC0 TO DAC7. DETERMINES WHICH DAC'S INPUT LATCH RECEIVES THE 8 BITS OF DATA IN THE NEXT BYTE. ACK: ACKNOWLEDGE BIT. THE MAX521 PULLS SDA LOW DURING THE 9TH CLOCK PULSE.
Figure 6. Command Byte
01 SDA ADDRESS BYTE START CONDITION ACK COMMAND BYTE (ADDRESSING DAC0) ACK 0 1 0 AD1 AD0 0 0 0 0 0 0 0 0 000 1
follows the command byte, A0-A2 of the command byte indicate the digital address of the DAC whose input data latch receives the digital output data. The data is transferred to the DAC's output latch during the STOP condition following the transmission. This allows all DACs to be updated and the new outputs to appear simultaneously (Figure 7). Setting the PD bit high powers down the MAX521 following a STOP condition (Figure 8a). If a command byte with PD set high is followed by an output byte, the addressed DAC's input latch will be updated and the data will be transferred to the DAC's output latch following the STOP condition (Figure 8b). If the transmission's last command byte has PD high, the voltage outputs will not reflect the newly entered data because the DAC will enter power-down mode when the STOP condition is detected. When in power-down, the DAC outputs float. In this mode, the supply current is a maximum of 20A. A command byte with the PD bit low returns the MAX521 to normal operation following a STOP condition, and the voltage outputs reflect the current outputlatch contents (Figures 9a and 9b). Because each subsequent command byte overwrites the previous PD bit, only the last command byte of a transmission affects the MAX521's power-down state. Setting the RST bit high clears all DAC input latches. The DAC outputs remain unchanged until a STOP condition is detected (Figure 10a). If a reset is issued, the following output byte is ignored. Subsequent pairs of command/output bytes overwrite the input latches (Figure 10b). All changes made during a transmission affect the MAX521's outputs only when the transmission ends and a STOP has been recognized. The R0, R1, and R2 bits are reserved bits that must be set to zero.
MAX521
1
1
1
1
1
1
1
0 ACK
00
0
0
00
0
1
0 ACK
OUTPUT BYTE (FULL SCALE)
COMMAND BYTE (ADDRESSING DAC1)
(
1 1 1 00 ACK 0 0 0 0 01 00 ACK 1 0 0 0 0 COMMAND BYTE (ADDRESSING DAC2) DAC1 INPUT LATCH SET TO FULL SCALE
DAC0 INPUT LATCH SET TO FULL SCALE 0 0 0 0
)
1 SDA
1
1
1
1
OUTPUT BYTE (FULL SCALE)
(
Figure 7. Setting DAC Outputs
)
ACK OUTPUT BYTE STOP (HALF SCALE) CONDITION DAC2 INPUT LATCH SET TO HALF SCALE DAC OUTPUTS CHANGE HERE: DACS 0 AND 1 GO TO FULL SCALE, DAC 2 GOES TO HALF SCALE.
(
)
(
)
9
_______________________________________________________________________________________
Octal, 2-Wire Serial 8-Bit DAC with Rail-to-Rail Outputs MAX521
(a) 01 SDA ADDRESS BYTE START CONDITION (b) 01 SDA ADDRESS BYTE START CONDITION NOTE: X = DON'T CARE ACK COMMAND BYTE (ADDRESSING DAC0) ACK OUTPUT BYTE (FULL SCALE) ACK STOP CONDITION DAC 0 INPUT LATCH SET TO FULL SCALE. DEVICE ENTERS POWER-DOWN STATE. DAC 0 OUTPUT LATCH SET TO FULL SCALE. 0 1 0 AD1 AD0 0 0 0 0 0 0 (PD) 10 ACK 0 1 0 AD1 AD0 0 0 (PD) 00001 X COMMAND BYTE X X ACK STOP CONDITION 0
(
DEVICE ENTERS POWER-DOWN STATE
)
0
00
0
1
1
1
1
1
1
1
1
(
)
(
)
Figure 8. Entering the Power-Down State
(a) 01 SDA ADDRESS BYTE START CONDITION (b) 01 SDA ADDRESS BYTE START CONDITION NOTE: X = DON'T CARE 0 1 0 AD1 AD0 0 0 1 0 AD1 AD0 0
(PD) 000000 X ACK X X COMMAND BYTE
0 ACK STOP CONDITION
(
DEVICE RETURNS TO NORMAL OPERATION
)
0
00 ACK
0
0
0
(PD) 01
11
0 ACK
0
0
0
0
0
0
0
0
COMMAND BYTE (ADDRESSING DAC7)
ACK OUTPUT BYTE STOP (SET TO 0) DAC7 OUTPUT CONDITION LATCH SET TO 0 DEVICE RETURNS TO NORMAL OPERATION. DAC 7 SET TO 0.
(
) (
)
Figure 9. Returning to Normal Operation from Power-Down
(a) 01 SDA ADDRESS BYTE START CONDITION ACK 0 1 0 AD1 AD0 0 0
(RST) 00010 X COMMAND BYTE X X
0 ACK
(
01 0 1 0 AD1 AD0 0 0 0 0 ADDRESS BYTE ACK
ALL INPUT LATCHES SET TO 0. 0 X X X
)
STOP CONDITION
(b) SDA START CONDITION NOTE: X = DON'T CARE
(RST) 010
(
ALL OUTPUTS SET TO 0.
)
0 ACK ADDITIONAL COMMAND BYTE/ OUTPUT BYTE PAIRS STOP CONDITION ALL DAC OUTPUTS SET TO 0 UNLESS CHANGED BY ADDITIONAL COMMAND BYTE/OUTPUT BYTE PAIRS.
XXXXXXXX ACK "DUMMY" OUTPUT BYTE
COMMAND BYTE
(
ALL INPUT LATCHES SET TO 0.
)
(
)
Figure 10. Resetting DAC Outputs
10 ______________________________________________________________________________________
Octal, 2-Wire Serial 8-Bit DAC with Rail-to-Rail Outputs
I2C Compatibility
The MAX521 is fully compatible with existing I2C systems. SCL and SDA are high-impedance inputs; SDA has an open drain which pulls the data line low during the 9th clock pulse. Figure 11 shows the MAX521 being used in a typical I2C application.
MAX521
C
SDA SCL SCL SDA
E PROM XICOR X24C04
2
Additional START Conditions It is possible to interrupt a transmission to a MAX521 with a new START (repeated start) condition (perhaps addressing another device), which leaves the input latches with data that has not been transferred to the output latches (Figure 12). Only the currently addressed MAX521 will recognize a STOP condition and transfer data to its output latches. If the MAX521 is left with data in its input latches, the data can be transferred to the output latches the next time the device is addressed, as long as it receives at least one command byte and a STOP condition. Early Stop Conditions The addressed MAX521 recognizes a STOP condition at any point in a transmission. If the STOP occurs during a command byte, all previous uninterrupted command and output byte pairs are accepted, the interrupted command byte is ignored, and the transmission ends (Figure 13a). If the STOP occurs during an output byte, all previous uninterrupted command and output byte pairs are accepted, the final command byte's PD and RST bits are accepted, the interrupted output byte is ignored, and the transmission ends (Figure 13b).
+5V
OCTAL DAC
SCL MAX521 SDA AD0 AD1
OCTAL DAC
SCL SDA AD0 AD1
MAX521
Figure 11. MAX521 Used in a Typical I2C Application Circuit
01 SDA START CONDITION
0
1
0
0
0
0
0 ACK
0
0
0
0
0
0
0
1
0 ACK
1
1
1
1
1
1
1
1
0 ACK
0
1
0
1
0
0
1
0
0 ACK
ADDRESS BYTE (DEVICE 0)
COMMAND BYTE ADDRESSING DAC1
OUTPUT BYTE (FULL SCALE)
ADDRESS BYTE (DEVICE 1)
(
0 0 0 0 0 0 1 00 ACK 1 1 1 1 1 1 1 1 0 ACK COMMAND BYTE (ADDRESSING DAC2) OUTPUT BYTE (FULL SCALE)
DEVICE 0's DAC1 INPUT LATCH SET TO FULL SCALE.
)
REPEATED START CONDITION
SDA STOP CONDITION ONLY DEVICE 1's DAC2 OUTPUT LATCH SET TO FULL SCALE. DEVICE 0's OUTPUT LATCHES UNCHANGED.
(
Figure 12. Repeated START Conditions
DEVICE 1's DAC2 INPUT LATCH SET TO FULL SCALE.
)(
)
______________________________________________________________________________________
11
Octal, 2-Wire Serial 8-Bit DAC with Rail-to-Rail Outputs MAX521
(a) 01 SDA ADDRESS BYTE START CONDITION ACK INTERRUPTED COMMAND BYTE EARLY MAX521's STATE STOP CONDITION REMAINS UNCHANGED. 0 1 0 AD1 AD0 0 0 (RST) (PD) 000110
(
)
(b) 01 SDA ADDRESS BYTE START CONDITION ACK 0 1 0 AD1 AD0 0 0 0 0
(PD) 0 RST 1 0
0
0
0
1
1
1
0
0
COMMAND BYTE (POWER DOWN)
ACK
INTERRUPTED OUTPUT BYTE EARLY STOP CONDITION
(
MAX521 POWERS DOWN; INPUT LATCHES REMAIN UNCHANGED IF RST = 0, DAC OUTPUTS RESET IF RST = 1.
)
Figure 13. Early STOP Conditions
R
R 2R D5 2R D6
R 2R D7
OUT_
2R
2R D0
REF_ AGND SHOWN FOR ALL 1s ON DAC
Reference Inputs The MAX521 can be used for multiplying applications. The reference accepts a 0V to VDD voltage, both DC and AC signals. The voltage at each REF input sets the full-scale output voltage for its respective DAC(s). The reference voltage must be positive. The DAC's input impedance is code dependent, with the lowest value occurring when the input code is 55 hex or 0101 0101, and the maximum value occurring when the input code is 00 hex. Since the REF input resistance (RIN) is code dependent, it must be driven by a circuit with low output impedance (no more than RIN / 2000) to maintain output linearity. The REF input capacitance is also code dependent, with the maximum value occurring at code FF hex (typically 120pF for REF4, and 30pF for REF0-REF3). The output voltage for any DAC can be represented by a digitally programmable voltage source as: VOUT = (N x VREF) / 256, where N is the numerical value of the DAC's binary input code. Output Buffer Amplifiers The MAX521 voltage outputs (OUT0-OUT7) are internally buffered precision unity-gain followers that slew up to 1V/s. The outputs can swing from 0V to VDD. With a 0V to 4V (or 4V to 0V) output transition, the amplifier outputs typically settle to 1/2LSB in 6s when loaded with 10k in parallel with 100pF. The buffer amplifiers are stable with any combination of resistive loads 2k and capacitive loads 300pF. The MAX521 is designed for unipolar-output, singlequadrant multiplication where the output voltages and the reference inputs are positive with respect to AGND. Table 1 shows the unipolar code.
Figure 14. DAC Simplified Circuit Diagram
Analog Section
DAC Operation The MAX521 contains eight matched voltage-output DACs. The DACs are inverted R-2R ladder networks that convert 8-bit digital words into equivalent analog output voltages in proportion to the applied reference voltages. DAC0-DAC3 each have separate reference inputs while DAC4-DAC7 all share a common reference input. Figure 14 shows a simplified diagram of one of the eight DACs.
12
______________________________________________________________________________________
Octal, 2-Wire Serial 8-Bit DAC with Rail-to-Rail Outputs MAX521
Table 1. Unipolar Code Table
SYSTEM GND
DAC CONTENTS 11111111 10000001 10000000 01111111 00000001 00000000
ANALOG OUTPUT 255 + VREF (------) 256 129 + VREF (------) 256 128 VREF + VREF (------) = ---- 256 2 127 + VREF (------) 256 1 + VREF (------) 256 0V
OUT2 OUT3 REF2 REF3 REF4 OUT1 OUT0 REF1 REF0 DGND AGND
__________Applications Information
Power-Supply Bypassing and Ground Management
Bypass VDD with a 0.1F capacitor, located as close to V DD and DGND as possible. The analog ground (AGND) and digital ground (DGND) pins should be connected in a "star" configuration to the highest quality ground available, which should be located as close to the MAX521 as possible. Careful PC board layout minimizes crosstalk among DAC outputs, reference inputs, and digital inputs. Figure 15 shows the suggested PC board layout to minimize crosstalk
Figure 15. PC Board Layout for Minimizing Crosstalk (bottom view, DIP package)
______________________________________________________________________________________
13
Octal, 2-Wire Serial 8-Bit DAC with Rail-to-Rail Outputs MAX521
__Ordering Information (continued)
PART MAX521AEPP MAX521BEPP MAX521AEWG MAX521BEWG MAX521AEAG MAX521BEAG MAX521BMJP TEMP. RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C PIN-PACKAGE 20 Plastic DIP 20 Plastic DIP 24 Wide SO 24 Wide SO 24 SSOP 24 SSOP 20 CERDIP** TUE (LSB) 1 2 1 2 1 2 2
REF0 REF3
____________________Chip Topography
REF1 OUT0 OUT1 OUT2 OUT3 REF2
DGND AGND
* Dice are specified at TA = +25C, DC parameters only. **Contact factory for availability.
0.212" (5.385mm)
_____Pin Configurations (continued)
TOP VIEW
OUT1 1 OUT0 2 REF1 3 REF0 4 DGND 5 AGND 6 N.C. 7 SCL 8 N.C. 9 SDA 10 OUT4 11 OUT5 12 24 OUT2 23 OUT3 22 REF2 21 REF3
AGND SCL SDA OUT4 OUT5 OUT6 OUT7 0.125" (3.175mm)
REF4 V DD AD1 AD0
MAX521
20 N.C. 19 REF4 18 VDD 17 AD1 16 N.C. 15 AD0 14 OUT7 13 OUT6
TRANSISTOR COUNT: 4518 SUBSTRATE CONNECTED TO VDD
SO/SSOP
14
______________________________________________________________________________________
Octal, 2-Wire Serial 8-Bit DAC with Rail-to-Rail Outputs
________________________________________________________Package Information
E D A3 A A2 E1
DIM A A1 A2 A3 B B1 C D1 E E1 e eA eB L INCHES MAX MIN 0.200 - - 0.015 0.175 0.125 0.080 0.055 0.022 0.016 0.065 0.045 0.012 0.008 0.080 0.005 0.325 0.300 0.310 0.240 - 0.100 - 0.300 0.400 - 0.150 0.115 INCHES MIN MAX 0.348 0.390 0.735 0.765 0.745 0.765 0.885 0.915 1.015 1.045 1.14 1.265 MILLIMETERS MIN MAX - 5.08 0.38 - 3.18 4.45 1.40 2.03 0.41 0.56 1.14 1.65 0.20 0.30 0.13 2.03 7.62 8.26 6.10 7.87 2.54 - 7.62 - - 10.16 2.92 3.81 MILLIMETERS MIN MAX 8.84 9.91 18.67 19.43 18.92 19.43 22.48 23.24 25.78 26.54 28.96 32.13
21-0043A
MAX521
L A1 e B D1
0 - 15 C B1 eA eB
Plastic DIP PLASTIC DUAL-IN-LINE PACKAGE (0.300 in.)
PKG. DIM PINS P P P P P N D D D D D D 8 14 16 18 20 24
DIM
D 0- 8 A e B
0.101mm 0.004in.
A1
C
L
A A1 B C E e H L
INCHES MAX MIN 0.104 0.093 0.012 0.004 0.019 0.014 0.013 0.009 0.299 0.291 0.050 0.419 0.394 0.050 0.016
MILLIMETERS MIN MAX 2.35 2.65 0.10 0.30 0.35 0.49 0.23 0.32 7.40 7.60 1.27 10.00 10.65 0.40 1.27
DIM PINS
E
H
Wide SO SMALL-OUTLINE PACKAGE (0.300 in.)
D D D D D
16 18 20 24 28
INCHES MIN MAX 0.398 0.413 0.447 0.463 0.496 0.512 0.598 0.614 0.697 0.713
MILLIMETERS MIN MAX 10.10 10.50 11.35 11.75 12.60 13.00 15.20 15.60 17.70 18.10
21-0042A
______________________________________________________________________________________
15
Octal, 2-Wire Serial 8-Bit DAC with Rail-to-Rail Outputs MAX521
___________________________________________Package Information (continued)
DIM A A1 B C D E e H L INCHES MILLIMETERS MAX MIN MIN MAX 0.078 1.73 0.068 1.99 0.008 0.05 0.002 0.21 0.015 0.25 0.010 0.38 0.008 0.09 0.004 0.20 SEE VARIATIONS 0.209 5.20 0.205 5.38 0.0256 BSC 0.65 BSC 0.311 7.65 0.301 7.90 0.037 0.63 0.025 0.95 8 0 0 8 INCHES MILLIMETERS MAX MIN MAX MIN 6.33 0.239 0.249 6.07 6.33 0.239 0.249 6.07 7.33 0.278 0.289 7.07 8.33 0.317 0.328 8.07 0.397 0.407 10.07 10.33
21-0056A
E
H
C
L
DIM PINS
e
A B D
A1
SSOP SHRINK SMALL-OUTLINE PACKAGE
D D D D D
14 16 20 24 28
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 (c) 1995 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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