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LTC1326 Micropower Precision Triple Supply Monitor
FEATURES
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DESCRIPTION
The LTC(R)1326 is a triple supply monitor intended for systems with multiple supply voltages. It provides micropower operation, small size and high accuracy supply monitoring. Tight 0.75% threshold accuracy and glitch immunity ensure reliable reset operation without false triggering. The 20A typical supply current makes the LTC1326 ideal for power-conscious systems. The RST output is guaranteed to be in the correct state for VCC3 down to 1V. The LTC1326 may also be configured to monitor any one or two VCC inputs instead of three, depending on system requirements. A manual pushbutton reset input provides the ability to generate a very narrow "soft" reset pulse (100s typ) or a 200ms reset pulse equivalent to a power-on reset. Both SRST and RST outputs are open-drain and can be OR-tied with other reset sources.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Simultaneously Monitors 5V, 3.3V and Adjustable Inputs Guaranteed Threshold Accuracy: 0.75% Low Supply Current: 20A Internal Reset Time Delay: 200ms Manual Pushbutton Reset Input Active Low and Active High Reset Outputs Active Low "Soft" Reset Output Power Supply Glitch Immunity Guaranteed RESET for VCC3 1V 8-Pin SO and MSOP Packages
APPLICATIONS
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Desktop Computers Notebook Computers Intelligent Instruments Portable Battery-Powered Equipment
TYPICAL APPLICATION
RST Output Voltage vs Supply Voltage
DC/DC CONVERTER 5V 3.3V 2.9V
3.5
SYSTEM LOGIC
3.0
RST OUTPUT VOLTAGE (V)
VCC5 = VCCA = 5V 4.7k PULL-UP FROM RST TO VCC3 TA = 25C
2.5 2.0 1.5 1.0 0.5
0.1F
VCC5 VCC3 VCCA LTC1326 RST PBR PUSHBUTTON RESET GND SRST
0 0 0.5 1.0 1.5 2.0 VCC3 (V) 2.5 3.0 3.5
1326 TA01
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1326 TA02
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LTC1326 ABSOLUTE
(Notes 1, 2)
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RATI GS
Operating Temperature Range ................... 0C to 70C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
Terminal Voltage VCC3, VCC5, VCCA .................................... - 0.5V to 7V RST, SRST ............................................ - 0.5V to 7V RST ......................................... - 0.5V to VCC3 + 0.3V PBR .......................................................... - 7V to 7V
PACKAGE/ORDER I FOR ATIO
TOP VIEW VCC3 VCC5 VCCA GND 1 2 3 4 8 7 6 5 PBR SRST RST RST
ORDER PART NUMBER LTC1326CMS8 MS8 PART NUMBER LTBA
MS8 PACKAGE 8-LEAD PLASTIC MSOP
TJMAX = 125C, JA = 160C/ W
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
VCC3 = 3.3V, VCC5 = 5V, VCCA = VCC3, TA = 25C unless otherwise noted.
SYMBOL VRT3 VRT5 VRTA VCC IVCC3 IVCC5 IVCCA tRST tSRST tUV IPBR VIL VIH tPW tDB tPB PARAMETER Reset Threshold VCC3 Reset Threshold VCC5 Reset Threshold VCCA VCC3 Operating Voltage VCC3 Supply Current VCC5 Input Current VCCA Input Current Reset Pulse Width Soft Reset Pulse Width VCC Undervoltage Detect to RST PBR Pull-Up Current PBR, RST Input Low Voltage PBR, RST Input High Voltage PBR Min Pulse Width PBR Debounce PBR Assertion Time to Reset Deassertion of PBR Input to SRST Output (PBR Pulse Width = 1s) PBR Held Less Than VIL RST in Correct Logic State PBR = VCC3 VCC5 = 5V VCCA = 1V RST Low with 10k Pull-Up to VCC3 SRST Low with 10k Pull-Up to VCC3 VCC5, VCC3 or VCCA Less Than Reset Threshold VRT by More Than 1% PBR = 0V
q q q q q q
CONDITIONS
q q q q q q q q q
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TOP VIEW VCC3 1 VCC5 2 VCCA 3 GND 4 8 PBR 7 SRST 6 RST 5 RST
ORDER PART NUMBER LTC1326CS8 S8 PART NUMBER 1326
S8 PACKAGE 8-LEAD PLASTIC SO
TJMAX = 125C, JA = 150C/ W
MIN 3.094 4.687 0.992 1
TYP 3.118 4.725 1.000 20 2.8
MAX 3.143 4.762 1.007 7 40 5 5 280 200
UNITS V V V V A A nA ms s s
-5 140 50
0 200 100 13
3 2 40
7
10 0.8
A V V ns
20 1.4 2.0
35 2.8
ms s
LTC1326
ELECTRICAL CHARACTERISTICS
VCC3 = 3.3V, VCC5 = 5V, VCCA = VCC3, TA = 25C unless otherwise noted.
SYMBOL VOL PARAMETER RST Output Voltage Low SRST Output Voltage Low RST Output Voltage Low VOH RST Output Voltage High (Note 3) SRST Output Voltage High (Note 3) RST Output Voltage High tPHL tPLH VOVR Prop Delay RST to RST High Input to Low Output Prop Delay RST to RST Low Input to High Output VCC5 Reset Override Voltage CONDITIONS ISINK = 5mA ISINK = 100A, VCC3 = 1V ISINK = 2.5mA ISINK = 2.5mA ISOURCE = 1A ISOURCE = 1A ISOURCE = 600A CRST = 20pF CRST = 20pF Override VCC5 Ability to Assert RST (Note 4)
q q q q q q q
MIN
TYP 0.15 0.05 0.15 0.15
MAX 0.4 0.4 0.4 0.4
UNITS V V V V V V V
VCC3 - 1 VCC3 - 1 VCC3 - 1 25 45 VCC3 0.025
ns ns V
The q denotes specifications which apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: All voltage values are with respect to GND.
Note 3: The output pins SRST and RST have weak internal pull-ups to VCC3 of 6A typ. However, external pull-up resistors may be used when faster rise times are required. Note 4: The VCC5 reset override voltage is valid for an operating range less than approximately 4.15V. Above this point the override is turned off and the VCC5 pin functions normally.
TYPICAL PERFORMANCE CHARACTERISTICS
IVCC3 vs Temperature
25 24 23 22
IVCC3 (A)
IVCC5 (A)
2.85 2.80 2.75 2.70 2.65 2.60 2.55 -35 25 5 -15 45 TEMPERATURE (C) 65 85 2.50 0 10 40 30 20 50 TEMPERATURE (C) 60 70
INPUT CURRENT (nA)
21 20 19 18 17 16 15 -55
UW
1326 G01
IVCC5 vs Temperature
3.00 2.95 2.90
VCCA Input Current vs Input Voltage
3 2 1 0 -1 -2 -3 0.8 0.85 0.9 0.95 1.0 1.05 1.1 1.15 1.2 INPUT VOLTAGE (V)
1236 G06
TA = 25C
1326 G02
3
LTC1326 TYPICAL PERFORMANCE CHARACTERISTICS
VCC5 Transient Immunity
50 45 RESET OCCURS ABOVE CURVE TA = 25C
TRANSIENT DURATION (s)
TRANSIENT DURATION (s)
35 30 25 20 15 10 5 0 0.01 0.1 1 0.001 VCC5 RESET COMPARATOR OVERDRIVE (V)
1326 G04
30 25 20 15 10 5 0 0.001 0.01 0.1 1 VCCA RESET COMPARATOR OVERDRIVE (V)
1326 G05
TRANSIENT DURATION (s)
40
VCC5 Threshold Voltage vs Temperature
4.750 VCC5 THRESHOLD VOLTAGE, VRT5 (V)
3.130 3.125 3.120 3.115 3.110 3.105 3.100 - 60 - 40 - 20
VCCA THRESHOLD VOLTAGE, VRTA (V)
VCC3 THRESHOLD VOLTAGE, VRT3 (V)
4.745 4.740 4.735 4.730 4.725 4.720 4.715 4.710 4.705 4.700 - 60 - 40 - 20 0 20 40 60 TEMPERATURE (C) 80 100
Reset Pulse Width vs Temperature
225 112.5
RESET PULSE WIDTH, tRST (ms)
220 215 210 205 200 195 190 - 50
110.0 107.5 105.0 102.5 100.0 97.5 95.0 - 50
PBR ASSERTION TIME TO RESET, tPB (SEC)
SOFT RESET PULSE WIDTH, tSRST (s)
- 25
50 25 0 TEMPERATURE (C)
4
UW
75
VCCA Transient Immunity
40 35 RESET OCCURS ABOVE CURVE TA = 25C 40 35 30 25 20 15 10 5
VCC3 Transient Immunity
RESET OCCURS ABOVE CURVE TA = 25C
0 0.001 0.01 0.1 1 VCC3 RESET COMPARATOR OVERDRIVE (V)
1326 G03
VCC3 Threshold Voltage vs Temperature
3.135
1.005 1.004 1.003 1.002 1.001 1.000 1.999 1.998 1.997 1.996
VCCA Threshold Voltage vs Temperature
0
20
40
60
80
100
TEMPERATURE (C)
1326 G07
1.995 - 60 - 40 - 20 0 20 40 60 TEMPERATURE (C)
80
100
1326 G08
1326 G09
"Soft" Reset Pulse Width vs Temperature
2.25 2.20 2.15 2.10 2.05 2.00 1.95
PBR Assertion Time to Reset vs Temperature
100
1236 G10
- 25
50 25 0 TEMPERATURE (C)
75
100
1236 G11
1.90 - 50
- 25
50 25 0 TEMPERATURE (C)
75
100
1236 G12
LTC1326
PIN FUNCTIONS
VCC3 (Pin 1): 3.3V Sense Input and Power Supply Pin for the IC. At least 1V must be applied to this pin for the RST to be in its guaranteed state. Bypass to ground with 0.1F ceramic capacitor. VCC5 (Pin 2): 5V Sense Input. VCCA (Pin 3): 1V Sense, High Impedance Input. If unused it can be tied to either VCC3 or VCC5. GND (Pin 4): Ground. RST (Pin 5): Reset Logic Output. Active high CMOS logic output, drives high to VCC3, buffered compliment of RST. An external pull-down on the RST pin will drive this pin high. RST (Pin 6): Reset Logic Output. Active low, open-drain logic output with weak pull-up to VCC3. Can be pulled up greater than VCC3 when interfacing to 5V logic. Asserted when one or more of the supplies are below trip thresholds and held for 200ms after all supplies become valid. Also asserted after PBR is held low for more than 2 seconds and for an additional 200ms after PBR is released. SRST (Pin 7): "Soft" Reset. Active low, open-drain logic output with weak pull-up to VCC3. Can be pulled up greater than VCC3 when interfacing to 5V logic. Asserted for 100s after PBR is held low for less than 2 seconds and released. PBR (Pin 8): Pushbutton Reset. Active low logic input with weak pull-up to VCC3. Can be pulled up greater than VCC3 when interfacing to 5V logic. When asserted for less than 2 seconds, outputs a soft reset 100s pulse on the SRST pin. When PBR is asserted for greater than 2 seconds, the RST output is forced low and remains low until 200ms after PBR is released.
BLOCK DIAGRAM
7A PBR 8
4.15V VCC5 2
25mV 25mV
VCC3 1 6A
VCCA 3
GND 4
REF
+
VCC3 INTERNAL
-
VCC3
+
-
+
-
+
-
+
+
-
-
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VCC3 6A 7 PBR TIMER SOFT RESET RESET SRST
VCC3
VCC3
200ms RESET GENERATOR
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RST
VCC3 5 RST
1326 BD
5
LTC1326
TI I G DIAGRA S
VCC Monitor Timing
VCCX VRTX tRST
RST PBR t < tPB tDB tSRST
1326 TD01
RST
SRST
APPLICATIONS INFORMATION
Operation The LTC1326 is a micropower, high accuracy triple supply monitoring circuit. The part has two basic functions: generation of a reset when power supplies are out of range, and generation of reset or a "soft" reset when the PBR is pulled low. Supply Monitoring All three VCC inputs must be above predetermined thresholds for 200ms before the reset output is released. The LTC1326 will assert reset during power-up, powerdown and brownout conditions on any one or more of the VCC inputs (assumes VCC3 1V). On power-up, before VCC3 reaches 1V, RST is pulled to a logic low of 0.4V or less. As long as any one of the VCC inputs is below its predetermined threshold, RST will stay a logic low. Once all of the VCC inputs rise above their thresholds, an internal timer is started and RST is released after 200ms. RST outputs the inverted state of what is seen on RST. RST is reasserted whenever any one of the VCC inputs drops below its predetermined threshold and remains asserted until 200ms after all of the VCC inputs are above their thresholds. On power-down, once any of the VCC inputs drop below its threshold, RST is held at a logic low. A logic low of 0.4V is guaranteed until VCC3 drops below 1V. The three precision voltage comparators internal to the LTC1326 have response times that are typically 13s. This slow response time helps prevent mistriggering due to transients on each of the VCC inputs. The part's ability to suppress transients can be improved by bypassing each of the VCC inputs with a 0.1F capacitor to ground. Pushbutton Reset The LTC1326 provides a pushbutton reset input pin. The PBR input has an internal pull-up current source to VCC3. If the PBR pin is not used it can be left floating. When the PBR is pulled low for less than tPB ( 2 sec), a narrow (100s typ) soft reset pulse is generated on the SRST output pin after the button is released. The pushbutton circuitry contains an internal debounce counter which delays the output of the soft reset pulse by typically 20ms. This pin can be OR-tied to the RST pin and issue what is called a "soft" reset. The SRST thereby resets the microprocessor without interrupting the DRAM refresh cycle. In this manner DRAM information remains undisturbed. Alternatively, SRST may be monitored by the processor to initiate a software-controlled reset. When the PBR pin is held low for longer than tPB ( 2 sec), a standard reset is generated. Once the 2 second period has elapsed, a reset signal is produced by the pushbutton logic, thereby clearing the reset counter. Once the button is released, the reset counter begins counting the reset period (200ms nominal). Consequently, the reset outputs remain asserted for approximately 200ms after the button is released. During a supply induced reset condition, the ability of the PBR pin to force a soft reset condition on the SRST pin is disabled. In other words SRST will remain high. If the PBR pin is held low, both during and after a supply induced reset (low RST), the RST pin will remain low until 200ms after the PBR goes high.
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Pushbutton Reset Function Timing
tPB
tRST
1326 TD02
LTC1326
APPLICATIONS INFORMATION
Dual and Single Supply Monitor Operation The VCC3, VCC5 and VCCA inputs may be individually disabled by the following techniques which allows the LTC1326 to be used as a dual or single supply monitor. The VCCA pin, if unused, can be tied to either VCC3 or VCC5. This is an obvious solution since the trip points for VCC3 and VCC5 will always be greater than the trip point for VCCA. The VCC5 input trip point is disabled if its voltage is equal to the voltage on VCC3 25mV and the voltage on VCC5 is less than 4.15V. In this manner the part will behave as a 3.3V monitor and the VCC5 reset will be disabled. The VCC5 trip point is reenabled when the voltage on VCC5 is equal to the voltage on VCC3 25mV and the two inputs are greater than approximately 4.15V. In this manner the LTC1326 can function as a 5V monitor with the 3.3V monitor disabled. When monitoring either 3.3V or 5V with VCC3 strapped to VCC5, (see Figure 1) the LTC1326 determines which is the appropriate range. The LTC1326 handles this situation as
LTC1326 3.3V OR 5V ADJUSTABLE SUPPLY R1 R2 1 2 3 4 VCC3 VCC5 VCCA GND PBR SRST RST RST 8 7 6 5
5V LTC1326
1326 F01
4.7k
SYSTEM RESET
Figure 1
5 VCC = VCC5 = VCCA = 0V TO 5V 4.7k PULL-UP FROM RST TO VCC3
ADJUSTABLE SUPPLY R1 R2
RST OUTPUT VOLTAGE (V)
4
1536 F03
3
2
1
0
0
1
3 4 2 SUPPLY VOLTAGE (V)
5
1326 F02
Figure 2. RST Voltage vs Supply Voltage
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shown in Figure 2. Above 1V and below VRT3, RST is held low. From VRT3 to approximately 4.15V the LTC1326 assumes 3.3V supply monitoring and RST is deasserted. Above approximately 4.15V the LTC1326 operates as a 5V monitor. Table 1 summarizes the state of RST and RST at various operating voltages with VCC3 = VCC5.
Table 1. Override Truth Table (VCC3 = VCC5)
INPUTS (VCC3 = VCC5 = VCC) 0V VCC 1V 1V VCC VRT3 VRT3 VCC 4.15V 4.15V VCC VRT5 VRT5 VCC RST -- 0 1 0 1 RST -- 1 0 1 0
Interfacing to 5V Logic The LTC1326 is powered internally from the VCC3 pin. In applications where the RESET signal is going to a 5V microprocessor, it is possible to have a case where the 5V supply is up and the 3.3V supply is at 0V. In this situation the LTC1326 doesn't have the drive capability to ensure a valid low on the RST pin. This is especially true if there is a pull-up resistor to VCC5. The circuit, Figure 3, will ensure proper assertion of system RESET to the 5V logic as long as either the 5V or 3.3V supply has at least 1V applied.
3.3V
1 2 3 4
VCC3 VCC5 VCCA GND
PBR SRST RST RST
8 7 6 5 4.7M HCT08 RESET
Figure 3. Triple Supply Monitor Interfacing to a 5V Microprocessor
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LTC1326
TYPICAL APPLICATIONS N
ADJUSTABLE SUPPLY OR DC/DC FEEDBACK DIVIDER
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Triple Supply Monitor (3.3V, 5V and Adjustable)
LTC1326 3.3V R1 5V 1 2 3 R2 4 VCC3 VCC5 VCCA GND PBR SRST RST RST 8 7 6 5 SYSTEM RESET
1326 TA03
Dual Supply Monitor (3.3V and 5V, Defeat VCCA Input)
LTC1326 3.3V 5V 1 2 3 4 VCC3 VCC5 VCCA GND PBR SRST RST RST 8 7 6 5
1326 TA04
SYSTEM RESET
LTC1326
TYPICAL APPLICATIONS N
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SRST Tied to RST and OR-Tying Other Sources to RST to Generate Reset and Reset
PUSHBUTTON 8 3.3V 4.7k SRST 7 RESET
LTC1326
PBR
6A
6A RST 6 VCC3 RST 5 RESET OTHER OPEN DRAIN RESET SOURCES OR-TIED TO RESET
1326 TA05
Using VCCA Tied to DC/DC Feedback Divider
2.9V LTC1435 VOSENSE 6 35.7k 1% 3.3V 2.8k 5V 1% 22.1k 1% LTC1326 1 2 3 4 VCC3 VCC5 VCCA GND PBR SRST RST RST
1326 TA06
8 7 6 5 SYSTEM RESET
ADJUSTABLE RESET TRIP THRESHOLD 2.74V
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LTC1326
TYPICAL APPLICATIONS N
Using the Short Pulse Width, Pushbutton Soft Reset Feature to Initiate Hard Reset
LTC1326 3.3V 5V 1 2 3 4 VCC3 VCC5 VCCA GND PBR SRST RST RST 8 7 6 5 RESET 40ns tP 10s
ADJUSTABLE SUPPLY OR DC/DC FEEDBACK DIVIDER
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PBR 20ms RST 200ms
1326 TA07
Triple Supply Monitor with 3.3V and 5V System Resets
3.3V 5V LTC1326 1 2 R1 R2 3 4 VCC3 VCC5 VCCA GND PBR SRST RST RST 8 7 6 5 TO 3.3V SYSTEM RESET TO 5V SYSTEM RESET Q1 2N7002
1326 TA08
LTC1326
PACKAGE DESCRIPTION
0.007 (0.18)
0.021 0.004 (0.53 0.01)
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254) 0- 8 TYP
0.016 - 0.050 0.406 - 1.270 *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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Dimensions in inches (millimeters) unless otherwise noted. MS8 Package 8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
0.118 0.004* (3.00 0.10) 8 76 5
0.192 0.004 (4.88 0.10)
0.118 0.004** (3.00 0.10)
1
23
4
0.040 0.006 (1.02 0.15)
0 - 6 TYP SEATING PLANE
0.006 0.004 (0.15 0.10)
0.012 (0.30)
0.025 (0.65) TYP
MSOP08 0596
S8 Package 8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 - 0.197* (4.801 - 5.004) 8 7 6 5
0.228 - 0.244 (5.791 - 6.197)
0.150 - 0.157** (3.810 - 3.988)
1
2
3
4
0.053 - 0.069 (1.346 - 1.752)
0.004 - 0.010 (0.101 - 0.254)
0.014 - 0.019 (0.355 - 0.483)
0.050 (1.270) TYP
SO8 0996
11
LTC1326
RELATED PARTS
PART NUMBER LTC690 LTC694-3.3 LTC699 LTC1232 LTC1536 DESCRIPTION 5V Supply Monitor, Watchdog Timer and Battery Backup 3.3V Supply Monitor, Watchdog Timer and Battery Backup 5V Supply Monitor and Watchdog Timer 5V Supply Monitor, Watchdog Timer and Pushbutton Reset Precision Triple Supply Monitor for PCI Applications COMMENTS 4.65V Threshold 2.9V Threshold 4.65V Threshold 4.37V/4.62V Threshold Meets PCI tFAIL Timing Specifications
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417 q (408) 432-1900 FAX: (408) 434-0507q TELEX: 499-3977 q www.linear-tech.com
1326F LT/TP 1197 4K * PRINTED IN THE USA
(c) LINEAR TECHNOLOGY CORPORATION 1997

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