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LT1671 60ns, Low Power, Single Supply, Ground-Sensing Comparator
FEATURES
s s
DESCRIPTIO
s s s s s s s s s
Low Power: 450A Fast: 60ns at 20mV Overdrive 85ns at 5mV Overdrive Low Offset Voltage: 0.8mV Operates Off Single 5V or Dual 5V Supplies Input Common Mode Extends to Negative Supply No Minimum Input Slew Rate Requirement Complementary TTL Outputs Inputs Can Exceed Supplies without Phase Reversal Pin Compatible with LT1394, LT1016 and LT1116 Output Latch Capability Available in 8-Lead MSOP and SO Packages
The LT (R)1671 is a low power 60ns comparator with complementary outputs and latch. The input common mode range extends from 1.5V below the positive supply down to the negative supply rail. Like the LT1394, LT1016 and LT1116, this comparator has complementary outputs designed to interface directly to TTL or CMOS logic. The LT1671 may operate from either a single 5V supply or dual 5V supplies. Low offset voltage specifications and high gain allow the LT1671 to be used in precision applications. The LT1671 is designed for improved speed and stability for a wide range of operating conditions. The output stage provides active drive in both directions for maximum speed into TTL, CMOS or passive loads with minimal cross-conduction current. Unlike other fast comparators, the LT1671 remains stable even for slow transitions through the active region, which eliminates the need to specify a minimum input slew rate. The LT1671 has an internal, TTL/CMOS compatible latch for retaining data at the outputs. The latch holds data as long as the LATCH pin is held high. Device parameters such as gain, offset and negative power supply current are not significantly affected by variations in negative supply voltage.
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S
s s s s s s s s
High Speed A/D Converters Zero-Crossing Detectors Current Sense for Switching Regulators Extended Range V/F Coverters Fast Pulse Height/Width Discriminators High Speed Triggers Line Receivers High Speed Sampling Circuits
TYPICAL APPLICATIO
5V 2k 1MHz CRYSTAL (AT-CUT)
Propagation Delay vs Overdrive
140 120 100 VS = 5V VSTEP = 100mV TA = 25C RL = 1M
1MHz Crystal Oscillator
TIME (ns)
80 FALLING EDGE (tPDHL) 60 40 20
+
2k LT1671 OUTPUT
-
2k 0.068F
1671 TA01 1671 TA01
0
U
RISING EDGE (tPDLH) 10 20 30 OVERDRIVE (mV) 40 50
1671 TA02
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1
LT1671
ABSOLUTE MAXIMUM RATINGS
Total Supply Voltage (V+ to V-) ............................... 12V Positive Supply Voltage ............................................. 7V Negative Supply Voltage .......................................... - 7V Differential Input Voltage ....................................... 12V Input and Latch Current (Note 2) ........................ 10mA Output Current (Continuous)(Note 2) ................. 20mA
PACKAGE/ORDER INFORMATION
TOP VIEW V+ 1 +IN 2 -IN 3 V- 4 8 7 6 5 Q OUT Q OUT GND LATCH ENABLE
ORDER PART NUMBER LT1671CMS8 MS8 PART MARKING LTCT
+IN 2 -IN 3 V- 4
MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 150C, JA = 250C/ W
S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150C, JA = 190C/ W
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. V + = 5V, V - = - 5V, VOUT(Q) = 1.4V, VLATCH = VCM = 0V unless otherwise noted.
SYMBOL VOS VOS T IOS IB VCMR CMRR PARAMETER Input Offset Voltage Input Offset Voltage Drift Input Offset Current
q
CONDITIONS RS 100 (Note 4)
q q
Input Bias Current Input Voltage Range (Note 6)
(Note 5)
q q q
Single 5V Supply Common Mode Rejection Ratio - 5V VCM 3.5V, TA > 0C - 5V VCM 3.3V, TA 0C Single 5V Supply 0V VCM 3.5V, TA > 0C 0V VCM 3.3V, TA 0C PSRR AV Power Supply Rejection Ratio Small Signal Voltage Gain 4.6V V + 5.4V - 7V V - - 2V 1V VOUT 2V
2
-
+
U
U
W
WW U
W
(Note 1)
Operating Temperature Range ................ - 40C to 85C Specified Temperature Range (Note 3) ... - 40C to 85C Junction Temperature ........................................... 150C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec.)................. 300C
TOP VIEW V+ 1 8 Q OUT 7 Q OUT 6 GND 5 LATCH ENABLE
ORDER PART NUMBER LT1671CS8 LT1671IS8 S8 PART MARKING 1671 1671I
MIN
TYP 0.8 4 10 120
MAX 2.5 4.0
UNITS mV mV V/C
100 150 280 350 3.5 3.5
nA nA nA nA V V dB dB dB dB dB dB V/V
-5 0 55 55 55 55 100
100 85 90 5000
q q
50 60 2500
LT1671
ELECTRICAL CHARACTERISTICS
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. V + = 5V, V - = - 5V, VOUT(Q) = 1.4V, VLATCH = VCM = 0V unless otherwise noted.
SYMBOL VOH VOL I+ I- VIH VIL IIL t PD1 t PD2 t PD t LPD t SU tH t PW(D) PARAMETER Output Voltage Swing High Output Voltage Swing Low Positive Supply Current
q
CONDITIONS 4.6V, IOUT = 400A V + 4.6V, IOUT = 4mA V+ IOUT = - 400A IOUT = - 4mA
q q q
MIN 2.7 2.4
TYP 3.1 3.0 0.3 0.4 450 75
MAX
UNITS V V
0.5 800 1000 200 250 0.8
V V A A A A V V nA ns ns ns ns ns ns ns ns ns
Negative Supply Current
q
LATCH Pin High Input Voltage LATCH Pin Low Input Voltage LATCH Pin Current Propagation Delay Propagation Delay (Note 7) Differential Propagation Delay (Note 7) Latch Propagation Delay (Note 8) Latch Setup Time (Note 8) Latch Hold Time (Note 8) Minimum Disable Pulse Width VLATCH = 0V VIN = 100mV, VOD = 20mV
q q q q
2 - 250 60 85 - 1000 80 110 100 130 30
VIN = 100mV, VOD = 5mV
q
VIN = 100mV, VOD = 5mV
15 60 - 15 35 30
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: This parameter is guaranteed to meet specified performance through design and characterization. It has not been tested. Note 3: The LT1671CS8 and LT1671CMS8 are guaranteed to meet specified performance from 0C to 70C and are designed, characterized and expected to meet these extended temperature limits, but are not tested at - 40C and 85C. The LT1671IS8 is guaranteed to meet the extended temperature limits. Note 4: Input offset voltage (VOS) is defined as the average of the two voltages measured by forcing first one output, then the other to 1.4V. Note 5: Input bias current (IB) is defined as the average of the two input currents. Note 6: Input voltage range is guaranteed in part by CMRR testing and in part by design and characterization.
Note 7: tPD and tPD cannot be measured in automatic handling equipment with low values of overdrive. The LT1671 is 100% tested with a 100mV step and 20mV overdrive. Correlation tests have shown that tPD and tPD limits can be guaranteed with this test, if additional DC tests are performed to guarantee that all internal bias conditions are correct. Propagation delay (t PD) is measured with the overdrive added to the actual VOS. Differential propagation delay is defined as: t PD = t PDLH - t PDHL Note 8: Latch propagation delay (t LPD) is the delay time for the output to respond when the LATCH pin is deasserted. Latch setup time (t SU) is the interval in which the input signal must remain stable prior to asserting the latch signal. Latch hold time (tH) is the interval after the latch is asserted in which the input signal must remain stable.
3
LT1671 TYPICAL PERFORMANCE CHARACTERISTICS
Gain Characteristics
5.0 4.5 4.0 OUTPUT VOLTAGE (V) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -3
50 60 100
TA = 125C TA = 25C TA = - 55C
TIME (ns)
TIME (ns)
-2 -1 1 2 0 DIFFERENTIAL INPUT VOLTAGE (mV)
Propagation Delay vs Input Overdrive
140 120 100 VS = 5V VSTEP = 100mV TA = 25C RL = 1M
TIME (ns)
TIME (ns)
200mV 120 100 80 STEP SIZE = 100mV
TIME (ns)
80 FALLING EDGE (tPDHL) 60 40 20
RISING EDGE (tPDLH)
0
10
20 30 OVERDRIVE (mV)
Input Offset Voltage vs Temperature
4 3 2
VOLTAGE (mV)
500
VS = 5V RL = 1M
INPUT BIAS CURRENT (nA)
400
1 0 -1 -2
300
VOLTAGE (V)
-3 -50 -25
50 0 75 25 TEMPERATURE (C)
4
UW
VS = 5V RL = 1M 3
1671 G01
Propagation Delay vs Load Capacitance
90
FALLING EDGE (tPDHL)
Propagation Delay vs Positive Supply Voltage
90
FALLING EDGE (tPDHL) 80 RISING EDGE (tPDLH) 70 V - = -5V VSTEP = 100mV VOD = 5mV TA = 25C RL = 1M 4.4 4.6 4.8 5.0 5.2 5.4 POSITIVE SUPPLY VOLTAGE (V) 5.6
1671 G03
80 RISING EDGE (tPDLH) 70 VS = 5V VSTEP = 100mV VOD = 5mV TA = 25C RL = 1M 0 10 20 30 40 OUTPUT LOAD CAPACITANCE (pF) 50
1671 G02
60
50
Propagation Delay vs Source Resistance
200 180 160 140
100
Propagation Delay vs Temperature
90 t PDHL t PDLH
VS = 5V RL = 1M VOD = 20mV TA = 25C
STEP SIZE = 800mV 400mV
80 70 60 50 40 30 20 10 VS = 5V VSTEP = 100mV VOD = 5mV RL = 1M
60 40
50
1671 TA02
40
0
5 10 SOURCE RESISTANCE (k)
15
1671 G05
0 -50 -25
50 0 75 25 TEMPERATURE (C)
100
125
1671 G06
Input Bias Current vs Temperature
6
VS = 5V RL = 1M
Positive Common Mode Limit vs Temperature
VS = 5V RL = 1M
5 4 3 2
200
VCM = -5V VCM = 0V
100
1
VCM = 3.5V
100
125
0 -50 -25
50 0 75 25 TEMPERATURE (C)
100
125
0 -50 -25
50 25 0 75 TEMPERATURE (C)
100
125
1671 G07
1671 G08
1671 G09
LT1671 TYPICAL PERFORMANCE CHARACTERISTICS
Negative Common Mode Limit vs Temperature
1 RL = 1M 0 VS = SINGLE 5V SUPPLY
INPUT VOLTAGE (V) 0.8 0.7 0.6 VOLTAGE (V) 0.5 0.4 0.3 0.2 TA = 25C TA = -55C TA = 125C VS = 5V VIN = 30mV OUTPUT VOLTAGE (V)
-1 -2 -3 -4 -5 -6 -50 -25 VS = 5V
50 0 75 25 TEMPERATURE (C)
Positive Supply Current vs V + Supply Voltage
0.6 0.5
3.5
V - = 0V VIN = -60mV IOUT = 0 CURRENT (mA)
CURRENT (mA)
CURRENT (A)
0.4 0.3 TA = 125C 0.2 0.1 0 TA = 25C TA = -55C
0
1
2
6 4 3 5 SUPPLY VOLTAGE (V)
Latch Pin Current vs Temperature
1.0 VS = 5V
0.8
CURRENT (A)
0.6
0.4
0.2
0 -50 -25
50 0 75 25 TEMPERATURE (C)
UW
100
1671 G10
Output Low Voltage (VOL) vs Output Sink Current
5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0 2 4 6 8 10 12 14
Output High Voltage (VOH) vs Output Source Current
VS = 5V VIN = -30mV TA = 125C TA = -55C TA = 25C
0.1 0
125
0
2
OUTPUT SINK CURRENT (mA)
1671 G11
4 8 6 10 12 OUTPUT SOURCE CURRENT (mA)
14
1671 G12
Positive Supply Current vs Switching Frequency
100
VS = 5V VSTEP = 50mV IOUT = 0 3.0 2.5 2.0 TA = 125C 1.5 1.0 TA = 25C 0.5 0 TA = -55C
Negative Supply Current vs V - Supply Voltage
V+ = 5V VIN = -60mV IOUT = 0
90
80
70
TA = 125C TA = 25C
60 TA = -55C 50 -8 -7 -6 -5 -4 -3 -2 -1 NEGATIVE SUPPLY VOLTAGE (V) 0
7
8
0.1
1 SWITCHING FREQUENCY (MHz)
10
1671 G14
1671 G13
1671 G15
Response to 15MHz 10mV Sine Wave
+IN 20mVP-P 10mV/DIV 3V Q OUT 1V/DIV 0V 50ns/DIV
1671 G17
100
125
1671 G16
5
LT1671 TYPICAL PERFORMANCE CHARACTERISTICS
tPD+ Response Time to 5mV Overdrive
1.4V 5mV +IN - 95mV Q OUT 5mV +IN - 95mV Q OUT
VS = 5V VOD = 5mV
20ns/DIV
1671 G18
PIN FUNCTIONS
V + (Pin 1): Positive Supply Voltage. Normally 5V. +IN (Pin 2): Noninverting Input. -IN (Pin 3): Inverting Input. V - (Pin 4): Negative Supply Voltage. Normally either 0V or - 5V. LATCH ENABLE (Pin 5): Latch Control Pin. When high, the outputs remain in a latched condition, independent of the current state of the inputs. GND (Pin 6): Ground. Q OUT (Pin 7): Noninverting Logic Output. This pin is high when +IN is above - IN and LATCH ENABLE is low. Q OUT (Pin 8): Inverting Logic Output. This pin is low when +IN is above - IN and LATCH ENABLE is low.
TI I G DIAGRA S
VOD
VIN
VIN tPD
VOUT
1671 TD01
6
UW W
tPD- Response Time to 5mV Overdrive
1.4V
0V
VS = 5V VOD = 5mV
0V 20ns/DIV
1671 G19
U
U
UW
U
LATCH ENABLE tSU VIN tPD VOUT
1671 TD02
tH
LT1671
APPLICATIONS INFORMATION
Common Mode Considerations The LT1671 is specified for a common mode range of - 5V to 3.5V on a 5V supply or a common mode range of 0V to 3.5V on a single 5V supply. A more general consideration is that the common mode range is 0V below the negative supply and 1.5V below the positive supply, independent of the actual supply voltage. The criterion for common mode limit is that the output still responds correctly to a small differential input signal. When either input signal falls below the negative common mode limit, the internal PN diode formed with the substrate can turn on, resulting in significant current flow through the die. An external Schottky clamp diode between the input and the negative rail can speed up recovery from negative overdrive by preventing the substrate diode from turning on. The zero crossing detector in Figure 1 demonstrates the use of a fast clamp diode. The zero crossing detector terminates the transmission line at its 50 characteristic impedance. Negative inputs should not fall below -2V to keep the signal current within the clamp diode's maximum forward rating. Positive inputs should not exceed the devices absolute maximum ratings nor the power rating on the terminating resistor.
RS 50 VIN 1N5712 RT 50 5V CABLE
+
LT1671
-
Figure 1. Fast Zero Crossing Detector
Either input may go above the positive common mode limit without damaging the comparator. The upper voltage limit is determined by an internal diode from each input to the positive supply. The input may go above the positive supply as long as it does not go far enough above it to conduct more than 10mA. Functionality will continue if the remaining input stays within the allowed common mode range. There will, however, be an increase in propagation delay as the input signal switches back into the common mode range.
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Input Bias Current Input bias current is measured with the output held at 1.4V. As with any PNP differential input stage, the LT1671 bias current flows out of the device. It will go to zero on an input which is high and double on an input which is low. LATCH Pin Dynamics The LATCH pin is intended to retain input data (output latched) when the LATCH pin goes high. The pin will float to a high state when disconnected, so a flow-through condition requires that the LATCH pin be grounded. The LATCH pin is designed to be driven with either a TTL or CMOS output. It has no built-in hysteresis. To guarantee data retention, the input signal must remain valid at least 35ns after the latch goes high (hold time), and must be valid at least - 15ns before the latch goes high (setup time). The negative setup time simply means that the data arriving 15ns after (rather than before) the latch signal is valid. When the latch signal goes low, new data will appear at the output in approximately 60ns (latch propagation delay). Measuring Response Time To properly measure the response of the LT1671 requires an input signal source with very fast rise times and exceptionally clean settling characteristics. The last requirement comes about because the standard comparator test calls for an input step size that is large compared to the overdrive amplitude. Typical test conditions are 100mV step size with 5mV overdrive. This requires an input signal that settles to within 1% (1mV) of final value in only a few nanoseconds with no ringing or settling tail. Ordinary high speed pulse generators are not capable of generating such a signal, and in any case, no ordinary oscilloscope is capable of displaying the waveform to check its fidelity. Some means must be used to inherently generate a fast, clean edge with known final value. The circuit shown in Figure 2 is the best electronic means of generating a fast, clean step to test comparators. It uses a very fast transistor in a common base configuration. The transistor is switched off with a fast edge from the generator and the collector voltage settles to exactly 0V in just a few nanoseconds. The most important feature of this
Q
Q
1671 F01
7
LT1671
APPLICATIONS INFORMATION
5V 0V -100mV 25 0.1F PULSE IN 0V -3V 50 400 750 -5V 130 2N3866 V1** 50 25 0.01F*
-5V
Figure 2. Response Time Test Circuit
circuit is the lack of feedthrough from the generator to the comparator input. This prevents overshoot on the comparator input, which would give a false fast reading on comparator response time. To adjust the circuit for exactly 5mV overdrive, V1 is adjusted so that the LT1671 output under test settles to 1.4V (in the linear region). Then V1 is changed by - 1V to set overdrive to 5mV. High Speed Design Techniques A substantial amount of design effort has made the LT1671 relatively easy to use. It is much less prone to oscillation than some slower comparators, even with slow input signals. However, as with any high speed comparator, there are a number of problems which may arise because of PC board layout and design. The most common problem involves power supply bypassing. Bypassing is necessary to maintain low supply impedance. DC resistance and inductance in supply wires and PC traces can quickly build up to unacceptable levels. This allows the supply line to move with changing internal current levels of the connected devices. This will almost always result in improper operation. In addition, adjacent devices connected through an unbypassed supply can interact with each other through the finite supply impedances. Bypass capacitors furnish a simple solution to this problem by providing a local reservoir of energy at the device, keeping supply impedances low.
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+
LT1671
Q
FET PROBE FET PROBE * TOTAL LEAD LENGTH INCLUDING DEVICE PIN. SOCKET AND CAPACITOR LEADS SHOULD BE LESS THAN 0.5 IN. USE GROUND PLANE ** (VOS + OVERDRIVE)/200
1671 F02
10k
-
Q 0.01F
Bypass capacitors should be as close as possible to the LT1671. A good high frequency capacitor such as a 0.1F ceramic is recommended, in parallel with a larger capacitor such as a 4.7F tantalum. Poor trace routes and high source impedances are also common sources of problems. Be sure to keep trace lengths as short as possible, and avoid running any output trace adjacent to an input trace to prevent unnecessary coupling. If output traces are longer than a few inches, be sure to terminate them with a resistor to eliminate any reflections that may occur. Resistor values are typically 250 to 400. Also, be sure to keep source impedances as low as possible, preferably 1k or less. About Level Shifts The LT1671's logic output will interface with many circuits directly. Many applications, however, require some form of level shifting of the output swing. With LT1671based circuits this is not trivial because it is desirable to maintain very low delay in the level shifting stage. When designing level shifters, keep in mind that the TTL output of the LT1671 is a sink-source pair (Figure 3) with good ability to drive capacitance (such as feedforward capacitors). Figure 4 shows a noninverting voltage gain stage with a 15V output. When the LT1671 switches, the baseemitter voltages at the 2N2369 reverse, causing it to switch very quickly. The 2N3866 emitter-follower gives a low impedance output and the Schottky diode aids current sink capability.
LT1671
APPLICATIONS INFORMATION
+V
OUTPUT = 0 +V (TYPICALLY 3V TO 4V)
1671 F03
Figure 3. Simplified LT1671 Output Stage
15V 1k 2N2369 LT1671 HP5082-2810 OUT 1k 12pF 1k
+ -
2N3866
15V
RISE TIME = 4ns FALL TIME = 5ns
Figure 4. Level Shift Has Noninverting Voltage Gain
Figure 5 is a very versatile stage. It features a bipolar swing that is set by the output transistor's supplies. This 3ns delay stage is ideal for driving FET switch gates. Q1, a gated current source, switches the Baker-clamped output transistor, Q2. The heavy feedforward capacitor from the
5V
+
INPUT LT1671
-
1N4148
4.7k
1000pF
0.1F
820
RISE TIME = 3ns FALL TIME = 3ns
Figure 5. Level Shift with Inverting Voltage Gain--Bipolar Swing
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LT1671 is the key to low delay, providing Q2's base with nearly ideal drive. This capacitor loads the LT1671's output transition, but Q2's switching is clean with 3ns delay on the rise and fall of the pulse. Figure 6 is similar to Figure 4 except that a sink transistor has replaced the Schottky diode. The two emitter-followers drive a power MOSFET that switches 1A at 15V. Most of the 7ns to 9ns delay in this stage occurs in the MOSFET and the 2N2369. When designing level shifters, remember to use transistors with fast switching times and high fT. To get the kind of results shown, switching times in the nanosecond range and an fT approaching 1GHz are required.
1k
1671 F04
+
LT1671
2N2369 2N3866
RL POWER FET 2N5160
-
1k 12pF
1k
1671 F06
RISE TIME = 7ns FALL TIME = 9ns
Figure 6. Noninverting Voltage Gain Level Shift
430 5V (TYP) 330
Q1 2N2907
HP5082-2810
5V OUTPUT -10V
Q2 2N2369 820
OUTPUT TRANSISTOR SUPPLIES (SHOWN IN HEAVY LINES) CAN BE REFERENCED ANYWHERE BETWEEN 15V AND -15V
1671 F05
-10V (TYP)
9
LT1671
APPLICATIONS INFORMATION
Crystal Oscillators Figure 7 shows a crystal oscillator circuit. In the circuit, the resistors at the LT1671's positive input set a DC bias point. The 2k-0.068F path sets up phase shifted feedback and the circuit looks like a wideband unity-gain follower at DC. The crystal's path provides resonant positive feedback and stable oscillation occurs.
5V 2k 1MHz TO 10MHz CRYSTAL (AT-CUT)
5V 1k
+
2k LT1671 OUTPUT
1k
-
2k
1671 F07
0.068F
Figure 7. 1MHz to 10MHz Crystal Oscillator
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Switchable Output Crystal Oscillator Figure 8 permits crystals to be electronically switched by logic commands. This circuit is similar to the previous examples, except that oscillation is only possible when one of the logic inputs is biased high.
XTAL X DX RX LOGIC INPUTS AS MANY STAGES AS DESIRED B XTAL A 1k A
XTAL B
1k
+
LT1671
D1
D2 OUTPUT
-
2k
1671 F08
75pF
= 1N4148 GROUND XTAL CASES
Figure 8. Switchable Output Crystal Oscillator. Biasing A or B High Places Associated Crystal in Feedback Path. Additional Crystal Branches Are Permissible
LT1671
PACKAGE DESCRIPTION
0.007 (0.18) 0.021 0.006 (0.53 0.015)
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
S8 Package 8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 - 0.197* (4.801 - 5.004) 8 7 6 5
0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254) 0- 8 TYP
0.016 - 0.050 0.406 - 1.270
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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Dimensions in inches (millimeters) unless otherwise noted. MS8 Package 8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
0.118 0.004* (3.00 0.102) 8 76 5
0.192 0.004 (4.88 0.10)
0.118 0.004** (3.00 0.102)
1 0.040 0.006 (1.02 0.15) 0 - 6 TYP SEATING PLANE 0.012 (0.30) 0.0256 REF (0.65) TYP
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4 0.034 0.004 (0.86 0.102)
0.006 0.004 (0.15 0.102)
MSOP (MS8) 1197
0.228 - 0.244 (5.791 - 6.197)
0.150 - 0.157** (3.810 - 3.988)
1 0.053 - 0.069 (1.346 - 1.752)
2
3
4
0.004 - 0.010 (0.101 - 0.254)
0.014 - 0.019 (0.355 - 0.483)
0.050 (1.270) TYP
SO8 0996
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LT1671
TYPICAL APPLICATION
4MHz Adaptive Trigger Circuit Line and fiber-optic receivers often require an adaptive trigger to compensate for variations in signal amplitude and DC offsets. The circuit in Figure 9 triggers on 2mV to 175mV signal from 100Hz to 4MHz while operating from a single 5V rail. A1, operating at a gain of 15, provides wideband AC gain. The output of this stage biases a 2-way peak detector (Q1 through Q4). The maximum peak is stored in Q2's emitter capacitor, while the minimum excursion is retained in Q4's emitter capacitor. The DC value of the midpoint of A1's output signal appears at the junction of the 500pF capacitor and the 3M units. This point always sits midway between the signal's excursions, regardless of absolute amplitude. This signal-adaptive voltage is buffered by A2 to set the trigger voltage at the
5V 2k
5V
+
A1 LT1227
-
13 2k 5V 36 750 510 Q3 15 14 12 11 10 Q4
0.005F 3M
10F
0.1F
100F
0.1F
2k 0.1F 470
INPUT Q1, Q2, Q3, Q4 = CA3096 ARRAY: TIE SUBSTRATE (PIN 16) TO GROUND = 1N4148
Figure 9. 4MHz Single Supply Adaptive Trigger. Output Comparator's Threshold Varies Ratiometrically with Input Amplitude, Maintaining Data Integrity over >85:1 Input Amplitude Range
RELATED PARTS
PART NUMBER LT1016 LT1116 LT1394 LT1720 DESCRIPTION UltraFastTM Precision Comparator 12ns Single Supply Ground-Sensing Comparator UltraFast Single Supply Comparator UltraFast Dual Single Supply Comparator COMMENTS Industry Standard 10ns Comparator Single Supply Version of LT1016 7ns, 6mA Single Supply Comparator Dual 4.5ns, 4mA Single Supply Comparator
UltraFast is a trademark of Linear Technology Corporation.
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
+
+ +
-
+
-
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LT1671's positive input. The LT1671's negative input is biased directly from A1's output. The LT1671's output, the circuit's output, is unaffected by > 85:1 signal amplitude variations. Bandwidth limiting in A1 does not affect triggering because the adaptive trigger threshold varies ratiometrically to maintain circuit output. Figure 10 shows operating waveforms at 4MHz. Trace A's input produces Trace B's amplified output at A1. The comparator's output is Trace C.
A = 10mV/DIV B = 50mV/DIV
C = 1mV/DIV
50ns/DIV
3 Q1 2 6 1 5 4 Q2 3M 0.005F 500pF 5V A2 LT1006
1671F10
Figure 10. Adaptive Trigger Responding to a 4MHz, 5mV Input. Input Amplitude Variations from 2mV to 175mV Are Accommodated
470
LT1671
TRIGGER OUT
1671 F09
1671F LT/TP 0499 4K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1998

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