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PMC-Sierra, Inc.
REFERENCE DESIGN
PMC-960552 ISSUE 1
PM5948 DART-BOARD
S/UNI - DUAL ATM REFERENCE TRANSCEIVER BOARD
PM5948 S/UNITM
155-DUAL
DART BOARD S/UNI-DUAL ATM REFERENCE TRANSCEIVER BOARD
Issue 1:
January, 1997
PMC-Sierra, Inc.
105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 (604 )415-6000
PMC-Sierra, Inc.
REFERENCE DESIGN
PMC-960552 ISSUE 1
PM5948 DART-BOARD
S/UNI - DUAL ATM REFERENCE TRANSCEIVER BOARD
PMC-Sierra, Inc.
105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 (604 )415-6000
PMC-Sierra, Inc.
REFERENCE DESIGN
PMC-960552 ISSUE 1
PM5948 DART-BOARD
S/UNI - DUAL ATM REFERENCE TRANSCEIVER BOARD
CONTENTS 1. 2. OVERVIEW...............................................................................................................1 DART board IMPLEMENTATION.........................................................................2 2.1. Important implementation principles ...........................................................2 2.2. Block diagram..................................................................................................2 2.3. Power supply and ground layers .................................................................3 2.4. Optical line side interface ..............................................................................3 2.5. ALOS+/- inputs ................................................................................................4 2.6. Interfacing TXD+/- outputs.............................................................................6 2.7. RXD+/- inputs...................................................................................................7 2.8. REFCLK +/- 19.44 MHz inputs......................................................................8 2.9. Drop side 50 MHz FIFO bus..........................................................................9 2.10. Drop side microcontroller interface ...........................................................11 2.11. Decoupling for Intrinsic Jitter on the DART board..................................11 DESIGN CONSIDERATIONS...............................................................................11 3.1. When do you use PECL/ECL instead of TTL/CMOS? .............................11 3.2. What are the main concerns of using PECL over ECL?.........................12 3.3. What PECL termination scheme is the best to use?................................12 3.4. How to convert the S/UNI-DUAL CMOS outputs to PECL levels? ........15 3.5. What can be done to minimize power supply transient voltages?.........16 3.6. What values should the decoupling capacitor be?...................................17 3.7. Where should the decoupling capacitors be placed?..............................18 3.8. What can be done to minimize ground noise?..........................................18 3.9. What to do with unused (CMOS) inputs? ...................................................18 3.10. Is it necessary to isolate the analog from the digital? ............................19 3.11. Should one isolate the transmit analog from the receive analog?.....19 3.12. How to isolate analog from digital and transmit from receive? ............19 3.13. How does layout affect high speed return current?................................20 3.14. When should ferrite beads be used?........................................................20 3.15. Is it necessary to de-couple every power pin of the S/UNI-DUAL?.....21 3.16. Loop filter using ceramic capacitors..........................................................21
3.
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PMC-Sierra, Inc.
REFERENCE DESIGN
PMC-960552 ISSUE 1
PM5948 DART-BOARD
S/UNI - DUAL ATM REFERENCE TRANSCEIVER BOARD
3.17. Loop filter using polarized tantalum capacitors ......................................23 3.18. How to drive the REFCLK inputs using one oscillator?.......................24 3.19. How accurate should the on board reference clock be?.......................30 3.20. CMOS vs. TTL terminology?.......................................................................31 4. ACCESSING the DART board .............................................................................32 4.1. DART board via DART Interface Card to SCI-PHY Mother Board .........32 4.2. Drop side loop-back .......................................................................................32 PM5348 S/UNI-DUAL............................................................................................33 5.1 S/UNI-DUAL register address map ..............................................................34
5.
APPENDIX A: PCB LAYOUT NOTES ..........................................................................1 A.1. Background.....................................................................................................1 A.2. Trace Impedance Control.............................................................................1 A.3. Routing.............................................................................................................3 APPENDIX B: DART board DROP SIDE CONNECTOR PINOUT...........................1 APPENDIX C: MECHANICAL DRAWINGS.................................................................1 APPENDIX D: DART board PARTS LIST....................................................................1 APPENDIX E: 4.7F Ceramic Multilayer X5R and X7R Capacitor Sources.........1 APPENDIX F: SCHEMATICS........................................................................................1 APPENDIX G: SCHEMATIC COMPONENT CROSS REFERENCE ......................1 APPENDIX H: SCHEMATIC SIGNAL CROSS REFERENCE .................................1 APPENDIX I: PCB ARTWORK .......................................................................................1 APPENDIX J: REFERENCES........................................................................................1 CONTACTING PMC-SIERRA ........................................................................................1
_____________________________________________________________________________________________ ii
PMC-Sierra, Inc.
REFERENCE DESIGN
PMC-960552 ISSUE 1
PM5948 DART-BOARD
S/UNI - DUAL ATM REFERENCE TRANSCEIVER BOARD
1. OVERVIEW The DART board is a 6 layer PCB subassembly that contains two PM5348 S/UNI-DUAL IC's, 19.44 MHz crystal oscillator clock reference, power supply decoupling, fiber optic transceiver devices and a 140 pin drop-side system connector. These devices are typically used to implement the core of an ATM user Network Interface. Each PM5348 contains two logical ATM interfaces, and therefore the DART board has a total of four such ATM SONET/SDH interfaces. The board also contains the optical serial fiber transceivers. For normal operation, the optical RX/TX fiber and the 140-pin edge connector (to the local P controller, and the drop side assembly/disassembly SAR) are required. Fig. 1 DART board overview * P controller * Power input * ATM SAR (DROP SIDE)
DUAL DART BOARD DUAL
SONET/SDH Fiber (LINE SIDE)
This 6 layer PCB contains two S/UNI-DUAL PM5348 chips. On the line side, each S/UNI-DUAL processes two, full duplex ATM packed, SONET/SDH 155 Mbit/s STS-3c/STM-1, or 51.8 Mbit/s (STS-2) data streams. This gives four logical ATM devices, each operating up to 155 Mbit/s in both receive and transmit directions for a board aggregate full duplex rate of 622 Mbit/s. The line side requires a stable 19.44 MHz (or 6.48 MHz for STS-2) reference clock to both PM5348 ICs. Clock jitter must be carefully controlled and, depending on the design, special attention must be given to buffers, propagation delays, clock skew, power supply decoupling, trace impedance and termination. The drop side provides a Saturn a Compliant Interface - PHYsical layer (SCIPHY) 16-bit Rx and 16 bit Tx bus. It may be clocked up to 50 MHz for an aggregate parallel transfer bandwidth of 800 megabits (16 bits x 50 MHz) in both receive and transmit directions. Configuration, control and status monitoring of the two S/UNI-DUAL chips is accomplished via the 140 pin connector using an 8-bit microcontroller on the external motherboard controller.
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REFERENCE DESIGN
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PM5948 DART-BOARD
S/UNI - DUAL ATM REFERENCE TRANSCEIVER BOARD
2. DART board IMPLEMENTATION 2.1. Important implementation principles To reduce digital and analog power/ground noise on the DART board, a multi-layer PCB with three ground planes is required. This simplifies design and reduces time to market. The 19.44 MHz reference TTL (not PECL) oscillator is buffered with a 74FCT541. A series transmission line termination method was used to reduce drive current and system noise. Transmission line traces of 75 characteristic impedance are implemented for the 19.44 Mhz reference clock. A compromise between 50 and 100 so that the traces are wide enough to be repeatable in manufacturing, and also have a high enough Zo to keep currents as low as possible. The connections used for the 155.52 Mbit/s PECL data, between the DUAL and the PMD, are wider 50 traces. 2.2. Block diagram Fig. 2 DART board block diagram
DART BOARD PM5948
Status
Loop Filter R's & C's
20 pin
PHY - 3 Ctrl
S/UNI-DUAL
PM5348
* four direct PHY controls * external Reference 19.44mHz * external FIFO clock (50mhz) * 16 bit RX & TX FIFO Bus PHY -2 Ctrl 8-bit uP I/F 100 pin
Loop Filter R's & C's
Tx/Rx [15:0] * generic 8-bit micro I/F * external RESET * +5VDC power, & Ground 20 pin ATM DATA BUS PHY - 1 Ctrl
Rs= 27
Loop Filter R's & C's
Zo
PM5348
PHY - 0 Ctrl S/UNI-DUAL
Loop Filter R's & C's
* *
* *
Optical I/F
Optical I/F
Status details for 75 * - see75 controlled TTL to PECL far end parallel terminations impedance trace #1 Component side trace layer #2 TX Ground Plane labeled as 'TA' on the shematics #3 Digital Ground Plane labeled 'D' on the schematics #4 +5VDC Power Plane labeled as 'Vcc' on the shematics #5 RX Ground Plane labeled as 'RA' on the schematics Six Layer PCB #6 Solder side trace layer ( discrete components)
all three ground planes shorted at the connector
2
4 SONET/SDH OC-3
* *
* *
Optical I/F
Optical I/F
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PM5948 DART-BOARD
S/UNI - DUAL ATM REFERENCE TRANSCEIVER BOARD
2.3. Power supply and ground layers The power supply is carefully distributed via power and ground planes. One power plane supplies the digital circuits directly and ferrite series elements are used to generate the other analog supplies. In addition, there are three separate ground planes that originate from the main drop side connector: Digital ground (D), line side Transmit Analog Ground (TA) and line side Receive Analog Ground (RA). To optimize jitter tolerance, the separate ground planes isolate the noisy digital circuits (grounds) from the more sensitive analog receive and transmit blocks. Fig. 3 Power and ground distribution
*
Power Connector
100F Bulk +
** *
10F Bulk + +
*
Ferrite
Vcc (digital power) Layer #4 Analog Power
*
* * * Ferrite
* *
.1F plus 10nF caps
* * * Analog Power
.01F caps
Star Ground Distribution
.1F plus 10F 10nF Bulk caps
* *
* *
* *
TA (Transmit Ground -Layer #2) D (Digital Ground - Layer #3) RA (Receive Ground -Layer #5)
2.4. Optical line side interface The serial line side utilizes four PMD (Physical Media Device) Optical Transceiver modules. The receive optics are connect directly to the S/UNI-DUAL RXD+/- inputs. To ensure that there is a clock in the absence of optical input, the signal detect (SD) output of the optics is connected to the ALOS- input of the S/UNI-DUAL (the ALOS+ input is grounded). In normal operation (good incoming signal) the S/UNI-DUAL device recovers the clock from the incoming data. In a loss of signal condition, the S/UNIDUAL will squelch the data on the receive data (RXD+/-) pins and the phase lock loop will switch to the reference clock (19.44 MHz) to keep the recovered clock in range. This technique guarantees that the S/UNI-DUAL will generate a SONET LOS indication if the Optical Transceiver loses optical input.
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The transmit line interface consists of the S/UNI-DUAL CMOS transmit outputs which are AC-coupled, attenuated, terminated, level shifted and fed into the transmit optics. Optical transceivers having a standard 9-pin duplex SC receptacle are used. In non-loop timed mode, the 155.52 MHz transmit clock source is synthesized from the local 19.44 MHz oscillator and the 155.52 MHz receive clock is recovered from the incoming data. 2.5. ALOS+/- inputs The S/UNI-DUAL analog Loss Of Signal inputs are designed to accept inputs from either a single ended PECL , balanced differential PECL, or single ended TTL or CMOS voltage source. These are true differential inputs, and they sense the difference between the inputs. Grounding the ALOS+ input, causes the ALOS- to be a single ended TTL threshold input. The 3.7V bias is derived internally from power and ground. Since SD (Signal Detect output from Optical Transceiver) is not a high speed signal, it's important, but not critical, that power and ground be in common and noise free with the PMD (Optics or UTP-5 I/F module). TTL threshold level gates are also added and the equivalent input structure looks like this: Fig. 4 ALOS block diagram
S/UNI-DUAL
3K Signal Detect (SD) from a Optical or UTP-5 PMD 121(80) ALOS119(82) ALOS+ 3.7Vdc TTL Level input buffer 1 0
** **
3K 3.7Vdc
3.7Vdc threshold differential PECL RXVR
MUX 1 S
2 TTL Level input buffer
These inputs would typically receive very slow changing signals. You would not expect SD (Signal Detect outputs from the optical PMD) to be changing a lot during normal operation. If ALOS is asserted, it means there is something drastically wrong with the signal source, (e.g. fiber loop is cut). ALOS a DC function and hence this signal must not be AC coupled. Also since the SD source is not high speed, the ALOS inputs do not require transmission line controlled impedance traces or termination schemes. Also connected to these input pins are two gates with their input thresholds set to traditional TTL levels. That is, a low is less than 0.8 V and a high is greater than 2V. To operate the inputs as a single ended TTL threshold inputs, the ALOS+ input must be grounded and the ALOS- pin must be connected to the TTL SD output. In this case, TTL gate #2 detects a logic low at ALOS+ and selects the '1' input which comes from ALOS-.
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When operating with PECL, the PECL signal is always >2.0 VDC. Therefore, the TTL gate #2 selects the MUX input '1', which comes from the differential PECL RXVR. a) Interfacing a single ended PECL SD output (most common) If the source of SD is a single ended PECL voltage level, then the ALOS+ must be AC coupled to RA (Receive Analog Ground, Layer #5) via a 0.01 F capacitor, and the SD is connected to the ALOS- input, with the appropriate 330 PECL pulldown close to the PMD. Notice that the PMD's analog signal detector output is labeled as SD (Signal Detect). The DUAL's input is labeled ALOS (Analog Loss Of Signal). These have inverse logic labels. However, a logic high means that there is sufficient signal level, and a logic low, means that the input signal is too low. Fig. 5 ALOS- driven from a single ended PECL source PMD SD PECL levels 330 0.01F S/UNI-DUAL ALOSALOS+
RA (Receive Analog Ground)
b) Interfacing to a TTL level SD output A PMD (OPTICS or UTP-5 interface) device with a single ended TTL level SD output can be connected as shown below. Fig. 6 ALOS- driven from a TTL source PMD SD S/UNI-DUAL ALOSALOS+ =RA=Receive Analog Ground
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c) Interfacing differential PECL SD outputs Notice that both pins are internally self biased to 3.7 Vdc via a 3K source impedance. The PECL inputs are high-Z CMOS differential structures. A PMD with traditional two PECL outputs can be connected as shown with 330 pulldowns close to the PMD to bias the PECL drivers. Fig. 7 ALOS driven from a differential PECL source PMD SD+ PECL SD330 RA (Receive Analog Ground) 2.6. Interfacing TXD+/- outputs TXD+/- are high speed data outputs running at 155.52 Mbit/s at worst case. If the data is alternate ones and zeros, a 77.26 MHz signal will result. TXD and RXD are the fastest signals on the board and proper attention must be taken to minimize jitter. Fig. 8 TXD driving a PMD with PECL inputs ALOS+ S/UNI-DUAL ALOS-
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The 237 ohm and 50 ohm resistors reduce the 5 Vp-p TXD to a safe 800 mVp-p PECL level. Ceramic 0.01F capacitors are used to AC couple and level shift these CMOS output to proper PECL levels. The transmission line effects are addressed with a 50 ohm PCB trace and the 50 Zo terminating resistors. The terminating 50 resistors are terminated into a locally generated Vbb of 3.7 Vdc. 2.7. RXD+/- inputs RXD+/- are high speed data inputs running at 155.52 Mbit/s at worst case. If the data is alternate ones and zeros, a 77.26 MHz signal will result. RXD and TXD are the fastest signals on the board and proper attention must be taken to minimize jitter. These inputs should be driven with a balanced PECL source. The S/UNI-DUAL has differential RXD inputs with common mode rejection. The DC bias voltage for these inputs is internally set to 3.7 Vdc, through a Thevenin 3K impedance. These resistors are tied to the power R1AVD1 and ground R1AVS1 pins. Hence, noise on these power pins may alter the 3.7 switching bias point. Proper decoupling of this supply is important for optimum jitter tolerance. Also, these PECL inputs have to be AC coupled else the 3.7V DC bias will be affected. Fig. 9 RXD block diagram
S/UNI-DUAL
3.7Vdc
3K
RXD RXD+
3K
* *
3.7Vdc
3.7Vdc threshold differential PECL RXVR
The DART board incorporates an HP optical PMD with PECL level RXD outputs. The following points were observed: 1) Bias the PECL outputs with 330 resistors to ground 2) Route the signal to the DUAL along proper PCB traces: * controlled trace impedance, 50 on the DART board * no vias or no sharp turns 3) 100 resistor termination between the two signals close to the DUAL. 4) AC couple to RXD+/- with 0.01uF ceramic high frequency capacitors. 5) Decouple R1AVD1 to R1AVS1 as shown with a series ferrite and capacitors Cx (two capacitors in parallel, 0.1 F with 0.01 F).
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Fig. 10 Terminating RXD PECL signal
Vcc=+5V
DART BOARD
0.01F
*
Optical PMD
Zo=50
Rt=2*Zo=100
*
Cx
Ferrite
*
RXD+ R1AVD1
DUAL
RXD-
*
330
Zo=50
*
0.01F RA
*
R1AVS1
*
RA
*
2.8. REFCLK +/- 19.44 MHz inputs The DUAL reference clock inputs are different than in the S/UNI-LITE PM5346. The DUAL IC has programmable inputs. You can drive these with either a two wire PECL or a single ended TTL or CMOS source. These inputs have the same input structure as the DUAL ALOS+/- inputs. A PECL two wire signal can be connected between REFCLK+ and REFCLK-. Or, TTL input mode can be selected by grounding REFCLK+. A TTL low input to TTL gate #2 forces the MUX to select the output of TTL gate #1. Fig. 11 REFCLK input block diagram
3.7Vdc
* ** *
TTL Level input buffer 1 0 3.7Vdc threshold differential PECL RXVR MUX 1 S
3K 112 REFCLK111 REFCLK+
*
S/UNI-DUAL
2 TTL Level input buffer
The DART board utilized a TTL (vs. PECL) 20ppm oscillator and a 74FCT541 high speed single ended TTL buffer. Fast slew rate FCT buffer is required to reduce clock jitter. A source series termination of 27 was used to DC drive the 75 ohm transmission line. The REFCLK+ is strapped to ground to enable single ended REFCLK- operation.
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Fig. 12 REFCLK as implemented on the DART board
TAVS1 TAVS2 REFCLK+
TTL Buffer 74FCT541 19.44Mhz TTL Oscillator Rs=27 Zo=75
DUAL #1
REFCLK-
Rs=27
Zo=75
REFCLKREFCLK+ TAVS2 TAVS1 DUAL #2
= TA - Transmit Analog Ground
2.9. Drop side 50 MHz FIFO bus The drop side refers to the parallel FIFO Receive and Transmit data bus and its associated handshake control signals as shown below: The FIFO RFCLK and TFCLK clock can be 50 MHz and can present careful timing and termination design to ensure error free operation. Please refer to the data sheet for detail timing information. Please note the output electrical specs and that driving a DC termination load of 50 or even 100 is not possible. Series source terminations of about 27 could be used or if timing permits (ie. clock speeds slower than 50 MHz), a bus driver could be used for driving off-board. Fig. 13 Drop side - PHY Interface block diagram
DART BOARD
16-bit TX FIFO bus 16-bit RX FIFO bus DUAL #1
SAR
RX & TX control (RCA, TCA, RSOC,TSOC, RRDENB, RFCLK,TFCLK) DUAL #2
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The associated drop side PHY bus timing is illustrated below. For complete detailed timing information, please refer to the S/UNI-DUAL, PM5348 Data Book, PN# PMC950919. Fig. 14 Multi-PHY mode timing 16-bit, TX FIFO near empty option
**** **** **** ****
XX XX W1 W2 XX W3
TFCLK TWRENBn TCAn TSOC1 TDAT[15:0] TXPRTY[1:0]
**** ****
W(n-4)
W(n-3)
W(n-2)
W(n-1)
W(n)
W1
Fig. 15 Multi-PHY Mode Timing, 16-bit, receive FIFO empty and Tristate options
RFCLK RRDENB1 RRDENB2 RCA1 RCA2 RSOC1 RDAT[15:0] RXPRTY[1:0]
W1 W2
**** **** **** **** **** **** **** ****
W(n-1) W(n) W1 W2 W3 W4
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2.10. Drop side microcontroller interface The S/UNI-DUAL powers up in a 'basic' default state and is ready to receive and transmit ATM cells. A microprocessor is required if one requires the ability to read or write to the internal status or control registers. Please refer to the PM5348 data sheet for P interface specifications. Relative to the RXD+/-, or the drop side FIFO interface, this is a slow bus and normal digital design rules should be followed. Fig. 16 DART board P interface
DART BOARD
8-bit data bus
P
control (RD, WR, A[8:0], RST, INTB, RSTB) Decode CS1 CS2
DUAL #1
DUAL #2
2.11. Decoupling for Intrinsic Jitter on the DART
board
To optimize intrinsic jitter on this reference design, it is beneficial to decouple the 5 Vdc power pins, TAVD1 and TAVD2 as shown in the enclosed schematics. A series ferrite is required with a 1.0F Tantalum in parallel with a 0.01F ceramic decoupled to their respective analog ground pins, RAVD1 and RAVD2. 3. DESIGN CONSIDERATIONS
3.1. When do you use PECL/ECL instead of TTL/CMOS? The faster the digital signal, the faster the technology one must use (implies fast slew rates also) to maintain data integrity. Also, the longer the traces, the more reliable the transmission technology required. The S/UNI-DUAL is a mixed mode CMOS semiconductor with high speed analog and digital circuits. Since PECL/ECL is more complex and expensive to use, it should be used only where necessary. In normal short distance layouts the 19.44 MHz REFCLK can be a single ended TTL or CMOS type as long as transmission line design rules are adhered to. Controlled impedance traces with proper termination are recommended. The RXD and TXD signals must be PECL due to the speed and jitter integrity.
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3.2.
What are the main concerns of using PECL over ECL?
As ECL uses the upper rail of the supply as the reference for the I/O and internal switching, a negative supply with the ground being the reference is a natural choice, as it is easier to keep the ground plane quieter than the power rail. Since ECL requires a negative power supply and most designers mixing TTL/CMOS with ECL only want a single supply, PECL (positive ECL) became a common choice. PECL operates the same as ECL but now has the noisier +5 Volt rail as the reference. PECL devices are differential; the noise on the inputs will be common mode noise and will not affect a differential input, but it will affect the internal reference, especially if the power supplying the transmitting device is not in common with the receiver. The S/UNI-DUAL RXD and REFCLK are differential inputs with common mode rejection. These inputs will decode a voltage difference between the input, and not with respect to ground. However the DC bias voltage is internally set to 3.7 Vdc through a Thevenin 3K impedance. These resistors are tied to the power R1AVD1 and ground R1AVS1 pins. Hence, noise on these power pins may alter the 3.7 switching bias point. Proper decoupling of this supply is important to optimize jitter tolerance. Also, these PECL inputs have to be AC coupled, otherwise the 3.7V DC bias will be affected.
3.3. What
PECL termination scheme is the best to use?
"Termination" applies to terminating a signal propagating down a transmission line to the characteristic impedance of line. If the line is not terminated to its characteristic impedance, there will be reflection back down the line. The amount of reflection at the load (receiver) is given by the load reflection coefficient: L = (RT - Zo)/(RT + Zo) where RT is the load impedance and Zo is the characteristic impedance of the line. The amount of reflection at the source (transmitter) is given by the source reflection coefficient: S = (RS - Zo)/(R S + Zo) where RS is the source impedance and Zo is the characteristic impedance of the line. The reflected signal propagates back and forth until the "ringing" dies out. There are 4 basic types of terminations used for PECL (or ECL): Open line termination, series termination, parallel termination, and Thevenin parallel termination. Since PECL (or ECL) signals only drive high, external biasing is need to pull the PECL signal low. This biasing has to be incorporated into the termination scheme.
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Unterminated lines (open line) should only be used for very short line lengths (less than 1/4 of an inch), or for low frequency signals. An unterminated line is shown below with resistor Re used to pull the PECL signal low: Fig. 17 Unterminated transmission line
The maximum unterminated line length is given by the following equation : L max = 0.5 * ( (CD / CO)2 + (tR / TPD)2 ) - CD / CO) where L = line length, tR = rise time, TPD = propagation delay per unit length, CO = capacitance per unit length, and CD = the distributed capacitance. The above equation assures that the undershoot will be limited to 15% of the full logic swing. Series terminated lines can be used when the interconnect distances are long or there are discontinuities in the characteristic impedance lines. A series resistor at the output of the driver reduces the voltage swing of the logic signal in half. The 1/2 amplitude signal propagates down the transmission line. At the end of the characteristic impedance line, the voltage doubles since the reflection coefficient is unity due to the unterminated line. The half amplitude swing along the transmission line reduces crosstalk, but if the distance between the end of the transmission line and the receiver input is not kept short as in Lmax above, the reflection is added to the signal and propagates back to the transmitter. A series terminated line is shown below where Rs + Zint//Re must equal Zo. Fig. 18 Series terminated transmission line
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Parallel terminated lines offer the best terminations for speed and power consumption. The receiver end of the transmission line terminates and biases the signal. The terminating resistor is the same value as the characteristic impedance of the transmission line. Unfortunately this requires another voltage supply as the terminating voltage (VT) is Vcc - 2 Volts. A parallel terminated line is shown below where RT equals Zo: Fig. 19 Parallel terminated transmission line VT
Thevenin terminated lines terminate the lines to the characteristic impedance and sets the terminating (VT) voltage. A Thevenin equivalent parallel termination is shown below: Fig. 20 Parallel Thevenin terminated transmission line
VT
The resistors R1 and R2 in parallel must equal Zo and the voltage at the input must pull the output of the transmitting gate to Vcc - 2 Volts. Working out the equations for Zo = 50 and PECL Vcc +5 Volt supply gives: R2 = 2.5 * Zo R1 = R2*2/3
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Note that the above examples show only one of the differential inputs. With the Thevenin termination care must be taken so that the Vcc and grounds of the differential signals are taken in close proximity of each other or the noise on Vcc and ground will not be in common with each other. Since the S/UNI-DUAL's PECL (pseudo ECL) inputs are internally self-biased, a hybrid of the parallel termination can be used which has minimum current draw and the terminating voltage (VT) is not required. By AC-coupling into the S/UNI-DUAL, the S/UNI-DUAL sets the internal switching threshold. A resistor 2 is placed between the differential outputs at the terminating end as shown below to terminate the line: Fig. 21 S/UNI-DUAL RXD driven by PECL PMD
0.01 F Out + PECL Transmiter
*
Re 330
Zo
*
2*Zo
RXD +
S/UNI-DUAL
Out -
*
Re 330
Zo
*
0.01 F
RXD -
The Re 330 resistors are placed close to the drivers and are required to properly bias the PECL output structures since PECL drives high only. 3.4. How to convert the S/UNI-DUAL CMOS outputs to PECL levels? The S/UNI-DUAL high speed CMOS outputs have to be AC-coupled, attenuated, level shifted and terminated into a PECL optical transmitter input. This can be done with a CMOS to PECL converter like a Motorola MC10H352, however a more cost effective way is shown below:
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Fig. 22 DUAL's TXD driving PECL input PMD
0.01 F TXD+ 237 5Vp-p S/UNI-DUAL 0.01F TXVD_AC 92 R1 237 Vcc Vbb 0.01F R2 680 237 TXD0.01 F Rs Zo= 50 TA Zo 50 Optical Transmiter Rs Zo= 50 Vcc PMD
*
TD+
* TXVS_AC 97 *
*
Ferrite
0.1F TA
*
*
Zo 50
800mVp-p differential
5Vp-p
*
TD-
The TxD+/- outputs are AC-coupled and then the series resistor Rs is used to attenuate the CMOS levels to PECL levels. The Vpp input (voltage requirement of PECL input) swing is given by the equation below with Rout (approximately 25 ohms) being the output impedance of the S/UNI-DUAL drivers. For Vpp = 800 mVolts of swing, Rs is approximately 240 ohms. Vpp = (Zo/((Rs + Rout) + Zo)*Vcc The Vbb voltage (3.7 volts for PECL) is generated by a voltage divider network which is set to the switching threshold of the optical transmitter: Vbb = Vcc* R2/(R2 + R1) 3.5. What can be done to minimize power supply transient voltages? High current draw during IC switching causes power supply transients I due to the inductance of the power lines. Large voltages appear on the power rails due to the transient current flowing through these power line inductances. The magnitude of the noise voltage can be reduced by minimizing the inductance of the power lines and by decreasing the magnitude of the transient currents. The power line inductance can be minimized by using a power plane. The transient currents on the power rails can be minimized by supplying the power from an alternate source such as a decoupling capacitor near the circuit that is drawing the current.
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The decoupling capacitance and the inductance of the wiring between the capacitor and the power pin determines the noise voltage at the power pin. Bulk decoupling capacitors are used to supply the bulk DC current, and the high frequency decoupling capacitors are used to supply all the transient current that is required when the circuit is switching. 3.6. What values should the decoupling capacitor be? The bulk decoupling value should be 10 times the value of all the decoupling capacitance combined and should be located where the power comes in. Capacitors with low internal inductance should be used such as a tantalum electrolytic. Stay away from aluminum electrolytic as their inductances are an order of magnitude larger than the tantalum capacitor. A ferrite bead (or 1 to 10 H inductor) can be used before the bulk capacitor to keep the power supply transient noise from entering the circuit. The power pin decoupling capacitor must be able to supply all the switching current. The minimum capacitance can be calculated by: C = I * t/V The transient voltage drop V in the supply voltage is caused by the transient current I occurring over time t. Using decoupling capacitors that are too large should be avoided. Since all capacitors have some inductance in series with the capacitance there will be a self-resonance at a certain frequency. Above this frequency, the inductor's impedance will increase, the effective impedance of the capacitor will increase and thus high frequency decoupling will suffer. The selfresonant frequency is given by the equation: 1 f= 2 LC For decoupling a particular frequency, the lower the capacitor's impedance (Xc) at resonance, the better. Due to the capacitor's self inductance (XL), the effective impedance of the capacitor (XCeff) is: 1 + 2fL XCeff = XC + XL = 2fC 0.1F due to XC resonance Frequency Note that the larger the capacitance (for the same inductance) the lower the resonant frequency. If the capacitor is too large, the self-resonance will be too low to be an effective bypass but if the capacitor is not large enough, there will be insufficient current to supply the transient current during switching. The smallest value capacitor to satisfy the above equations should be used. It is rarely necessary that a capacitor larger than 0.01 F be used.
17
0.01F due to X L
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3.7. Where should the decoupling capacitors be placed? The decoupling capacitor should be placed as close to the IC power pin as possible reduce the wiring inductance. IF there are two capacitors like 1.0uF and 0.01uF, place the 0.01uF closest to the pins. Ideal placement for an SMT device is on the component side at the pins, where trace length and even vias are eliminated. There are 5 sources of inductance: the inductance of the capacitor, the inductance of the wiring between the capacitor and the IC power pin, the power pin lead inductance inside the IC, the ground pin lead inductance inside the IC, and the ground inductance between the IC pin and ground. The capacitor inductance is negligible if the correct capacitor is used. There is no control over the lead frame inductance. To keep the inductance low, both the power lead and the ground lead should be keep as short as possible (less than 1.5 inches). The inductance for a trace is given by: L= 0.005 In(2h/w) H/inch where In is the inverse log, h is the height between power or ground lead and the ground plane and w is the width of the power or ground lead. Note that doubling the width of the trace or reducing h will only decrease L approximately by 20 %, but decreasing the length by 50% will decrease the inductance by 50%. A typical board has about 15 nH of inductance per inch. 3.8. What can be done to minimize ground noise? Return currents and power supply transients during high current consumption produce most of the ground noise. Since ground noise cannot be controlled by decoupling capacitors, the only way to minimizing the effect of ground noise is to minimize ground impedance and design circuits as to minimize currents. The best way to minimize ground impedance is to use a ground plane. It is not advisable to use ferrite beads in the ground path as this will inhibit the return currents from leaving and raise the ground noise level. This is a problem since TTL and CMOS logic are referenced to ground. 3.9. What to do with unused (CMOS) inputs? All unused inputs should be connected to their inactive state to prevent unintentional switching which produces noise generation and power consumption. For the CMOS inputs the inactive low state can be connected to ground and the inactive high state can be connected to the power rail (Vcc) through a series resistor (4.7k).
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3.10. Is it necessary to isolate the analog from the digital? Yes. The digital CMOS circuits have high immunity to external noise (approximately 0.3 * Vcc) whereas a small amount of external noise coupled into the analog circuits can be devastating. The analog circuits operate on low voltage swings (600 mVolts for the S/UNI-DUAL PECL inputs) as compared to the large (5 Volt) of the CMOS inputs. The CMOS circuits can also generate a lot of switching noise, especially when a large number of circuits are running synchronously all timed to the same system clock. If the analog power and grounds are not isolated from each other it is unlikely that the device will be able to do clock and data recovery without any bit errors. 3.11. Should one isolate the transmit analog from the receive analog?
Yes. Any noise on the S/UNI-DUAL receive analog power and ground inputs or on the PECL inputs will impact the internal PLL's ability to recover the clock from the incoming data. Added noise will degrade jitter tolerance and add jitter to the recovered clock. It is also important to keep the analog optical receiver in common with the receiver portion of the S/UNI-DUAL, especially the grounds. The S/UNIDUAL PECL inputs are differential and will reject common mode noise. However, they are internally self-biased between Vcc and ground (about 3.7 Vdc) and therefore must be AC-coupled. This 3.7V reference must be stable with reference to the incoming signal so that the switching threshold does not move and thus cause bit data jitter. It is especially important to keep the ground plane between the optical receiver in common with the RAVS1 & RAVS2 inputs of the S/UNI-DUAL. Ideally, any transmission trace should be routed directly over top of it's respective ground plane. On the transmit side of the S/UNI-DUAL, a 155.52 MHz clock is synthesized from a 19.44 MHz reference clock. Any added noise on the power or ground inputs impacts the resulting 155.52 MHz clock. The added noise will increase the intrinsic jitter of the transmitter. The power and ground of the optical transmitter can be in common with the analog transmit power and ground of the S/UNI-DUAL. 3.12. How to isolate analog from digital and transmit from receive? The DART board has three separate grounds, one for digital, one for analog 155.52 Mbit/s transmit , and one for the high speed analog receive. All three grounds are shorted together at the main connector. Digital +5 power is Vcc and is used directly with some local 0.1 uF decoupling. The other analog +5 power supplies are derived with series ferrites and local decoupling to the appropriate Transmit (TA)or Receive (RA) analog grounds. It is very important to keep the TX of the optics on the same ground as the DUAL. The same goes for the RX ground plane since the DUAL RXD internal 3.7V reference is derived from power and ground.
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One of our previous reference designs used cuts (channels ) in the power/ground planes to isolate currents. This is more difficult to control and to predict the final results. Using this method, several PCB revisions may be required to achieve the optimum end result. 3.13. How does layout affect high speed return current? At low speeds return current follows the path of least resistance back to the driver. At high speeds, however, the return current follows the path of least inductance which lies on the plane directly under the signal trace, as the total loop area between the outgoing and returning paths is minimized. In other words, the highspeed return current follows a path that is almost the "mirror image" of the signal trace on the plane underneath the trace. This tight coupling provides good flux cancellation so that common-mode current is reduced. Therefore, high speed traces should not cross cuts or heavily perforated areas (where tight spacing through-hole components reside) on the power and ground planes, as any cuts on these planes may interrupt the return currents, causing them to seek alternative paths back to the driver. The different routes taken by the outgoing and return currents will both induce common-mode noise on other nearby signal traces. In addition, by routing high speed signals over continuous power planes, the return current paths of these signals are known and other signals will not cross over these return currents, reducing the possibility of noise coupling. Detailed discussions on high-speed design are provided by the references. 3.14. When should ferrite beads be used? Ferrite beads are mainly used on power rails to pass DC current but to attenuated the higher frequency noise that is riding on the DC rail. The impedance of ferrite beads increases with frequency. At DC the ferrite bead is like a short, but at higher frequencies, the impedance of a ferrite bead can increase to over 100 ohms (depending on the bead and frequency). Ferrite beads attenuate high frequency noise from the power supply from getting into a circuit, but they also stop high frequency noise from leaving the circuit. It is important, therefore, to use proper bypass decoupling when using ferrite beads. Ferrite beads should be avoided on CMOS I/O power pins as the high current switching of the CMOS circuits causes a I/t noise to be introduced into the power rail. Ferrite beads should also be avoided on the ground bus as this inhibits the return currents. Ferrite beads can be used on the S/UNI-DUAL analog power pins as they draw very little current. The ferrite beads isolate all the receive inputs from each other. As the noise frequencies and levels are different in every design, it is hard to decide if beads are necessary and at what frequency should they be effective. However, it is harder to insert a ferrite bead after the board is built than it is to short out the bead if it is not needed.
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The S/UNI-DUAL analog power pin RAVD2 generates a 311 MHz oscillation. If there is no ferrite bead on this input, the 311 MHz signal can get into the other analog power pins and performance can be affected. Ferrite beads can be used on the optical receiver as the receiver portion draws very little current. Ferrite beads can also be used on the optical transmitter power rails as the transmitter drives a differential PECL pair which draws constant current. Most optical module vendors recommend using ferrite beads on both the receive and transmit power rails. PECL (ECL) circuits draw constant current regardless of the frequency of operation as opposed to CMOS, which only draws current during switching. The DUAL does not have true PECL drivers, they are CMOS matched complimentary drivers. There will always be one of the two drivers turned on, and there will be a constant current drawn through the power pins. 3.15. Is it necessary to de-couple every power pin of the S/UNI-DUAL? The S/UNI-DUAL can generate a lot of simultaneous synchronous and asynchronous switching noise. Especially if the drop side clock frequencies of the transmit and receive are synchronous and both logical devices are operational. It is important to decouple every power pin so as to reduce self generated noise and also prevent this noise from coupling onto the other planes and power pins.
3.16. Loop filter using ceramic capacitors The internal op-amp in the S/UNI-DUAL's clock recovery unit (CRU) regenerates a 155.52 MHz clock from the incoming SONET data. NOTE: the component values below are provisional. The capacitors (C1, C2) determine the amount of "peaking" in the jitter transfer curve. The capacitor C1 should be non-polarized because when the S/UNI-DUAL is held in reset, it is reverse-biased at approximately 2.0 VDC. Also, for some process extremes, the capacitors may operate with a DC. reverse-bias of up to 1.0 VDC. In addition, under normal operating conditions, when the PLL is locked, the LF+ pin will be at about +1.0 VDC average. Since the S/UNI-DUAL is a terminating device, the loop filter values were chosen to achieve maximum jitter tolerance performance in the LAN application. C1 and C2 should be of a temperature stable Ceramic X7R or X5R (X=55C, 5=+85C, 7=+125C, and R = 15% capacitance variation over this temperature). The X5R and X7R devices are available in initial tolerance of 20%, 15%, 10% and are available in 6.3V, 10V, 16V, 25V or 50V. Y5V and Y5U should be avoided as these ceramics exhibit poor temperature tolerance for this application.
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Fig. 23 Clock recovery loop filter using ceramic X5R capacitors
RAVD2
RXD+/RRCLK+/-
Phase/Freq Detector
Prefilter
OpAmp
VCO
recovered clock
LF+ LFRAVD2 R2 C2 R1 C1 RE RAVS2 LFO
on-chip off-chip
RAVS2
2N3904
Line Rate (Mbit/s) 155.52
R1 (1%) 68.1
R2 (1%) 200
C1, C2 (X5R, 20%) 4.7 F
RE (1%) 100
Table 1:
Recommended Component Values
Please see Appendix E for capacitor vendor details. A few suggested manufacturers of X5R and X7R ceramic capacitors are: Manufacturer PN# Taiyo Yuden LMK316BJ475ML Taiyo Yuden EMK325BJ475MN TDK CC1206JX5R475K PHILIPS 2220RR475K8AB0C AVX SM015C475KAJ240 Prestidio 3736X7R475K1NT91A Vitramon VJ2225Y475KXXAT
F 4.7 4.7 4.7 4.7 4.7 4.7 4.7
Type X5R X5R X5R X7R X7R X7R X7R
VDC 10V 16V 6.3V 25V 50V 25V 25V
Footprint 1206 (0.12" by .10") 1210 (0.12" by .10") 1206 (0.12" by .06") 2220 (0.22" by .20") 3230 (0.32" by .30") 3736 (0.37" by .36") 2225 (0.22" by .25")
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3.17. Loop filter using polarized tantalum capacitors Due to footprint requirements, or sourcing constraints, two polarized Tantalum capacitors connected in series may be a more desirable option. Either back to back (-'ve to -'ve) or anode to anode (+'ve to +'ve) may be used to form one non-polar capacitor. Since the effective capacitance will be halved, two 33 F capacitors must be used to form one 15 F (actually 16.5 F) non-polar capacitor. Since the LF+ pin will always have a positive DC bias (about +1 Vdc when in lock), C2 may be a single polarized capacitor with the positive terminal connected to the LF+ pin. However, C1 is made up of a series combination of C1a and C1b as shown in the schematic below. AVX corporation publishes several articles on back to back tantalums. The capacitor C1 should be non-polarized because when the S/UNI-DUAL is held in reset, the capacitor C1 could be reverse-biased up to approximately 2.0V. Also, for some process extremes, this capacitor may operate with a dc reverse-bias of up to 1.0 Vdc. Fig. 24 Clock recovery loop filter with tantalum polarized capacitors
RAVD2
RXD+/RRCLK+/-
Phase/Freq Detector
Prefilter
OpAmp
VCO
recovered clock
LF+ R2 LFR1 RAVD2 LFO
on-chip off-chip
RAVS2
+
C2
+ +
C1a C1b
2N3904
RE
RAVS2
Line Rate (Mbit/s) 51.84
R1 (1%) 68.1
R2 (1%) 200
C2 (Tantalum, 20%, ) 15 F
C1a & C1b (Tantalum, 20%, F) 33 F
RE (1%) 100
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3.18. How to drive the REFCLK inputs using one oscillator? The REFCLK , 19.44 MHz clock input block diagram is show below. These inputs can be driven with balanced AC coupled PECL source. Or if you ground REFCLK+, you can drive the REFCLK- with a single ended TTL gate. In this case the clock must be less than 0.4V for a low and 2V or more for a logic high. Fig. 25 Block diagram of DUAL's REFCLK inputs
3.7Vdc
* ** *
TTL Level input buffer 1 0 3.7Vdc threshold differential PECL RXVR MUX 1 S
3K 112 REFCLK111 REFCLK+
*
S/UNI-DUAL
2 TTL Level input buffer
In most applications it's more cost effective or technically desirable to supply a single ended 19.44 MHz reference clock. Generally, PECL clocks are very expensive and if you don't have to route the clock source a great distance a TTL/CMOS device is more than adequate, provided you design with care. Fig. 26 Ideal reference clock
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Fig. 27 Reference clock potential problems
Noise Overshoot Transmission Line Reflection Thresholds Slow dv/dt Undershoot
v
t Ideal low intrinsic jitter is required if you use the 'non-loop time' mode TX clocking. However, even in loop-time mode, the fall-back is the reference clock if the RX clocking is lost due to a loss of RX clock. For non-loop time, whatever method you decide to use, please ensure that there is minimum jitter generated in the 155.52 MHz TX clock. As shown in the diagram above, ensure that you provide a low noise, free of jitter, properly terminated, minimum over/undershoot reference. If it's a single ended clock, then attention must be paid to routing, termination, supply noise, and grounding. Since the PLL multiplies the reference clock by 8 to derive 155.52 it also multiplies any jitter at the input. So, jitter of 1.0 ns at the input is only 2% of the 19.44 MHz reference. However the output 155.52 MHz TX clock will have the same 1 ns jitter but now it's 1 ns/6.4 ns = 15% jitter. As shown below, the system designer has several choices in clock generation and distribution. In all cases, to optimize intrinsic jitter, power supply decoupling is required. Note the larger 1.0 uF caps on TAVD1 and TAVD2. Please mount capacitors, especially the 0.01 uF, right at the pins. Fig. 28 Decoupling REFCLK power pins
Vcc
Ferrite
Vcc
Ferrite
Vcc
Ferrite 1uF .01uF
** *
TAVD1
TAVS1
.1uF
* * *
TTL/CMOS OSCILLATOR
*
.1uF
*
buffer if required
Vcc
TA
Ferrite
SUNIDUAL
REFCLK-
transmission line & coupling components
.01uF
*.01uF
1uF .01uF
*
TA
* * *
TA
TAVD1
TA
*
TAVS2 REFCLK+
TA = Transmit Analog Ground Plane
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a) Series source termination The series termination may be the most desirable as it offers the lowest current consumption by the drivers, virtually zero current in the signal trace, and zero ground return currents. Therefore, the least amount of board noise to interfere with the analog circuitry. We chose trace Zo = 75 because trace widths are easily manufacturable, and Rs is large enough and not swamped by the buffer source Z. The DART board incorporates the FCT541 circuit below. The FCT541 was chosen as it has faster rise time compared to 74ACT541 or 74F541. Fig. 29 REFCLK using series termination with two loads
TTL buffer with about 50 source Z FCT541 TTL or CMOS OSCILLATOR
Zo=75
111 REFCLK+ TA
SUNI-DUAL PECL INPUTS
Rs
25
112 REFCLK-
very short traces
TA
to another S/UNI-DUAL
Fig. 30 REFCLK using series source termination and one load
111 REFCLK+ TA TTL or CMOS OSCILLATOR
Zo=75 SUNI-DUAL PECL INPUTS
Rs
25
112 REFCLK-
TA The REFCLK+ signal must be connected to the TA (Transmit Analog Ground) and the signal source must be properly terminated. Also, very carefully decouple TAVD1 to TAVS1 and TAVD2 to TAVS2 as per schematic. Do not substitute/remove ferrites or capacitors.
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Grounding the REFCLK+, internally turns off the PECL 3.7 Vdc threshold inputs, and enables the TTL level threshold (low = less than 0.8 V and high = more than 2.0V) gates. The TTL oscillator should be placed as close to the buffer as possible as it is unterminated. The reason for using the TTL oscillator is to match the 74FCT541's TTL input level. A CMOS oscillator connected to these TTL inputs will cause duty cycle distortion on the output clock as TTL and CMOS signals switch at different thresholds. At the input thresholds, the edges must be sharp and free of noise, etc. When a different oscillator and buffer pair is used, it is important to match the output level of the oscillator to the input level of the buffer in order to avoid duty cycle distortion. Notice the FCT541 has TTL input thresholds (0.4V and 2V) and CMOS level outputs. As on our DART board, series terminations may be the best choice since it offers the lowest power consumption, and the least amount of noise generated into the circuit. The buffer(s) is driving into a high impedance load hence the current will be almost zero except for current required due to stray capacitance (gate input capacitance). The source impedance must match the Zo of the trace. This source impedance is the sum of both the driver gate impedance and Rs, the external resistor. In our case we chose Rs = 25 with trace Zo = 75 . Careful check at the destination with a scope will assure the proper Rs selected. Make sure the inputs don't see any jitter or steps especially at the TTL input gate thresholds. If you only have one DUAL on your PCB, then a buffer chip like the FCT541 is not required and you can use the oscillator to drive the Rs (source series resistor) directly. If you have multiple destinations it's a good idea to use multiple drivers with their own Rs. Multi drop is not recommended with the same driver as reflections will be a serious problem, depending on the trace length. If you have only one Analog ground plane and multiple isolation cuts as in the SORD (S/UNI-LITE) reference design, then more careful attention must be placed to the routing and ground returns. b) Parallel termination at the load using TTL thresholds In the DUAL if you ground the REFCLK+ pin, the REFCLK- becomes a TTL threshold single ended input. Parallel termination may be used. However, the driver must be able to drive the necessary current into the far end Rt termination. At Zo = 50 , Rt must be 50 and thus the current is 5V/50= 100 mA. This will generate a lot of noise due to the driver switching, trace and ground return currents and is not recommended. To halve the drive current, you could use Rt with Zo traces =100. But in practice, these are thin (0.008" wide) traces and may be difficult to manufacture reliably. Driving multiple loads is not recommended due to high current demands for this type design.
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Fig. 31 Driving a 50 Ohm parallel termination load
N RE OT CO
V=2.4 to 5Vp-p
TTL or CMOS OSC. TA Zo=50
M
M
EN
DE
S/UNI DUAL
D
Rt
REFCLKREFCLK+
50
current =48 to 100 mA
TA
c) Parallel termination with DUAL's PECL input thresholds To reduce drive current, thus lower power and noise, it may be better to utilize the PECL thresholds of the REFCLK inputs. Care must be taken not to over load the DUAL inputs past the power rails. Simply decouple the REFCLK+ to TA (Transmit analog Ground) with a 0.01 uF cap and drive the REFCLK- with an AC coupled 800 mV clock. Here the current is 1/3 of method b) above. Fig. 32 Parallel termination using DUAL's PECL inputs
TTL or CMOS OSC. TA
Too M 800mVVp-p & Cu any Co mpo rren t is T n 2.4 to 5Vp-p oo H ents igh
Rs=100 Zo=50 Rt 50 0.01F
S/UNI DUAL REFCLK-
current = 16 to 33 mA
TA
REFCLK+
Rs(min) =
Rt[Vo(min) - Vi(min)] Vi
In this case, for a 50 transmission trace, Rt = 50 , Vi(min), & Vo(min)= 2.4V, Rs = 100 . The maximum current , if Vo(max)=5V, would only be about 5V/150 = 33 mA. The signal at the DUAL would be about 5V x 50/150 = 1.67 Vp-p max. If the TTL output was only 2.4 Vp-p ( as per worst case spec), then the current max = 16 mA and the input would be 800 mVp-p. For Zo = 100 , Rt = 100 , then Rs = 200
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d) Multidrop parallel termination with PECL load One may be tempted to connect the one clock trace to two different devices and terminate at the far end. The concern is that the transmit and receive grounds could be isolated by channels cut into the ground plane. Potential difference between the grounds will affect one of the reference clock inputs. For example, if the reference clock is terminated to the ground of one device, the other device will get a less than ideal signal. A second problem may arise if the clock signal trace crosses the cuts in the ground plane (i.e. from transmit ground island to receive ground island). In that case, ground return current from the receive side cannot follow the signal trace back to the driver. Instead, it will seek an alternative path of least inductance. Consequently, this ground current will induce common-mode noise on signals nearby. One solution may be to run a 50 ohm clock trace to the vicinity of the two inputs and then split into two 100 ohm traces. There will be no Zo discontinuity at the junction of the 50 and the two 100 traces. The two 100 traces will look like a 50 trace since they are in parallel. The following diagram illustrates this solution: Fig. 33 Multidrop parallel termination of the REFCLK
10 nF REFCLK+ 100 100 Ohm 50 Ohm 100 Ohm 100 10 nF REFCLKS/UNI 10 nF DUAL REFCLK+ 10 nF S/UNI DUAL REFCLK-
CMOS OSC
= TA=
Transmit Analog Ground
The drawback of the above solution is that, based on the layer setup described in Appendix F, the width of an 100 Ohm trace is less than 3 mil. This width may be difficult for board manufacturer to fabricate accurately. Inaccuracy in trace impedance will cause the signals to be improperly terminated. e) PECL oscillator This is the most expensive method but least risky in terms of layout and possible noise. As shown above, we've used single ended TTL in most of our reference designs with no adverse effects as long as careful attention is placed at design and layout stages. Use PECL drivers (or PECL Oscillator) if long traces are required, especially, if the clock is on a different board in your system.
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Fig. 34 PECL oscillator driving long traces into REFCLK
50 Ohm Zo PECL OSC RE 330 RE 330 Transmit Analog Ground Zo 50 Ohm 10 nF REFCLKS/UNI DUAL REFCLK+ 10 nF
100 2*Zo
TA
TA=
f) PECL oscillator driving two PECL single ended loads Another alternative uses a single PECL source clock to drive two different PECL inputs. A PECL driver has two outputs , the +'ve and -'ve. Use the PECL oscillator 'out+' to drive one DUAL's REFCLK- , while the REFCLK+ is decoupled to ground with a 0.01F capacitor. The PECL oscillator 'out-' is connected to the other DUAL's REFCLK-. Appropriate terminations are required in each case. PECL oscillators tend to be more expensive than the combined costs of a TTL oscillator and a buffer. is required. However, if the traces are long, or off-board, a good choice would be a PECL oscillator and PECL buffers if there are multiple loads. 3.19. How accurate should the on board reference clock be? The on board reference clock is required to provide an alternative timing reference in the event that the primary timing reference becomes unavailable. For example, if the network equipment (NE) is configured for line timing mode in which the transmitted signals are timed from the clock derived from the received signal, the alternative timing reference allows the NE to provide the capability to switch to the secondary clock if the incoming signal becomes unsuitable to derive the clock from. For interfacing between WAN equipment, or between private and public ATM equipment, the Bellcore specification GR-CORE-253, Issue 2, Dec. 2,1995, Section 5.4.1 , requires the accuracy of the on board reference clock to be +/- 20 ppm or better. In an interface between private ATM user devices and private ATM network equipment, the ATM Forum specification "ATM PHYsical Medium Interface Specification for 155 Mbit/s over Twisted Pair Cable", version 1.0 Ballot Draft, 1994, requires the transmitter at the ATM user device to have a free-running transmit reference clock at 155.52 Mbit/s with an accuracy of +/- 100 ppm or better. In the DART board design, a TTL 19.44 MHz oscillator is used as a reference from which the 155.52 Mb/s is generated without loss of clock accuracy. Some of the vendors that provide these 19.44 MHz oscillators are listed below:
30
PMC-Sierra, Inc.
REFERENCE DESIGN
PMC-960552 ISSUE 1
PM5948 DART-BOARD
S/UNI - DUAL ATM REFERENCE TRANSCEIVER BOARD
Vendor
Motron Industries 605-665-9321 Connor Winfield 708-851-4722 K&L Oscillatek Champion 708-451-1000 Oak Frequency Control Group 717-486-3411 Ecliptek 714-433-1200 Table 3: 19.44 MHz 3.20. CMOS vs. TTL terminology?
+/-20ppm or better Yes Yes Yes Yes Yes No
+/-100ppm Yes Yes Yes Yes Yes Yes
Oscillator Vendors
TTL vs. CMOS terminology may be a little confusing due to the evolution of the naming convention. Even though these refer to semiconductor family types, it's the voltage levels of the logic highs and lows that are important. Their speed in the application is also relevant. The letter 'T' in the device prefix usually means that the IC's input thresholds are set at the traditional levels. That is a zero will be decoded if the voltage is lower than 0.4 volts. And a logic high will be decoded if the input detects 2.0 volts or more. The letter 'C' in the prefix means that the device outputs will switch from Vss to Vcc power rails (typically zero to 5 volts depending on loading). TTL is not guaranteed to drive past 2.4V and a pull may be required if interfacing to other types of logic like PECL or CMOS. Relative Speed & Slew Rate 74C541 74LS541 74S541 74HC541 74F541 74FCT541 slowest slower slow faster fast fastest DEVICE EXAMPLES TTL Level CMOS CMOS Outputs Level Outputs Hi>2.4V High = 5V Inputs 1/2 Low<0.8V Vcc Yes Yes Yes No No Yes No No Yes Yes Yes Yes No No Yes Yes No Yes TTL Level Inputs Hi > 2.0V Low <0.4V No Yes Yes No Yes Yes
31
PMC-Sierra, Inc.
REFERENCE DESIGN
PMC-960552 ISSUE 1
PM5948 DART-BOARD
S/UNI - DUAL ATM REFERENCE TRANSCEIVER BOARD
We chose to use the 74FCT541 since it has the fastest output slew rate, low power, TTL inputs and drives to the rails. 4. ACCESSING the DART board 4.1. DART board via DART Interface Card to SCI-PHY Mother Board The arrangement below was used to test the functionality of the DART board. The SCI-PHY motherboard is a standard PMC-Sierra controller that allows access to the DART board's DUAL IC registers and. This motherboard also incorporates SAR functionality which provides a means of transmitting and receiving ATM cells via the SCI-PHY 16-bit bus. At 50 MHz FIFO clock, this motherboard is capable of servicing all four logical PHY devices running at 155.52 Mbits/s (OC-3) line rates. The DART Interface Card was specially designed for the DART board to allow for connector pinout differences, power input, and to allow for simple drop side digital loop back, as outlined below in the next section. Fig. 35 Testing the DART board DART Interface Card DART BOARD Optic Fiber
RS-232 In-House Test Motherboard
Loopback Control
4.2. Drop side loop-back The Interface Card provides capability for drop-side digital loop back of one PHY device at a time. Any one of the PHY RX FIFO stream can be routed to any one of the four TX FIFOs. Because we wanted to run the 16-bit bus at 50 MHz, we could not tolerate gate delays. A simple mechanical loop back jumper connector shorts out the RX 16 -bit PHY bus to the TX bus. A mechanical switch selects which PHY is the FIFO source, and another switch selects the destination PHY. Only one PHY is the source and one PHY is the destination at any one time. The SCI-PHY motherboard can be connected to the Interface Card at all times in order to be able to configure and monitor the PHY Devices.
32
PMC-Sierra, Inc.
REFERENCE DESIGN
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PM5948 DART-BOARD
S/UNI - DUAL ATM REFERENCE TRANSCEIVER BOARD
An external Line Bit Error tester generates SONET ATM cells and drives them into the optical Input. The RX FIFO cells are routed back to the TX FIFO through the jumper block. The PHY device then transmits the cells back to the Bit Error Tester via the optical transceiver. Fig. 36 Drop side loop-back DART Interface Card Digital Data Loopback Jumper Block 4 PHY logical devices DART BOARD
SCI-PHY Mother Board
Optic Fiber
Bit error tester
one PHY device at a time 5. PM5348 S/UNI-DUAL For electrical, mechanical and register details, please refer to the S/UNI-DUAL PM5348 Data Sheet available either from your local PMC-Sierra Inc. Representative or from our Web Page at: http://www.pmc-sierra.com The PM5348 Dual User Network Interface (S/UNI-DUAL) is a monolithic integrated circuit that implements SONET/SDH processing and ATM mapping functions for two 155 Mbit/s or 51 Mbit/s ATM User Network Interfaces. It is fully compliant with SONET and SDH requirements and ATM Forum User Network Interface specifications. The S/UNI-DUAL is software configurable, allowing feature selection without changes to external wiring. The S/UNI-DUAL receives two SONET/SDH channels via separate bit serial interfaces, recovers their corresponding clock and data, and processes section, line and path overhead for each channel. Each channel performs framing (A1, A2), descrambling, detects alarm conditions, and monitors section, line, and path bit interleaved parity (B1, B2, B3), accumulating error counts at each level for performance monitoring purposes. Line and path far end block error indications (M0 or M1, G1) are also accumulated for each channel. Each channel of the S/UNI-DUAL interprets the received payload pointers (H1, H2) and extracts the synchronous payload envelope which carries the received ATM cell payload.
33
PMC-Sierra, Inc.
REFERENCE DESIGN
PMC-960552 ISSUE 1
PM5948 DART-BOARD
S/UNI - DUAL ATM REFERENCE TRANSCEIVER BOARD
Each channel of the S/UNI-DUAL frames to the ATM payload using cell delineation. HCS error correction is provided. Idle/unassigned cells may be dropped according to a programmable filter. Cells are also dropped upon detection of an uncorrectable header check sequence error. The ATM cell payloads are descrambled. Legitimate ATM cells are written to a four cell FIFO buffer. The ATM cells are read from each channel's FIFO via a synchronous interface with cell-based handshake using either a split 8 bit wide datapath, a direct 8 bit wide datapath or a direct 16 bit wide datapath. Counts of received ATM cell headers that are errored and uncorrectable, those that are errored and correctable, and all passed cells are accumulated independently for each channel's performance monitoring purposes. The S/UNI-DUAL transmits two SONET/SDH channels via separate bit serial interfaces and formats section, line, and path overhead for each channel. Each channel performs framing pattern insertion (A1, A2), scrambling, alarm signal insertion, and creates section, line, and path bit interleaved parity (B1, B2, B3) as required to allow performance monitoring at the far end. Line and path far end block error indications (M0 or M1, G1) are also inserted. Each channel of the S/UNI-DUAL generates the payload pointer (H1, H2) and inserts the synchronous payload envelope which carries the ATM cell payload. It supports the insertion of a variety of errors into the transmit stream, such as framing pattern errors, bit interleaved parity errors, and illegal pointers, which are useful for system diagnostics. ATM cells are written to each channel's internally programmable-length 4-cell FIFO via a synchronous interface using either a split 8 bit wide datapath, a direct 8 bit wide datapath, or a direct 16 bit wide datapath. Idle/unassigned cells are automatically inserted when the internal FIFO contains less than one cellEach channel of the S/UNI-DUAL generates the header check sequence and scrambles the payload of the ATM cells. Payload scrambling can be disabled. No line rate clocks are required directly by the S/UNI-DUAL as it synthesizes the transmit clock and recovers the receive clocks using a single 19.44 MHz or 6.48 MHz reference clock. The S/UNI-DUAL is configured, controlled and monitored via a generic 8-bit microprocessor bus interface. It is implemented in low power, +5 Volt CMOS technology. It has TTL and PECL compatible inputs, has TTL/CMOS compatible outputs and is packaged in a 160 pin MQFP package. 5.1 S/UNI-DUAL register address map For register details, please refer to the S/UNI-DUAL PM5348 Data sheet available either from your local PMC-Sierra Inc. Representative or from our Web Page at: http://www.pmc-sierra.com
34
PMC-Sierra, Inc.
REFERENCE DESIGN
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PM5948 DART-BOARD
S/UNI - DUAL ATM REFERENCE TRANSCEIVER BOARD
The microprocessor interface provides access to the S/UNI-DUAL device registers via the 140-pin SCI-PHY connector. The microprocessor interface block provides normal and test mode registers, and the logic required to connect to the microprocessor interface. The normal mode registers are required for normal operation, and test mode registers are used to enhance the testability of the S/UNIDUAL. The S/UNI-DUAL address space extends from 0x000H to 0x1FFH. Of the 9 address bits, address bit 8 (A8) being the most significant bit and A0 being the least significant bit) is set low to access the S/UNI-DUAL normal mode register space .
35
PMC-Sierra, Inc.
REFERENCE DESIGN
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PM5948 DART-BOARD
S/UNI - DUAL ATM REFERENCE TRANSCEIVER BOARD
APPENDIX A: PCB LAYOUT NOTES A.1. Background
The DART board is a 6-layer board that has both through-hole and SMT (surface mount technology) components. The large IC are placed on the top side and most of the discrete devices are located on the solder side with power and ground planes buried internally. All routing traces are located on the two external sides for accessibility reasons. Layer 1 2 3 4 5 6 A.2. Schematic Label Component side TA D VCC RA Solder Side Trace Impedance Control Description signal traces and mainly components is the Transmit Ground (labeled 'TA') is the ground and power respectively. +5 volt power plane Receive Ground Plane signal traces and discrete components
To reduce signal degradation due to reflection and radiation, the impedance of the traces that carry high speed signals such as transmitted and received data should be treated as microstrip transmission lines and terminated with matching impedance. The trace width is calculated using the formula Zo = 87 5.98 x h x ln 0.8 x w + t r + 1.41
based on the following layer setup: Fig. 37 Printed Circuit Board Stacking
w t
1 Oz Copper
dielectric r
Ground Plane
h1 t h2 h3
dielectric r dielectric r
1 Oz Copper 1 Oz Copper
1 Oz Copper
Power Plane
t
where
A1
PMC-Sierra, Inc.
REFERENCE DESIGN
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PM5948 DART-BOARD
S/UNI - DUAL ATM REFERENCE TRANSCEIVER BOARD
r = relative dielectric constant, nominally 5.0 for G -10 fibre - glass epoxy t = thickness of the copper, fixed according to the weight of copper selected. For 1 oz copper, the thickness is 1.4 mil (2 oz = 2.88mil). This thickness can be ignored if w is great enough. h1, h2, h3 = thickness of dielectric. w = width of copper
The parameters h1, h2, and h3 can be specified. For example, if a 20 mil (including the copper thickness on both sides of the board) two layer core is selected, dielectric material that has the same relative dielectric constant can be added to both sides of the core to construct a 4 layer board. Since all the controlled impedance traces are on the component side, only h1 is relevant in calculating the trace width. The calculation for the reference design is shown in the tables below:
Parameters Board Thickness (mil) Nominal 62 (including copper thickness) 10
Separation between layers 1 and 2 (mil) Separation between layers 2 and 3 (mil) Separation between layers 3 and 4 (mil) Relative dielectric constant
30.5
10
4.2
Parameter
Data 4.2 10 1.4 50 17
r
h (mil) t (mil) for 1oz Zo (Ohm) W (mil)
A2
PMC-Sierra, Inc.
REFERENCE DESIGN
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PM5948 DART-BOARD
S/UNI - DUAL ATM REFERENCE TRANSCEIVER BOARD
Since h1 is proportional to the width of the traces, a small h1 will result in the traces being too thin to be accurately fabricated. Wider traces can be more precisely manufactured, but they take up too much board space. Therefore, the thickness of the board should be chosen so that the traces take up as little board space as possible yet still leaving enough margin to allow accurate fabrication. The low speed signals use 8 to 10 mil traces. Power and ground traces should be made as wide as possible to reduce the line inductance. All 50 Ohm traces are 17 mils wide. A.3. Routing
Routing is based on the design considerations as well as manufacturability. Several suggestions are listed below: * * Turns and corners should be rounded to curves to avoid discontinuity in the signal path. Allow at least 10 mil clearance among vias, traces, and pads to prevent short and reduce crosstalk. If possible, allow 20 mil or more clearance around vias as manufacturers may have minimum clearance requirements. For the traces that run between pads of the 140 pin edge connector, clearance of 6 mil and trace width of 8 mil can be used. However, the number and lengths such traces should be kept to a minimum. The differential signal pairs should be of equal length so that both signals arrive at the inputs at the same time. They should also run parallel and close to one another for as long as possible so that noise will couple onto both lines and become common mode noise which is ignored by the differential inputs. Even though single ended inputs should not run parallel to one another in close proximity, all of the single ended signals that run parallel to one another on the dropside interface are low speed signals and are sampled after they have all settled down; therefore, they should not cause any concern. All power and ground traces should be made as wide as possible to provide low impedance paths for the supply current as well as to allow quick noise dissipation. The oscillator used in a 14 pin DIP package. The connections to the oscillator are setup so that an oscillator with a smaller footprint (8 pin) can also be plugged in. An FCT541 buffer with series source terminations must be used. Since vias have an impedance, avoid them where possible, especially on critical traces such as TXD and RXD. Also where decoupling is critical, try to place capacitors at the pins (component side) and not have vias in series with the capacitors.
A3
*
*
*
*
*
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S/UNI - DUAL ATM REFERENCE TRANSCEIVER BOARD
APPENDIX B: DART BOARD DROP SIDE CONNECTOR PINOUT The system connector interfaces this DART board to the local ATM layer drop side controller. It has a total 140-pins to allow for the following functionality: * 8 bit micro controller interface * power, 5Vdc, 10% * ground * control logic to four logical PHY devices * 16 bit wide TX and RX parallel FIFO access and control via SCI-PHY bus The DART SCI-PHY edge connector interface includes all the signals required to connect the DART board to a high layer protocol entity (i.e. AAL processor). Cells can be written to the S/UNI-DUAL/s transmit FIFO and read from the S/UNI-DUAL/s receive FIFO using this interface. The edge connector is made up of one 100 pin and two 20 pin dual line female connectors as shown in table below for a total of 140 pins. It consists of signals appropriate to read and write to the registers of the two DUAL devices on the daughter board, and it provides the necessary power and ground. TTL signal levels are used on this interface. Since there are four logical PHY devices on the DART board, J1, J2 and J3 below have four sets of PHY control signals such as RCA, TCA, RRDENB, and TWRENB. Fig. 38 DART board Expansion Connector 2 4 6 8 10 12 14 16 18 20
CHASSIS GND RRDMPH3 CHASSIS GND RRA1 RRA0 RCA2 RCA3 RCA4 TCA2 TCA3
1 3 5 7 9 11 13 15 17 19
NU RCAPH3 CSB2 RRDEN4B RRDEN3B RRDEN2B TWREN4B TWREN3B TWREN2B TCA4
NU=Not Used on This board but defined
B1
PMC-Sierra, Inc.
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PM5948 DART-BOARD
S/UNI - DUAL ATM REFERENCE TRANSCEIVER BOARD
J1 20-PIN EXPANSION PHY CONTROL SIGNALS S i g n al Name Type P I N Function NC NC 1 Reserved CHASSIS Power 2 Safety ground used by Interface devices such as GND the Fiber Optic Transceiver or UTP-5 Electrical Line 6 interface. RCAMPH3 NC 3 Not used on DART board, no connect. 4 CSD2B Input 5 Active low, PHY 8 bit microprocessor chip select used to select U3, S/UNI-DUAL #2 internal registers. Chip select for DUAL #1 is on pin 89 of J3, the 100 pin connector RRDEN4B Input 7 Active low Receive Read Enable used to enable reading the S/UNI receive FIFO of PHY device # RRDEN3B 9 2,3 or 4. See J3 pin 47 for RRDEN1B. RRDEN2B 11 The active low receive read enable Input (RRDEN1B) is used to initiate reads from one logical PHY device on the SUNI-DUAL receive FIFO. When sampled low using the rising edge of RFCLK, a word is read from the SUNI-DUAL internal synchronous FIFO and output on the RDAT[15:0] bus. When sampled high using the rising edge of RFCLK, no read is performed. RRDENxB must operate in conjunction with RFCLK to access the SUNI-DUAL FIFO at a high enough instantaneous rate ( 19.44 MHz)as to avoid FIFO overflows. The ATM layer device may deassert RRDEN1B at anytime it is unable to accept another byte. When the RCA signal is configured to be deasserted with zero octets (as opposed to four) in the SUNI-DUAL FIFO, it is not an error condition to hold the read enable (RRDEN1B) active. In this situation, the RCA signal identifies the valid octets. RRA1 Input 8 Not used on DART board, defined for RCMP Board. It's a UTOPIA Level 2 address bit 1 & 0. RRA0 10
B2
PMC-Sierra, Inc.
REFERENCE DESIGN
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S/UNI - DUAL ATM REFERENCE TRANSCEIVER BOARD
RCA2 RCA3 RCA4
Output
12 14 16
TWREN4B TWREN3B TWREN2B
Input
13 15 17
TCA2 TCA4 TCA3
Output
18 19 20
Active high receive cell available (RCA) signal (polarity selectable in S/UNI-DUAL) indicates when a cell is available on the first logical PHY device. Used by S/UNI chip to notify the hardware on the drop side that there is at least one ATM cell ready to be read out of the receive FIFO. RCA can be configured to be de-asserted when either zero or four words remain in the S/UNI-DUAL FIFO. RCA is updated on the default rising edge of RFCLK but it's active edge is programmable. The active low transmit write enable Input (TWRENB) is used to initiate writes to the SUNIDUAL transmit FIFO. When sampled low using the rising edge of TFCLK, the word on TDAT[15:0] is written into the SUNI-DUAL transmit FIFO. When sampled high using the rising edge of TFCLK, no write is performed. A complete 53 octet cell must be written to the SUNI-DUAL transmit FIFO before it is inserted into the SPE. The transmit cell available (TCA) signal indicates when a cell is available in the S/UNI-DUAL transmit FIFO. When high, TCA indicates that the S/UNIDUAL transmit FIFO is not full and a complete cell may be written in. When TCA goes low, it indicates either that the S/UNI-DUAL transmit FIFO is near full and can accept no more than four writes or that the transmit FIFO is full. Selection is made using a register bit in the S/UNI-DUAL TACP FIFO Control register. To reduce FIFO latency, the FIFO depth at which TCA indicates "full" can be set to one, two, three or four cells by the S/UNI-DUAL TACP FIFO Control register. If the programmed depth is less than four, additional cells may be written after TCA is asserted. TCA is updated on the rising edge of TFCLK. The active polarity of this signal is programmable in the S/UNI-DUAL and defaults to active high. TCA1 is on pin 18 of 100 pin connector
B3
PMC-Sierra, Inc.
REFERENCE DESIGN
PMC-960552 ISSUE 1
PM5948 DART-BOARD
S/UNI - DUAL ATM REFERENCE TRANSCEIVER BOARD
J2 20-PIN EXPANSION CONNECTOR S i g n al Name Type P I N Function RDAT[15:8] is the high order byte of the Received Output 1 RDAT[8] FIFO cell word RDAT[15:0]. Please refer to the 2 RDAT[9] S/UNI-DUAL data sheet for the 27 word cell data 3 RDAT[10] structure. 4 RDAT[11] 5 RDAT[12] 6 RDAT[13] 7 RDAT[14] 8 RDAT[15] RXPRTY1 Output 9 Programmable function receive parity bit. In 16 bit mode, it's the receive parity bit for the Receive Data Bus RDAT[15:0] . In split bus mode, this is the parity bit for channel 2 of RDAT[15:8] . In 8-bit bus mode it is not used. GND Power 10 Ground (used as analog and digital ground) 11 TXPRTY1 Input 12 Programmable function transmit parity bit input for the transmit ATM cell Data Bus. In 16 bit mode, it's the parity bit of TDAT[15:0] . In 8-bit split bus mode, this is the parity for channel #2 of TDAT[15:8]. In 8bit bus mode, this is not used. TDAT[15:8] is the high order byte of the Transmit INPUT 14 TDAT[8] FIFO cell word RDAT[15:0]. Please refer to the 13 TDAT[9] S/UNI-DUAL data sheet for the 27 word cell data 16 TDAT[10] structure. 15 TDAT[11] 18 TDAT[12] 17 TDAT[13] 20 TDAT[14] 19 TDAT[15]
B4
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S/UNI - DUAL ATM REFERENCE TRANSCEIVER BOARD
J3 100-PIN CONNECTOR S i g n al Name Type P I N Function GND Power 1,2,13 Ground, used on PCB as Digital Ground(D), ,16,17 Transmit Analog Ground (TA) and Receive Analog ,20,21 Ground (RA) ,24,25 ,28,29 ,41,44 ,45,48 ,49,52 ,53,56 ,57,69 ,70,75 ,76,81 ,82,90 ,91,94 ,95,99 ,100 TDAT[7:0] is the low order byte of the transmit FIFO Input 3 TDAT[0] cell word TDAT[15:0]. Please refer to the S/UNI5 TDAT[1] DUAL data sheet for the 27 word cell data structure. 9 TDAT[2] 11 TDAT[3] 4 TDAT[4] 6 TDAT[5] 10 TDAT[6] 12 TDAT[7] TXPRTY0 Input 14 Programmable function transmit parity input bit for the transmit ATM cell Data Bus. This input is ignored in 16 bit mode. In 8-bit split bus mode, this is the parity for channel #1 of TDAT[7:0]. In 8-bit bus mode, the parity of TDAT[7:0] and input TXPRTY[0] is checked. VCC Power 7,8,35 +5 Volts DC Power 36,63, 64,85, 86 TSOC Input 15 The transmit start of cell (TSOC) signal marks the start of cell on the TDAT[15:0] bus. When TSOC is high, the first octet of the cell is present on the TDAT[15:0] stream. It is not necessary for TSOC to be present at each cell. An interrupt may be generated on the INTB signal if TSOC is high during any byte other than the first byte. TSOC is sampled on the rising edge of TFCLK
B5
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S/UNI - DUAL ATM REFERENCE TRANSCEIVER BOARD
TCA1 NC
Output
TFCLK
Input
18 19 23 26 42 51 54 55 62 83 87 22
See pin 18,19,20 of J1 for TCA description No Connect
TWREN1B RDAT[0] RDAT[1] RDAT[2] RDAT[3] RDAT[4] RDAT[5] RDAT[6] RDAT[7] RXPRTY0
Input Output
Output
27 31 33 37 39 30 32 38 40 34
The transmit write clock (TFCLK) is used to write ATM cells to the SUNI-DUAL four cell transmit FIFO. TFCLK cycles at a 50MHz or lower instantaneous rate. A complete 53 octet cell must be written to the SUNI-DUAL FIFO before being inserted in the synchronous payload envelope (SPE). TDAT[15:0], TXPRTY, TWRENB and TSOC are sampled on the rising edge of TFCLK. TCA is updated on the rising edge of TFCLK. See description of J1 pin 13, 15,17 RDAT[7:0] is the low order byte of the Received FIFO cell word RDAT[15:0]. Please refer to the S/UNI-DUAL data sheet for the 27 word cell data structure.
RSOC
Output
43
RCA1 RRDEN1B
Output Input
46 47
Programmable function receive parity bit. In 16 bit mode, this pin is held low. In split bus mode, this is the parity bit for for channel #1 on RDAT[7:0] . In 8bit bus mode, this is the parity bit for both channels. The receive start of cell (RSOC) signal marks the start of cell on the RDAT[15:0] bus. When RSOC is high, the first octet of the cell is present on the RDAT[15:0] stream. RSOC is updated on the rising edge of RFCLK. See J1 pin 12,14, & 16 for full description. See connector J1 pins 7,9 & 11 for details on the other three RRDENxB signals
B6
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S/UNI - DUAL ATM REFERENCE TRANSCEIVER BOARD
RFCLK
Input
50
A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] A[8]
Input
Input & Output
Input
59 61 65 67 58 60 66 68 71 73 77 79 74 78 80 84 72
The receive read clock (RFCLK) is used to read ATM cells from the SUNI-DUAL receive FIFO. RFCLK must cycle at a 50 MHz or lower instantaneous rate, but at a high enough rate to avoid FIFO overflow ( 19.44 MHz @ 155.52 MHz line rate). RRDENB is sampled using the rising edge of RFCLK. RSOC, RDAT[15:0], RXPRTY and RCA are updated on the rising edge of RFCLK. The address bus A[7:0] selects specific registers during S/UNI-DUAL register accesses.
The bi-directional data bus D[7:0] is used during by the local microprocessor to read and write to the S/UNI-DUAL control and status registers.
INTB
Open Drain Output
88
CSB1 RSTB
Input Input
89 92
Address bit 8 used by S/UNI-DUAL. When low, the user accessible registers (0x000 to 0x0FF) are available to the local microcontroller. When high, the test mode registers (0x100 to 0x1FF) can be accessed. In normal operation only the lower 256 locations are defined and used. The active low interrupt (INTB) signal goes low when a S/UNI-DUAL interrupt source is active, and that source is unmasked. The S/UNI-DUAL may be enabled to report many alarms or events via interrupts. Examples are loss of signal (LOS), loss of frame (LOF), line AIS, line remote defect indication (RDI), loss of pointer (LOP), path AIS, path RDI and many others. INTB returns high when the interrupt is acknowledged via an appropriate register access. INTB is an open drain output. and must be pulled high with a resistor. The active low chip select from the local uP must be low to access U2, S/UNI-DUAL #1 registers. The active low reset (RSTB) signal provides an asynchronous S/UNI-DUAL reset.
B7
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PM5948 DART-BOARD
S/UNI - DUAL ATM REFERENCE TRANSCEIVER BOARD
RDB
Input
93
RDY WRB
Input
96 97
ALE
Input
98
The active low read enable (RDB) signal is low during S/UNI-DUAL register read accesses. The S/UNI-DUAL drives the D[7:0] bus with the contents of the addressed register while RDB and CSB are low. Not Used The active low write strobe (WRB) signal is low during a S/UNI-DUAL register write accesses. The D[7:0] bus contents are latched into the addressed register on the rising WRB edge while the selected CSB1 or CSB2 is low. The address latch enable (ALE) is active high and latches the address bus A[7:0] when low. When ALE is high, the internal S/UNI-DUAL address latches are transparent. It allows the S/UNI-DUAL to interface to a multiplexed address/data bus. The S/UNI-DUAL ALE has an integral pull up resistor. Not Used.
B8
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REFERENCE DESIGN
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PM5948 DART-BOARD
S/UNI - DUAL ATM REFERENCE TRANSCEIVER BOARD
APPENDIX C: MECHANICAL DRAWINGS
.217
.100
Hold down post .100 .050 .010 .260 .437
.100
AMP 101911-8 Edge Connector
6"
TEST POINTS
S/UNI
TM
HP OPTICS
S/UNI-DUAL
PM5348
- 155-DUAL
DROP SIDE 140-pin connector
HP OPTICS
74FCT541
19.44mHz Osc.
6"
S/UNI
-
TM
155-DUAL
HP OPTICS
S/UNI-DUAL
PM5348
HP OPTICS
LED's
PCB Board Dimensions
C1
PMC-Sierra, Inc.
REFERENCE DESIGN
PMC-960552 ISSUE 1
PM5948 DART-BOARD
S/UNI - DUAL ATM REFERENCE TRANSCEIVER BOARD
APPENDIX D: DART BOARD PARTS LIST
NO. Part Name - Value Part Number Description Jedec Type SOT23 SOIC20W CAP200 SMDCAP1206 Ref Des Q1-Q4 U4, U5 C89,C91,C117,C119 C3,C7,C21,C25, C76,C80,C81,C83, C85,C93-C96,C101,C107,C108,C110, C112,C120-C123,C141,C142,C145 C146,C150,C151,C154,C155,C157 5 0.01F CAP, CERAMIC Ceramic, decoupling, high frequency Low ESR and low ESL SMDCAP805 C2,C5,C8-C12,C15-C19,C22, C23,C27-C59,C64-C68,C73-C75, C82,C84,C86-C88,C90, C92,C103,C109-C111,C114-C116, C118,C124,C128-C139,C148 6 47PF CAP 7 100F CAPACITOR,16V 8 10 F CAPACITOR,16V NPO_805 ELECTROLYTIC TANT TEH SMDCAP805 CAP320 SMDTANCAP_C C4,C20,C26,C113 C1 C6,C13,C14,C24,C78,C98,C102 C105,C126,C140,C143,C144,C147 C149,C152,C153, C156 9 4.7F X5R Ceramic SMT Cap. NON-POLARIZED Taiyo Yuden inc. PN# LMK316BJ475ML-B, 4.7F, 10V, X5R, 20%, 1206 size C60,C63,C69,C72,C79,C97,C106,C125 8 4 1 17 84 Qty 4 2 4 28
1 2N3904 2 74FCT541
SOT23-BASE 74FCT541DW, FCT octal buffer Decoupling, 10 or 16V Ceramic, decoupling, high frequency Low ESR and low ESL
3 1.0 F CAP TANTALUM 4 0.1F CAP, CERAMIC
see app note inside this document section 3.16 and 3.17 and Appendix E next for capacitor vendor sources
1 0 CONN100-AMP_103911-8 1 1 CONN20-AMP_103911-2 1 2 HEADER2-BASE 1 3 INDUCTOR-FB,50,
AMP -- 103911-8 AMP_103911-2 DIGI-KEY S1011-36-ND FAIR-RITE PN# 2743019447
AMP_103911-8 AMP_103911-2 JUMPER2 INDUCTOR_FB
P2 P1,P3 J1,J2 L3-L32
1 2 2 30
DO NOT SUBSTITUTE 1 4 LCD_PMD-HPBR-5205 1 5 LED10-RED,25MA,2.1V 1 6 19.44MHZ OSC, TTL, DIP 1 7 RESISTOR-100,1% 1 8 RESISTOR-200,1% 1 9 RESISTOR-237,1% 2 0 RESISTOR-27,5% 2 1 RESISTOR-330,5% 2 2 RESISTOR-4.7K,5% 2 3 RESISTOR-49.9,1% 2 4 RESISTOR-68.1,1% 2 5 RESISTOR-681,1% 2 6 4.7K RES_ARRAY_15pos 2 7 1K RES_ARRAY_8_pos 2 8 SMA-BASE 2 9 SUNIDUAL PM5348 3 0 TEST POINT HEADER TOTAL COMPONENT COUNT 20 PPM, see app note SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD Test Points only PMC-Sierra Inc. DIGI-KEY S1011-36-ND HP -- HPBR-5205
.18" by .12" by .12" high PMD-SOCKET DIP20_LED CRYS14 SMDRES805 SMDRES805 SMDRES805 SMDRES805 SMDRES805 SMDRES805 SMDRES805 SMDRES805 SMDRES805 SOIC16 SOIC16 SMA PQFP160 TST_PT_1 U6-U9 U1 Y1 R3,R6,R11,R17,R51,R54,R58,R61 R40,R43,R45,R48 R1,R2,R4,R5,R9,R10,R12,R16,R87-R90 R7,R8 R66-R68,R72-R74,R78-R80,R84-R86 R13-R15,R26, R29-R39,R44,R49 R64,R65,R70,R71,R76,R77,R82,R83 R52,R53,R59,R60 R63,R69,R75,R81 RN1-RN3,RN5 RN4,RN6,RN7 J3,J4 U2,U3 TP3-TP17,TP19-TP35,TP39-TP42 4 1 1 8 4 12 2 12 17 8 4 4 4 3 2 2 1 276
D1
PMC-Sierra, Inc.
REFERENCE DESIGN
PMC-960552 ISSUE 1
PM5948 DART-BOARD
S/UNI - DUAL ATM REFERENCE TRANSCEIVER BOARD
APPENDIX E: 4.7F Ceramic Multilayer X5R and X7R Capacitor Sources * 20 % and 10% basic tolerance * Stable X5R and X7R 15% tolerance over temperature: (X7R rated from -55 to +125C and X5R from -55C to +85C) * small size Surface Mount, some may only be reflow qualified * unpolarized * Part #'s below are for bulk, check Data Sheet for other packaging
Manufacturer Taiyo Yuden Inc. Distributor's PN# EMK325BJ475MN-B LMK316BJ475ML-B
F
%
Type
DCV
Footprint
Thick 1.9mm 1.6mm 1.6mm 1.9mm
4.7 20% X5R 16V 1210 (0.12" by .10") 4.7 20% X5R 10V 1206 (0.12" by .06") special factory order for 10% LMK316BJ475KL-B 4.7 10% X5R 10V 1206 (0.12" by .06") EMK325BJ475KN-B 4.7 10% X5R 16V 1210 (0.12" by .10") Manufacturer: Taiyo Yuden Inc. , 16-20 Ueno 6-chome, Taito-ku, Tokyo, Japan Phone: 03-3833-5441, FAX: 03-3835-4754 Rep.: Ty Bowman, Chicago, USA, 847-925-0888 Distributor : Canada; Electro Source, 6875 Royal Oak Rd., Burnaby BC, 604-435-2533 UK; Taiyo Yuden Westfield. London Road, High Wy. Combe Buckingham Shire HP11,1MA Phone:(44) 1494-464642 FAX: (44) 1494-474743 CC1206JX5R475K 4.7 10% X5R 6.3V 1206 (0.12" by .06") ( internal Manufacturer's PN # C3216X5R0J475K) TDK Corp. of America: 1600 Feehanville Drive, Mount Prospect, Ill. USA 60056 1996 Edition Electronic Components Distributor Catalog page 15-20 Phone: (847) 803-6100 FAX: (847) 803-6296 Distributor: Enerlec Sales, Brenda, Richmond BC, Canada, 604-273-0882 2220RR475J8AB0C 4.7 5% X7R 25V 2220 (0.22" by .20") 2220RR475K8AB0C 4.7 10% X7R 25V 2220 (0.22" by .20") 2220RR475M8AB0C 4.7 20% X7R 25V 2220 (0.22" by .20") Philips Electronics Ltd., 601 Milner Avenue, Scarborough, Ontario, Canada Compact X7R Series Catalog Phone (416) 292-5161 FAX: (416) 292-4477 SM015C475KAJ240 4.7 10% X7R 50V 3230 (0.32" by .30") SM015C475MAJ240 4.7 20% X7R 50V 3230 (0.32" by .30") AVX Corporation, Myrtle Beach, SC USA, SMPS Series Capacitors Catalog Phone: (803) 448-9411 FAX: (803) 448-1943 AVX Limited, Aldershot England Phone: (252-336868 FAX: 252-346643 3736X7R475K1NT91A 4.7 many X7R 25V 3736 (0.37" by .36") Prestidio Components Inc., 7169 Construction Court, San Diego, CA USA 92121 EEM 1997 Catalog; page A1122-1123 Phone: (619) 578-9390 FAX: 1-800-538-3880
TDK
PHILIPS
AVX
Prestidio
Vitramon
VJ2225Y475JXXAT 4.7 5% X7R 25V 2225 (0.22" by .25") VJ2225Y475KXXAT 4.7 10% X7R 25V 2225 (0.22" by .25") VJ2225Y475MXXAT 4.7 20% X7R 25V 2225 (0.22" by .25") Manufacturer: Vitramon, #10 Route 25, Monroe, CT 06468, Mail: PO Box 544, CT 06601 Phone (203) 268-6261 FAX: (203) 452-5670
D1
PMC-Sierra, Inc.
REFERENCE DESIGN
PMC-960552 ISSUE 1
PM5948 DART-BOARD
S/UNI - DUAL ATM REFERENCE TRANSCEIVER BOARD
APPENDIX F: SCHEMATICS
E1
PMC-Sierra, Inc.
REFERENCE DESIGN
PMC-960552 ISSUE 1
PM5948 DART-BOARD
S/UNI - DUAL ATM REFERENCE TRANSCEIVER BOARD
APPENDIX G: SCHEMATIC COMPONENT CROSS REFERENCE
F1
PMC-Sierra, Inc.
REFERENCE DESIGN
PMC-960552 ISSUE 1
PM5948 DART-BOARD
S/UNI - DUAL ATM REFERENCE TRANSCEIVER BOARD
APPENDIX H: SCHEMATIC SIGNAL CROSS REFERENCE
G1
PMC-Sierra, Inc.
REFERENCE DESIGN
PMC-960552 ISSUE 1
PM5948 DART-BOARD
S/UNI - DUAL ATM REFERENCE TRANSCEIVER BOARD
APPENDIX I: PCB ARTWORK
H1
PMC-Sierra, Inc.
REFERENCE DESIGN
PMC-960552 ISSUE 1
PM5948 DART-BOARD
S/UNI - DUAL ATM REFERENCE TRANSCEIVER BOARD
APPENDIX J: REFERENCES * * * American National Standards for Telecommunications, ANSI T1.105.03 1994 Bell Communications Research, Bellcore GR-253-CORE, Issue 2, Dec. 2, 1995 International Telecommunications Union, ITU-T Recommendation G.958 "Digital Line Systems Based on the Synchronous Digital Hierarchy for use on Optical Fibre Cables" PMC-Sierra, PMC5348 databook, Issue 5, January 1997, PMC-950919, "S/UNI-155-DUAL, Saturn User Network Interface 155.52 & 51.84 Mbit/s" PMC-Sierra, S/UNI-LITE (PM5347) and the Optical Reference Design (SORD board), PM5946, PMC-950112 Ott, Henry W., "Noise Reduction Techniques in Electronic Systems", Second Edition, John Wiley & Sons. Montrose, Mark I., "Printed Circuit Board Design Techniques for EMC Compliance", IEEE Press, 1995. Graham, Martin and Johnson, Howard W., "High-Speed Digital Design: A Handbook of Black Magic", PRT Prentice-Hall Inc, 1993. Tokin catalog EC-110E and User's manual EC-111E, 1996, USA 1-408-432-8020
* * * * * *
I1
PMC-Sierra, Inc.
REFERENCE DESIGN
PMC-960552 ISSUE 1
PM5948 DART-BOARD
S/UNI - DUAL ATM REFERENCE TRANSCEIVER BOARD
CONTACTING PMC-SIERRA PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com http://www.pmc-sierra.com
Document Information: Corporate Information: Applications Information: Web Site:
Seller will have no obligation or liability in respect of defects or damage caused by unauthorized use, mis-use, accident, external cause, installation error, or normal wear and tear. There are no warranties, representations or guarantees of any kind, either express or implied by law or custom, regarding the product or its performance, including those regarding quality, merchantability, fitness for purpose, condition, design, title, infringement of thirdparty rights, or conformance with sample. Seller shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon, the information contained in this document. In no event will Seller be liable to Buyer or to any other party for loss of profits, loss of savings, or punitive, exemplary, incidental, consequential or special damages, even if Seller has knowledge of the possibility of such potential loss or damage and even if caused by Seller's negligence. (c) 1997 PMC-Sierra, Inc. PMC-960552(R1) Printed in Canada Issue date: January, 1997
PMC-Sierra, Inc.
105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 (604 )416-6000

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