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| PRELIMINARY REFERENCE DESIGN PMC- 971116 ISSUE 2 PM5347 S/UNI-PLUS APS SOFTWARE REFERENCE DESIGN PM5347 AUTOMATIC PROTECTION SWITCHING (APS) SOFTWARE REFERENCE DESIGN PRELIMINARY ISSUE 2:FEBUARY 1997 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMINARY REFERENCE DESIGN PMC- 971116 ISSUE 2 PM5347 S/UNI-PLUS APS SOFTWARE REFERENCE DESIGN CONTENTS 1 INTRODUCTION...................................................................................... 1 1.1 2 3 AUDIENCE .................................................................................... 1 DESIGN OVERVIEW ............................................................................... 2 FUNCTIONAL DESCRIPTION................................................................. 7 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 OCTAL PLUS CONFIGURATION .................................................. 7 SD TIMER ISR .............................................................................. 8 BERM CLEARING ISR................................................................ 10 WTR TIMER ISR ......................................................................... 11 OCTAL PLUS INTERRUPT SERVICE ROUTINE........................ 12 EVALUATE NEW REQUESTS..................................................... 13 GENERATE K1 AND K2 BYTES ................................................. 14 SELECT AND BRIDGE CHANNEL TRAFFIC ............................. 18 4 IMPLEMENTATION ................................................................................ 19 4.1 4.2 DEVELOPMENT TOOLS ........................................................... 19 PROGRAM STRUCTURE AND ROUTINES ............................... 20 5 6 REFERENCES....................................................................................... 26 APPENDIX A ......................................................................................... 27 i PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMINARY REFERENCE DESIGN PMC- 971116 ISSUE 2 PM5347 S/UNI-PLUS APS SOFTWARE REFERENCE DESIGN 1 INTRODUCTION Automatic Protection Switching allows the recovery of a failed channel link between two nodes by switching traffic to a redundant protection channel. APS utilizes the K1 and K2 bytes in the SONET line overhead to implement a bitoriented protocol for switching operation. The APS architecture consists of selectors, and bridges for each channel and a central controller. This document describes the design, functionality, and implementation of an APS controller interfaced to PMC S/UNI-PLUS devices. This design is an extension to the Octal PLUS with APS reference design. The Octal PLUS reference with APS design document, PMC-960553, describes the hardware implementation of APS using S/UNI-PLUS devices. Please refer to PMC-960505 for a tutorial on APS system operation and architecture. 1.1 Audience This software reference design document has been prepared for customers who are implementing Automatic Protection Switching using PMC-Sierra S/UNI or SONET/SDH family chipsets. 1 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMINARY REFERENCE DESIGN PMC- 971116 ISSUE 2 PM5347 S/UNI-PLUS APS SOFTWARE REFERENCE DESIGN 2 DESIGN OVERVIEW The APS Controller is implemented by an interrupt driven software program written for the Motorola HC16Z1 series microcontroller. The microcontroller sits on the SWAN reference design board (PMC-970127) which is interfaced to the Octal PLUS board. The Octal PLUS consists of eight OC-3 ports, containing APS Bridge and Select hardware on board. Figure 1 depicts the APS setup using the SWAN and the Octal PLUS boards. Channel eight is used as the redundant channel to provide protection for the remaining seven working channels. Figure 1: Automatic Protection Switching Setup SWAN MCHC16Z1 PMC970127 Octal PLUS OPTICS I/F #1 PMC S/UNI155-PLUS Bridge & Selector 2 PMC960553 OPTICS Protection I/F #8 Channel The APS controller monitors the SONET line overhead K1 and K2 bytes and controls the bridging and selecting of traffic to and from the protection channel. It updates the transmit K1 and K2 bytes according to the status of the local node and requests services from the remote node if needed. For linear APS, two automatic switch initiation criteria are defined in Bellcore GR253-CORE. The first criteria is associated with a hard failure and is labeled as Signal Fail (SF). SF is declared when any of the following conditions has been detected: Loss of Signal (LOS), Loss of Frame (LOF), Line Alarm Indication PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMINARY REFERENCE DESIGN PMC- 971116 ISSUE 2 PM5347 S/UNI-PLUS APS SOFTWARE REFERENCE DESIGN Signal (AIS-L), or a Line BER threshold exceeding a range of 10 to 10 . The second criteria is associated with a soft failure and is called Signal Degrade -5 (SD). SD is declared when a BER exceeding a user-provisionable range of 10 -9 to 10 has been detected. After a failure condition due to either SD or SF has been detected, Bellcore GR-253-CORE requires the APS controller to complete an automatic switch within 50 ms. The software design in this application note will meet the 50 ms requirement and takes into account the APS bytes signaling time and software execution time. The S/UNI-PLUS device provides all the hardware required to detect both SF and SD criteria. For the SF criteria, the S/UNI-PLUS generates a hardware interrupt when any of LOS, LOF, and AIS-L conditions has been declared. The -4 integral BERM block can be programmed to detect a SF BER range of 10 to -5 10 . For the SD criteria, the S/UNI-PLUS's 20-bit BIP counter can used to -5 -9 detect a BER range of 10 to 10 . The APS controller polls the BIP counter at a defined interval to check if accumulated BIP error has exceed a maximum threshold calculated based on the BER defined. In addition, the S/UNI-PLUS supports extraction and insertion of APS K1/K2 bytes and detection of APS byte failure. The APS controller can insert K1 and K2 bytes in the transmit stream by writing to the transmit K1 and K2 registers. The S/UNI-PLUS filters and captures the K1 and K2 bytes allowing them to be read via the receive K1 and K2 registers. Figure 2 shows the flowchart for the APS controller software program. The software design is implemented as an interrupt driven program. The controller stays in the main loop until it is interrupted by a hardware or software interrupt. The interrupt service routines then perform the APS controller functions. The configuration step sets up the S/UNI-PLUS for BERM detection, enables interrupts to detect LOS, LOF, AIS-L failures. The eighth S/UNI-PLUS is setup to detect change in the received K1/K2 bytes and APS bytes failure. After configuring the Octal PLUS, the program goes into a continuous loop and waits for interrupts to occur. Four types of interrupts are defined for the controller program: * * * * SD Timer Software Interrupt BERM Timer Software Interrupt WTR Timer Software Interrupt Octal PLUS Hardware Interrupt 3 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE -3 -5 PRELIMINARY REFERENCE DESIGN PMC- 971116 ISSUE 2 PM5347 S/UNI-PLUS APS SOFTWARE REFERENCE DESIGN Each of the above four interrupts is serviced by its respective interrupt service routine (ISR). Note, the S/UNI-PLUS BERM block is configured to detect an SF condition. Therefore, this condition is incorporated in the interrupts generated from the Octal PLUS board. Figure 2: Flowchart of the APS Controller Configure Octal PLUS Main Loop SD Timer Interrupt BERM Clearing Interrupt WTR Timer Interrupt Octal PLUS Interrupt External User Request SD Timer ISR BERM Clearing ISR WTR Timer ISR Octal PLUS ISR User Request ISR New APS Request? Y N Evaluate New Request Priority of New Request Current Request? N Y Generate APS K1 and K2 Bytes Select and Bridge Channel Traffic 4 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMINARY REFERENCE DESIGN PMC- 971116 ISSUE 2 PM5347 S/UNI-PLUS APS SOFTWARE REFERENCE DESIGN The SD Timer interrupt service routine polls the BIP count to check if it has exceeded the SD threshold. If the BIP count exceeds the preset threshold, SD condition is declared and a new APS request is initiated. The BERM Clearing interrupt service routine checks whether a previously declared excessive SF BER has been cleared. The S/UNI-PLUS BERM block does not generate a clearing interrupt when the failure link has recovered from an excessive BER. To solve this problem, the APS controller polls the BERM block to determine whether a clearing threshold has been reached. If clearing has been detected, a new APS request is initiated. The WTR Timer interrupt service routine keeps track of the wait time required for switching back to a working channel. The WTR Timer is only activated when a clearing condition for SF or SD has been declared. If WTR period has timed out, a new APS request is initiated. The Octal PLUS interrupt service routine determines the source of the hardware interrupt from the Octal PLUS board. An interrupt from the Octal PLUS board indicates that one of the LOS, LOF, AIS-L, SF (BERM), APS bytes failure, or change in APS bytes conditions have occurred. Upon receiving an interrupt the controller will check the registers of all the S/UNI-PLUS devices and determine the source of the interrupt. It initiates a new APS request based on the result of the check. At the end of each interrupt service routine, if a new APS request is initiated, the controller evaluates the new APS request and determine their priority level according to Bellcore GR-253-CORE specification. If the priority level of the new request is lower than the current request, the new request is logged for later execution and the controller returns to the main loop. If the new request has a higher priority, new APS K1 and K2 bytes will be generated and written into the transmit K1 and K2 registers on the S/UNI-PLUS. The APS signals are transmitted and received on the protection channel. The protection channel S/UNI-PLUS is responsible for receiving the APS bytes, checking if the bytes are valid, and to transmit the bytes out to the remote node. New K1 and K2 APS bytes are generated for new requests and are written into the S/UNI-PLUS device to be transmitted over the protection channel. The controller will then set the selectors and bridges corresponding to the current transmit and receive K1 and K2 bytes. After a protection switch has occurred, the eighth S/UNI-PLUS will select the failure channel line to monitor for line recovery. The protected working channel S/UNI-PLUS will take over the APS signaling duty from the eighth S/UNI-PLUS. The APS signaling will still be done through the protection line. 5 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMINARY REFERENCE DESIGN PMC- 971116 ISSUE 2 PM5347 S/UNI-PLUS APS SOFTWARE REFERENCE DESIGN The user external request functionality has not been discussed so far. The external requests include lockout of protection, forced switch, and manual switch This functionality has not been implemented because this software design is meant for demonstrating an implementation of APS using PMC S/UNI-PLUS devices. The user external request routine does not require any hardware functionality and can be implemented as an extension to this design. The flowchart shows where the external request can be added to the program. 6 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMINARY REFERENCE DESIGN PMC- 971116 ISSUE 2 PM5347 S/UNI-PLUS APS SOFTWARE REFERENCE DESIGN 3 3.1 FUNCTIONAL DESCRIPTION Octal PLUS Configuration The following two register configurations are required for the seven working channel S/UNI PLUS devices on the Octal PLUS board. 3.1.1 Setting up the BERM Block The BERM block is setup to monitor Signal Failure (SF) BER conditions of 10 or -5 10 . Table 1 shows the required values for accumulation period and threshold for the BERM block registers, 0x72 to 0x75. Table 1: Accumulation and Threshold Values for BER BER 10-4 10-5 Accumulation Period LSB 0x34 0x90 Accumulation Period MSB 0x00 0x01 Threshold LSB 0x4D 0x3E Threshold MSB 0x00 0x00 -4 3.1.2 Enabling S/UNI-PLUS Interrupts Table 2 lists all the interrupt bits that need to be set to generate interrupts for the APS controller to detect APS Byte Failure, Change in Received APS Bytes, Loss of Frame, Loss of Signal, Line AIS and excessive BER conditions. Table 2: Interrupt Enable Registers Register 0x10 0x10 0x19 0x70 0x70 Bit 1 2 5 0 7 Name LOFE LOSE LAISE BERE BERTEN Value 1 1 1 1 1 Description Enable LOF Interrupt Enable LOS Interrupt Enable LAIS Interrupt Enable BERM interrupt Enable BERM Monitoring 7 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMINARY REFERENCE DESIGN PMC- 971116 ISSUE 2 PM5347 S/UNI-PLUS APS SOFTWARE REFERENCE DESIGN 3.1.3 Protection Channel S/UNI-PLUS Setting Table 3 lists the interrupt bits needed to be set for the protection channel S/UNIPLUS. The APS bytes are sent and received on the protection channel. Thus, only the protection channel S/UNI-PLUS needs to monitor the change in APS bytes and APS byte failures. The transmit K1 byte is set to "0F" to indicate extra channel traffic is being carried on the protection channel and K2 byte is set to "FD" to indicate bidirectional 1:N linear APS. Table 3: Interrupt Enable Register for the eighth S/UNI-PLUS Register 0x0B 0x0B Bit 6 7 Name COAPSE PSBFE Value 1 1 Description Enable Change in APS bytes Interrupt Enable APS Failure Byte Interrupt 3.1.4 Octal PLUS Configuration Register The configuration registers are set to their default values during initialization. For default settings, the APS Control/Status register in the configuration register is set to "00H". At default, the protection channel is used to carry extra channel traffic to and from the eighth S/UNI-PLUS at default. The extra channel traffic is unprotected and will be lost when the protection channel is used for protecting a failed working channel. 3.2 SD Timer ISR The Signal Degrade (SD) condition is detected and cleared by polling the Line BIP registers of all the S/UNI-PLUS's to check if the accumulated error has exceeded a preset threshold. The polling period or integration period for the SD software timer is set to half of the APS initiation time criterion defined by Bellcore GR-253-CORE. This is explained in the APS application note, PMC-960505. 3.2.1 Detecting SD To select a proper threshold count, Gaussian statistics are used to ensure 95% probability of detecting an excessive BER. Details regarding this calculation can be found in a application note, programming the Bit Error Rate Monitor (BERM), 8 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMINARY REFERENCE DESIGN PMC- 971116 ISSUE 2 PM5347 S/UNI-PLUS APS SOFTWARE REFERENCE DESIGN on the PMC web site (PMC-950820). Table 4 lists the integration period and the -5 -6 -7 threshold value associated with BER of 10 , 10 , and 10 . The APS controller checks the BIP count for each S/UNI-PLUS device when it has been interrupted by the SD timer at the end of each integration period. It checks the accumulated errors in BIP registers, 0x1A, 0x1B, and 0x1C. If the polled BIP error exceeds the calculated threshold shown in the table, an SD condition is declared and a new APS request is initiated. If polled BIP error is within threshold set, the routine returns to the program to wait for the end of the next integration period. Table 4: Integration Period and Threshold Count for SD Timer BER (SD) 10 10 10 -5 Switching Initiation Time Criteria (sec) 0.1 1 10 Integration Period (sec) 0.05 0.5 5.0 Threshold Count 62 62 62 -6 -7 3.2.2 Clearing SD After an SD condition has been declared, the APS controller uses the SD Timer for clearing the SD condition. Bellcore GR-253-CORE requires that clearing SD BER value be 1/10 of the declaring SD BER. Table 5 lists the threshold for clearing a SD BER. As soon as the polled accumulated BIP error falls within the threshold, the controller declares SD Clearing and issues a new APS request. Table 5: SD Clearing Integration Period and Threshold Settings BER (SD) 10 10 10 -5 Clearing BER required 10 10 10 -6 Switching Initiation Time Criteria (sec) 1 10 83 Integration Period (sec) 0.5 5 41 Threshold Count 62 62 51 -6 -7 -7 -8 9 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMINARY REFERENCE DESIGN PMC- 971116 ISSUE 2 PM5347 S/UNI-PLUS APS SOFTWARE REFERENCE DESIGN 3.3 BERM Clearing ISR The BERM Timer is enabled when BERM block has declared a SF condition. Bellcore GR-253-CORE requires that the clearing SF BER value be 1/10 of the declaring SF BER. After an SF has been declared due to excessive BER, the controller will write new values into the BERM block as shown in table 5. The BERM block will stop generating interrupts only if BER falls below the clearing threshold. Table 5: BERM Clearing Period and Threshold Settings BER (SF) 10 10 -4 Clearing BER required 10 10 -5 Accumulation Period LSB 0x90 0xA0 Accumulation Period MSB 0x01 0x0F Threshold LSB 0x3E 0x3E Threshold MSB 0x00 0x00 -5 -6 Since the BERM block interrupt bit is cleared when it is read, it is difficult to ascertain if the SF condition has been cleared by just checking that bit within the BERM clearing ISR. Figure 3 shows the process used for clearing the SF status declared by the BERM block implemented in this design. The Octal PLUS Interrupt Service Routine uses a BERM_STATUS flag to indicate the current SF BER status and uses a BERM_TOGGLE flag to indicate if a new interrupt has arrived since the last integration period. The BERM clearing ISR uses a counter, BT_COUNT, to keep track and wait for a preset number of integration periods during which no further BERM interrupts have been detected before clearing the SF status. The BT_TOGGLE flag is used by the BERM ISR to check if interrupts are still being generated by comparing to the BERM_TOGGLE flag. For the first BERM interrupt, BERM_STATUS will be set to 1, BERM_TOGGLE to 0, BT_COUNT to 0, and BT_TOGGLE to 0. The BERM clearing timer will be enabled to interrupt with the same period as the BERM integration period. The BERM block will continuously generate an interrupt if the detected threshold is higher than the clearing threshold set. The controller toggles BERM_TOGGLE every time it enters the Octal PLUS ISR. When the program enters the BERM Clearing ISR, the controller compares the value of BT_TOGGLE to the BERM_TOGGLE bit. If they are the same, it implies that no interrupt has occurred since the last check. The controller will increment BT_COUNT by one. If the toggle bits are different, it suggests that a new interrupt has occurred. The BT_TOGGLE bit will be set to the current BERM_TOGGLE bit and BT_COUNT will be reset to zero. When the BT_COUNT counter has reached 2, SF clearing is declared and a new APS request is generated. 10 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMINARY REFERENCE DESIGN PMC- 971116 ISSUE 2 PM5347 S/UNI-PLUS APS SOFTWARE REFERENCE DESIGN Bellcore GR-253-CORE specifies that to reduce the chance of rapid switch between channel during SD or SF clearing due to intermittent failure conditions, a maximum delay of 10 seconds can be allotted for clearing. For this example, a delay of two integration period is employed to ensure the failure condition has been cleared. This delay counter can be set to any value within the 10 sec by the user. Figure 3: BERM Clearing Process Octal PLUS ISR (Condition: BERM Interrupt Detected) BERM Timer ISR (Condition: BERM Clearing Timer Interrupted) BERM_STATUS = 0 BERM_TOGGLE = X Enable BERM Clearing Timer Set BT_TOGGLE = BERM_TOGGLE BT_COUNT = 0 BT_TOGGLE=0/1 BT_TOGGLE BERM_TOGGLE (Set BT_COUNT=0, BT_TOGGLE = BERM_TOGGLE) First BERM Interrupt BT_TOGGLE = BERM_TOGGLE BT_COUNT = 1 BT_TOGGLE = 0/1 BERM_STATUS = 1 BERM_TOGGLE = 0 No BERM Interrupt BERM Interrupted at the next integration BT_TOGGLE = BERM_TOGGLE BT_COUNT = 2 BT_TOGGLE = 0/1 BERM_STATUS = 1 BERM_TOGGLE = 1 No BERM Interrupt Clear SF BER Status * BERM_TOGGLE bit changes status everytime a BERM interrupt occurs * BT_TOGGLE = BERM_TOGGLE signifies that no BERM interrupt has come in since last check 3.4 WTR Timer ISR The WTR Timer is enabled when a SD and SF condition has recovered and the controller is waiting for a preset duration before initiating to switch back to the working channel. The WTR Timer ISR counts and keeps track of the WTR period and generates a request when the WTR timer has expired. The WTR timer period can be user provisioned from 5 to 12 minutes at 1 minutes interval. 11 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMINARY REFERENCE DESIGN PMC- 971116 ISSUE 2 PM5347 S/UNI-PLUS APS SOFTWARE REFERENCE DESIGN 3.5 Octal PLUS Interrupt Service Routine The Octal PLUS ISR examines all the interrupt status bits in all the S/UNI-PLUS devices to determine the source of the interrupt. For the working channel S/UNI-PLUS, the controller checks the interrupt registers for SF conditions. Table 6 lists all the registers and interrupt bits for SF declaration. By examining register 0x02, the APS controller can tell if an interrupt occurred for RSOP (LOS, LOF), RLOP (AIS-L), APS bytes, or BERM. All the failure conditions with the exception of the BERM block, generates both a detection and clearing interrupt. The ISR generates a new APS request based on the status of the interrupt bit read. The BERM clearing routine within the Octal PLUS ISR is discussed in the BERM clearing ISR section. Table 6: Interrupt Status Bits for Working Channel S/UNI-PLUS Register 0x02 0x02 0x02 0x11 0x11 0x11 0x11 0x18 0x19 0x71 Bit 0 1 7 1 2 4 5 1 1 0 Bit Name RSOPI RLOPI MISCI LOFV LOSV LOFI LOSI LAISV LAISI BERI Description Logic one when interrupt occurred in RSOP Logic one when interrupt occurred in RLOP Logic one when interrupt occurred for BERM Logic one when LOF is declared Logic one when LOS is declared Logic one when change in LOF state occurred Logic one when change in LOS state occurred Logic one when LAIS is declared Logic one when change in AIS state occurred Logic one when BER exceeded threshold For the protection channel S/UNI-PLUS, the controller checks for a change of APS bytes and APS bytes failure as shown in table 7. The received APS bytes are read from register 0x0C for K1 and 0x0D for K2 bytes in the S/UNI-PLUS. Table 7: Interrupt Status Bits for Protection Channel S/UNI-PLUS Register 0x0B 0x0B 0x0B Bit 0 2 3 Bit Name PSBFV COAPSI PSBFI Description Logic one when APS byte failure occurred Logic one when received new APS bytes Logic one when change in APS byte failure state occurred 12 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMINARY REFERENCE DESIGN PMC- 971116 ISSUE 2 PM5347 S/UNI-PLUS APS SOFTWARE REFERENCE DESIGN All the interrupt status bits, PSBFI, LOFI, LOSI, LAISI, and BERI bits are cleared when read. The controller generates a new APS request for evaluation after determining the source of the interrupt. 3.6 Evaluate New Requests After receiving requests from the interrupt service routines, the controller determines the priority level of the new request based on table 8. Any interrupts generated due to LOS, LOF, AIS-L, and excessive BER in the BERM block are considered as signal fail (SF) condition. The SD condition is declared from the SD timer routine indicating that BIP errors have exceeded the programmed threshold. Column two lists the requests that are generated locally and column three displays all the requests associated with received K1 byte. When more than one channel generates the same request, the lower channel number has higher priority than the higher channel number. Table 8: Priority Level for Interrupts Generated Priority Level Highest Conditions Detected Received K1 Bits 8 - 5 1111 1110 LOS, LOF, AIS-L, BERM Alarm 1101 1100 BIP > Threshold 1011 1010 1000 SF and SD clearing 0110 0010 0001 WTR Timed Out Lowest 0000 No Request Description Lockout of Protection Forced Switch SF : Higher Priority SF : Lower Priority SD : Higher Priority SD : Lower Priority Manual Switch Wait-to-restore Reverse Request Do not revert The priority of a new request due to a local failure condition or received K1/K2 bytes is compared with the current local request. A received "Reverse Request" 13 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMINARY REFERENCE DESIGN PMC- 971116 ISSUE 2 PM5347 S/UNI-PLUS APS SOFTWARE REFERENCE DESIGN will not be considered in the comparison since it assumes the same priority as the request that has been previously sent. The new request is ignored if the current local request has a higher priority. If priorities are the same, it implies the channel is in the process of being switched to the protection channel or the status has not changed. If new request has a higher priority, the current local request will be replaced by it. 3.7 Generate K1 and K2 Bytes APS bytes K1 and K2 are generated for new requests evaluated to be valid. The new APS bytes are written to the transmit K1 and K2 registers, 0x22 and 0x23, on the S/UNI-PLUS to be inserted into the transmit stream. Figure 4 shows the structure of the K1 and K2 bytes. Figure 4: K1 and K2 Bytes Structure K1 Byte 8 7 6 5 4 3 2 1 8 7 6 K2 Byte 5 4 3 2 1 Type of Request 1) Failure Condition 2) State Request 3) External Request Request Source Channel Number 0 -> Null Channel 1-7 -> Working Channel 15 -> Extra Traffic Channel Bridged Channel Number For Bidirectional Linear 1:N APS "1101" Bits 5 to 8 in the transmit K1 byte indicates the type of request sent by local site. Table 4 shows the value associated with each specific request. The LSB nibble in the K1 byte indicates the channel requesting the switching. The default request channel will be "1111" when the protection channel is not used for switching. The MSB nibble in K2 byte represents the channel currently bridged on the protection channel. Again, "1111" or extra traffic channel will be the default value. The LSB nibble in the K2 byte will always be set to "1101" for l:N bidirectional APS. The K1 and K2 values generated are based on three factors: the current received APS bytes, the current transmitting APS bytes, and any local failure or clearing request. The next section lists the APS K1 and K2 bytes generated for both local and remote requests. 14 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMINARY REFERENCE DESIGN PMC- 971116 ISSUE 2 PM5347 S/UNI-PLUS APS SOFTWARE REFERENCE DESIGN 3.7.1 Local Detected Conditions and Requests 3.7.1.1 Signal Fail (SF) and Signal Degrade (SD) Request For SF and SD condition, the generated K1 and K2 byte will be the following: K1 Byte SF/SD Code SF/SD Channel # No Change K2 Byte 1101 3.7.1.2 Signal Failure and Signal Degrade Clearing Request For revertive switching, when a local condition that caused an automatically initiated switch clears, the Wait-to-Restore (WTR) state is activated. The generated K1 and K2 byte is: K1 Byte 0110 WTR Channel # No Change K2 Byte 1101 3.7.1.3 Wait-To-Restore Timed Out Request After the WTR times out, the APS controller will issue "No Request" request on the K1 Byte and requests to switch the protected traffic back to the working channel. K1 Byte No Request 1111 (Default) No Change K2 Byte 1101 15 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMINARY REFERENCE DESIGN PMC- 971116 ISSUE 2 PM5347 S/UNI-PLUS APS SOFTWARE REFERENCE DESIGN 3.7.2 Remote Received Requests 3.7.2.1 Received SF or SD Request When the controller evaluates the received SF or SD request to be the highest priority request, the transmit K1 byte will be set to Reverse Request to acknowledge the SF or SD request. K1 Byte 0010 Same as Received K1 K2 Byte Same as K1 Channel # 1101 3.7.2.2 Received Reverse Request The Reverse Request indicates that the remote node has acknowledged the local switch request. The controller will perform the bridge and select action. K1 Byte No Change No Change K2 Byte Change to Request Channel 1101 3.7.2.3 Received Wait-To-Restore Request The received "Wait-to-Restore" request indicates that the remote site is initiating a wait period before requesting to switch back to the working channel. The local site does not have to take any actions and should still transmit the same APS bytes. K1 Byte No Change No Change No Change K2 Byte 1101 16 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMINARY REFERENCE DESIGN PMC- 971116 ISSUE 2 PM5347 S/UNI-PLUS APS SOFTWARE REFERENCE DESIGN 3.7.2.4 Received No-Request Request The received "No Request" request indicates that the remote site is ready to switch traffic from the protection channel back to the working channel. The local site will issue a "No Request" to acknowledge the request and bridge the extra channel traffic back to the protection channel. K1 Byte 0000 Same as Received K1 K2 Byte 1111 1101 17 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMINARY REFERENCE DESIGN PMC- 971116 ISSUE 2 PM5347 S/UNI-PLUS APS SOFTWARE REFERENCE DESIGN 3.8 Select and Bridge Channel Traffic The selector and bridge are controlled through on board configuration registers of the Octal PLUS. The APS control/status register is located in address x782. All the bits in the APS register can be either read or written. Table 9: APS Control/Status Register x782 Bit 7 6 5 4 3 2 1 0 Bit Name unused APSS[2] APSS[1] APSS[0] unused APSB[2] APSB[1] APSB[0] "000" => Extra Traffic Control the bridge Control the selector to each of the seven working channels Description The values for the control signals are determined from the receive and the transmit APS K1 and K2 bytes. Bridging takes place whenever the received K1 bytes requests a bridge unless the request is invalid. The channel to be bridged will be indicated in the lower nibble of the received K1 byte. The upper nibble of the transmit K2 byte will indicate the channel currently bridged on the protection channel. Selecting takes place when there is a match between the transmitted K1 and received K2 bytes. The controller will select the channel indicated in the APS bytes by writing values into the APS register. 18 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMINARY REFERENCE DESIGN PMC- 971116 ISSUE 2 PM5347 S/UNI-PLUS APS SOFTWARE REFERENCE DESIGN 4 4.1 IMPLEMENTATION Development Tools The APS controller program is written in FORTH and HC16 Assembly languages using polyFORTH software development system from Forth, Inc. (www.forth.com). Some basic knowledge of FORTH is helpful in understanding the code. FORTH was chosen as the programming environment because it is well suited for code development for microcontrollers such as the HC16 sitting on the SWAN board. FORTH provides easy tools for development and debugging without the need for any extra program tools such as compilers and linkers. The polyFORTH environment is also interactive so there is no need to recompile the code for each change implemented. Each FORTH program is defined and constructed from words. There are a number of core words that are common in every FORTH, and by using these words more words can be constructed. Routines in FORTH are a collection of words. In contrast to other programming languages like C and FORTRAN, FORTH operates in reverse polish notation (RPN). This requirement arises from the simple architecture of FORTH; built on the concept of a parameter stack and a return stack. This architecture lends itself well to microcontroller environments. The majority of the APS controller program has been written in assembly to minimize software execution time. The SWAN board uses a 16.78 MHz HC16 microcontroller. Each instruction cycle is 30 ns and each write or read to the Octal PLUS boards takes approximately 200 ns. New APS bytes require three frames to be captured and filtered by the S/UNI-PLUS devices. A complete protection switch requires a total of three APS bytes changes to take place. Actual measurement of switching time was taken from the implemented APS setup as described. The measurement was taken from when a failure has been detected to when the local site has finished selecting the protected line. The measured time was within the Bellcore GR-253-CORE switching requirement of 50 ms. Appendix A contains the entire code listing in both assembly and forth. Because the assembly code was developed in the FORTH RPN environment, the assembly operand precedes the mnemonic. The '\' character suppresses compilation and is used to add comments to the code. In addition, FORTH comments are also demarcated by '(' and ')'. These are used interchangeably throughout the code. 19 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMINARY REFERENCE DESIGN PMC- 971116 ISSUE 2 PM5347 S/UNI-PLUS APS SOFTWARE REFERENCE DESIGN 4.2 Program Structure and Routines The controller program is implemented by various interrupt service routines as described in the functional description. This section goes through the names and functions of the main routines implemented for the program. The naming convention used in this program for labeling routines is with "<" and ">". Figure 5 shows the overall program structure of the controller software. All the interrupts generated from the Octal PLUS board are processed by the interrupt service routine, 20 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMINARY REFERENCE DESIGN PMC- 971116 ISSUE 2 PM5347 S/UNI-PLUS APS SOFTWARE REFERENCE DESIGN Figure 5: Program Structure < PT-ISR > BERM Clearing or WTR Time Out < PLUS-ISR > Check interrupt bits for all S/UNI-PLUS < SD-ISR > Check BIP Error BERM_INT =1 or WTR_INT = 1 SD_INT = 1 SF_INT = 1 or APS_INT = 1 < CHK-INT > Interrupt Check Subroutines < SF-INT > < SD-INT > < APS-INT > < WTR-INT > < BERM-INT > Check interrupt flags SF_REQ =1 or SD_REQ = 1 Or REMOTE_REQ =1 < CHK-REQ > Check request flags Local Requests Remote Requests Local Request Subroutines < Local-SF-Declare > < Local-SD-Declare > < Local-WTR-Declare > < Local-No-Request > < Clearing > Remote Request Subroutines < Remote-SF-SD > < Remote-WTR > < Remote-RR > < Remote-NR > < SWITCHING > < SELECT> Generate new K1/K2 bytes < WR-K1-K2> Write K1, K2 APS Bytes 21 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMINARY REFERENCE DESIGN PMC- 971116 ISSUE 2 PM5347 S/UNI-PLUS APS SOFTWARE REFERENCE DESIGN The Interrupt Check Subroutines < SF - INT > < SD - INT > < APS - INT > < BERM - INT > < WTR - INT > Action Set SF_REQ flag if interrupt result in a valid request Set SD_REQ flag if interrupt result in a valid request Load Received K1, K2 Bytes, Set REMOTE_REQ flag Reset BERM Values, calls < SF - INT > to evaluate Jumps to issue No Request subroutine The PRELIMINARY REFERENCE DESIGN PMC- 971116 ISSUE 2 PM5347 S/UNI-PLUS APS SOFTWARE REFERENCE DESIGN Table 11: Local Request Subroutines Local Request Subroutines < LOCAL - SF - DECLARE > < LOCAL - SD - DECLARE > < LOCAL - WTR - DECLARE > < LOCAL - NO - REQUEST > Action Set TX_K1 to send "D" as request Set TX_K1 to send "B" as request Set TX_K1 to send "6" as request Set TX_K1 to send "0" as request For remote request, Remote Request Subroutines < REMOTE - SF - SD > < REMOTE - WTR > < REMOTE - RR > < REMOTE - NR > Action Set TX_K1 to send Reverse Request ( 2 ) Declare SD,SF if any local SF,SD outstanding Acknowledge Reverse Request, Perform Switch Set TX_K1 to send No Request ( 0 ) The Switching Subroutines < BRIDGE > < SELECT > < SET-RX-APS > < WR-APS-REG > Function Set up the transmit APS channel, APS_TX, address Set up the Octal PLUS logic address map Enable APS byte detection interrupt for the current APS receive (APS_RX) channel Write bridge and select values into Octal-PLUS APS Control and Status Register 23 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMINARY REFERENCE DESIGN PMC- 971116 ISSUE 2 PM5347 S/UNI-PLUS APS SOFTWARE REFERENCE DESIGN 4.2.1 Conventions Used In the APS controller program implemented, SF condition is represented by "D" (higher priority) and SD condition is represented by "B" (higher priority). For carrying extra channel traffic, K1 is set to "0F" and K2 to "FD". 4.2.2 Channel Addressing After a working channel has been switched to the protection channel, the protection channel S/UNI-PLUS will select the failure channel to listen for recovery and the protected working channel S/UNI-PLUS will perform APS signaling. As a result, the logic channel address need to be changed when a protection switch has occurred. Figure 5 shows the addressing of the Octal PLUS logic channels during a switch. A total of eight chip selects are used to control and monitor the 8 S/UNI-PLUS devices on the Octal PLUS board. During configuration, address C0000H to C3800H are assigned to the eight chip selects at a spacing of 800H bytes. The left address map in figure 5 shows the normal addressing setup with CH1 at C0000H and proceeds up to C3000 for CH7. As for the APS channel, the addressing is separate into two components: transmit APS channel (APS_TX) and receive APS channel (APS_RX). Both TX_APS and RX_APS are assigned th to address C3800H ( 8 S/UNI-PLUS ) during configuration. At this point, both transmit and receive APS K1 and K2 bytes signaling are done through the eighth channel S/UNI-PLUS. When a channel failure has occurred, the local site bridges the working channel's transmit traffic over the protection channel. The change in addressing is shown nd in figure 5 as the middle address map. The TX_APS address has changed to 2 S/UNI-PLUS's address (C0800H). This allows the second S/UNI-PLUS now to act as the TX_APS channel. This addressing change is transparent to the remote site, since it continues to receive APS bytes signaling on the protection channel line. The right hand address map shows the addressing after a selection nd has taken place. RX_APS has been changed to 2 S/UNI-PLUS since it will now act as the receive APS channel. Logical channel 2 address has been changed th to C3800H to reflect that the 8 S/UNI-PLUS is listening to channel 2 line for th recovery. When the 8 S/UNI-PLUS has detected that the channel 2 line has recovered, the address map will revert back to the original logic channel to physical address mapping shown in figure 5. 24 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMINARY REFERENCE DESIGN PMC- 971116 ISSUE 2 PM5347 S/UNI-PLUS APS SOFTWARE REFERENCE DESIGN Figure 5: Address Map after Bridge and Selection Logic Channel Physical Address CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7 C0000 C0800 C1000 Logic Channel Physical Address CH 1 CH 2 CH 3 C0000 C0800 C1000 C1800 C2000 C2800 C3000 Logic Channel Physical Address CH 1 CH 2 CH 3 CH 4 CH 5 C0000 C3800 C1000 C1800 C2000 C2800 C3000 CH2 Fibre Failure C1800 C2000 C2800 C3000 CH 4 CH 5 Bridge CH2 traffic onto protection channel CH 6 CH 7 Select Protection Channel traffic for CH2 S/UNI-PLUS, route link 2 traffic to protection th channel 8 S/UNIPLUS CH 6 CH 7 TX_APS RX_APS C3800 C3800 TX_APS RX_APS C0800 C3800 TX_APS RX_APS C0800 C0800 NORMAL BRIDGED PROTECTED 25 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMINARY REFERENCE DESIGN PMC- 971116 ISSUE 2 PM5347 S/UNI-PLUS APS SOFTWARE REFERENCE DESIGN 5 REFERENCES * * PMC-Sierra, Inc., PM5347 S/UNI-PLUS Data Sheet, Issue 5, September 1996 PMC-Sierra, Inc., Network Survivability Using Automatic Protection Switching(APS) Over SONET/SDH Point-to-Point & Ring Networks, Issue 2, June 1996 Bell Communication Research - SONET Transport Systems: Common Generic Criteria, GR-253-CORE, Issue 2, December 1995 ANSI, Synchronous Optical Network (SONET) Automatic Protection Switching, ANSI T1.105.01-1994 Fiber Network Survivability, Tsong-Ho Wu Motorola Inc., M68HC16 Z Series User's Manual, MC68HC16ZUM/AD, 1997 * * * * 26 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMINARY REFERENCE DESIGN PMC- 971116 ISSUE 2 PM5347 S/UNI-PLUS APS SOFTWARE REFERENCE DESIGN 6 APPENDIX A Automatic Protection Switching Program Code 27 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ AUTOMATIC PROTECTION SWITCHING (APS) PROGRAM This program provides APS controller functionality to the Octal-PLUS with APS Reference Design Board This program runs on the HC16 on the SWAN reference board Edward Chen Applications PMC-Sierra, Inc. January 1998 \ SIM DEFINITIONS HOST HEX FFA00 CONSTANT FFA04 CONSTANT FFA11 CONSTANT FFA15 CONSTANT FFA17 CONSTANT FFA1B CONSTANT FFA1D CONSTANT FFA1F CONSTANT SIMMCR SYNCR PORTE DDRE PEPAR PORTF DDRF PFPAR \ \ \ \ \ \ \ \ Module System Port E Port E Port E Port F Port F Port F Configuration Register Clock Control Register Byte data reg. data direction reg. pin assignment reg. data reg. data direction reg. pin assignment reg. \ SIM DEFINITIONS CONT'D HOST EDATE HEX FFA44 CONSTANT CSPAR0 FFA48 CONSTANT CSBARBT FFA4C CONSTANT CSBAR0 FFA50 CONSTANT CSBAR1 FFA54 CONSTANT CSBAR2 FFA58 CONSTANT CSBAR3 FFA5C CONSTANT CSBAR4 FFA60 CONSTANT CSBAR5 FFA64 CONSTANT CSBAR6 FFA68 CONSTANT CSBAR7 FFA6C CONSTANT CSBAR8 FFA70 CONSTANT CSBAR9 FFA74 CONSTANT CSBAR10 \ INITIALIZE CHIP SELECTS HOST DEFINITIONS HEX : INIT-CHIP-SELECTS1 AAAA CSPAR0 F E! 02AA CSPAR1 F E! FC00 5B70 FC08 5B70 FC10 5B70 FC18 5B70 ; CSBAR2 CSOR2 CSBAR3 CSOR3 CSBAR4 CSOR4 CSBAR5 CSOR5 F E! 0F E! F E! 0F E! F E! 0F E! F E! 0F E! FFA46 FFA4A FFA4E FFA52 FFA56 FFA5A FFA5E FFA62 FFA66 FFA6A FFA6E FFA72 FFA76 CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CSPAR1 CSORBT CSOR0 CSOR1 CSOR2 CSOR3 CSOR4 CSOR5 CSOR6 CSOR7 CSOR8 CSOR9 CSOR10 ( S/UNI-PLUS #1 TO #4 ) ( PLUS-X0, C0000, CH1 ) ( PLUS-X1, C0800, CH2 ) ( PLUS-X2, C1000, CH3 ) ( PLUS-X3, C1800, CH4 ) \ INITIALIZE CHIP SELECTS HOST DEFINITIONS HEX : INIT-CHIP-SELECTS2 FC20 CSBAR7 F E! 5B70 CSOR7 0F E! FC28 CSBAR8 F E! 5B70 CSOR8 0F E! FC30 CSBAR9 F E! 5B70 CSOR9 0F E! FC38 CSBAR1 F E! 5B70 CSOR1 0F E! FFF8 CSBAR10 F E! 4841 CSOR10 0F E! ( S/UNI-PLUS #5 TO #8 ) ( PLUS-Y0, C2000, CH5 ) ( PLUS-Y1, C2800, CH6 ) ( PLUS-Y2, C3000, CH7 ) ( PLUS-Y3, C3800, CH8 APS ) ( IRQ3 IACK ) ; \ SERIAL OUTPUT ROUTINE VARIABLE CH-SEND HOST HEX CREATE ASC 30 C, 31 C, 32 C, 33 C, 34 C, 35 C, 36 C, 37 C, 20 C, 0D C, 0A C, \ \ 0, SP, 1, CR, 2, LF, 3, 4, 5, 6, 7, HOST DEFINITIONS HEX : INIT-SCI 0037 SCCR0 F E! 0008 SCCR1 F E! ; \ INITIALIZE PORTE AND PORTF HOST DEFINITIONS HEX : INIT-PORTF ( --- ) ( Initializes port F ) ( MODCLK/PF0=RED LED; IRQ1/PF1=YELLOW LED; IRQ2/PF2=GREEN LED ) ( rest are set as inputs ) 00 PORTF F EC! ( all zero at port outputs ) 08 PFPAR F EC! ( all I/O , CONFIGURE IRQ3 ) 07 DDRF F EC! ( PF0,1,2 = o/p ; rest i/p ) ; HOST HEX : INIT-PORTE ( --- ) ( Initializes port E ) EF PORTE F EC! ( all ones at port outputs ) 10 PEPAR F EC! ( PE five for xilinx, all I/O except PE4 - ) E2 DDRE F EC! ( PE1,PE5,PE6,PE7 O/P, rest I/O ) ; \ on-chip RAM ( 30 Nov 1997) HOST DEFINITIONS HEX FFB00 CONSTANT RAMMCR FFB04 CONSTANT RAMBAH FFB06 CONSTANT RAMBAL HOST DEFINITIONS HEX : INIT-ON-CHIP-RAM ( --- ) ( initialize on chip ram to sit in FF0000 TO FF03FF ) ( 0000 RAMMCR F E! ) ( unlock base addres registers ) 00FF RAMBAH F E! ( base address high word ) 0000 RAMBAL F E! ( base address low word ) 0800 RAMMCR F E! ( lock RAM base address so it can not be ch) 400 0 DO 0 I F E! 2 +LOOP ; \ GENERAL PURPOSE TIMER DEFINITIONS HOST EDATE HEX FF900 CONSTANT GPTMCR FF904 CONSTANT FF906 CONSTANT DDRGP FF907 CONSTANT FF908 CONSTANT OC1M FF90A CONSTANT FF90C CONSTANT PACTL FF90D CONSTANT FF90E CONSTANT TIC1 FF910 CONSTANT FF912 CONSTANT TIC3 FF914 CONSTANT FF916 CONSTANT TOC2 FF918 CONSTANT FF91A CONSTANT TOC4 FF91C CONSTANT FF91E CONSTANT TCTL1 FF91F CONSTANT FF920 CONSTANT TMSK1 FF921 CONSTANT FF922 CONSTANT TFLG1 FF923 CONSTANT FF924 CONSTANT CFORC FF925 CONSTANT FF926 CONSTANT PWMA FF927 CONSTANT GPTICR PDR TCNT PACNT TIC2 TOC1 TOC3 TI4/O5 TCTL2 TMSK2 TFLG2 PWMC PWMB \ GENERAL PURPOSE TIMER DEFINITIONS CONT'D HOST EDATE HEX ( GENERAL-PURPOSE TIMER MODULE REGISTERS ) FF928 CONSTANT PWMCNT FF92A CONSTANT PWMBUFA FF92B CONSTANT PWMBUFB FF92C CONSTANT PRESCL \ INITIALIZE GPT FOR IC1 INPUT HOST EDATE HEX CODE INIT-GPT D ,E ,X ,Y ,Z ,K PSHM 0F # LDAB TBEK 0083 # LDD GPTMCR STD \ interr. arbitration 0450 # LDD GPTICR STD \ vectr base addr 50 , req. level 0001 # LDD TCTL1 STD \ IC1 on RISING edge only 0106 # LDD TMSK1 STD \ enable IC1, /256 0000 # LDD TFLG1 STD \ clear IC1 flag 00 # LDAB TBEK D ,E ,X ,Y ,Z ,K PULM NEXT \ ROUTINE FOR SELECTING CURRENT S/UNI-PLUS VARIABLE NDEV HOST HEX DEFINITIONS : DEV CR ." DEVICE SET TO ADDR: " NDEV @ U. CR ; : SET 800 * 800 - NDEV ! ; \ SHOWS S/UNI-PLUS # 1 REGISTERS HOST DEFINITIONS HEX : Z1 ( --- ) ( read all S/UNI-PLUS registers ) CR ." S/UNI-PLUS REGISTERS ." 0123456789ABC CR 80 0 DO I 2 U.R ." --- " 10 0 DO I J + C EC@ ." " 2 U.R LOOP CR 10 +LOOP HOST HEX : WX0 ( b a --- ) C EC! ; HOST HEX : RX0 ( a --- ) C EC@ . ; HOST HEX : RMX0 ( m a --- ) C EC@ AND . ; HOST HEX : RSX0 ( A --- ) C EC@ ; " D E CR F" ; \ SHOWS S/UNI-PLUS # 2 REGISTERS HOST DEFINITIONS HEX : Z2 ( --- ) ( read all S/UNI-PLUS registers ) CR ." S/UNI-PLUS REGISTERS ." 0123456789ABC CR 80 0 DO I 2 U.R ." --- " 10 0 DO I J + 800 + C EC@ ." " 2 U.R CR 10 +LOOP HOST : WX1 ( b a --- ) 800 + C EC! ; HOST : RX1 ( a --- ) 800 + C EC@ . ; " D E CR F" LOOP ; \ SHOWS S/UNI-PLUS # 3 REGISTERS HOST DEFINITIONS HEX : Z3 ( --- ) ( read all S/UNI-PLUS registers ) CR ." S/UNI-PLUS REGISTERS ." 0123456789ABC CR 80 0 DO I 2 U.R ." --- " 10 0 DO I J + 1000 + C EC@ ." " 2 U.R CR 10 +LOOP HOST : WX2 ( b a --- ) 1000 + C EC! ; HOST : RX2 ( a --- ) 1000 + C EC@ . ; " D E LOOP ; CR F" \ SHOWS S/UNI-PLUS # 4 REGISTERS HOST DEFINITIONS HEX : Z4 ( --- ) ( read all S/UNI-PLUS registers ) CR ." S/UNI-PLUS REGISTERS ." 0123456789ABC CR 80 0 DO I 2 U.R ." --- " 10 0 DO I J + 1800 + C EC@ ." " 2 U.R CR 10 +LOOP HOST : WX3 ( b a --- ) 1800 + C EC! ; HOST : RX3 ( a --- ) 1800 + C EC@ . ; " D E LOOP ; CR F" \ SHOWS S/UNI-PLUS # 5 REGISTERS HOST DEFINITIONS HEX : Z5 ( --- ) ( read all S/UNI-PLUS registers ) CR ." S/UNI-PLUS REGISTERS ." 0123456789ABC CR 80 0 DO I 2 U.R ." --- " 10 0 DO I J + 2000 + C EC@ ." " 2 U.R CR 10 +LOOP HOST : WY0 ( b a --- ) 2000 + C EC! ; HOST : RY0 ( a --- ) 2000 + C EC@ . ; " D E LOOP ; CR F" \ SHOWS S/UNI-PLUS # 6 REGISTERS HOST DEFINITIONS HEX : Z6 ( --- ) ( read all S/UNI-PLUS registers ) CR ." S/UNI-PLUS REGISTERS ." 0123456789ABC CR 80 0 DO I 2 U.R ." --- " 10 0 DO I J + 2800 + C EC@ ." " 2 U.R CR 10 +LOOP HOST : WY1 ( b a --- ) 2800 + C EC! ; HOST : RY1 ( a --- ) 2800 + C EC@ . ; " D E LOOP ; CR F" \ SHOWS S/UNI-PLUS # 7 REGISTERS HOST DEFINITIONS HEX : Z7 ( --- ) ( read all S/UNI-PLUS registers ) CR ." S/UNI-PLUS REGISTERS ." 0123456789ABC CR 80 0 DO I 2 U.R ." --- " 10 0 DO I J + 3000 + C EC@ ." " 2 U.R CR 10 +LOOP HOST : WY2 ( b a --- ) 3000 + C EC! ; HOST : RY2 ( a --- ) 3000 + C EC@ . ; " D E LOOP ; CR F" \ SHOWS S/UNI-PLUS # 8 REGISTERS HOST DEFINITIONS HEX : Z8 ( --- ) ( read all S/UNI-PLUS registers ) CR ." S/UNI-PLUS REGISTERS ." 0123456789ABC CR 80 0 DO I 2 U.R ." --- " 10 0 DO I J + 3800 + C EC@ ." " 2 U.R CR 10 +LOOP HOST : WY3 ( b a --- ) 3800 + C EC! ; HOST " D E LOOP ; CR F" : RY3 ( a --- ) 3800 + C EC@ . ; \ SHOWS CURRENT S/UNI-PLUS REGISTERS HOST DEFINITIONS HEX EDATE : ZZ ( --- ) ( read all S/UNI-PLUS registers ) CR CR ." S/UNI-PLUS CHANNEL " NDEV @ 800 + 800 / . CR ." S/UNI-PLUS REGISTERS ." 0123456789ABC CR 80 0 DO I 2 U.R ." --- " 10 0 DO I J + NDEV @ + C EC@ ." " 2 U.R CR 10 +LOOP HOST HEX : WDZ ( b a --- ) NDEV @ + C EC! ; HOST HEX : RDZ ( a --- ) NDEV @ + C EC@ . ; HOST HEX : RDMZ ( m a --- ) NDEV @ + C EC@ AND . ; HOST HEX : RDSZ ( a --- ) NDEV @ + C EC@ ; " D E CR F" LOOP ; \ DISABLE AND ENABLE INTERRUPTS HOST DEFINITIONS HEX CODE EI ( --- ) \ ENABLE INTERRUPTS FF1F # ANDP \ CPU lowest priority , everybody disturbs NEXT CODE DI ( --- ) \ DISABLE INTERRUPTS 00C0 # ORP \ CPU highest priority , nobody can disturb NEXT \ STATUS MONITOR 15:39 12-01-97 HEX DEFINITIONS HEX : STAT CR CR ." S/UNI-PLUS CHANNEL " NDEV @ 800 + 800 / . CR ." SUNI_INTR (02) " FF 02 RDMZ ." RLOPI: " 02 02 RDSZ AND 0 > ABS . ." RSOPI: " 01 02 RDSZ AND 0 > ABS . CR ." APS_STATS (0B) " 1D 0B RDMZ CR ." RSOP_INTR (11) " 7F 11 RDSZ AND DUP DUP . ." LOSV : " 04 AND 0 > ABS . ." LOFV: " 02 AND 0 > ABS . CR ." RLOP_INTR (19) " 0F 19 RDMZ CR ." RLOP_STAT (18) " 03 18 RDMZ ." LAISV: " 02 18 RDSZ AND 0 > ABS . CR ." BERM_INTR (71) " 01 71 RDMZ CR CR ; \ PERFORMANCE MONITORING HOST DEFINITIONS HEX : PMON CR CR ." S/UNI-PLUS CHANNEL " CR 00 00 WDZ ." RSOP_BIP = " 13 RDZ 12 RDZ ." RLOP_BIP = " 0F 1C RDMZ 1B ." RLOP_FEBE = " 0F 1F RDMZ 1E ." RPOP_BIP = " 39 RDZ 38 RDZ ." RPOP_FEBE = " 3B RDZ 3A RDZ ." RCELL_CNT = " 1F 5B RDMZ 5A 12:23 12-01-97 NDEV @ 800 + 800 / . CR RDZ 1A RDZ CR RDZ 1D RDZ CR CR CR RDZ 59 RDZ CR ." TCELL_CNT = " 1F 66 RDMZ 65 RDZ 64 RDZ CR CR ; \ INIT-PROGRAM HOST DEFINITIONS HEX 0 17 THRU HOST DEFINITIONS HEX : INIT-MICRO DI INIT-ON-CHIP-RAM INIT-CHIP-SELECTS1 INIT-CHIP-SELECTS2 INIT-PORTF INIT-PORTE EI ; 12:23 12-01-97 \ \ REGISTER DEFINITIONS FOR S\UNI-PLUS HOST DEFINITIONS HEX 0000 CONSTANT MASTER_RESET 0002 CONSTANT MASTER_INTERRUPT 0B 0C 0D 10 11 19 1A 1B 1C 20 CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT APS_CONTROL_STATUS RECEIVE_K1 RECEIVE_K2 RSOP_CONTROL RSOP_STATUS RLOP_INTERRUPT RLOP_BIP_LSB RLOP_BIP_ISB RLOP_BIP_MSB TLOP_CONTROL ( 0x00 ) ( 0x02 ) ( ( ( ( ( ( ( ( ( ( 0x0B 0x0C 0x0D 0x10 0x11 0x19 0x1A 0x1B 0x1C 0x20 ) ) ) ) ) ) ) ) ) ) \ PLUS REG'S CONT HOST DEFINITIONS HEX 22 CONSTANT TRANSMIT_K1 23 CONSTANT TRANSMIT_K2 70 71 72 73 74 75 CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT BERM_CONTROL BERM_INTERRUPT BERM_LINE_BIP_LSB BERM_LINE_BIP_MSB BERM_LINE_BIP_THR_LSB BERM_LINE_BIP_THR_MSB ( 0x22 ) ( 0x23 ) ( ( ( ( ( ( 0x70 0x71 0x72 0x73 0x74 0x75 ) ) ) ) ) ) 82 CONSTANT OCTAL_APS_CONTROL ( 0x82 ) \ APS VARIABLE LIST HOST HEX VARIABLE PLUS_LOS 9 ALLOT VARIABLE PLUS_LOF 9 ALLOT VARIABLE PLUS_AISL 9 ALLOT VARIABLE PLUS_BERM 9 ALLOT VARIABLE SF_VAL 9 ALLOT VARIABLE SD_VAL 9 ALLOT VARIABLE SF_INT VARIABLE BERM_INT VARIABLE APS_INT VARIABLE SF_REQ VARIABLE SD_REQ ( 02 Dec 1997) \ \ \ \ LOS STATUS LOF STATUS AISL STATUS BERM STATUS VARIABLE SD_INT VARIABLE WTR_INT \ INTERRUPT FLAGS VARIABLE BERM_REQ VARIABLE WTR_REQ \ REQUESTS FLAGS \ APS VARIABLE LIST CONT'D HOST HEX VARIABLE CUR_REQ_PRI VARIABLE NEW_REQ_PRI VARIABLE REQ_CHAN VARIABLE BERM_ENABLE VARIABLE TEMP1 VARIABLE TEMP3 VARIABLE VARIABLE VARIABLE VARIABLE VARIABLE TX_K1 RX_K1 SF_SUM REMOTE_REQ APS_REG VARIABLE BERM_TOGGLE VARIABLE TEMP2 VARIABLE TEMP VARIABLE TX_K2 VARIABLE RX_K2 VARIABLE REMOTE_CMD 10:39 21/11/97 \ PRIORITY VARS \ BERM VARIABLES \ STORES K1/K2 BYTES \ APS VARIABLE LIST CONT'D VARIABLE SD_COUNT VARIABLE SD_LIMIT VARIABLE BIP_COUNT VARIABLE SD_THR VARIABLE SD_CLEAR_WAIT VARIABLE SD_CLEAR_CNT 9 ALLOT VARIABLE PICRV VARIABLE WTR_LIMIT VARIABLE BT_FLAG VARIABLE BT_COUNT VARIABLE BT_TOGGLE VARIABLE SD_CHK VARIABLE CLEAR_CHAN VARIABLE CNT VARIABLE PLUS_ADDR 20 VARIABLE APS_RX \ INITIALIZE S/UNI-PLUS VARIABLE PITRV VARIABLE WTR_COUNT VARIABLE BT_LIMIT VARIABLE SF_CHK VARIABLE PT_USED ALLOT VARIABLE APS_TX REGISTERS TO DETECT ERROR ( 01 Dec 1997) HOST DEFINITIONS HEX : INIT-APS-REG CR ." INITIALIZING APS" CR 06 RSOP_CONTROL WDZ ( BERM SETUP TO DETECT 1e-4 BER ) 81 BERM_CONTROL WDZ 34 BERM_LINE_BIP_LSB WDZ 00 BERM_LINE_BIP_MSB WDZ 4D BERM_LINE_BIP_THR_LSB 00 BERM_LINE_BIP_THR_MSB 20 TLOP_CONTROL ; WDZ WDZ WDZ \ INITIALIZE REGISTER FOR APS SIGNALLING AND DETECTION HOST DEFINITIONS HEX : INIT-APS-REGA CR ." INITIALIZING APS SUNI-PLUS " CR 40 APS_CONTROL_STATUS WDZ 20 TLOP_CONTROL WDZ ; \ PHYSICAL PERMENENT ADDRESS OF S/UNI-PLUS HOST HEX CREATE ADDR_MAP 0000 , 0000 , 800 , 1000 , 1800 , 2000 , 2800 , 3000 , 3800 , \ INITIALIZE VARIABLES HOST HEX DEFINITIONS : INIT-APS-VAR1 8 0 DO 0 PLUS_LOS I + ! 0 PLUS_LOF I + ! 0 PLUS_BERM I + ! 0 PLUS_AISL I + ! 0 SF_VAL I + ! 0 SD_VAL I + ! 0 SD_CLEAR_CNT I + ! LOOP 00 SF_INT ! 00 APS_INT ! 00 WTR_INT ! 00 BERM_TOGGLE ! 00 BERM_INT ! 00 TEMP1 ! 00 TEMP2 ! 00 TEMP3 ! 00 REMOTE_CMD ! 00 REMOTE_REQ ! 00 CUR_REQ_PRI ! 00 APS_REG C! ; \ INITIALIZE VARIABLE CONT'D HOST DEFINITIONS HEX : INIT-APS-VAR2 0F TX_K1 C! FD TX_K2 C! 00 SF_SUM C! 00 SF_REQ ! 00 BT_COUNT ! 00 SD_REQ ! 00 RX_K1 C! 00 RX_K2 C! 01 REQ_CHAN C! 00 NEW_REQ_PRI C! 00 TEMP C! 00 SF_CHK ! 00 SD_CHK ! 00 PT_USED ! 00 CLEAR_CHAN ! 9 0 DO -800 800 I * + PLUS_ADDR I 2 * + ! LOOP 00 PLUS_ADDR ! 3800 APS_TX ! 3800 APS_RX ! ; \ INIT-APS ( 05 Dec 1997) HOST DEFINITIONS HEX : INIT-APS INIT-APS-VAR1 INIT-APS-VAR2 INIT-APS-REG ; HOST DEFINITIONS HEX : INIT-VARS INIT-APS-VAR1 INIT-APS-VAR2 ; \ DISPLAY APS STATUS HOST DEFINITIONS HEX : SHOW-OCTAL-STATUS CR ." APS CONTROL STATUS REGISTER [ SELECT | BRIDGE ]: APS_REG C@ U. CR CR ." TRANSMIT K1 BYTE: " TX_K1 C@ U. CR ." K2 BYTE: " TX_K2 C@ U. CR CR ." RECEIVED K1 BYTE: " RX_K1 C@ U. CR ." K2 BYTE: " RX_K2 C@ U. CR CR ; \ INITIALIZE IC1 USE FOR SD DETECTION HOST DEFINITIONS HEX CODE INIT-SD D ,E ,X ,Y ,Z ,K PSHM 00 # LDAB TBEK 00C8 # LDD SD_LIMIT STD 0000 # LDD SD_COUNT STD 003E # LDD SD_THR STD 0000 # LDD SD_INT STD 0014 # LDAB SD_CLEAR_WAIT STAB D ,E ,X ,Y ,Z ,K PULM NEXT " ( 0.05 SEC, BER => -5 ) ( 62, for -5, -6, -7 ) ( WAIT 5 SEC TO CLEAR) \ PERIODIC INTERRUPT TIMER ROUTINE HOST DEFINITIONS HEX LABEL \ 01 # \ 3E # 00 # 0540 0101 0005 0000 LDAB BERM_LINE_BIP_MSB ,X STAB LDAB BERM_LINE_BIP_THR_LSB ,X STAB LDAB TBEK 01 # LDD BERM_ENABLE STD # LDD PICRV STD # LDD PITRV STD ( 0.0625 SEC INTERVAL ) # LDD BT_LIMIT STD # LDD BT_COUNT STD \ \ SET FLAG VALUES HOST DEFINITIONS HEX : SFLAG 1 PLUS_LOS 1 + C! 1 PLUS_LOF 1 + C! ; HOST DEFINITIONS HEX : CFLAG 0 PLUS_LOS 1 + C! 0 PLUS_LOF 1 + C! ; \ DEBUG OUTPUT HOST DEFINITIONS HEX : PLUSV CR ." REQ_CHAN: " REQ_CHAN C@ U. CR ." TEMP1: " TEMP1 @ U. CR ." BERM_INT: " BERM_INT @ U. CR ." TEMP2: " TEMP2 @ U. ." TEMP3: " TEMP3 @ U. CR ." SF_INT: " SF_INT @ U. ." APS_INT: " APS_INT @ U. CR ." SF_SUM: " SF_SUM C@ U. ." WTR_INT: " WTR_INT @ U. CR ." SD_REQ: " SD_REQ @ U. ." SF_REQ: " SF_REQ @ U. CR ." REMOTE_REQ: " REMOTE_REQ @ U. ." REMOTE_CMD: " REMOTE_CMD @ U. CR ." NEW_REQ_PRI: " NEW_REQ_PRI C@ U. ." CUR_REQ_PRI: " CUR_REQ_PRI C@ U. CR ." APS REGISTER: " APS_REG C@ U. CR ; \ SHOW SF AND SD STATUS FOR EIGHT CHANNELS HOST HEX DEFINITIONS : SHOW-OCTAL-REG CR ." PLUS_LOS: "8 CR CR ." PLUS_LOF: "8 CR CR ." PLUS_BERM: " 8 CR CR ." SF_VAL: "8 CR CR ." SD_VAL: "8 CR ; \ SHOW APS STATUS HOST DEFINITIONS HEX : ILOOP CR CR ." S/UNI-PLUS 1 2 3 4 5 6 7 " CR ." --------------------------------- " 1 DO PLUS_LOS I + C@ U. ." 1 DO PLUS_LOF I + C@ U. ." 1 DO PLUS_BERM I + C@ U. ." 1 DO SF_VAL I + C@ U. ." 1 DO SD_VAL I + C@ U. ." " LOOP " LOOP " LOOP " LOOP " LOOP SHOW-OCTAL-REG CR ; HOST HEX : APS SHOW-OCTAL-STATUS ILOOP ; \ PLUS-ADDR OUTPUT HOST DEFINITIONS HEX : ADDRV CR ." PLUS ADDRESS " CR ." 1 2 3 4 5 6 7 " CR ." ------------------------------------- " CR ." " PLUS_ADDR 2 + @ . ." " PLUS_ADDR 4 + @ . PLUS_ADDR 6 + @ . PLUS_ADDR 8 + @ . PLUS_ADDR A + @ . PLUS_ADDR C + @ . PLUS_ADDR E + @ . CR CR ." APS_TX: " APS_TX @ U. CR CR ." APS_RX: " APS_RX @ U. CR ; HOST DEFINITIONS HEX : OCTAL ILOOP ADDRV ; \ WTR VARIABLES OUTPUT HOST DEFINITIONS HEX : WTRV CR ." PICRV: " PICRV @ U. CR ." PITRV: " PITRV @ U. CR ." PICR: " PICR F E@ U. CR ." PITR: " PITR F E@ U. CR ." WTR_COUNT: " WTR_COUNT @ U. CR ." WTR_LIMIT: " WTR_LIMIT @ U. CR ; \ BERM VARIABLES OUTPUT HOST DEFINITIONS HEX : BERMV CR ." PICRV: " PICRV @ U. ." PITRV: " PITRV @ U. CR ." PICR: " PICR F E@ U. ." PITR: " PITR F E@ U. CR ." BT_COUNT: " BT_COUNT @ U. ." BT_LIMIT: " BT_LIMIT @ U. CR ." BERM_ENABLE " BERM_ENABLE @ U. CR ." BERM_TOGGLE " BERM_TOGGLE @ U. ." BT_TOGGLE " BT_TOGGLE @ U. CR ." PT_USED " PT_USED @ U. CR ; \ DISPLAY SD ISR VARIABLE VALUES HOST DEFINITIONS HEX : SDV CR ." SD_LIMIT: " SD_LIMIT @ . ." SD_COUNT: " SD_COUNT @ . CR ." SD_THR: " SD_THR @ . ." SD_VAL: " SD_VAL C@ U. CR ." SD_INT: " SD_INT @ U. CR ." SD_CLEAR_WAIT: " SD_CLEAR_WAIT C@ U. CR ." SD_VAL: " SD_VAL C@ U. CR CR ." CHANNEL 1 2 3 4 5 6 7" CR ." --------------------------------- " CR ." SD_VAL: " SD_VAL 8 DUMP CR ." SD CLEAR_CNT: " SD_CLEAR_CNT 8 DUMP CR ; \ READ OUT REGISTERS HOST DEFINITIONS HEX : KOUT CR ." TX_K1: " TX_K1 C@ U. ." TX_K2: " TX_K2 C@ U. CR ." RX_K1: " RX_K1 C@ U. ." RX_K2: " RX_K2 C@ U. CR ." REQ_CHAN: " REQ_CHAN C@ U. CR ." SF_CHK: " SF_CHK C@ U. CR ." SD_CHK: " SD_CHK C@ U. CR ; 08:15 12-01-97 \ LABEL 00 # 00 # 3800 RTS \ ROUTINE TO WRITE K1, K2 VALUES TO REGISTERS HOST DEFINITIONS HEX LABEL \ SET BANKS \ CLEARS INTERRUPTS AFTER SWITCHING ( 28 Dec 1997) HOST HEX LABEL APS_RX LDX 40 # LDAB APS_CONTROL_STATUS ,X STAB RTS \ |
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