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S/UNI-2XGE Reference Design Preliminary
PM3386
S/UNI-2XGE
S/UNI Dual Gigabit Ethernet Controller
Reference Design
Preliminary Issue 3: September, 2001
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use Document ID: PMC-2000991, Issue 3
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S/UNI-2XGE Reference Design Preliminary
Legal Information
Copyright
(c) 2001 PMC-Sierra, Inc. The information is proprietary and confidential to PMC-Sierra, Inc., and for its customers' internal use. In any event, you cannot reproduce any part of this document, in any form, without the express written consent of PMC-Sierra, Inc. PMC-2000991 (P3)
Disclaimer
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage.
Trademarks
S/UNI is a registered trademark of PMC-Sierra, Inc.
Patents
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S/UNI-2XGE Reference Design Preliminary
Contacting PMC-Sierra
PMC-Sierra 8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: (604) 415-6000 Fax: (604) 415-6200 Document Information: document@pmc-sierra.com Corporate Information: info@pmc-sierra.com Technical Support: apps@pmc-sierra.com Web Site: http://www.pmc-sierra.com
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Table of Contents
Legal Information ................................................................................................................ 2 Contacting PMC-Sierra ....................................................................................................... 3 Table of Contents ................................................................................................................ 4 List of Figures...................................................................................................................... 7 1 Introduction.................................................................................................................. 9 1.1 1.2 2 2.1 2.2 2.3 3 4 5 6 7 8 Reference Design Functionality.......................................................................... 9 Reference Design Features:............................................................................... 9 PL3 Drop Side Loop Back ................................................................................ 12 PL3 Transparent ............................................................................................... 13 Integration into a Multi-Service Reference Design System .............................. 14
Applications ............................................................................................................... 11
References ................................................................................................................ 15 Definitions.................................................................................................................. 16 Device block diagram ................................................................................................ 18 Reference Design Functional Description................................................................. 19 6.1 Block Diagram .................................................................................................. 19 System Functional description .................................................................................. 20 Implementation Description....................................................................................... 21 8.1 8.2 Root Drawing, Sheet 1...................................................................................... 21 2xGE Block, Sheet 2......................................................................................... 21 8.2.1 8.2.2 8.2.3 8.3 8.4 8.3.1 8.4.1 8.4.2 8.5 8.5.1 Optical Line Side Interface................................................................... 21 Optical Power Supply Filtering............................................................. 22 125MHz PHY Reference Clock Circuit ................................................ 22 GMII Interface ...................................................................................... 24 POS-PHY Level 3 Interface ................................................................. 24 Microprocessor Interface ..................................................................... 26 Power Filtering Recommendations...................................................... 28
2xGE Block, Sheet 3......................................................................................... 24 2xGE Block, Sheet 4......................................................................................... 24
2xGE Block, Sheet 5......................................................................................... 27
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8.6
FPGA Block, Sheet 6 ........................................................................................ 30 8.6.1 8.6.2 8.6.3 Control Register Function .................................................................... 31 S/UNI-2xGE POS-PHY Level 3 Interface ............................................ 33 Status LEDs and Reset Circuit ............................................................ 33 System Side POS-PHY Level 3 Interface............................................ 34 Configuration Circuit ............................................................................ 34 Power Supply Decoupling.................................................................... 35 100 MHz PL3 Clock Distribution .......................................................... 35 100 MHz Clock Source Switching........................................................ 36
8.7 8.8
FPGA Block, Sheet 7 ........................................................................................ 34 8.7.1 8.8.1 8.8.2 FPGA Block, Sheet 8 ........................................................................................ 34
8.9
FPGA Block, Sheet 9 ........................................................................................ 35 8.9.1 8.9.2
8.10 CPCI Interface Block, Sheet 10........................................................................ 36 8.10.1 CPCI Interface Controller..................................................................... 36 8.11 CPCI Interface Block, Sheet 11 ........................................................................ 37 8.11.1 CPCI J1 Connector .............................................................................. 37 8.11.2 ESD Strip ............................................................................................. 37 8.12 cPCI Power_Block, Sheet 12 ........................................................................... 37 8.12.1 Hot Swap Controller System Block...................................................... 38 8.13 System Interface, Sheet 13 .............................................................................. 39 8.13.1 POS-PHY Level 3 Interface ................................................................. 39 9 Physical Design considerations ................................................................................ 44 9.1 9.2 10 PCB Layout Issues ........................................................................................... 44 Thermal Issues ................................................................................................. 45 9.2.1 Sample calculations ............................................................................. 45
Electrical Design Considerations .............................................................................. 47 10.1 PECL Interface Issues ...................................................................................... 47 10.2 Optical Transceiver Terminations ..................................................................... 47 10.3 Power Up/Down Considerations....................................................................... 48 10.4 Grounding ......................................................................................................... 49 10.5 System Side Transmission Line Terminations .................................................. 49
11
Schematics Revision 1 .............................................................................................. 52
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PCB Layout Revision 1 ............................................................................................. 53 Bill of Materials (BOM) Revision 1 ............................................................................ 54
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List of Figures
Figure 1: PL3 Drop Side Loop Back ................................................................................. 12 Figure 2: PL3 Transparent ................................................................................................ 13 Figure 3: PM3386 Multi-Service Application ..................................................................... 14 Figure 4: PM3386 S/UNI-2xGE Block Diagram. ............................................................... 18 Figure 5: Reference Design Block Diagram...................................................................... 19 Figure 6: System Level Block Diagram............................................................................. 20 Figure 7: PM3386 to ODL Interface .................................................................................. 21 Figure 8: ODL to PM3386 Interface .................................................................................. 22 Figure 9: Ecliptek 125MHz Oscillator Waveform .............................................................. 23 Figure 10: S/UNI-2xGE Reference Design RSX Signal.................................................... 25 Figure 11: S/UNI-2xGE Reference Design RFCLK Signal ............................................... 26 Figure 12: 3.3V Analog Supply Filter Architecture ............................................................ 28 Figure 13: 1.8V Analog Filter Architecture ........................................................................ 29 Figure 14: FPGA Block Diagram....................................................................................... 31 Figure 15: S/UNI-2xGE Reference Design TSX Signal .................................................... 33 Figure 16: Host Processor cPCI Interface ........................................................................ 37 Figure 17: cPCI Hot Swap Controller................................................................................ 38 Figure 18: PM3386 Transmit SERDES to Optical Transmitter ......................................... 47 Figure 19: Optical Receiver to PM3386 SERDES ............................................................ 48 Figure 20: System Interface Terminations ........................................................................ 50 Figure 21: Series Source Termination .............................................................................. 51
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List of Tables
Table 1: CLK_125 Timing Requirements.......................................................................... 22 Table 2: Virtex Pin Distribution.......................................................................................... 30 Table 3: LED Display Function ......................................................................................... 34 Table 4: PL3 High Speed RX Interface, J11 ..................................................................... 40 Table 5: PL3 High Speed TX Interface, J10 ..................................................................... 42 Table 6: Reference Design PCB Stack Up (Preliminary).................................................. 44 Table 7: PM3386 Reliability Information .......................................................................... 45
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1
Introduction
The PM3386 S/UNI-2xGE standard product finds application in equipment implementing high density Gigabit Ethernet Interfaces. The PM3386 has dual channel SERDES and GMAC functional blocks with embedded FIFOs that provide a high density, low power solution for direct connection to optical modules. Alternatively, a GMII interface is provided for connection to Gigabit Ethernet physical layer devices. For connectivity to upstream devices the S/UNI-2xGE supports a POS-PHY Level 3 interface which provides full bandwidth support via a 32-bit interface operating at 104MHz. The S/UNI-2xGE may find application within Multi-Service Edge and Core routers. Gigabit Ethernet is also becoming more widespread within Internet points of presence as a low cost, high speed Layer 2 interconnect solution. The S/UNI-2xGE Reference Design provides a line card solution that can be integrated into a larger multi service reference design system via the common POS-PHY Layer 3 system interface. The line side supports independent user selectable optical or direct GMII interfacing on each channel. On the system side an FPGA provides configurable packet processing capability.
1.1
Reference Design Functionality
1. Supports one or two optical Gigabit Ethernet physical interfaces via a dual IEEE 802.3 compliant internal SERDES. 2. Provides access to a standard GMII interface for interconnection to external Gigabit Ethernet transceivers. 3. Provides a POS-PHY Level 3, 104 MHz, 32-bit System Interface to an external high-speed connector. 4. Optionally performs system side loopback of the POS-PHY Level 3 interface. 5. Initialization, configuration, control, and performance monitoring are provided via a CompactPCI bus interface.
1.2
Reference Design Features:
The reference design is based on a cPCI form factor card. The reference design will consist of: * * * * One PM3386 S/UNI-2xGE. Two Gigabit Ethernet capable Optical Transceivers. Access to the standard GMII interface via a high speed matched impedance connector. FPGA capable of supporting the 100MHz POS-PHY Level 3 interface for drop-side loop back, trfansparent or packet processing operations.
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* * *
One PLX PCI9030 Interface chip for interfacing to the host processor. Reference oscillators required for Gigabit Ethernet and POS-PHY L3 interfaces. Powered by +1.8 and +3.3 Volt supplies. +5.0 Volt components are avoided where possible.
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2
Applications
The S/UNI-2xGE Reference Design demonstrates a physical interface implementation for Gigabit Ethernet that can be used in the following applications where ethernet services are deployed. * * * Core/Edge Routers Multi-Service Switches/Routers SONET/SDH Transport Muxes
These applications typically integrate various interfaces including Gigabit Ethernet, ATM, SONET, or DS3. With the POS-PHY interface, numerous service cards implementing various physical layer protocols can be integrated into a common architecture implementing higher layer functions such as scheduling and traffic classification. This type of modularity increases expansion capabilities while simplifying line card development and aiding time to market. Connections between Edge and Core Routers within a POP, or Enterprise Routers and MultiService switches are also becoming attractive applications for Gigabit Ethernet. Please refer to the S/UNI-2xGE Technical Overview (PMC-1991728) for more information on S/UNI-2xGE applications. The 2xGE reference design operates in one of two modes: * * PL3 Drop Side Loop Back PL3 Transparent.
The following sections outline in more detail these two options.
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2.1
PL3 Drop Side Loop Back
Typically, the S/UNI-2xGE performs data recovery on the ingress Gigabit Ethernet streams, MAC level frame checking and then sends the frame to an upper layer device (such as an IP processor) via the POS-PHY Level 3 Interface. Extensive statistics for SNMP and RMON are maintained by the device. On the S/UNI-2xGE Reference Design the FPGA can be used to loop the received packets back to the PL3 compliant TX interface on the PM3386. This loop back is performed on a PHY by PHY basis (i.e. each packet will be looped back to same port from which it was received.) In addition, the FPGA can be configured to generate and/or receive packets on board. In the egress direction, the PL3 add data is formatted into physical frames with proper inter-frame gap, preamble and start of frame delimiter. The physical packet is then serialized for transmission via the optical interface or output to an external GE PHY via the GMII interface, as required.
Figure 1: PL3 Drop Side Loop Back
S/UNI-2xGE REFERENCE DESIGN
PM3386 S/UNI 2xGE Optical Link Gig Ethernet Test Unit Optical Link
TX+/RX+/or GMII
FPGA TX
POS-PHY Level 3 POS Packet Loop-back, Receive or Generate
SYS I/F Conn
TX+/RX+/or GMII
RX
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2.2
PL3 Transparent
Ingress processing will be performed identically to the PL3 Loopback mode discussed above. Upon output to the PL3 interface, the FPGA will be used to direct the packets to the POS-PHY Level 3 compliant RX interface provided via a high-speed connector. This interface will provide Ethernet frames to an external system such as an Ethernet tester or Link Layer device, as well as accept packets generated by this external system. If necessary, the FPGA can provide timing adjustments or packet processing for applications such as Ethernet over SONET. (See Application Note PMC-2001398 for more information). The POS-PHY Level 3 compliant TX interface on the PM3386 will accept packets via the FPGA. The egress data will then be properly formatted and output to the selected Gigabit Ethernet port.
Figure 2: PL3 Transparent
S/UNI-2xGE REFERENCE DESIGN
PM3386 S/UNI 2xGE
TX+/RX+/or GMII
Optical Link Gig Ethernet Test Unit Optical Link
FPGA TX
POS-PHY Level 3
SYS I/F Conn
Other PL3 Devices via Backplane
TX+/RX+/or GMII
RX
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2.3
Integration into a Multi-Service Reference Design System
As discussed in the Application Examples section, the S/UNI-2xGE reference design card may be implemented into a multi-service system that utilizes a number of PMC's other PL3 compliant devices. Such a system can provide multi service line interfaces including Ethernet over SONET.
Figure 3: PM3386 Multi-Service Application
POS-PHY Level 3
Gigabit Ethernet Line Card # 1
TX +/RX +/Copper GE PHY PM3386 S/UNI 2xGE
Upper Layer Device(s)
Scheduler
Gigabit Ethernet
Twisted Pair
Optical Transceiver
Switch Fabric
Classification/ Forwarding
Mag
Gigabit Ethernet
GMII
Switch Fabric Device
OC-48 POS Line Card # 2
Upper Layer Device(s)
Scheduler
OC-48
Optical Transceiver
TX +/RX +/-
PM5381 S/UNI 2488 Classification Forwarding Switch Fabric Device
OC-12 OC-12
Optical Transceiver Optical Transceiver Optical Transceiver
Quad OC-12 POS Line Card # n
Upper Layer Device(s)
Scheduler
PM5380 S/UNI 4x622 Classification Forwarding
OC-12 OC-12
Optical Transceiver
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3
References
1. CompactPCITM Specification, PICMG 2.0 R2.1, September 2, 1997. 2. IEEE 802.3 Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications. 3. PMC-Sierra, Inc., PMC-2001398 "Gigabit Ethernet Over SONET Using the S/UNI-2xGE", Issue 1, September, 2000. 4. PMC-Sierra, Inc., PMC-1991129 "PM3386 S/UNI-2xGE Dual Gigabit Ethernet Controller Data Sheet", Issue 5, November, 2000. 5. PMC-Sierra, Inc., PMC-980495 "POS-PHY Level 3", Issue 4, November 1999. 6. PMC-Sierra, Inc., PMC-1991728 "S/UNI-2xGE Technical Overview", Issue 1, October.
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4
Definitions
The following table defines abbreviations used throughout this document.
CSMA/CD 1000BASE-T 1000BASE-SX 1000BASE-LX Auto-Negotiation Base Page Comma CommaComma+ Data Frame DTE EOF EOP EOS Even Parity Carrier Sense Multiple Access with Collision Detection. IEEE 802.3-1998 Physical Layer specification for 1000 Mb/s CSMA/CD LAN using four pairs of Category 5 balanced copper cabling. IEEE 802.3-1998 using short wavelength laser devices over multimode fiber IEEE 802.3-1998 using long wavelength laser devices over multimode and singlemode fiber. The algorithm that allows two devices at either end of a link segment to negotiate common data service functions. The first 16-bit message exchanged during IEEE 802.3-1998 Auto-Negotiation. The seven-bit sequence that is part of an 8B/10B code-group that is used for the purpose of code-group alignment. The seven-bit sequence (1100000) of an encoded data stream. The seven-bit sequence (0011111) of an encoded data stream. Consists of Destination Address, Source Address, Length Field, logical link control (LLC) Data, PAD, and Frame Check Sequence. Any source or destination of data connected to the local area network. End of frame. End of packet Ethernet over SONET The count of the number of 1's in the data word of n bits. If there are an odd number of 1s, then the parity bit will be a 1 so that including the parity bit, the number of 1s are an even number. Same as Data Frame A mode of operation that supports simultaneous communication between a pair of stations, provided that the Physical Layer is capable of supporting simultaneous transmission and reception without interference. Gigabit Media Independent Interface. Inter-Packet Gap (IPG): A delay or time gap between CSMA/CD physical packets intended to provided interframe recovery time for other CSMA/CD sublayers and for the Physical Medium. Management Information Base (MIB): A repository of information to describe the operation of specific network device. Media Access Control (MAC): The data link sublayer that is responsible for transferring data to and from the Physical Layer. Media independent Interface (MII): A transparent signal interface at the bottom of the Reconciliation sublayer. General class of pages optionally transmitted by Auto-Negotiation able devices following the base page word negotiation.
Frame Full Duplex
GMII IPG
MIB MAC MII Next Page
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Nibble Packet
A group of four data bits. The unit of exchange on the MII. The logical unit of data transferred across the POS-PHY Level 3 interface. This generally corresponds to the Data Frame as defined previously, although the CRC may or may not be present in the POS-PHY Level 3 egress direction. Consists of a Data Frame as defined previously, preceded by the Preamble and the Start Frame Delimiter, encoded, as appropriate, for the Physical Layer (PHY) type. SATURN compatible Packet over SONET interface specification for physical layer devices. POS-PHY level 3 defines an interface for bit rates up to and including 2.488 Gbit/s. POS-PHY Level 3 The count of the number of 1's in the data word of n bits. If there are an odd number of 1s, then the parity bit will be a 0 so that including the parity bit, the number of 1s are an odd number Start of Frame. Start of Packet.
Physical Packet POS-PHY
PL3 Odd Parity
SOF SOP
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5
Device block diagram
Figure 4: PM3386 S/UNI-2xGE Block Diagram.
MDC MDIO RX_CLK RX_DV RX_ER RXD [7:0] GTX_CLK TX_EN TX_ER TXD [7:0]
Ethernet Statistics
POS-PHY Level 3 Ingress Interface
PAUSE [1:0] PAUSED [1:0] RFCLK RENB RDAT[31:0] RMOD[1:0] RPRTY RVAL RSOP REOP RERR RSX
Enhanced Gigabit MAC Flow Ctrl / Auto-Negotiation Address Filtering
GMII Interface
POS PHY Ingress FIFO Gigabit Media Access Controller
RXD +/-
Data Recovery/ Serial to Parallel 8B/10B Encoder/ Decoder
Egress Interface
DTPA[1:0] STPA PTPA TADR TFCLK TENB TDAT[31:0] TMOD[1:0] TPRTY TSOP TEOP TERR TSX
SD CLK125
PLL Clock Multiply
TXD +/ATP[3:0]
Parallel to Serial SERDES Microprocessor Interface PCS MAC
POS PHY Egress FIFO
JTAG
PMD_SEL [1:0]
RSTB
ALE CSB WDB RDB
TRSTB
TMS
INTB A [11:0]
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D [15:0]
TDO
TCK
TDI
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6
6.1
Reference Design Functional Description
Block Diagram
This figure depicts the major functional blocks of the Reference Design.
Figure 5: Reference Design Block Diagram
Power Supply Filters and Regulator
100 MHz Reference Osc.
POS-PHY Level 3
GigabitEthernet ODL Channel 0 GigE GMII I/F
TXD0+/RXD0+/-
Tx GMII 0 Rx GMII 0
PM3386 S/UNI-2xGE GigabitEthernet ODL Channel 1 GigE GMII I/F
Tx GMII 0 Rx GMII 0 TXD1+/RXD1+/-
POS-PHY Level 3
Packet Loopback/ Transparent/EOS FPGA
Control Signals
AMP HS3 Connector
FPGA PROM
Processor Interface
Ext. FPGA Download
125 MHz External Reference clock
Status LEDs
125 MHz Internal Reference clock 125 MHz Ref Osc.
125 MHz External Reference clock
PLX PCI Bridge cPCI J1 Connector
cPCI Power Management
cPCI PCI Bus
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7
System Functional description
This Reference Design Board utilizes a 6U cPCI form factor and may only be tested within the cPCI environment. This system is composed of a cPCI chassis, the S/UNI-2xGE Reference Design PCB, single board computer with PCI support and operating system SW, and an external PC with terminal emulation software. In addition, an external Gigabit Ethernet test setup, such as a SmartBits unit is required to generate traffic and run system tests. The cPCI chassis in conjunction with a custom system side backplane provides expansion capability for a multiservice reference system implementation.
Figure 6: System Level Block Diagram
cPCI CHASSIS Power supply
GigE Tester
OR
S/UNI-2xGE Reference Design PCB
uP I/F J1 cPCI Backplane
O/S on Floppy
HD
cPCI Host Processor
RS-232
POS-PHY Level 3 Interface PL3 Tester or Custom Backplane Dumb Terminal or PC Terminal Emulator
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8
Implementation Description
The following descriptions refer to the S/UNI-2xGE Reference Design Schematics found in Section 11.
8.1
Root Drawing, Sheet 1
The root drawing provides a hierarchical overview of the S/UNI-2xGE reference design. Each of the major functional blocks of the design are shown, and the interconnections between the 2xGE_BLOCK, FPGA_BLOCK, SYS_INTERFACE, PCI_INTERFACE and POWER_BLOCK are drawn and labeled. On all sub-sheets of the design the interconnect signals are labeled with a "\I" suffix.
8.2
8.2.1
2xGE Block, Sheet 2
Optical Line Side Interface
The Optical Interface consists of the Gigabit Ethernet optical transceivers, power supply filtering and PECL interconnection to the serial line side interface on the S/UNI-2xGE. Two different optical transceivers are used on the board to characterize operation. One is an Infineon V23826K305-C353 1x9 AC coupled unit, the other is an Infineon 2x5 LC unit, V23818-K305-L57. Both transceivers are internally AC coupled which eliminates the need for external terminations on the reference design, simplifying layout and improving signal integrity. The traces for each of TXD+/- and RXD+/- (LVPECL) are controlled impedance 50 ohm. Trace lengths should be matched between pairs and the total length minimized to avoid signal degradation. Figure 7 below provides a block diagram of the internal termination architecture used to interface the internally terminated S/UNI-2xGE PECL pins to the ODLs.
Figure 7: PM3386 to ODL Interface
PM3386
TX -
AVDH
ODL Transmitter
50W
50 W 50 W
PECL Output
TX +
TX -
50W
TX +
PECL Input
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Figure 8: ODL to PM3386 Interface
ODL Receiver
TX -
PM3386
50 W 50W
TX -
PECL Output
TX +
50W
50 W
TX +
PECL Input
8.2.2
Optical Power Supply Filtering
The power supplies are filtered as recommended by the manufacturer. The TX and RX supplies are filtered with a 1uH series inductor, and two 4.7uF Tantalum capacitors. A series resistor is inserted to help prevent the LC filter structure from ringing. A noisy analog supply may require additional filtering to achieve proper operation.
8.2.3
125MHz PHY Reference Clock Circuit
The PM3386 requires a 125 MHz Reference Clock from which to synthesize the line rate clock. In SERDES mode, the PM3386 requires only one clock source. The CLK_125 input should be supplied from a reliable clock source such as an on board oscillator or external timing circuit. The clock source must meet the following requirements, outlined in Table 1, for 802.3 compliant operation:
Table 1: CLK_125 Timing Requirements Parameter
Nominal CLK_125 Reference Frequency Frequency Deviation from Nominal CLK125 Reference Clock Duty Cycle CLK_125 Reference Clock Deterministic Jitter (peak to peak above 200 KHz) CLK_125 Reference Clock Total Jitter (peak to peak above 200 KHz) CLK_125 Reference Clock Rise / Fall Time
Min
125 -100 40
Max
125 +100 60 0.007 56 0.020 160 1
Units
MHz ppm % UI ps UI ps ns
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In GMII mode, the PM3386 requires 3 separate clock inputs. The RX_CLK0 and RX_CLK1 inputs must be present for the respective PHY devices. This clock source is typically generated by the Gigabit Ethernet PHY device. Additionally, the CLK_125 input must be present and meet the timing requirements above. It can be sourced from the PHY device if a valid clock is provided, otherwise the 125MHz reference clock can be sourced from a high precision on board oscillator. Additionally, the PM3386 can operate with one channel in SERDES mode and one channel in GMII mode. In this configuration, the PM3386 shares the CLK125 input for both channels, and a valid RX_CLK must be input to the channel operating in GMII mode. The Reference Design provides the reference clock via an Ecliptek 125MHz HCMOS crystal oscillator or from an external source via an SMB connector. Other oscillator vendors that could be used include Connor-Winfield, Raltron and MMD. Figure 9 below shows a captured waveform of the CLK_125 signal on the S/UNI-2xGE Reference Design.
Figure 9: Ecliptek 125MHz Oscillator Waveform
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8.3
8.3.1
2xGE Block, Sheet 3
GMII Interface
The two GMII interfaces on the S/UNI-2xGE are routed to a pair of high speed matched impedance connectors. GMII channel 0 is routed to J11 and GMII channel 1 is routed to J12. Each connector distributes the GMII signals associated with a single channel, and provides access to the management interface, the global reset signal, and the 125MHz system clock. The Samtec QSE-020-01-F-D connectors provide a matched impedance interface to a daughter card or other external hardware that implements a physical interface via the standard GMII port on the S/UNI2xGE. All high speed outputs are source terminated with 33 ohm resistors.
8.4
8.4.1
2xGE Block, Sheet 4
POS-PHY Level 3 Interface
The PM3386 interfaces to higher layer devices via a 104MHz POS-PHY Level 3 interface. On the S/UNI-2xGE Reference Design, the output signals are source terminated with 33 ohm resistors. No end terminations are used. The PL3 interconnection between the S/UNI-2xGE and the FPGA is made with short 50 ohm traces. Figure 10 below shows a captured waveform of the PM3386 output RSX signal on the S/UNI2xGE Reference design. Figure 11 shows the 100MHz POS-PHY Level 3 RFCLK signal that drives the FPGA and PM3386 PL3 interfaces.
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S/UNI-2XGE Reference Design Preliminary
Figure 10: S/UNI-2xGE Reference Design RSX Signal
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Figure 11: S/UNI-2xGE Reference Design RFCLK Signal
8.4.2
Microprocessor Interface
Sheet 4 also shows the microprocessor interface on the S/UNI-2xGE. The interface operates in non-multiplexed mode, and the chip select signal is generated by the PCI bridge device, eliminating the need for on board decode logic. A valid read or write cycle occurs when both the SUNI_CSB and WRB or RDB signal is asserted with valid address and data on the bus. The side band flow control signals PAUSE<1..0> and PAUSED<1..0> are routed to the FPGA and can be used to initiate flow control on the S/UNI-2xGE or signal higher layer devices that the S/UNI-2xGE is receiving PAUSE frames. This functionality can be utilized effectively in EOS applications to handle near and far end backpressure across the network. See PMC-2001398 for more information regarding EOS applications. Header J9 is provided to allow the user to select which line side interface is active on the S/UNI2xGE. Any combination of SERDES or GMII interfacing is valid, as long as the configuration is set before power-up. By default, with no jumpers installed the S/UNI-2xGE reference design will power-up in dual SERDES mode.
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8.5
2xGE Block, Sheet 5
The power supply configuration for the S/UNI-2xGE is shown on Sheet 5. The PM3386 is a 0.18 micron device which requires 1.8V and 3.3V digital and analog supplies for proper operation: * 3.3V Digital I/O - VDDO. Supplied via the CPCI interface. VDDO is well decoupled to ground. 0.1uF decoupling capacitors are placed next to the following pins: C3, V4, H4, AD3, AC9, AC19, AD24, Y23, J23, D24, B25. 1.8V Digital Core - VDDI. Supplied via a switching 1.8V regulator in the POWER_BLOCK. VDDI is well decoupled to ground. 0.1uF capacitors are placed next to the following pins: G1, M4, W4, AC8, AC16, AC20, V23, F23, D16, D10. 3.3V Quiet Analog - AVDQ. Quiet Analog power for the analog cells. The CPCI 3.3V supply is filtered and decoupled for AVDQ. 3.3V Quiet Digital - VDDQ. The CPCI 3.3V supply is filtered and decoupled for VDDQ. 3.3V Analog - AVDH. The 3.3V analog pins are filtered and decoupled to improve performance of the analog blocks. Figure 12 below outlines the pin groupings and filter architecture. 1.8V Analog - AVDL. The 1.8V core analog pins are filtered and decoupled to improve performance of the analog core blocks.
*
* * *
*
Until full characterization of the device can be completed all filter values should be considered preliminary.
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8.5.1
Power Filtering Recommendations
Figure 12: 3.3V Analog Supply Filter Architecture
0.47 +3.3V
AVDH_1 Pins: H26, J24, L25 0.1uF
10uF X5R
0.47
AVDH_2 Pins: N24, R23, U24
10uF X5R
0.1uF
3
AVDH_3 Pin: L24
10uF X5R
0.1uF
The Supply Filtering for the 1.8V AVDL pins is shown below in Figure 13.
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Figure 13: 1.8V Analog Filter Architecture
1 +1.8V
AVDL_1 Pins: H23, K23, K24 0.1uF
10uF X5R
0.47
AVDL_2 Pin: H24 0.1uF
10uF X5R
1
AVDL_3 Pins: G23, P25, N26
10uF X5R
0.1uF
1
AVDL_4 Pins:P23, T24, T25 0.1uF
10uF X5R
0.47
AVDL_5 Pin: P26 0.1uF
10uF X5R
0.47
AVDL_6 Pin: N23 0.1uF
10uF X5R
1
AVDL_7 Pin: N25 0.1uF
10uF X5R
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The 1.8V filter architecture provides optional connection to a 1.8V regulated supply that is placed near to the S/UNI-2xGE device. All 0.1uF capacitors should be placed as close as possible to the pads on the device. Effort should be made to place the resistor and 10uF capacitor filter circuit as close as possible to the power pins as well. Larger 10uF bulk capacitors are provided for further decoupling and should be placed near each corner of the device.
8.6
FPGA Block, Sheet 6
The FPGA supports a number of functions on the S/UNI-2xGE Reference Design. These include: * * * * PL3 system side loopback. Reset logic Packet processing for EOS or other applications LED control for status monitoring.
Since two full POS-PHY Level 3 interfaces are implemented on the FPGA to allow for packet processing capability and transparent interfacing to the system side, the FPGA requires a very high number of I/Os. This reference design uses a Xilinx Virtex-E FPGA. The XCV200E6BG352 provides up to 260 I/Os in a low power 1.8V and 3.3V 352 pin BGA package. Table 2 below outlines the distribution of I/Os on the device.
Table 2: Virtex Pin Distribution Signal Type
S/UNI PL3 I/F SYS PL3 I/F Micro I/F Status/Control Total
No. of Pins
42 TX, 42 RX, 84 Total 42 TX, 42 RX, 84 Total 34 Total 35 Total 233 I/Os
Description
POS-PHY Level 3 data bus and control pins S/UNI-2xGE interface. PL3 data bus and control pins - system side interface. 16 data lines, 11 address lines, 7 control lines. Reference clocks, PM3386 control and status, LEDs, General Purpose I/O, Reset logic. Note: 13 Unused - routed to test points.
Figure 14 below shows a block diagram of the FPGA used on the S/UNI-2xGE Reference Design.
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Figure 14: FPGA Block Diagram
SUNI_TDAT<31..0> SUNI_TMOD<1..0> SUNI_TERR SUNI_TEOP SUNI_TENB SUNI_TSOP SUNI_TADR SUNI_TFCLK LA<13..2> LD<15..0> FPGA_CSB WRB RDB PAUSE<1..0> PAUSED<1..0>
SYS_TDAT<31..0> SYS_TMOD<1..0> SYS_TERR SYS_TEOP SYS_TENB SYS_TSOP SYS_TADR SYS_TFCLK
Latch
Latch
uP IF SUNI_CTL_ REGISTER Loopback / Transparent Select
LED<6..0>
SUNI_RDAT<31..0> SUNI_RMOD<1..0> SUNI_RERR SUNI_REOP SUNI_RENB SUNI_RSOP SUNI_RADR SUNI_RFCLK
SYS_RDAT<31..0> SYS_RMOD<1..0> SYS_RERR SYS_REOP SYS_RENB SYS_RSOP SYS_TADR SYS_RFCLK
Latch
Latch
8.6.1
Control Register Function
The S/UNI-2xGE FPGA functionality is controlled via the S/UNI Control Register. The register bit functions are outlined below.
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Register 00H: S/UNI Control Register Bit
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W
Type
R R R/W R/W
Function
SUNI_PAUSED1 SUNI_PAUSED0 SUNI_PAUSE1_ENB SUNI_PAUSE0_ENB Unused Unused Unused Unused Unused Unused Unused RESET TXENA RXENA XPRNT_ENA LPBK_ENA
Default
0 0 0 0 X X X X X X X 0 0 0 0 1
Bits 0 and 1 configure the loopback/transparent functionality of the FPGA. The following combinations are valid: * * * * 0x01 : LPBK_ENA. The receive PL3 bus is looped back to the S/UNI-2xGE. 0x10 : XPRNT_ENA. The FPGA passes the RX and TX interfaces transparently to/from the backplane connector. 0x11 : Loop and Pass. In this mode the Receive data will be looped to the TX inputs and passed to the backplane connector. 0x00 : Not used. Could be used to implement packet processing functionality.
The RXENA and TXENA bits are used to enable the Receive and Transmit S/UNI side PL3 interfaces. Setting these bits to `1' enables the interface. Bit 4 is the software reset bit. When set to a 1, the reference design global reset is asserted, resetting the S/UNI-2xGE, but not the FPGA. Setting Bit 12 or 13 will set the PAUSE pin on the corresponding channel. The S/UNI-2xGE will output PAUSE frames to assert flow control while this bit is set high. It is synchronously sampled by the PM3386 on the rising edge of RFCLK, but can be set or cleared in the Pause Control Register at any time.
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When read, bits 14 and 15 indicate the status of the PAUSED pins on the PM3386. When high, PAUSE frames are being received on the respective Gigabit Ethernet channel.
8.6.2
S/UNI-2xGE POS-PHY Level 3 Interface
Each output pin on the PL3 bus (Transmit side) is source terminated with a 33 ohm resistor. On the receive side, the signals are source terminated at the PM3386 and no end terminations are used since the trace lengths between the S/UNI-2xGE and the Virtex device are relatively short. The TSX output from the FPGA on the S/UNI-2xGE Reference Design is shown below in Figure 15.
Figure 15: S/UNI-2xGE Reference Design TSX Signal
8.6.3
Status LEDs and Reset Circuit
Sheet 6 also shows the status LEDs and the pushbutton reset circuit for the S/UNI-2xGE Reference Design. A single LED is wired to the DONE pin and will turn on after the Virtex FPGA is successfully configured. Table 3 below outlines the function of the remaining LEDs.
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Table 3: LED Display Function Bit (D3)
Bit 7 Bit 6 Bit 5 Bit 4
Function
Done Unused PAUSED1 PAUSED0
Bit (D3)
Bit 3 Bit 2 Bit 1 Bit 0
Function
PAUSE1 PAUSE0 Transparent Loopback
The pushbutton reset is provided via a MAX811 voltage monitor device that will assert a reset signal when the voltage supply is below 3.08V. The minimum reset pulse is 140ms. By logically ORing the RESET_PB signal with PWROK_1_8V, and RSTOB (from the cPCI bus) within the FPGA the system reset signal (SUNI_RSTB) is generated. A 16x2 100mil header provides access to the microprocessor interface bus for debugging purposes. Matched impedance MICTOR connectors that have been used in past reference designs for access to the PL3 bus are not used in this design due to the constraints they put on routing and the excessive lead times of the parts themselves. No headers are provided on the board due to space contstraints, but if probing of the PL3 bus is required the user can pass all PL3 bus signals through the FPGA and probe the signals at the backplane connector (POS Transparent Mode). A small test jig could be built to interface to a logic analyzer if desired.
8.7
8.7.1
FPGA Block, Sheet 7
System Side POS-PHY Level 3 Interface
Sheet 7 provides the remainder of the S/UNI PL3 interface signals and the system side PL3 interface. As on the S/UNI interface, all outputs are source terminated with 33 ohm resistors.
8.8
8.8.1
FPGA Block, Sheet 8
Configuration Circuit
The S/UNI-2xGE Reference Design FPGA can be configured in 3 ways: * * * Via an EPROM. Via an XCHECKER cable. Via the JTAG port.
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Jumpers allow the user to select between EPROM configuration or configuration via the XCHECKER cable. By default the FPGA will download configuration information from the EPROM. To configure the device via the XCHECKER cable, install all jumpers on J7 and remove the EPROM. If the EPROM is installed and the configuration is downloaded via the XCHECKER cable, the downloaded configuration will be overwritten by the contents of the EPROM. The JTAG port is always active and takes priority over the other configuration modes, if used.
8.8.2
Power Supply Decoupling
The Virtex family of devices are capable of operating at speeds well above 200MHz. With a number of I/Os switching simultaneously at high speeds, a stable power supply is essential to achieve good performance and signal quality. The XCV200E is part of the Virtex-E family of 0.18m devices which uses 3.3V for I/O and 1.8V for core power. On the S/UNI-2xGE reference design the 3.3V digital supply is provided by the cPCI interface and is well decoupled to ground. The 1.8V digital supply is provided via the switching regulator in the POWER_BLOCK and is also well decoupled to ground. Based on Xilinx recommendations, eight 10uF bulk capacitors are added to further decouple the device, and placed near each I/O bank on the Virtex device. Finally, four 0.47uF capacitors are placed at the corners.
8.9
8.9.1
FPGA Block, Sheet 9
100 MHz PL3 Clock Distribution
A 100 MHz oscillator, 100 ppm, is used for the POS-PHY Level 3 interface. No series termination resistor is used between the oscillator output and the input to due to the extremely short trace length. A clock distribution driver is used to provide low skew clocks to the PM3386, the FPGA, and to the external HS3 connector. The PI49FCT3807D (the 110MHz rated FCT3807C would suffice) was selected as the clock driver as it provides up to 10 outputs with a maximum skew of 350 ps and can operate from a +3.3 Volt supply. The +3.3 Volt supply is bypassed with two capacitors to help reduce power supply glitches when all 10 outputs switch simultaneously at 100 MHz. Each output from the FCT3807 is source terminated through a 33 ohm resistor in order to match the impedance of the 50 W traces distributing the clock signal. Correct termination of the clock signals is especially important to ensure monotonic, glitch-free, clocking of the S/UNI device, the FPGA, and the external system.
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8.9.2
100 MHz Clock Source Switching
The clock architecture on the S/UNI-2xGE Reference Design has been developed to operate as either a clock master or a clock slave when connected to an external system. The 100MHz PL3 clock is distributed to the FPGA and the S/UNI device via solder bridges and to the system side backplane. By configuring the solder bridges to source the clock from the on board oscillator or from the FPGA, the board can operate as a clock master or clock slave. If the external system is the clock master, The FPGA routes the TFCLK and RFCLK signals from the backplane to the S/UNI-2xGE, taking advantage of the built in Delay Lock Loop architecture to improve clock performance.
8.10
8.10.1
CPCI Interface Block, Sheet 10
CPCI Interface Controller
The cPCI Host Processor Interface is based on the PCI 9030 device. This device is a 3.3V/5V compliant PCI v2.2 32-bit, 33MHz Bus Target Interface Device, that provides flexible local bus configurations and Hot Swap capability. The PCI 9030 operates with a 32-bit non-multiplexed bus on the local bus side. It provides up to four configurable chip selects and up to nine user configurable general purpose I/O pins eliminating the need for external glue logic to interface to devices on the local bus. The PCI9030 provides full Hot Swap capability and has the required 1V cPCI bus precharge voltage function built in, eliminating the need for external pull-up resistors and voltage regulator. A serial EEPROM is used for device configuration after a reset. This design supports the Fairchild Semiconductor 93CS66LEN (4K) or 93CS56LEN (2K) serial EEPROM.
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Figure 16: Host Processor cPCI Interface
LA<31..2> LD<31..0> CONTROL LA<31..2> LD<31..0> CONTROL AD<31:0> C/BE<3:0> CONTROL
CPCI J1
LOCAL BUS
PLX 9030 PCI Target
RESET\
PCI BUS
EEPROM
8.11
8.11.1
CPCI Interface Block, Sheet 11
CPCI J1 Connector
An AMP Z-PACK connector is used to provide a cPCI compliant J1 interface. For details regarding this interface, please refer to the current Compact PCI specifications.
8.11.2
ESD Strip
An ESD strip is integrated into the PCB along the front edge
8.12
cPCI Power_Block, Sheet 12
Note: A discrepancy exists between the power-up sequencing used in this reference design and the power-up sequencing described in the S/UNI-2xGE Datasheet (PMC-1991129) and its related errata (PMC-2010140). Please refer to the S/UNI-2xGE Datasheet (PMC-1991129) and its related errata (PMC-2010140) for the proper power-up sequencing recommendations.
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EECS EESK EEDI EEDO
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8.12.1
Hot Swap Controller System Block
The Hot Swap Controller is used to allow a board to be safely inserted or removed from a live cPCI slot. The Hot Swap controller on the Power Supply Board System Block is implemented using the Linear Technology LTC1643L-1 The Hot Swap controller allows the supply voltages to be ramped up at a programmable rate, detects over-current and over-voltage conditions, and shuts down power to the board until those conditions are rectified. The LTC1643L-1 PWRGD# logic ignores the +/-12V rails which is applicable in systems that do not implement or have poor 12V supplies. The +12V and -12V supplies are controlled with on-chip switches, while external N-channel MOSFETS are used to control the 3.3V and 5V supplies. A DC/DC converter is used to generate 1.8V from the 5V rail.
Figure 17: cPCI Hot Swap Controller
Q IRF7413 Q IRF7413 10 W 10 W V(I/O) CompactPCI Connector 100 W
+5V_PCI +3.3V_PCI
5V 5A 3.3V 7.6A
3Vin 3Vsense GATE 3Vout 5Vin 5Vsense 5Vout 12Vin VEEin ON# V(I/O) 12V 2k PWRGD# 0.1uF 0.1uF GND TIMER 0.01uF FAULT# 12Vout VEEout 12V 500mA -12V 100mA
+12V_PCI -12V_PCI BD_SELB
LT1643L-1
HEALTHYB GND
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8.13
8.13.1
System Interface, Sheet 13
POS-PHY Level 3 Interface
The S/UNI-2xGE POS-PHY L3 interface is connected to the FPGA and to the drop side HS3 connector. The HS3 connector uses a PMC-Sierra, Inc. proprietary pin out for the PL3 bus as shown in the following two tables
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Table 4: PL3 High Speed RX Interface, J11 Pin Name
RDAT[0] RDAT[1] RDAT[2] RDAT[3] RDAT[4] RDAT[5] RDAT[6] RDAT[7] RDAT[8] RDAT[9] RDAT[10] RDAT[11] RDAT[12] RDAT[13] RDAT[14] RDAT[15] RDAT[16] RDAT[17] RDAT[18] RDAT[19] RDAT[20] RDAT[21] RDAT[22] RDAT[23] RDAT[24] RDAT[25] RDAT[26] RDAT[27] RDAT[28] RDAT[29] RDAT[30] RDAT[31] RPRTY Output
Type
Output
Pin No.
B4 A4 E5 D5 C5 B5 A5 E6 D6 C6 B6 A6 E7 D7 C7 B7 A7 E8 D8 C8 B8 A8 E9 D9 C9 B9 A9 E10 D10 C10 B10 A10 A3
Function
Receive Packet Data Bus For POS-PHY Level 3 this bus carries Packets that are read from the selected receive FIFO.
Receive Bus Parity The receive parity signal indicates the parity of the RDAT bus.
RENB
Input
E1
Receive Write Enable The RENB signal is an active low input which is used to initiate reads from the receive FIFO.
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Pin Name
RVAL
Type
Output
Pin No.
B3
Function
Receive Data Valid RVAL indicates signals RDAT, RSOP, REOP, RMOD, RPRTY and RERR are valid. This signal is not used in UTOPIA mode.
RSOP
Output
D4
Receive Start of Packet This signal marks the start of packet on the RDAT bus.
RERR
Output
C4
Receive Error This signal indicates that the current packet has been aborted.
REOP RMOD[1] RMOD[0] RSX
Output Output
E4 D3 C3
Receive End of Packet This signal marks the end of packet on the RDAT bus. Receive Word Modulo Indicates number of bytes in the last RDAT bus transaction of a packet. Receive Start of Transfer RSX indicates when the in-band PHY port address is present on RDAT bus. 104 MHz Receive Bus Slave Clock Input Provided to the PM3386 RFCLK input via CMOS switches during RX Slave mode operation.
Output
E3
RFCLK
Input
F1
RSYSCLK
Output
C1
104 MHz Receive Bus Master Clock Output Provided to the external system and timed to coincide with RFCLK signal to PM3386 during RX Master mode operation.
GND
Power
AB1 -AB10, CD1 -CD10, EF1 - EF10
Ground
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Table 5: PL3 High Speed TX Interface, J10 Pin Name
TDAT[0] TDAT[1] TDAT[2] TDAT[3] TDAT[4] TDAT[5] TDAT[6] TDAT[7] TDAT[8] TDAT[9] TDAT[10] TDAT[11] TDAT[12] TDAT[13] TDAT[14] TDAT[15] TDAT[16] TDAT[17] TDAT[18] TDAT[19] TDAT[20] TDAT[21] TDAT[22] TDAT[23] TDAT[24] TDAT[25] TDAT[26] TDAT[27] TDAT[28] TDAT[29] TDAT[30] TDAT[31] TPRTY Input
Type
Input
Pin No.
C4 B4 A4 E5 D5 C5 B5 A5 E6 D6 C6 B6 A6 E7 D7 C7 B7 A7 E8 D8 C8 B8 A8 E9 D9 C9 B9 A9 E10 D10 B10 A10 D4
Function
Transmit Packet Data Bus This data bus carries the POS packet octets that are written to the selected transmit FIFO.
Transmit Bus Parity. The transmit parity signal indicates the parity of the TDAT bus. Transmit Write Enable. The TENB signal is an active low input which is used to initiate writes to the transmit FIFO
TENB
Input
C2
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Pin Name
TSOP
Type
Input
Pin No.
B3
Function
Transmit Start of Packet This signal indicates the first byte in a packet.
TERR
Input
E4
Transmit Error This signal indicates the current packet must be aborted.
TEOP
Input
C3
Transmit End of Packet This signal marks the end of a packet on the TDAT bus.
TMOD[1] TMOD[0] TADR
Input Input
B2 A2 E1
Transmit Word Modulo This signal indicates the size of the current word. Transmit PHY Address Allows selection of either PHY channel on the S/UNI2xGE for polling.
TSX
Input
A3
Transmit Start of Transfer TSX indicates when the in-band PHY port address is present on TDAT bus.
TFCLK
Input
F10
104 MHz Transmit Bus Slave Clock Input Provided to the PM3386 TFCLK input via switches during TX Slave mode operation.
TSYSCLK
Output
C10
104 MHz Transmit Bus Master Clock Output Provided to the external system and timed to coincide with TFCLK signal to PM3386 during TX Master mode operation.
GND
Power
AB1 -AB10, CD1 -CD10, EF1 - EF10
Ground
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9
9.1
Physical Design considerations
PCB Layout Issues
Because of the high speed 1.25GHz PECL differential drivers, and fast edged signals on the PL3 bus, the reference design PCB requires careful layout. Typically the drivers have rise/fall times below 1ns. High speed traces should be as short as possible, controlled impedance transmission lines used where indicated and standard terminations must be incorporated to prevent signal reflections. Standard FR-4 PCB material can be used for this application with as many layers as required to derive the final board thickness, achieve enough layers for signal routing and attain the required trace impedance. Please refer to the first page of the artwork for more details on the reference design PCB.
Table 6: Reference Design PCB Stack Up (Preliminary) Layer
TOP GND1_PLANE VCC1_PLANE SIG1 SIG2 VCC2_PLANE GND2_PLANE SIG3 SIG4 VCC3_PLANE GND3_PLANE BOTTOM
Location
Top Signal Layer, Component Side Power Plane Ground Signal Layer Signal Layer Power Plane Ground Signal Layer Signal Layer Power Plane Ground Bottom Signal Layer, Solder Side
Although only one ground plane is required, additional planes can be used to attain the desired board thickness and correct trace impedance. A ground layer or a power plane can be used to achieve the desired signal transmission line trace impedance assuming there is adequate coupling between them. All traces on the board are 50 characteristic impedance, except the cPCI bus traces which are required to be 65 ohms.
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9.2
Thermal Issues
As stated in the product datasheet, the power dissipation is estimated at 2W. In order to achieve long term reliability, the device junction temperature (Tj) must be kept below 105C. The design of the chip cooling system will be influenced by a number of factors including: * * * * ambient temperature in which the device will operate proximity of other devices that may impede airflow orientation of device on board air movement through the design
The table below outlines basic thermal reliability information for the PM3386.
Table 7: PM3386 Reliability Information RESULTS Confidence Level Package Type Ambient Temperature Theta JA at Operating Ambient Base Failure Rate at TJ=55 deg C Junction Temperature Failure Rate at Ambient Temperature MTBF at Ambient Temperature
Notes 1. 2. 3. 4. 5. Theta JA is for a dense board device in natural convection. Calculated FIT Rate (Failure rate at ambient temperature) FIT is defined as failure rate per billion hours See PMC-920615 for key to Branding Suffixes Refer to PMC-930812 for other details (deg C) (deg C/Watt) (FITS) (deg C) (FITS) (years) 60% 352 UBGA 40 19 24 111 892 128 90% 352 UBGA 40 19 35 111 1280 89 60% 352 UBGA 60 19 24 131 2547 45 90% 352 UBGA 60 19 35 131 3653 31
9.2.1
Sample calculations
In order to maintain a junction temperature Tj below 105C with only natural convection cooling in a dense board implementation, the ambient air temperature surrounding the device could not exceed:
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Max temperature
= 105C - (qJA x Power Dissipated) = 105C - (19C/W x 2 Watts) = 67C
In many cases where the ambient temperature is expected to be higher or on boards that are more densely populated, additional heatsinking is required. The reference design has been designed to operate in an environment with limited airflow and potentially high ambient temperatures. As a result, a heatsink and external airflow (via a fan) should be used to compensate. The AAVID 335514 heatsink provides a thermal resistance between the case temperature and the ambient air temperature (qSA ) of 7.9C/W at 200 LFM. Based on a thermal resistance between the device junction and the device case (qJC) of 1C/W, and a thermal resistance between the device case and the heatsink (qCS) of ~0.1C/W, this heatsink will allow operation at ambient temperatures of up to: Max temperature = 105C - ((qJC + qCS + qSA) x Power Dissipated) = 105C - ((1+0.1+7.9)C/W x 2 Watts) = 87C
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10
10.1
Electrical Design Considerations
PECL Interface Issues
Because of the transmission stub created by the ODL internal PCB trace and through-hole solder mounting pins, care should be taken when artworking traces between the optics and the S/UNI2xGE. No vias should be present on the point to point traces except where required for terminating components. Any vias present along the traces will degrade jitter performance. These differential traces should be of equal length and have as few corners as possible. To prevent transmission stubs, terminating components (resistors) should be placed after the IC pin(s) and on the solder side (bottom) of the PCB.
10.2
Optical Transceiver Terminations
The PECL transmit and receive interface on the S/UNI-2xGE requires AC coupling to operate correctly. When interfacing the PM3386 to ODLs that to not have integrated terminations, Figure 18 and Figure 19 below outline the recommended interface terminations.
Figure 18: PM3386 Transmit SERDES to Optical Transmitter
PM3386
TX -
AVDH
VBIASODL 49.9 W
Fiber-Optic Transmitter
TX -
50 W 50 W
PECL Output
TX +
C1 C2
49.9 W
PECL Input
TX +
PM3386
TX -
AVDH
Fiber-Optic Transmitter
C3 C4 100 W
TX -
50 W 50 W PECL Input
PECL Output
TX +
TX +
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Figure 19 represents a typical application showing the transmit datapath termination. Note that the characteristic impedance for the termination is 50 W single ended or 100 W differential. Values for C1, C2, C3, and C4 are recommended to be 100nF. Please note that the many transceivers on the market may contain the needed termination resistors and capacitors. In addition the TX_EN0 or TX_EN1 signal may be used as the transmit enable while in SERDES mode.
Figure 19: Optical Receiver to PM3386 SERDES
Fiber-Optic Receiver
TX -
PM3386
50 W C1
TX -
PECL Output
TX +
R2
C2
50 W
TX +
PECL Input
R1
Figure 19 represents a typical application showing the receive datapath termination. Please note the internal 50 W single ended termination within the PM3386 receive PECL cells. Follow the manufactures recommended requirements when interfacing the Fiber-Optic Receiver to the PM3386. Differing Fiber-Optic Receivers require differing values for the R1 and R2 termination resistors. RXSD0 and RXSD1 may be used as the input signal detect for transceivers that support this feature.
10.3
Power Up/Down Considerations
Due to ESD protection structures in the pads it is necessary to exercise caution when powering a device up or down. ESD protection devices behave as diodes between power supply pins and from I/O pins to power supply pins. Under extreme conditions it is possible to blow these ESD protection devices or trigger latch up. For more information on the required power up sequence, refer to the S/UNI-2xGE data sheet. The following features on the S/UNI-2xGE reference design ensure power up and power down occurs properly. * AVDQ A 10 ohm resistor is placed in series between the 3.3 Volt supply and the AVDQ pins. The 10ohm resistor and a 10mF capacitor.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use Document ID: PMC-2000991, Issue 3
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S/UNI-2XGE Reference Design Preliminary
*
VDDO, AVDQ, and AVDH VDDO, AVDQ, and the AVDH pins are supplied from the same 3.3V power plane. This keeps the voltage difference between the AVDH pins, VDDO and AVDQ pins small preventing current flow from AVD pins to the VDDO, and AVDQ pins.
10.4
Grounding
A single ground plane is recommended with no power or ground cuts in the plane. This one ground plane is shared among digital and analog signals. One ground plane simplifies design and layout. More than one ground layer can be used but all ground connections (vias) should be made to all layers to make it appear as one ground plane. Characteristic impedances can be realized by providing the current return path either through a ground or power plane. Since the ODLs are optically isolated, there is no requirement for extensive high-voltage and/or high energy protection as in other metallic physical mediums such as T1/E1.
10.5
System Side Transmission Line Terminations
The S/UNI-2xGE is capable of system side interface speeds up to 104 MHz. Because of the high frequency content of the system side signals, terminations may be required to ensure reliable data transmission across the interface. A "series source terminating resistor" may be required in a system where the PL3 Bus drivers have a fast rise/fall time and the distance between the 2xGE and the link layer device is substantial. If we consider that these CMOS PL3 drivers have typical 1ns edges then traces longer than 0.89in/2.26cm should be terminated. On the S/UNI-2xGE Reference Design source terminations are implemented on the PL3 bus and work to eliminate signal reflections at the output pins. As stated above, if the trace length is sufficiently short additional terminations are not necessary. Since the drivers are CMOS and have limited current drive/source capabilities, parallel far end terminations can't be used. For point to point transmission, series source termination is a good option. The figure below illustrates the relative positioning and values of series source termination resistors. Resistor values may vary depending on Zo transmission line impedance and the output impedance of the I/O driver.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use Document ID: PMC-2000991, Issue 3
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S/UNI-2XGE Reference Design Preliminary
Figure 20: System Interface Terminations
Link Layer Device S/UNI-2xGE
Input 5 pF
Output
Zo
R1 RO1
Output
RO2
Notes:
R2
Zo
5 pF Input
- Terminations shown are for 3.3V Link Layer Device - Zo (trace impedance) 50W R1 = Zo - RO1 33W R2 = Zo - RO2 33W
Because of the relative uncertainty of the output impedance (RO1 and RO2), it's best to have Zo as large as possible so that the output impedance is as small as possible relative to Zo. However, a large Zo means a narrow, difficult to manufacture PCB trace. A small Zo would require wide traces and would take up a lot of PCB real-estate. On PCBs with BGA and other high density components a narrow trace is required to be able to route between chip pins/balls. A "series source termination" scheme assumes that the far end has infinite impedance. However, as shown in Figure 21, all CMOS type infinite impedance inputs have finite capacitive inputs of about 5pF. Initially when the rising or falling edge hits the input pin, the far end looks like a short circuit until the capacitor is charged/discharged at which point the input looks like an infinite impedance. This causes a small glitch reflected back which may cause a problem. A simple way to solve this is to put another series resistor at the input to the far-end pin, equal to the impedance of the transmission line. On the S/UNI-2xGE Reference Design Post-Layout simulations have shown that end terminations are not necessary and do not improve performance.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use Document ID: PMC-2000991, Issue 3
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S/UNI-2XGE Reference Design Preliminary
Figure 21: Series Source Termination
0
T
TIME
Glitch due to input Capacitance
2T
Link Layer Device
S/UNI-2xGE
Ro 2
R2
Zo = 50W
Zin = Zo = 50W
Input
Outputs
Ro 2 + R 2 = Zo = 50W
Ro 2
Zin = // Xc
Zin = Rs + // Xc
Input
C 5pF Inputs
R2
Zo = 50W
Rs = Zo
C 5pF
0
T
TIME
No Glitch
2T T = time it takes for edge to reach far end of transmission trace.
each trace shows voltage vs. time at this position
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S/UNI-2XGE Reference Design Preliminary
11
Schematics Revision 1
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use Document ID: PMC-2000991, Issue 3
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PAGES 2..5 2XGE_BLOCK SUNI_TDAT<31..0> SUNI_TMOD<1..0> SUNI_TERR SUNI_TEOP SUNI_TENB SUNI_TSX SUNI_TSOP SUNI_TPRTY SUNI_TADR SUNI_TFCLK SUNI_DTPA0 SUNI_DTPA1 SUNI_PTPA SUNI_STPA SUNI_PAUSE1 SUNI_PAUSE0 SUNI_PAUSED1 SUNI_PAUSED0 F SUNI_RDAT<31..0> SUNI_RMOD<1..0> SUNI_RERR SUNI_REOP SUNI_RENB SUNI_RSX SUNI_RSOP SUNI_RPRTY SUNI_RVAL SUNI_RFCLK E PHY_INTB0 PHY_INTB1 SUNI_RDAT<31..0> SUNI_RMOD<1..0> SUNI_RERR SUNI_REOP SUNI_RENB SUNI_RSX SUNI_RSOP SUNI_RPRTY SUNI_RVAL SUNI_RFCLK PHY_INTB0 PHY_INTB1 SUNI_RDAT<31..0> SUNI_RMOD<1..0> SUNI_RERR SUNI_REOP SUNI_RENB SUNI_RSX SUNI_RSOP SUNI_RPRTY SUNI_RVAL SUNI_RFCLK PHY_INTB0 PHY_INTB1 SUNI_TDAT<31..0> SUNI_TMOD<1..0> SUNI_TERR SUNI_TEOP SUNI_TENB SUNI_TSX SUNI_TSOP SUNI_TPRTY SUNI_TADR SUNI_TFCLK SUNI_DTPA0 SUNI_DTPA1 SUNI_PTPA SUNI_STPA SUNI_PAUSE1 SUNI_PAUSE0 SUNI_PAUSED1 SUNI_PAUSED0 FPGA_BLOCK SUNI_TDAT<31..0> SUNI_TMOD<1..0> SUNI_TERR SUNI_TEOP SUNI_TENB SUNI_TSX SUNI_TSOP SUNI_TPRTY SUNI_TADR SUNI_TFCLK SUNI_DTPA1 SUNI_DTPA0 SUNI_PTPA SUNI_STPA SUNI_PAUSE1 SUNI_PAUSE0 SUNI_PAUSED1 SUNI_PAUSED0
PAGES 6..9
PAGE 13 SYS_INTERFACE SYS_TDAT<31..0> SYS_TMOD<1..0> SYS_TERR SYS_TEOP SYS_TENB SYS_TSX SYS_TSOP SYS_TPRTY SYS_TADR SYS_TDAT<31..0> SYS_TMOD<1..0> SYS_TERR SYS_TEOP SYS_TENB SYS_TSX SYS_TSOP SYS_TPRTY SYS_TADR
SYS_TDAT<31..0> SYS_TMOD<1..0> SYS_TERR SYS_TEOP SYS_TENB SYS_TSX SYS_TSOP SYS_TPRTY SYS_TADR
G
G
SYS_TFCLK
SYS_TFCLK
SYS_TFCLK
SYS_RSYSCLK SYS_TSYSCLK
SYS_RSYSCLK SYS_TSYSCLK
SYS_RSYSCLK SYS_TSYSCLK
F SYS_RDAT<31..0> SYS_RMOD<1..0> SYS_RERR SYS_REOP SYS_RENB SYS_RSX SYS_RSOP SYS_RPRTY SYS_RVAL SYS_RFCLK SYS_RDAT<31..0> SYS_RMOD<1..0> SYS_RERR SYS_REOP SYS_RENB SYS_RSX SYS_RSOP SYS_RPRTY SYS_RADR SYS_RFCLK SYS_RDAT<31..0> SYS_RMOD<1..0> SYS_RERR SYS_REOP SYS_RENB SYS_RSX SYS_RSOP SYS_RPRTY SYS_RVAL SYS_RFCLK
E GPIO<8..0> PWROK_1_8V
SUNI_RSTB
LA<23..2>
LD<31..0>
FPGA_INTB
SUNI_CSB
FPGA_CSB
READYB
LW/RB
RSTOB
ADSB
RDB
WRB
SUNI_RSTB LA<23..2> D LD<31..0> SUNI_CSB SUNI_INTB RDB WRB
SUNI_RSTB LA<23..2> LD<31..0> SUNI_CSB FPGA_CSB SUNI_INTB FPGA_INTB RDB WRB ADSB LW/RB READYB RSTOB GPIO<8..0>
PAGES 10..11 PCI_INTERFACE LA<23..2> LD<31..0> SUNI_CSB FPGA_CSB SUNI_INTB FPGA_INTB RDB WRB ADSB LW/RB READYB RSTOB GPIO<8..0> C D
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PAGE 12 POWER_BLOCK PWROK_1_8V 5V_PCI 3_3V_PCI 12V_PCI VEE_PCI BD_SELB HEALTHYB VIO_PCI PWROK_1_8V 5V_PCI 3_3V_PCI 12V_PCI VEE_PCI BD_SELB HEALTHYB VIO_PCI PWROK_1_8V 5V_PCI 3_3V_PCI 12V_PCI VEE_PCI BD_SELB HEALTHYB VIO_PCI
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PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-2000991 DOCUMENT ISSUE NUMBER: 1.0 DRAWING: SUNI_2XGE_R1_ROOT SUNI_2XGE_R1_ROOT Tue Oct 10 16:25:26 2000 10 9 8 7 6 5 4 3 TITLE: S/UNI-2XGE REFERENCE DESIGN ROOT DRAWING ENGINEER: BDV 2 ISSUE DATE: YY/MM/DD REVISION NUMBER: 1.0 PAGE:1 1 OF 13 A
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3.3 V
0 4.7UF R57 C58 1.0UH L4 4.7UF
GIGABIT ETHERNET OPTICS INTERNALLY AC TERMINATED 1X9 TRANSCEIVER
C59
G
G
5
U13
VCCRX RXGND SD RXDP RXDN
4 2 3 NU R56
RX
OPTICAL SIGNAL F
3.3V
V23826-K305-C353 EXTERNAL 125MHZ REFCLK J4
1
F
TX
TXDP TXDN
8 7
VCCTX TXGND 3.3 V
6 9 0 4.7UF R55 C61 1.0UH L3 4.7UF C60 J25
U10 SUNI-2XGE PM3386 1 of 7 RXSD1 RXD1P RXD1N PLACE TERMINATION RESISTOR CLOSE TO HEADER
3
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1
49.9
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HEADER3
R58
4
NET_50 NET_50
K26 K25
SMB
NET_50 NET_50
M25 M26
TXD1P TXD1N CLK125
G25
E CLK_125 J10 EXT
3 2 1
3.3 V Y1 OSC_EH26
3 1 .47 R62 0.1UF C66 10UF C93
R24
RXSD0 RXD0P RXD0N
OSC
OUTPUT TRI_STATE 125.000MHZ
VCC GND
4 2
LC 2X5 SMALL FORM FACTOR TRANSCEIVER 3.3 V
0 4.7UF R53 C62
NET_50 NET_50
R25 R26
INTERNALLY AC TERMINATED
1.0UH L2 4.7UF C64
D
2
NU
R54
NET_50 NET_50
U26 U25
TXD0P TXD0N SLSI
D
U14
VCCRX RXGND SD RXDP RXDN
3 5 4
RX
OPTICAL SIGNAL
3.3V
V23818-K305-L57
1
C
TX
TXDP TXDN TXDIS VCCTX TXGND
9 10 8
C
3.3 V
6 0 4.7UF R28 C65 1.0UH 4.7UF L1 7
C63
B
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PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-2000991 DOCUMENT ISSUE NUMBER: 1.0 DRAWING: 2XGE_BLOCK 2XGE_BLOCK Tue Jan 30 16:25:07 2001 10 9 8 7 6 5 4 3 TITLE: S/UNI-2XGE REFERENCE DESIGN OPTICAL LINE SIDE INTERFACE ENGINEER: BDV 2 ISSUE DATE: YY/MM/DD REVISION NUMBER: 1.0 PAGE:2 1 OF 13 A
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UBGA U10 SUNI-2XGE PM3386 2 of 7 RXD0_7 RXD0_6 RXD0_5 RXD0_4 RXD0_3 RXD0_2 RXD0_1 RXD0_0 RX_CLK0 RX_DV0 RX_ER0 TXD0_7 TXD0_6 TXD0_5 TXD0_4 TXD0_3 TXD0_2 TXD0_1 TXD0_0 GTX_CLK0 TX_EN0 TX_ER0 MDIO MDC GMII-CH0 RXD0<7..0>
AD21 AF22 AE21 AD20 AF21 AE20 AD19 AF20 AC21 AE22 AF23 AA25 AA24 Y25 Y24 W26 W25 W23 W24 AD22 AE23 AF24 AE19 AD18 7 6 5 4 3 2 1 0
G
3G5>
3G6<
RXD0<7..0>
7 6 5 4 3 2 1 0 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43
136P QSE J12 P1 P3 P5 P7 P9 P11 P13 P15 P17 P19 P21 P23 P25 P27 P29 P31 P33 P35 P37 P39 P2 P4 P6 P8 P10 P12 P14 P16 P18 P20 P22 P24 P26 P28 P30 P32 P34 P36 P38 P40
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44
RX_CLK0 RX_DV0 RX_ER0 TXD0<7..0> RN57 RN57 RN57 RN57 RN56 RN56 RN56 RN56 RN58
8 7 6 5 8 7 6 5 5 1 2 3 4 1 2 3 4 4
F
33 33 33 33 33 33 33 33 33
3F5> 3F5> 3F5> 3F2<
MDC MDIO SUNI_RSTB\I TX_ER0 TX_EN0 GTX_CLK0 TXD0<7..0>
7 6 5 4 3 2 1 0
3E6> 3D2<> 3F6<> 6D3> 3F6> 3F6> 3F6> 3F6>
7 6 5 4 3 2 1 0
F
3F6< 3F6< 3F6<
RX_CLK0 RX_DV0 RX_ER0
1
GTX_CLK0 TX_EN0 TX_ER0 MDIO MDC
3F2< 3F2< 3F2< 3D2<> 3F2<> 3D2< 3F2<
TP59
CLK_125_0 PHY_INTB0\I
6C3<
GND1 GND2 GND3 GND4
HISPD_HEADER20X2
E E
UBGA U10 SUNI_2XGE PM3386 3 of 7 RXD1_7 RXD1_6 RXD1_5 RXD1_4 RXD1_3 RXD1_2 RXD1_1 RXD1_0 D RX_CLK1 RX_DV1 RX_ER1 TXD1_7 TXD1_6 TXD1_5 TXD1_4 TXD1_3 TXD1_2 TXD1_1 TXD1_0 GTX_CLK1 TX_EN1 TX_ER1 ATP1 ATP0 C GMII-CH1
5V
3D6<
RXD1<7..0>
7 6 5 4 3 2 1 0 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43
141P QSE J11 P1 P3 P5 P7 P9 P11 P13 P15 P17 P19 P21 P23 P25 P27 P29 P31 P33 P35 P37 P39 P2 P4 P6 P8 P10 P12 P14 P16 P18 P20 P22 P24 P26 P28 P30 P32 P34 P36 P38 P40
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44
RXD1<7..0>
B21 A22 D20 C21 B22 A23 D21 C22 B20 C20 A21 C18 D17 A19 B18 C17 A18 B17 C16 C19 A20 B19 M23 M24 7 6 5 4 3 2 1 0
3E5>
MDC MDIO SUNI_RSTB\I TX_ER1 TX_EN1 GTX_CLK1 TXD1<7..0>
7 6 5 4 3 2 1 0
3E6> 3F2<> 3F6<> 6D3> 3C6> 3C6> 3C6> 3D6>
RX_CLK1 RX_DV1 RX_ER1 TXD1<7..0> RN53 RN53 RN53 RN53 RN54 RN54 RN54 RN54 RN52
4 3 2 1 4 3 2 1 1 5 6 7 8 5 6 7 8 8
33 33 33 33 33 33 33 33 33
3D5> 3D5> 3D5> 3D2<
3D6< 3D6< 3D6<
TP53
1
RX_CLK1 RX_DV1 RX_ER1 CLK_125_1 PHY_INTB1\I
D
7 6 5 4 3 2 1 0
6C3<
GND1 GND2 GND3 GND4
HISPD_HEADER20X2
GTX_CLK1 TX_EN1 TX_ER1
3D2< 3D2< 3D2<
C 3.3 V
1 2 3
PWRBLOCK_3 J8 3.3V GND 5V
B
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PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-2000991 DOCUMENT ISSUE NUMBER: 1.0 DRAWING: 2XGE_BLOCK 2XGE_BLOCK Tue Jan 30 16:25:09 2001 10 9 8 7 6 5 4 3 TITLE: S/UNI-2XGE REFERENCE DESIGN GMII I/F AND COPPER PHY I/F ENGINEER: BDV 2 ISSUE DATE: YY/MM/DD REVISION NUMBER: 1.0 PAGE:3 1 OF 13 A
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UBGA U10 SUNI-2XGE PM3386 4 of 7 TDAT31 TDAT30 TDAT29 TDAT28 TDAT27 TDAT26 TDAT25 TDAT24 TDAT23 TDAT22 TDAT21 TDAT20 TDAT19 TDAT18 TDAT17 TDAT16 TDAT15 TDAT14 TDAT13 TDAT12 TDAT11 TDAT10 TDAT9 TDAT8 TDAT7 TDAT6 TDAT5 TDAT4 TDAT3 TDAT2 TDAT1 TDAT0 TMOD1 TMOD0 TERR TEOP TENB TSX TSOP TPRTY TFCLK TADR E DTPA1 DTPA0 PTPA STPA TX-INTERFACE
AE4 AF3 AF4 AD5 AC17 AF19 AE18 AD17 AF18 AE17 AD16 AF17 AE16 AF16 AD15 AE15 AD14 AE14 AE13 AD13 AF12 AE12 AD12 AF11 AC12 AE11 AF10 AD11 AE10 AF9 AD10 AE9 AF8 AC10 AD9 AE8 AC7 AD6 AF5 AD7 AD8 AE7 AF6 AE6 AF7 AE5 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUNI_TDAT<31..0>\I
6G9> 7E3>
G
G
F
UBGA U10
10G4>
F SUNI-2XGE PM3386 6 of 7 LD<15..0>\I D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ALE CSB INTB RDB WRB RSTB
B10 D11 A9 C10 B9 A8 C9 B8 A7 C8 B7 A6 C7 B6 A5 D7 A16 A15 B16 B15 C15 G3 C5 A4 D6 B5 C6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LA<23..2>\I
12 11 10 9 8 7 6 5 4 3 2 C14 B14 B13 C13 A12 B12 C12 A11 B11 A10 C11
6G4<>
10F3<> 6F3<
SUNI_TMOD<1..0>\I SUNI_TERR\I SUNI_TEOP\I SUNI_TENB\I SUNI_TSX\I SUNI_TSOP\I SUNI_TPRTY\I SUNI_TFCLK\I SUNI_TADR\I
6E9> 6F9> 6F9> 6F9> 6G9> 6F9> 6F9> 6E9> 9E2> 6E9> 6E9< 6F9< 6F9< 6F9<
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
3.3 V
4.7K
3.3 V
3.3 V
R24
4.7K
R63 4.7K
R64
4.7K
RN38 RN39 RN41 RN38
6 6 8 7
3 3 1 2
33 33 33 33
SUNI_DTPA1\I SUNI_DTPA0\I SUNI_PTPA\I SUNI_STPA\I
R25
E
3.3 V
6F9> 6E9>
SUNI_PAUSE1\I SUNI_PAUSE0\I SUNI_PAUSED1\I SUNI_PAUSED0\I SUNI_PMD_SEL1 SUNI_PMD_SEL0
Y4 AB1 AA2 Y3 F25 V24
PAUSE1 PAUSE0 PAUSED1 PAUSED0 PMD_SEL1 PMD_SEL0
100MIL 6F9< 6F9< J9
1 3 5 2 4 6
SUNI_CSB\I SUNI_INTB\I RDB\I WRB\I SUNI_RSTB\I
1 1 1 1
10D2> 10C2< 10C2> 10C2> 6D3>
TP50 TP49 TP52 TP51
D
C
UBGA U10 SUNI-2XGE PM3386 5 of 7 RDAT31 RDAT30 RDAT29 RDAT28 RDAT27 RDAT26 RDAT25 RDAT24 RDAT23 RDAT22 RDAT21 RDAT20 RDAT19 RDAT18 RDAT17 RDAT16 RDAT15 RDAT14 RDAT13 RDAT12 RDAT11 RDAT10 RDAT9 RDAT8 RDAT7 RDAT6 RDAT5 RDAT4 RDAT3 RDAT2 RDAT1 RDAT0 RMOD1 RMOD0 RENB RERR REOP RVAL RSX RSOP RPRTY RFCLK RX-INTERFACE
HEADER 3X2
4.7K
R59 4.7K
R60
V1 T4 U2 T3 U1 T2 T1 R3 R2 R1 P4 P3 P2 N2 N3 M1 M2 M3 L1 L2 K1 L3 K2 K3 J2 H1 K4 J3 H2 H3 G2 F1 W2 Y1 AA1 V3 V2 W3 U4 Y2 U3 W1
RN35 RN35 RN35 RN34 RN35 RN34 RN34 RN34 RN33 RN33 RN33 RN33 RN32 RN32 RN32 RN31 RN32 RN31 RN31 RN30 RN31 RN30 RN30 RN30 RN29 RN29 RN29 RN28 RN28 RN29 RN28 RN28 RN36 RN36
6 7 5 5 8 6 7 8 6 8 7 5 5 7 6 5 8 7 6 5 8 6 7 8 5 8 6 5 6 7 7 8 6 5
3 2 4 4 1 3 2 1 3 1 2 4 4 2 3 4 1 2 3 4 1 3 2 1 4 1 3 4 3 2 2 1 3 4
33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33
1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R23
6E9<
4.7K
SUNI_RDAT<31..0>\I
INSTALL JUMPER TO ENABLE GMII DEFAULT UNINSTALLED FOR SERDES
TRSTB TDI TDO TMS TCK JTAG-CON-MIS
S_TCK
S_TRSTB S_TDI S_TDO S_TMS
D
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SUNI_RMOD<1..0>\I SUNI_RENB\I
6E9< 6F9< 6E9> 6E9< 6F9< 6F9< 6F9< 6E9< 6F9< 9E2>
B
RN36 RN37 RN39 RN37 RN37 RN36
7 8 8 7 6 8
2 1 1 2 3 1
33 33 33 33 33 33
SUNI_RERR\I SUNI_REOP\I SUNI_RVAL\I SUNI_RSX\I SUNI_RSOP\I SUNI_RPRTY\I SUNI_RFCLK\I
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PMC-Sierra, Inc.
A DRAWING: 2XGE_BLOCK 2XGE_BLOCK Tue Jan 30 16:25:12 2001 DOCUMENT NUMBER: PMC-2000991 DOCUMENT ISSUE NUMBER: 1.0 TITLE: S/UNI-2XGE REFERENCE DESIGN PL3 & MICRO INTERFACE ENGINEER: 10 9 8 7 6 5 4 3 BDV 2 ISSUE DATE: YY/MM/DD REVISION NUMBER: 1.0 PAGE:4 1 OF 13 A
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DO NOT INSTALL R59 TO R65 USED FOR OPTIONAL 1.8V ANALOG REGULATOR SUPPLY
1.8 V 1.8V ANALOG REGULATOR G 3.3 V 1.8 VA AVDH_2
0.1UF 2 1
1.8 VA
NU
PLACE 0.1UF CAPACITORS NEAR EACH ANALOG POWER PIN RESISTOR AND 10UF CAPS CAN BE PLACED FARTHER AWAY AVDH_1
H26 J24 L25 N24 R23 U24 L24 H23 H24 K23 K24 G23 P23 P26 T24 T25 P25 N26 N23 N25 AC22 AC20 AC16 AC11 AC8 AC6 F23 F24 V23 AA23 W4 R4 M4 G1 D10 D12 D16 D19 D23 C24 B25 D18 D13 D8 D4 C3 B2 H4 N4 V4 AC4 AD3 AE2 AC9 AC14 AC19 AC23 AD24 AE25 Y23 T23 J23 D24 E24 AB24 AC24 H25 P24 C109 AC15 G24 AA3 L4 D15
UBGA U10 SUNI-2XGE PM3386 7 of 7 AVDH6 VSS_39 AVDH5 VSS_38 AVDH4 VSS_37 AVDH3 VSS_36 AVDH2 VSS_35 AVDH1 VSS_34 AVDH0 VSS_33 VSS_32 AVDL12 VSS_31 AVDL11 VSS_30 AVDL10 VSS_29 AVDL9 VSS_28 AVDL8 VSS_27 AVDL7 VSS_26 AVDL6 VSS_25 AVDL5 VSS_24 VSS_23 AVDL4 AVDL3 VSS_22 AVDL2 VSS_21 AVDL1 VSS_20 AVDL0 VSS_19 VSS_18 VDDI_17 VSS_17 VDDI_16 VSS_16 VDDI_15 VSS_15 VDDI_14 VSS_14 VDDI_13 VSS_13 VDDI_12 VSS_12 VDDI_11 VSS_11 VDDI_10 VSS_10 VDDI_9 VSS_9 VDDI_8 VSS_8 VDDI_7 VSS_7 VDDI_6 VSS_6 VDDI_5 VSS_5 VDDI_4 VSS_4 VDDI_3 VSS_3 VSS_2 VDDI_2 VDDI_1 VSS_1 VDDI_0 VSS_0 VDDO_27 VDDO_26 VDDO_25 VDDO_24 VDDO_23 VDDO_22 VDDO_21 VDDO_20 VDDO_19 VDDO_18 VDDO_17 VDDO_16 VDDO_15 VDDO_14 VDDO_13 VDDO_12 VDDO_11 VDDO_10 VDDO_9 VDDO_8 VDDO_7 VDDO_6 VDDO_5 VDDO_4 VDDO_3 VDDO_2 VDDO_1 VDDO_0 AVDQ_1 AVDQ_0 VDDQ_4 VDDQ_3 VDDQ_2 VDDQ_1 VDDQ_0 POWER 1.8 V VSSQ_4 VSSQ_3 VSSQ_2 VSSQ_1 VSSQ_0
1.0 R48
NU
R49
G AVDL_1
0.1UF
1%
C55 10UF
6
C56
LP3966ES-1.8 VOUT VIN SENSE SD GND TAB
3
10K
4 0.1UF 5
AVDH_3 AVDL_1 AVDL_2 AVDL_3 AVDL_4 AVDL_5
U15 SMT_REG
F AVDL_6 AVDL_7
PLACE DECOUPLING CAPACITORS NEAR POWER PINS 1.8 V 1.8 VA
1 1 1
1.8 V
1 1 1 1
3.3 V
1 1 1 1
G1, M4, W4, AC8. AC16, AC20, V23, F23, D16, D10
0.1UF C98 0.1UF C96 0.1UF C94 0.1UF C100 0.1UF C103 0.1UF C105 0.1UF C107 0.1UF C115 0.1UF C118 0.1UF
TP55 TP56
TP70 TP66
TP13 TP62
C117
1.8VA 1.8VA 1.8VA
1.8VD 1.8VD 1.8VD
3.3VD 3.3VD 3.3VD
TP65
TP57
TP20
PLACE TESPOINTS THROUGHOUT BOARD
0.1UF C99 0.1UF C97 0.1UF C95 0.1UF 0.1UF C101 0.1UF C104 0.1UF C119 0.1UF C106 0.1UF C113 0.1UF C116 0.1UF
C125
AF15 F26 AB2 J1 A17
1.8 V
1.8 VA
NU 1.0 R37 0.1UF 10UF C120 C48
C92
NU
R38
1%
C45
TP58
TP15
TP69
C114
1
10UF
E
1.8VA
1.8VD
3.3VD 3.3 V
A26 B26 C25 A25 B24 A14 A13 B3 A2 A1 B1 C2 N1 P1 AD2 AE1 AF1 AF2 AE3 AF13 AF14 AE24 AF25 AF26 AE26 AD25 AD26 AC25 AC26 AB26 Y26 V26 T26 L26 J26 G26 E26 D26 D25 C26
10UF
C126 10UF
C57
R33
1.8 V
1.8 VA
NU .47 R52 0.1UF 10UF C123 C40
NU
R51
1%
C112
C42
AVDL_2
F
1.8 V
1.8 VA
NU 1.0 R43 0.1UF
NU
R44
1%
AVDL_3 E
AVDL_4
PLACE DECOUPLING CAPACITORS NEAR POWER PINS 3.3 V D
.47 R50 0.1UF 10UF C124 C41
C3, H4, V4, AD3, AC9, AC19, AD24, Y23, J23, D24, B25 AVDH_1
D 1.8 V 1.8 VA
NU .47 R41 0.1UF 10UF C121 C46
NU
R42
1%
AVDL_5
3.3 V
10 0.1UF R35
3.3 V
1.0 R36 0.1UF 10UF C108 C49
1.8 VA
NU .47 R45 0.1UF 10UF
C
AVDH_2 3.3 V
NU
R46
C AVDL_6
C110
1%
0 R34 0.1UF C102 10UF C52
3.3 V PLACE 1 BULK DECOUPLING CAP ON EACH CORNER OF DEVICE
3.3 R47 0.1UF 10UF C122
1.8 V
1.8 VA NU
NU 1.0
AVDH_3 3.3 V 1.8 V
1%
R40
C44
AVDL_7
0.1UF 10UF
R39
B
B
C111
C43
10UF
10UF
10UF
10UF
10UF
10UF
10UF
C50
C54
C39
C37
C51
C53
C38
10UF
C36
PMC-Sierra, Inc.
A DRAWING: 2XGE_BLOCK 2XGE_BLOCK Tue Jan 30 16:25:16 2001 DOCUMENT NUMBER: PMC-2000991 DOCUMENT ISSUE NUMBER: 1.0 TITLE: S/UNI-2XGE REFERENCE DESIGN POWER SUPPLY ENGINEER: 10 9 8 7 6 5 4 3 BDV 2 ISSUE DATE: YY/MM/DD REVISION NUMBER: 1.0 PAGE:5 1 OF 13 A
C47
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G BGA U9 XCV200E-6BG352C 1 of 4 RN415 RN425 RN437 RN416 RN426 RN408 RN385 RN375
4 4 2 3 3 1 4 4
G
9E5> 4G6< 7E3> 4E7< 4E7< 4E7< 4E7< 4E5< 4E5> 4B7> 4B7> 4B7> 4B7> 4B7> 4E7> 4E5> 4E7> 4F7< 4E7< 4E7> 4E5< 4B7< 4B7> 4E7<
FPGA_TFCLK1 SUNI_TDAT<31..0>\I SUNI_TENB\I
4 3
LD<31..0>\I IO_2_10 IO_2_9 IO_2_8 IO_2_7 IO_2_6 IO_2_5 IO_2_4 IO_2_3 IO_2_2 IO_2_1 IO_L32P IO_L31P IO_L29P IO_L28P IO_L25P IO_L23P
C2 E3 F4 D1 G3 H3 G2 K3 K2 N3 N4 M2 L3 J1 F1 G4 M1 L2 L4 J2 J4 F2 F3 C1 M4 H2 E2 D2 E4 J3 D3 M3 G1 N2 P3 T3 V2 1 W3 W4 AA1 AA3 AB3 AD1 AB4 AA4 AC1 AA2 Y1 U3 T4 T2 R1 1 1 5 9 2 12 11 15 3 2 12 13 8 5
4F2<>
10F3<> 6F3< 10G4>
LA<23..2>\I
SUNI_TSOP\I
1
F
SUNI_TSX\I SUNI_TERR\I SUNI_PAUSE1\I SUNI_PAUSED1\I SUNI_RMOD<1>\I SUNI_RSX\I SUNI_REOP\I SUNI_RPRTY\I SUNI_RVAL\I SUNI_STPA\I SUNI_PAUSED0\I SUNI_DTPA0\I SUNI_TMOD<1>\I SUNI_TEOP\I SUNI_PTPA\I
2
33 33 33 33 33 33 33 33
D14 D22 C23 B24 C22 A24 B21 C20 D18 B18 D16 C15 B15 D15 C16 A18 C18 B19 A21 B22 D20 B23 B17 C17 D17 B20 A23 A16 C19 C21 D21 A15
GCK3 IO_0_12 IO_0_11 IO_0_10 IO_0_9 IO_0_8 IO_0_7 IO_0_6 IO_0_5 IO_0_4 IO_0_3 IO_0_2 IO_0_1 IO_L8P IO_L7P IO_L6P IO_L5P IO_L4P IO_L3P IO_L2P IO_L1P IO_L0P IO_L7N IO_L6N IO_L5N IO_L3N IO_L1N IO_VREF_0_L8N IO_VREF_0_L4N IO_VREF_0_L2N IO_VREF_0_L0N IO_LVDS_DLL_L9N
LOGIC ANALYZER/PROBE HEADER
10F3<> 6G4<> 4F2<>
LD<15..0>\I J5
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31
LA<23..2>\I
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 2 3 4 5 6 7 8 9 10 11 12 13
10G4>
FPGA_CSB\I
6 13 7 4 6
10D2>
RN407 RN406 RN427 RN388 RN397
0
2 3 2 1 2 4 1 2 4
33 33 33 33 33 33 33 33 33
SUNI_PAUSE0\I SUNI_RENB\I SUNI_RSOP\I SUNI_TADR\I SUNI_RMOD<0>\I SUNI_DTPA1\I SUNI_TMOD<0>\I SUNI_TPRTY\I SUNI_RERR\I
RN395 RN428 RN417 RN405
E
4B7> 4E7> 4F7< 4E7< 4B7>
IO_L31N IO_L29N IO_L28N IO_L27N IO_L25N IO_L24N IO_L23N IO_L22N IO_VREF_2_L30P IO_VREF_2_L26P IO_VREF_2_L24P IO_VREF_2_L22P IO_DOUT_BUSY_L21P IO_D2_L27P IO_DIN_D0_L21N IO_D3_L30N IO_D1_L26N IO_IRDY_L32N
RDB\I READYB\I
7 8 0 10 14 4 3 1
10C2> 10C2<
P_1 P_3 P_5 P_7 P_9 P_11 P_13 P_15 P_17 P_19 P_21 P_23 P_25 P_27 P_29 P_31
P_2 P_4 P_6 P_8 P_10 P_12 P_14 P_16 P_18 P_20 P_22 P_24 P_26 P_28 P_30 P_32
F
FPGA_CSB\I RDB\I WRB\I SUNI_CSB\I
10D2> 10C2> 10C2> 10D2>
HEADER 16X2 CONN_MALE WRB\I DIN 3.3 V
0.1UF
TP37
10C2> 8F8>
E
9 10 11
C26
9E5> 4D6>
FPGA_RFCLK1 SUNI_RDAT<31..0>\I
30 21 19 11 14 13 4 2 B14 B13 B10 A9 B7 C8 D8 B5 B4 C5 A3 A4 A7 C10 D11 B11 A12 C6 C7 A6 D9 B8 B9 C11 A11 B12 C13 D6 B6 C9 C12 A13 D5 C4
D
0 3 12 20 22 24 28 7 10 9 16 15 18 23 25 27 29 5 8 17 26 31 6 1
TP36
1
GCK2 IO_1_10 IO_1_9 IO_1_8 IO_1_7 IO_1_6 IO_1_5 IO_1_4 IO_1_3 IO_1_2 IO_1_1 IO_L18P IO_L16P IO_L14P IO_L13P IO_L12P IO_L10P IO_L19N IO_L18N IO_L17N IO_L16N IO_L15N IO_L14N IO_L13N IO_L12N IO_L11N IO_L10N IO_VREF_1_L19P IO_VREF_1_L17P IO_VREF_1_L15P IO_VREF_1_L11P IO_LVDS_DLL_L9P IO_WRITE_L20N IO_CS_L20P
IO_3_10 IO_3_9 IO_3_8 IO_3_7 IO_3_6 IO_3_5 IO_3_4 IO_3_3 IO_3_2 IO_3_1 IO_L42P IO_L41P IO_L40P IO_L39P IO_L37P IO_L36P IO_L35P IO_L33P IO_L41N IO_L39N IO_L36N IO_L35N IO_L33N IO_TRDY_1 IO_D7_L43P IO_D6_L38P IO_D4_L34P IO_INIT_L43N IO_D5_L37N IO_VREF_3_L42N IO_VREF_3_L40N IO_VREF_3_L38N IO_VREF_3_L34N
LW/RB\I
3
10C2>
2
SOT143 U8 VCC
4
MAX811T
SW1 RESET 320P
3 2
PBNO
TP34
2 0 4
RESET_PB FPGA_RFCLK2
9E5>
RESET MR GND
1
1
FPGA_TFCLK2
5
9E5>
TP31
6 1
D SUNI_RSTB\I
3D2< 3F2< 4E3<
6 4 2
PWROK_1_8V\I
3
12D8> 6B7< 10C2> 3F5>
AB2 Y2 1 V1 U2 R2 P1 1 AC3 V3 1 R3 AD2 U4 AC2 Y3 V4 R4
TP32
LED<6..0>
8 5
ADSB\I
TP35 TP33
0
PHY_INTB0\I
INIT
7
8F8<
C
C PHY_INTB1\I FPGA_INTB\I RSTOB\I
3D5> 10C2< 10C2> 10D2<>
1
GPIO<8..0>\I
VIRTEX_ONE
B
6D3> 8D10>
LED<6..0> DONE
6 5 4 A1 A2 A3 A4
B GREEN D3
K1 K2 K3 K4
RN60 200
2 3 4 5 16 7 8 9 10
RSIP9
LED SSF-LXH5147
3 2 1 0 A1 A2 A3 A4
GREEN D2
K1 K2 K3 K4
TP72
1
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-2000991 DOCUMENT ISSUE NUMBER: 1.0 TITLE: S/UNI-2XGE REFERENCE DESIGN FPGA PL3 I/F ENGINEER: BDV 2 ISSUE DATE: YY/MM/DD REVISION NUMBER: 1.0 PAGE:6 1 OF 13 A
LED SSF-LXH5147
A DRAWING: FPGA_BLOCK FPGA_BLOCK Tue Jan 30 16:24:57 2001
10
9
8
7
6
5
4
3
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G
13F9>
SYS_TFCLK\I BGA U9
G
13D9<
SYS_RDAT<31..0>\I
13D9< 13B9< 13B9< 13B9>
0
XCV200E-6BG352C 2 of 4 SYS_RMOD<1>\I SYS_REOP\I SYS_RSX\I SYS_RENB\I SYS_RPRTY\I RN18 RN18 RN19 RN20 RN19 RN21 RN22 RN21 RN24 RN23 RN22 RN20 RN21 RN20 RN23 RN23 RN22 RN23 RN21 RN19 RN22 RN19 RN18 RN24 RN20
1 4 1 2 3 1 2 4 3 3 4 4 3 1 1 4 3 2 2 4 1 2 2 1 3 3 1 8 5 8 7 6 8 7 5 6 6 5 5 6 1 8 1 8 5 6 7 7 5 8 1 7 7 1 8 6 1 6 8
SYS_TDAT<31..0>\I IO_6_10 IO_6_9 IO_6_8 IO_6_7 IO_6_6 IO_6_5 IO_6_4 IO_6_3 IO_6_2 IO_6_1 IO_L75P IO_L74P IO_L73P IO_L72P IO_L71P IO_L70P IO_L69P IO_L68P IO_L67P IO_L66P IO_L65P
AB24 AA23 AC25 Y23 Y25 AA26 W25 V26 T24 P23 P24 R25 T26 U25 U24 U23 W24 Y24 AB25 AC26 AD25 R26 T25 T23 V25 V23 AA24 AC24 N26 R24 Y26 AA25 AD26 M26 L23 K24 H23 F26 F25 F23 C26 E23 D24 C25 F24 H24 H25 J25 L24 M24 N24 D25 E25 G24 G25 J23 K23 J26 K25 M23 M25 L26 E24 D26 G26 N25 1 3 4 4 3 1 1 1 4 3 1 3 2 2 4 2 4 1 2 4 4 1 1 3 2 1 1 1 2 3 3 1 12 16 9 20 18 13 21 23 31
13H9>
33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33
13D9<
3 9 8 17 14 11 4 6 1 13 15 10 12 5
F
AE13 AE3 AD5 AC6 AF4 AD7 AE7 AD8 AD10 AE10 AD13 AE12 AD11 AF9 AD9 AF6 AC7 AC5 AF12 AD12 AE11 AC11 AE9 AF7 AC9 AE6 AD6 AF3 AD4 AC12 AE8 AE5 AE4 AC13
GCK0 IO_4_10 IO_4_9 IO_4_8 IO_4_7 IO_4_6 IO_4_5 IO_4_4 IO_4_3 IO_4_2 IO_4_1 IO_L54P IO_L52P IO_L51P IO_L50P IO_L48P IO_L46P IO_L44P IO_L54N IO_L53N IO_L52N IO_L51N IO_L50N IO_L49N IO_L48N IO_L47N IO_L46N IO_L45N IO_L44N IO_VREF_4_L53P IO_VREF_4_L49P IO_VREF_4_L47P IO_VREF_4_L45P IO_LVDS_DLL_L55P
RN51 4 RN51 2
1
5 7
33 33
29 26 27 28 22 19 11 8 7 30 24 25 15 10
SUNI_F_RFCLK SUNI_F_TFCLK
9E4< 9E4<
F
TP39
TP27 TP23
13C9<
7
SYS_RERR\I SYS_RSOP\I SYS_RMOD<0>\I
E
16 2
13C9< 13D9<
TP25 TP24 TP26
13D9<
18
SYS_RVAL\I SYS_RFCLK\I
RN18 RN25
IO_L75N IO_L73N IO_L72N IO_L71N IO_L69N IO_L67N IO_L65N IO_TRDY_2 IO_VREF_6_L74N IO_VREF_6_L70N IO_VREF_6_L68N IO_VREF_6_L66N IO_7_11 IO_7_10 IO_7_9 IO_7_8 IO_7_7 IO_7_6 IO_7_5 IO_7_4 IO_7_3 IO_7_2 IO_7_1 IO_L85P IO_L83P IO_L81P IO_L80P IO_L79P IO_L77P IO_L76P IO_L86N IO_L85N IO_L84N IO_L83N IO_L82N IO_L81N IO_L80N IO_L79N IO_L78N IO_L77N IO_VREF_7_L78P IO_VREF_7_L86P IO_VREF_7_L84P IO_VREF_7_L82P IO_IRDY_L76N
1 1
TP38 TP46
1 1
TP44 TP42
E
17 14 6
13B9> 13H9>
SUNI_TDAT<31..0>\I
TP48
6 5 5 6 8 8 8 5 6 8 6 7 7 5 7 5
6G9> 4G6<
SYS_TDAT<31..0>\I
20 21 25 31
RN24 RN25 RN25 RN26
13G9> 13H9> 13H9>
4 2 4 4
SYS_TPRTY\I SYS_TSX\I SYS_TSOP\I
TP29
5 7 5 5 1
33 33 33 33
D
1 5 2
AF14 AF15 AE15 AD16 AE18 AD19 AC19 AF21 AD21 AD22 AF24 AC22 AC21 AF23 AE21 AF20 AD18 AD17 AC16 AE16 AD15 AE22 AE20 AC17 AF18 AE17 AE23 AD20 AC18 AC15 AD14
GCK1 IO_5_11 IO_5_10 IO_5_9 IO_5_8 IO_5_7 IO_5_6 IO_5_5 IO_5_4 IO_5_3 IO_5_2 IO_5_1 IO_L64P IO_L63P IO_L62P IO_L61P IO_L60P IO_L59P IO_L58P IO_L57P IO_L56P IO_L63N IO_L61N IO_L59N IO_L58N IO_L57N IO_VREF_5_L64N IO_VREF_5_L62N IO_VREF_5_L60N IO_VREF_5_L56N IO_LVDS_DLL_L55N
RN46 RN47 RN49 RN49 RN49 RN50 RN44 RN43 RN43 RN43 RN50 RN49 RN48 RN48 RN46 RN46 RN44 RN44 RN50 RN48 RN47 RN47 RN47 RN46
33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33
29 27 20 16 15 13 6 10 7 5 14 21 22 24 30 31 8 12 17 18 23 26 25 28
D
13F9>
3
SYS_TERR\I SYS_TEOP\I SYS_TADR\I RN27 3 TP28 RN26 3 RN26 1 RN25 3
1 6 6 8 6
13G9> 13F9>
28 26 24 22 0
TP45
7 5 5 8 8 6 7 8
33 33 33 33 33 33 33
13H9>
29 30 27 4
SYS_TMOD<0>\I RN27 RN27 RN27 SYS_TMOD<1>\I SYS_TENB\I RN26 RN24
2 2 7 7 4 1 2 5 8 7
13H9> 13G9>
C
23 19
33 33
RN50 RN44 RN48
TP40 TP47 TP41
7 6 6
33 33 33
11 9 19
C
TP43
VIRTEX_TWO
B
B
PMC-Sierra, Inc.
A DRAWING: FPGA_BLOCK FPGA_BLOCK Tue Jan 30 16:25:00 2001 DOCUMENT NUMBER: PMC-2000991 DOCUMENT ISSUE NUMBER: 1.0 TITLE: SUNI 2XGE REFERENCE DESIGN FPGA PL3 I/F ENGINEER: 10 9 8 7 6 5 4 3 BDV 2 ISSUE DATE: YY/MM/DD REVISION NUMBER: 1.0 PAGE:7 1 OF 13 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
1.8 V
PLACE NEAR EACH CORNER OF FPGA 3.3 V
0.1UF
C84 0.1UF
0.1UF
0.1UF
C81 0.1UF
C79 0.1UF
0.1UF
C75 0.1UF
C73 0.1UF
C69 0.1UF
C86
C82
C78
C71
47UF
C23 47UF
C28 47UF
C34 47UF
+
+
+
C31
+
G
PLACE CAPS NEAR PINS A20,C14,D10,K4,P2,T1,AC10,AF16,R23,L25 PLACE BULK DECOUPLING CAPS NEAR EACH I/O BANK OF FPGA 3.3 V
G
10UF
10UF
C32 10UF
C30 10UF
C24 10UF
C25 10UF
C27 10UF
+
+
+
+
+
+
+
C33
3.3 V 3.3 V
3 4.7K 4.7K
3.3 V
4.7K R11 4.7K 2 R10
1.8 V JTAG CONFIG AND READBACK 3.3 VFPGA_JTAG 100MIL J6 1 P_1 3.3V 2 P_2 TCK 3 P_3 TDI 4 P_4 TDO 5 P_5 TMS 6 P_6 GND
A20 B16 C14 D12 D10 K4 L1 P2 T1 W2 AC10 AF11 AE14 AF16 AE19 V24 R23 P25 L25 J24 N23 K26 G23 AE25 W23 U26 AF17 AC20 AC14 AF10 AE2 AC8 Y4 U1 P4 K1 H4 B2 D13 D7 A10 D19 B25 A17
F
44
VCC
SOCKET U4 41 VPP
0.1UF C127
GND
GND
27
CEO
XC1702L-PC44 DATA 2 CLK 5 OE 19 CE 21
DIN CCLK INIT
6E3< 6C3>
C3 AD3 AC4 AC23 AB23 AD24
BGA U9 XCV200E-6BG352C 3 of 4 CCLK DONE PROGRAM M2 M1 M0 CONTROL TCK TDI TDO TMS DXP DXN
C24 B3 D4 D23 AE24 AD23
6 RN17 RN17
BGA U9 XCV200E-6BG352C 4 of 4 VCCINT_20 VCCINT_19 VCCINT_18 VCCINT_17 VCCINT_16 VCCINT_15 VCCINT_14 VCCINT_13 VCCINT_12 VCCINT_11 VCCINT_10 VCCINT_9 VCCINT_8 VCCINT_7 VCCINT_6 VCCINT_5 VCCINT_4 VCCINT_3 VCCINT_2 VCCINT_1 VCCO_24 VCCO_23 VCCO_22 VCCO_21 VCCO_20 VCCO_19 VCCO_18 VCCO_17 VCCO_16 VCCO_15 VCCO_14 VCCO_13 VCCO_12 VCCO_11 VCCO_10 VCCO_9 VCCO_8 VCCO_7 VCCO_6 VCCO_5 VCCO_4 VCCO_3 VCCO_2 VCCO_1 POWER GND_32 GND_31 GND_30 GND_29 GND_28 GND_27 GND_26 GND_25 GND_24 GND_23 GND_22 GND_21 GND_20 GND_19 GND_18 GND_17 GND_16 GND_15 GND_14 GND_13 GND_12 GND_11 GND_10 GND_9 GND_8 GND_7 GND_6 GND_5 GND_4 GND_3 GND_2 GND_1
A26 A25 A22 A19 A14 A8 A5 A2 A1 B26 B1 E26 E1 H26 H1 N1 P26 W26 W1 AB26 AB1 AE26 AE1 AF26 AF25 AF22 AF19 AF13 AF8 AF5 AF2 AF1
C35
+
CONFIGURATION EPROM
C29 10UF
F
7
3
24
TCK TDI TDO TMS 4.7K RN17
8
E 3.3 V
0.1UF
1
3.3 V
E
J14 XCHECKER 3.3V 1 1 GND 2 2 33 CCLK 4 4 DONE 5 5 DIN 6 6 PROGRAMB 7 7 INIT 8 8 DONE 9 9
HEADER9
DONE
C15
6B7<
D
D
3.3 V
P_MODE J7
P_1 P_3 P_5 P_2 P_4 P_6
2 4 6
1 3 5
HEADER 3X2
4
3
5
6
7
2
C
4.7K 4.7K 4.7K
INSTALL JUMPERS FOR SLAVE SERIAL (XCHECKER) MODE UNINSTALL JUMPERS FOR MASTER SERIAL (EPROM) DEFAULT MODE
C
RN45 RN45 RN45
3.3 V
0.1UF
C88 0.1UF
C80 0.1UF
0.1UF
C76 0.1UF
C74 0.1UF
0.1UF
0.1UF
C68 0.1UF
C70 0.1UF
0.1UF
C87 0.1UF
C77
C72
C67
C83
C85
B
PLACE DECOUPLING CAPS NEAR PINS B2,K1,U1,AE2,AF10,AF17,AE25,U26,K26,B25,A17,A10
B
PMC-Sierra, Inc.
A DRAWING: FPGA_BLOCK FPGA_BLOCK Tue Jan 30 16:25:03 2001 DOCUMENT NUMBER: PMC-2000991 DOCUMENT ISSUE NUMBER: 1.0 TITLE: S/UNI-2XGE REFERENCE DESIGN FPGA POWER & CONFIGURATION ENGINEER: 10 9 8 7 6 5 4 3 BDV 2 ISSUE DATE: YY/MM/DD REVISION NUMBER: 1.0 PAGE:8 1 OF 13 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G
G
F
F
3.3 V
0.1UF 4 8 15 20 C90 0.1UF
SUNI PL3 INTERFACE CLOCK SOURCE SELECTION
C91
U11 E
1
VCC VCC VCC VCC
1
PI49FCT3807
7F3>
SUNI_F_TFCLK
1 1
SB4 12 SB3 12 SB2 12 SB1 12
2 2 2 2
SUNI_TFCLK\I
4E7<
E SUNI_RFCLK\I
4B7<
3.3 V
8PIN_DUAL-P1NC HCMOS 100.000MHZ 3.3V 100PPM U12
8
A
0.1UF
VDD
OUT
5 1
4 C89
GND NC/TS
B0 B1 B2 B3 B4 B5 B6 B7 B8 B9
3 RN55 5 7 9 11 RN59 12 14 16 18 19
8 7 6 5 4 3 2 1
1 2 3 4 5 6 7 8
33
33
SUNI_O_TFCLK SUNI_O_RFCLK SYS_RSYSCLK\I SYS_TSYSCLK\I FPGA_RFCLK2 FPGA_RFCLK1 FPGA_TFCLK2 FPGA_TFCLK1 CLK1 CLK2
1 1
13C9< 13F9< 6D3< 6E9< 6D3< 6G9<
7F3>
SUNI_F_RFCLK
1
33 R26 33 R27
CLK100
TP60
GND GND GND GND GND
CLK100
TP61
PLACE BUFFER LESS THAN 2CM FROM OSCILLATOR D
2 6 10 13 17
D
C
C
B
B
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-2000991 DOCUMENT ISSUE NUMBER: 1.0 DRAWING FPGA_BLOCK FPGA_BLOCK LAST_MODIFIED=Tue Jan 30 16:25:05 2001 10 9 8 7 6 5 4 3 TITLE: S/UNI 2XGE REFERENCE DESIGN REFCLK AND PL3 CLOCK ENGINEER: BDV 2 ISSUE DATE: YYYY/MM/DD REVISION NUMBER: 1.0 PAGE:9 TRUE 1 OF 13 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE
11H7> 11H7>
REV
DESCRIPTION
DATE
APPR
H
H PLACE DECOUPLING CAPACITORS NEAR EACH POWER PIN
11H7>
3_3V_LONG
0.1UF C17 0.1UF C137 0.1UF C134 0.1UF C133 0.1UF 0.1UF C136 10UF C5 10UF C135 C18
VIO_LONG 3_3V_LONG PQFP U1 V_I/O VDD0 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10
133 117 162 100 85 70 56 45 32 14 1 52
0.1UF
11H8<>
AD<31..0>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C132
LA<23..2>\I LA23 LA22 LA21 LA20 LA19 LA18 LA17 LA16 LA15 LA14 LA13 LA12 LA11 LA10 LA9 LA8 LA7 LA6 LA5 LA4 LA3 LA2 LAD31 LAD30 LAD29 LAD28 LAD27 LAD26 LAD25 LAD24 LAD23 LAD22 LAD21 LAD20 LAD19 LAD18 LAD17 LAD16 LAD15 LAD14 LAD13 LAD12 LAD11 LAD10 LAD9 LAD8 LAD7 LAD6 LAD5 LAD4 LAD3 LAD2 LAD1 LAD0
131 130 129 128 127 125 124 123 121 120 119 118 116 115 114 111 110 109 108 107 106 105 61 62 63 64 65 67 68 69 72 73 74 77 79 80 81 82 83 84 86 87 89 90 91 92 93 95 96 97 98 99 102 104 94 134 135 136 137 157 156 155 154 148 147 54 71 75 103 138 126 144 139 53 145 150 153 152 151 149 142 76 141 140 143 55 1 58 1 59 1 60 1 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4F5< 6F1< 6G3<
G
F
RN12 RN12 RN12 RN11 RN11 RN11 RN11 RN1 RN2 RN2 RN2 RN2 RN3 RN3 RN3 RN3 RN6 RN7 RN7 RN7 RN7 RN8 RN8 RN8 RN9 RN9 RN9 RN9 RN10 RN10 RN10 RN10
2 3 4 1 2 3 4 2 1 2 3 4 1 2 3 4 4 1 2 3 4 1 2 3 1 2 3 4 1 2 3 4
7 6 5 8 7 6 5 7 8 7 6 5 8 7 6 5 5 8 7 6 5 8 7 6 8 7 6 5 8 7 6 5
10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10
173 174 175 2 3 4 5 6 9 10 11 12 15 16 17 18 30 33 34 35 36 37 38 39 41 42 43 46 47 48 49 50 169
AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 PME
G
LD<31..0>\I
4F2<> 6G4<> 6F3<
F
TP1
PME 1
11H8<>
C/BE<3..0>
3 2 1 0
E
RN1 RN4 RN6 RN8 RN5
R2
3 1 3 4 1 2 4 3 2 4 1 1 2 1 3 4
6 8 6 5 8 7 5 6 7 5 8 8 7 8 6 5
10 10 10 10 10
10
7 19 29 40 23 51 20 8 25 28 172 26 171 27 24 170 21 22
C/BE3 C/BE2 C/BE1 C/BE0 DEVSEL ENUM FRAME IDSEL LOCK PAR PCLK PERR RST SERR STOP INTA IRDY TRDY
3.3 V E 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K RN13
5 4
11F5<> 11C5< 11E5<> 11E5> 11B5<> 11C5<> 11C5> 11A5<> 11D5> 11F5< 11C5<> 11G5< 11D5<> 11B5<> 11H7>
P_DEVSELB P_ENUMB P_FRAMEB P_IDSEL P_LOCKB P_PAR P_CLK P_PERRB P_RSTB P_SERRB P_STOPB P_INTAB P_IRDYB P_TRDYB VIO_PCI\I
RN4 RN1 RN5 RN6 RN5 RN1 RN6 RN5 RN12 RN4 RN4
10 10 10 10 10 10 10 10 10 10 10
PCI9030-PQFP
4
2
2
1
1
3
4
3
5
7
7
8
8
6
5
6
RN15
RN15
RN16
RN16
RN15
RN16
RN14
RN14
8
1
RN16
4.7K GPIO<8..0>\I
6C3<>
D U2
2
B A
VCC OUT GND
3 4
GPIO8 GPIO7/LA24 GPIO6/LA25 GPIO5/LA26 GPIO4/LA27 GPIO3/CS3* GPIO2/CS2* GPIO1/LLOCK0* GOIO0/WAIT0* CS1 CS0 CPCISW BCLKO ALE LPMRESET ADS LPMINT BTERM BLAST LED_ON LCLK LGNT LINTI2 LINTI1 LREQ LRESETO LW/R* MODE RD WR READY LBE3 LBE2 LBE1 LBE0
D
12D8> 11C5>
1 PWROK_1_8V\I
5
FPGA_CSB\I SUNI_CSB\I
1 1 1
6F1< 6F3< 4E2< 6E1<
BD_SELB\I
TP5 TP10 TP11
CPCISW BCLKO ALE ADSB\I
6C3<
3.3 V DIP8_SOCKET U5
NM93CS66LEN
112
BD_SEL*/TEST
4.7K
R15
1
LED_ON
TP4
C16
C
8 7 6 5 R14
4.7K
VCC PRE PE GND
CS SK DI DO
1 2 3 4
158 161 159 160
EECS EEDI EEDO EESK
0.1UF
SUNI_INTB\I FPGA_INTB\I RSTOB\I LW/RB\I RDB\I WRB\I READYB\I
TP6 TP7 TP8 TP9
4E3> 6C3> 6C3< 6E3< 4E2< 6E1< 6F3< 4E2< 6E1< 6E3< 6E3>
C
4.7K
R16
11H7>
3_3V_LONG 4.7K 5 4.7K 6 4.7K
TP2
1
164 165 168 167 166
TRST TCK TDI TDO TMS VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13
7
3.3 V RN13 4 RN13 3 RN13
2
4.7K
4.7K
4.7K
176 163 146 132 122 113 101 88 78 66 57 44 31 13
B
B
8
7 2
4.7K
1
R61
RN14
RN14
3
6
A
NOTES: 1. 2. 3. 4. 5.
ALL 10 OHM STUBS WITHIN 0.6 OF J1 ALL PCI SIGNAL TRACES < 1.5 EXCEPT P_CLK P_CLK TRACE MUST BE 2.5 +/- 0.1 CPCI BUS TRACES ARE 65 OHM 39 OHM STUB RESISTOR ON REQB PLACED NEAR BRIDGE PIN DRAWING: PCI_INTERFACE PCI_INTERFACE Tue Jan 30 16:25:20 2001
RN15
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-2000991 DOCUMENT ISSUE NUMBER: 1.0 TITLE: S/UNI-2XGE REFERENCE DESIGN CPCI INTERFACE ENGINEER: BDV 2 ISSUE DATE: YY/MM/DD REVISION NUMBER: 1.0 PAGE:10 1 OF 13 A
10
9
8
7
6
5
4
3
10
9
8
7
6
5
4
3
2
1
REVISIONS
AD<31..0>
10G8<> 10C8< 10H5< 10H6<
ZONE
REV
DESCRIPTION
DATE
APPR
H C/BE<3..0>
10E8<>
H
10D8< 12F8<
3.3 V
12F8<
12G8<
10G6<
1 4 2 3
4.7K 4.7K 4.7K 4.7K
3_3V_PCI\I
5V_PCI\I
PLACE DECOUPLING CAPS CLOSE TO CONNECTOR 3_3V_LONG VIO_PCI\I VIO_LONG RN61 8 RN61 5 RN61 7 RN61 6 5V_PCI\I
0.1UF
CPCI J1
G
J1 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 ZPACK5X22A CPCI
A1 A2 A3 A4 A5 A6 A7 AD<30> A8 AD<26> A9 C/BE<3> A10 AD<21> A11 AD<18> A15 A16 A17 A18 A19 A20 AD<12> A21 A22 AD<7> A23 A24 AD<1> A25 B1 B2 B3 B4 B5 B6 B7 AD<29> B8 B9 B10 B11 AD<17> B15 B16 B17 B18 B19 AD<15> B20 B21 AD<9> B22 B23 AD<4> B24 B25 C1 C2 C3 C4 C5 C6 C7 AD<28> C8 C9 AD<23> C10 C11 AD<16> C15 C16 C17 C18 C19 AD<14> C20 C21 AD<8> C22 C23 AD<3> C24 C25 D1 D2 D3 D4 D5 D6 D7 D8 AD<25> D9 D10 AD<20> D11 D15 D16 D17 D18 D19 D20 AD<11> D21 D22 AD<6> D23 D24 AD<0> D25 E1 E2 E3 E4 E5 E6 AD<31> E7 AD<27> E8 AD<24> E9 AD<22> E10 AD<19> E11 C/BE<2> E15 E16 E17 E18 C/BE<1> E19 AD<13> E20 AD<10> E21 C/BE<0> E22 AD<5> E23 AD<2> E24 E25
3_3V_PCI\I
0.1UF C7 0.1UF
VIO_PCI\I
0.1UF
C131 10UF
C129 10UF
C130 10UF
C128 10UF
+
+
+
+
C9
C8
P_INTAB
10D8>
30 26 3 21 18
12V_PCI\I P_DEVSELB P_SERRB
10E8> 10D8>
10 R1 0.1UF C2 10UF
VEE_PCI\I
0.1UF
10UF
C4
C1
F
F1 F3 F5 F7 F9 F11 F13 F15 F17 F19 F21 F23 F25
F1 F3 F5 F7 F9 F11 F13 F15 F17 F19 F21 F23 F25
12 7 1
+
C3
+
C6
G
F
VEE_PCI\I HEALTHYB\I
29
12E8< 12E8>
P_IDSEL
17
10E8< 10E8<
P_FRAMEB
E
15 9 4
E
P_RSTB
28 23 16
P1
10D8<
M1 STRIP3
3
1
10M 2 R18
HOLE_SIZE= 150 MIL
MOUNTING HOLE
D
P_IRDYB
STRIP2
10D8<
ESD STRIP
10M R19
TP74 T CHASSIS D TP73 T CHASSIS
14 8 3
STRIP1
CPCI ESD STRIP
1
P_ENUMB 12V_PCI\I
10E8> 12E8<
P_CLK
25 20
10E8<
C
10M
R17
C
BD_SELB\I P_STOPB P_PAR
11 6 0
10D8< 12E8< 10D8> 10E8<>
B
B
31 27 24 22 19 2
P_TRDYB P_LOCKB P_PERRB
1 13 10 0 5 2
10D8> 10E8< 10E8>
DRAWING: TITLE=PCI_INTERFACE ABBREV=PCI_INTERFACE LAST_MODIFIED=Tue Jan 30 16:25:23 2001
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-2000991 DOCUMENT ISSUE NUMBER: 1.0 TITLE: S/UNI-2XGE REFERENCE DESIGN CPCI CONNECTOR ENGINEER: BDV 2 ISSUE DATE: YY/MM/DD REVISION NUMBER: 1.0 PAGE:11 1 OF 13 A
A
10
9
8
7
6
5
4
3
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G
HOT SWAP CONTROLLER
5V
G
11H7>
5V_PCI\I
Q2 8IRF7413 3 2 5 4 1
0.01 R6 7 6
7 6
Q1 8 IRF7413 3 2 5 4 1
3.3 V +5V
11H8>
3_3V_PCI\I
0.01 R13 0.01 R12
+3.3V
220UF
R9
10
10
C14
R7
+
F
11H7>
100 R8 0.047UF
+12V
F
VIO_PCI\I
10 11 13 12 1.2K 2.0K 2.0K
SSOP-1 U3
R3
R5
R4
3V_IN
GATE
3V_OUT
5V_IN
3V_SENSE
11C5> 11F5> 11C5>
12V_PCI\I VEE_PCI\I BD_SELB\I
5V_SENSE
5V_OUT
14
9
3
1 2 5 6
12V_IN VEE_IN ONB FAULTB
12V_OUT VEE_OUT
16 15
12V_OUT VEE_OUT
LTC1643LCGN
5V
E
11F5<
7 0.1UF 2
C13
+12V
R30 63.4
3.3 V
R32
560
560
R31
150
R29
PWRGDB
GND
HEALTHYB\I
0.1UF C10
TIMER
E
D1
C12
8
4
GREEN D4
K1 K2 K3 K4
0.01UF
1
VEE
C11
A1 A2 A3 A4
LED SSF-LXH5147
GND VEE
D
10D8< 6D3<
D PWROK_1_8V\I
5V
3.3 V
1.8 V
220UF
100K
U7
2.2UF
C
7 8 C21
+
R22
VCC
MAX812REUS-T
C22
+
U6 SIE501.8R VIN1 VOUT1 1 VIN2 VOUT2 2 VOUT3 4 PWROK SENSE TRIM ENABLE GND GND
5 6 3 2.2UF C19 220UF
4.7K
R21
4
C
+
C20 182
1
R20
MR
RESET GND
+
3
2
9 10 11
B
B
DRAWING: TITLE=POWER_BLOCK ABBREV=POWER_BLOCK LAST_MODIFIED=Tue Jan 30 16:25:28 2001
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-1991414 DOCUMENT ISSUE NUMBER: 1.0 TITLE: SUNI-2XGE REFERENCE DESIGN POWER_BLOCK ENGINEER: 10 9 8 7 6 5 4 3 BDV 2 ISSUE DATE: YY/MM/DD REVISION NUMBER: 3 PAGE:12 1 OF 13 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE
7G3< 7E10< 7C8<
REV
DESCRIPTION
DATE
APPR
SYS_TDAT<31..0>\I SYS_TMOD<1..0>\I H
H
7D8<
SYS_TSOP\I
J3
0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
7D8<
SYS_TSX\I
2 7 12 17 22 27 31
G
7D8<
A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 A9 B9 A10 B10 AMP_HS3_6X10 FEMALE_RA
B1 B2 1 B3 B4 B5 B6 B7 B8 B9 B10
1 6 11 16 21 26 30
G
SYS_TPRTY\I
J3
7C8< 7D8<
SYS_TENB\I SYS_TEOP\I
9E5>
SYS_TSYSCLK\I
C1 C2 C3 C4 0 C5 5 10 C6 15 C7 20 C8 25 C9 C10
C1 D1 C2 D2 C3 D3 C4 D4 C5 D5 C6 D6 C7 D7 C8 D8 C9 D9 C10 D10 AMP_HS3_6X10 FEMALE_RA
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
4 9 14 19 24 29
7G8<
SYS_TFCLK\I F
J3
F
7D8< 7D8<
SYS_TADR\I SYS_TERR\I
3 8 13 18 23 28
J3
AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10
J3
CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10
J3
EF1 EF2 EF3 EF4 EF5 EF6 EF7 EF8 EF9 EF10
E1 E2 E3 E4 E5 E6 E7 E8 E9 E10
E
AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AMP_HS3_6X10 FEMALE_RA
CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10 AMP_HS3_6X10 FEMALE_RA
EF1 EF2 EF3 EF4 EF5 EF6 EF7 EF8 EF9 EF10 AMP_HS3_6X10 FEMALE_RA
E1 F1 E2 F2 E3 F3 E4 F4 E5 F5 E6 F6 E7 F7 E8 F8 E9 F9 E10 F10 AMP_HS3_6X10 FEMALE_RA
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10
E
7G9> 7F8> 7E8> 7E8>
SYS_RDAT<31..0>\I SYS_RMOD<1..0>\I SYS_RVAL\I
J2
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
D
7F8>
SYS_RPRTY\I
1 6 11 16 21 26 31
7E8>
SYS_RSOP\I
A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 A9 B9 A10 B10 AMP_HS3_6X10 FEMALE_RA
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10
D
0 5 10 15 20 25 30
J2
9E5>
SYS_RSYSCLK\I
0
C
7E8>
SYS_RERR\I
C1 C2 C3 C4 C5 4 C6 9 14 C7 19 C8 24 C9 29 C10
C1 D1 C2 D2 C3 D3 C4 D4 C5 D5 C6 D6 C7 D7 C8 D8 C9 D9 C10 D10 AMP_HS3_6X10 FEMALE_RA
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
1 3 8 13 18 23 28
C
7E8<
SYS_RFCLK\I
J2
1 1 1 1 1 1 1 1
7F8< 7F8> 7F8>
SYS_RENB\I SYS_RSX\I SYS_REOP\I
2 7 12 17 22 27
B
E1 E2 E3 E4 E5 E6 E7 E8 E9 E10
E1 F1 E2 F2 E3 F3 E4 F4 E5 F5 E6 F6 E7 F7 E8 F8 E9 F9 E10 F10 AMP_HS3_6X10 FEMALE_RA
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10
PLACE HEADERS THROUGHOUT BOARD
TP64 TP71 TP68 TP63 TP54 TP30 TP22 TP12
GND GND GND GND GND GND GND GND
1 1 1 1 1 1 1 1
TP14 TP17 TP21 TP3 TP16 TP18 TP19 TP67
GND GND GND GND GND GND GND GND
B
J2
AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10
J2
CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10
J2
EF1 EF2 EF3 EF4 EF5 EF6 EF7 EF8 EF9 EF10
A
AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AMP_HS3_6X10 FEMALE_RA
CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10 AMP_HS3_6X10 FEMALE_RA
EF1 EF2 EF3 EF4 EF5 EF6 EF7 EF8 EF9 EF10 AMP_HS3_6X10 FEMALE_RA
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-2000991 DOCUMENT ISSUE NUMBER: 1.0 DRAWING TITLE=SYS_INTERFACE ABBREV=SYS_INTERFACE LAST_MODIFIED=Tue Jan 30 16:25:25 2001 6 5 4 3 TITLE: S/UNI-2XGE REFERENCE DESIGN SYSTEM INTERFACE ENGINEER: BDV 2 ISSUE DATE: YYYY/MM/DD REVISION NUMBER: 1.0 PAGE:13 1 OF 13 A
10
9
8
7
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
UBGA U10 SUNI-2XGE PM3386 4 of 7 TDAT31 TDAT30 TDAT29 TDAT28 TDAT27 TDAT26 TDAT25 TDAT24 TDAT23 TDAT22 TDAT21 TDAT20 TDAT19 TDAT18 TDAT17 TDAT16 TDAT15 TDAT14 TDAT13 TDAT12 TDAT11 TDAT10 TDAT9 TDAT8 TDAT7 TDAT6 TDAT5 TDAT4 TDAT3 TDAT2 TDAT1 TDAT0 TMOD1 TMOD0 TERR TEOP TENB TSX TSOP TPRTY TFCLK TADR E DTPA1 DTPA0 PTPA STPA TX-INTERFACE
AE4 AF3 AF4 AD5 AC17 AF19 AE18 AD17 AF18 AE17 AD16 AF17 AE16 AF16 AD15 AE15 AD14 AE14 AE13 AD13 AF12 AE12 AD12 AF11 AC12 AE11 AF10 AD11 AE10 AF9 AD10 AE9 AF8 AC10 AD9 AE8 AC7 AD6 AF5 AD7 AD8 AE7 AF6 AE6 AF7 AE5 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUNI_TDAT<31..0>\I
6G9> 7E3>
G
G
F
UBGA U10
10G4>
F SUNI-2XGE PM3386 6 of 7 LD<15..0>\I D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ALE CSB INTB RDB WRB RSTB
B10 D11 A9 C10 B9 A8 C9 B8 A7 C8 B7 A6 C7 B6 A5 D7 A16 A15 B16 B15 C15 G3 C5 A4 D6 B5 C6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LA<23..2>\I
12 11 10 9 8 7 6 5 4 3 2 C14 B14 B13 C13 A12 B12 C12 A11 B11 A10 C11
6G4<>
10F3<> 6F3<
SUNI_TMOD<1..0>\I SUNI_TERR\I SUNI_TEOP\I SUNI_TENB\I SUNI_TSX\I SUNI_TSOP\I SUNI_TPRTY\I SUNI_TFCLK\I SUNI_TADR\I
6E9> 6F9> 6F9> 6F9> 6G9> 6F9> 6F9> 6E9> 9E2> 6E9> 6E9< 6F9< 6F9< 6F9<
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
3.3 V
4.7K
3.3 V
3.3 V
R24
4.7K
R63 4.7K
R64
4.7K
RN38 RN39 RN41 RN38
6 6 8 7
3 3 1 2
33 33 33 33
SUNI_DTPA1\I SUNI_DTPA0\I SUNI_PTPA\I SUNI_STPA\I
R25
E
3.3 V
6F9> 6E9>
SUNI_PAUSE1\I SUNI_PAUSE0\I SUNI_PAUSED1\I SUNI_PAUSED0\I SUNI_PMD_SEL1 SUNI_PMD_SEL0
Y4 AB1 AA2 Y3 F25 V24
PAUSE1 PAUSE0 PAUSED1 PAUSED0 PMD_SEL1 PMD_SEL0
100MIL 6F9< 6F9< J9
1 3 5 2 4 6
SUNI_CSB\I SUNI_INTB\I RDB\I WRB\I SUNI_RSTB\I
1 1 1 1
10D2> 10C2< 10C2> 10C2> 6D3>
TP50 TP49 TP52 TP51
D
C
UBGA U10 SUNI-2XGE PM3386 5 of 7 RDAT31 RDAT30 RDAT29 RDAT28 RDAT27 RDAT26 RDAT25 RDAT24 RDAT23 RDAT22 RDAT21 RDAT20 RDAT19 RDAT18 RDAT17 RDAT16 RDAT15 RDAT14 RDAT13 RDAT12 RDAT11 RDAT10 RDAT9 RDAT8 RDAT7 RDAT6 RDAT5 RDAT4 RDAT3 RDAT2 RDAT1 RDAT0 RMOD1 RMOD0 RENB RERR REOP RVAL RSX RSOP RPRTY RFCLK RX-INTERFACE
HEADER 3X2
4.7K
R59 4.7K
R60
V1 T4 U2 T3 U1 T2 T1 R3 R2 R1 P4 P3 P2 N2 N3 M1 M2 M3 L1 L2 K1 L3 K2 K3 J2 H1 K4 J3 H2 H3 G2 F1 W2 Y1 AA1 V3 V2 W3 U4 Y2 U3 W1
RN35 RN35 RN35 RN34 RN35 RN34 RN34 RN34 RN33 RN33 RN33 RN33 RN32 RN32 RN32 RN31 RN32 RN31 RN31 RN30 RN31 RN30 RN30 RN30 RN29 RN29 RN29 RN28 RN28 RN29 RN28 RN28 RN36 RN36
6 7 5 5 8 6 7 8 6 8 7 5 5 7 6 5 8 7 6 5 8 6 7 8 5 8 6 5 6 7 7 8 6 5
3 2 4 4 1 3 2 1 3 1 2 4 4 2 3 4 1 2 3 4 1 3 2 1 4 1 3 4 3 2 2 1 3 4
33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33
1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R23
6E9<
4.7K
SUNI_RDAT<31..0>\I
INSTALL JUMPER TO ENABLE GMII DEFAULT UNINSTALLED FOR SERDES
TRSTB TDI TDO TMS TCK JTAG-CON-MIS
S_TCK
S_TRSTB S_TDI S_TDO S_TMS
D
C
SUNI_RMOD<1..0>\I SUNI_RENB\I
6E9< 6F9< 6E9> 6E9< 6F9< 6F9< 6F9< 6E9< 6F9< 9E2>
B
RN36 RN37 RN39 RN37 RN37 RN36
7 8 8 7 6 8
2 1 1 2 3 1
33 33 33 33 33 33
SUNI_RERR\I SUNI_REOP\I SUNI_RVAL\I SUNI_RSX\I SUNI_RSOP\I SUNI_RPRTY\I SUNI_RFCLK\I
B
PMC-Sierra, Inc.
A DRAWING: 2XGE_BLOCK 2XGE_BLOCK Tue Jan 30 16:25:12 2001 DOCUMENT NUMBER: PMC-2000991 DOCUMENT ISSUE NUMBER: 1.0 TITLE: S/UNI-2XGE REFERENCE DESIGN PL3 & MICRO INTERFACE ENGINEER: 10 9 8 7 6 5 4 3 BDV 2 ISSUE DATE: YY/MM/DD REVISION NUMBER: 1.0 PAGE:4 1 OF 13 A
S/UNI-2XGE Reference Design Preliminary
12
PCB Layout Revision 1
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use Document ID: PMC-2000991, Issue 3
53
S/UNI-2XGE Reference Design Preliminary
13
1 2
Bill of Materials (BOM) Revision 1
Manufacturer
PERICOM TI
No. Part Number
PI49FCT3807DQ SN74AHC1G08DCKR
RefDes
U11 U2
Description
IC 3.3V 1:10 CMOS CLOCK DRIVER QSOP20 D GRADE IC SINGLE 2-INPUT POSITIVE AND GATE Z-PACK 6 ROW HS3 BACKPLANE CONNECTOR, RIGHT ANGLE RECEPTACLE CAP CERAMIC X7R 0603 50V 0.01UF CAP CERAMIC X7R 1206 50V 0.047UF
Qty
1 1
3 4 5
120673-1 ECU-V1H103KBV ECU-V1H473KBW
AMP PANASONIC PANASONIC
J2, J3 C11 C13 C1, C2, C10, C12, C15-C17, C26, C55, C66C92, C94-C137 C5, C18, C36C54, C56, C57, C93 C3, C4, C6-C9 C24, C25, C27, C29, C30, C32, C33, C35 C19, C21 C14, C20, C22 C58-C65 C23, C28, C31, C34 J10 J6 J5 J7, J9 J14 J11, J12 L1-L4
2 1 1
6
ECJ-1VB1C104K
PANASONIC
CAP CERAMIC X7R 0603 16V 0.1UF CAP CERAMIC X5R 1210 10V 10UF CAP TANCAPC 16V 20% 10UF
80
7 8
GRM42-2X5R106K10 ECS-H1CC106R
MURATA PANASONIC
24 6
9 10 11 12 13 14 15 16 17 18 19 20
ECS-T0JY106R ECS-H1VC225R ECE-V1AA221P ECS-T0JY475R ECS-H0JD476R PZC36SAAN PZC36SAAN PZC36DAAN PZC36DAAN DIGI-KEY S1011-36-ND QSE-020-01-F-D ELJ-FD1R0KF
PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC SULLINS ELECTRONICS SULLINS ELECTRONICS SULLINS SULLINS ELECTRONICS ? SAMTEC PANASONIC
CAP TANCAPA 6.3V 20% 10UF CAP TANCAPC 35V 20% 2.2UF
8 2
CAP ELECTRO VA SMD 10V 20% 220UF 3 CAP TANCAPA 6.3V 20% 4.7UF CAP TANCAPD 6.3V 20% 47UF CONN HEADER STRAIGHT 36POS MALE .1" SINGLE ROW CONN HEADER STRAIGHT 36POS MALE .1" SINGLE ROW 8 4 1 1
CONN HEADER 2 ROW 0.1"X0.1" 2X16 1 CONN HEADER STRAIGHT 6POS MALE .1" DUAL ROW 3X2 100 MIL SPACING HEADER CONNECTOR, SMD 2ROW, 20 POSITION/ROW, WITH GND 2 1 2
INDUCTOR 1.0UH 10% TYPE FD 0805 4
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use Document ID: PMC-2000991, Issue 3
54
S/UNI-2XGE Reference Design Preliminary
21
IRF7413
INTERNATIONA L RECTIFIER
Q1, Q2
IC POWER MOSFET
2
22
LP3966ES-1.8
NATIONAL SEMI LINEAR TECHNOLOGY
U15
3A FAST ULTRA LOW DROPOUT LINEAR REGULATOR 1.8V TO263-5 1 IC CPCI HOT SWAP CONTROLLER W/ 12V POWERGD DISABLED
23
LTC1643L1CGN
U3
1
24
MAX811TEUS-T
MAXIM
U8
IC 4 PIN UP VOLTAGE MONITOR WITH MANUAL RESET INPUT 3.08V SOT143 1 IC VOLTAGE MONITOR WITH MANUAL RESET INPUT 2.63V SOT143 MOUNTING HOLE .150" DIA SOCKET FOR PART# NM93CS66LEN 100.000MHZ HCMOS OSCILLATOR PIN1-NC OSCILLATOR 125.000MHZ 3.3V [TOL= 50PPM] [TEMP= 0-70C] [DUTY= 5%] RIGHT ANGLE PCB MOUNT SPST PUSH BUTTOM IC 3.3V PCI TARGET INTERFACE(32-BIT, 33MHZ, PQFP PACKAGE) CONN TB 3 PIN RES 0805 1/10W 1% .47 OHM RES 0805 1/10W 5% .47 OHM
25 26 27 28
MAX812REUS-T MOUNTING HOLE 614-93-308-31-012 MB3100H-100.000MH Z
MAXIM N/A MILL MAX MMD
U7 M1 U5 U12
1 1 1 1
29 30
EH2645TTS-125.000 M DIGIKEY -- CKN4002-ND
ECLIPTEK ? PLX TECHNOLOGY ONSHORE TECHNOLOGY PANASONIC PANASONIC PANASONIC PANASONIC VISHAY PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC
Y1 SW1
1 1
31 32 33 34 35 36 37 38 39 40 41 42 43
PCI9030-AA60PI ED120/3DS ERJ-6RQFR47V ERJ-6RQJR47V ERJ-3GSY0R00V ERJ-6GEY0R00V WSL2512-R01-1 ERJ-6RQF1R0V ERJ-3GSYJ122V ERJ-3GSYJ100V ERJ-3EKF1000V ERJ-3GSYJ104V ERJ-3GSYJ103V
U1 J8 R41, R45, R50, R52 R62 R34 R28, R53, R55, R57 R6, R12, R13 R36, R37, R39, R43, R48 R5
1 1 4 1
RES 0603 1/16W 5% ZERO OHM 1 RES 0805 1/10W 5% ZERO OHM 4 RES 2512 1W 1% 0.01 OHM RES 0805 1/10W 1% 1.0 OHM RES 0603 1/16W 5% 1.2K OHM 3 5 1 5 1 1 1
R1, R2, R7, R9, R35 RES 0603 1/16W 5% 10 OHM R8 R22 R33 RES 0603 1/16W 1% 100 OHM RES 0603 1/16W 5% 100K OHM RES 0603 1/16W 5% 10K OHM
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use Document ID: PMC-2000991, Issue 3
55
S/UNI-2XGE Reference Design Preliminary
44 45 46 47 48 49
ERJ-8GEYJ106V ERJ-3GSYJ151V ERJ-3EKF1820V ERJ-3GSYJ202V ERJ-6RQF3R3V ERJ-3GSYJ330V
PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC
R17-R19 R30 R20 R3, R4 R47 R26, R27 R10, R11, R14R16, R21, R23R25, R59-R61, R63, R64 R58 R31, R32 R29 RN1-RN12 RN18-RN44, RN46-RN59 RN13-RN17, RN45, RN61 RN60
RES 1206 1/8W 5% 10M OHM RES 0603 1/16W 5% 150 OHM RES 0603 1/16W 1% 182 OHM RES 0603 1/16W 5% 2.0K OHM RES 0805 1/10W 1% 3.3 OHM RES 0603 1/16W 5% 33 OHM
3 1 1 2 1 2
50 51 52 53 54 55 56 57
ERJ-3GSYJ472V ERJ-3EKF49R9V ERJ-3GSYJ561V ERJ-3EKF63R4V EXB-V8V100JV EXB-V8V330JV EXB-V8V472JV 750101R200
PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC CTS
RES 0603 1/16W 5% 4.7K OHM RES 0603 1/16W 1% 49.9 OHM RES 0603 1/16W 5% 560 OHM RES 0603 1/16W 1% 63.4 OHM RES_ARRAY_4_SMD-10 RES_ARRAY_4_SMD-33 RES_ARRAY_4_SMD-4.7K BUSSED RESISTOR NETWORK 200 OHM SIP10 REGULATOR 5.0V TO 1.8V 6A, 100MV MAX RIPPLE CONVERTER
14 1 2 1 12 41 7 1
58 59 60 61 62 63 64 65 66
SIE501.8R 131-3701-341 SSF-LXH5147LGD PM3386 V23818-K305-L57 V23826-K305-C353 540-99-044-17-400 000 XCV200E-6BG352C ZM4742A
IPD CONVERTERS U6 JOHNSON COMPONENTS LUMEX PMC SIERRA INFINEON INFINEON J4 D2-D4 U10 U14 U13
1
50 OHM RIGHT ANGLE BULKHEAD JACK RECEPTACLE 1 LED QUAD GREEN HORIZONTAL IC DUAL GIGABIT ETHERNET CONTROLLER IC LC 2X5 GIGABIT ETHERNET TRANSCEIVER IC 1X9 AC COUPLED GIGABIT ETHERNET TRANSCEIVER 3 1 1 1
MILL MAX MANUFACTURING U4 XILINX DIODES INC U9 D1
IC CONFIGURABLE OTP EPROM PLCC44 SOCKETED 1 IC HIGH DENSITY 1.8V VIRTEX FPGA (352BGA PACKAGE) ZENER DIODE 12.0V 5% 1.0W SURFACE MOUNT 1 1
67
352068-1
AMP
J1
CONNECTOR ZPACK CPCI 2MM HM 110 POS. TYPE A WITH GND SHIELD 1
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use Document ID: PMC-2000991, Issue 3
56
S/UNI-2XGE Reference Design Preliminary
Notes
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use Document ID: PMC-2000991, Issue 3
57

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