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Released Digital Correction Signal Processor Data Sheet PMC-2001646 ISSUE 3
PMC-Sierra, Inc.
PM7800 PALADIN-10
Digital Correction Signal Processor
PM7800 PALADIN-10 Digital Correction Signal Processor
Data Sheet
PROPRIETARY AND CONFIDENTIAL Released Issue 3: July, 2001
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
Released Digital Correction Signal Processor Data Sheet PMC-2001646 ISSUE 3
PMC-Sierra, Inc.
PM7800 PALADIN-10
Digital Correction Signal Processor
PUBLIC REVISION HISTORY
Issue No. Issue 1 Issue 2 Issue Date January, 2001 March, 2001 ECN Number N/A N/A Details of Change Document created. Modified voltage tolerances for VDD and VDDI. Modified CPUMODE2 connection (tied to VDD rather than GND). Minor editorial changes. * Removed I2C references throughout to reflect the fact that I2C is not supported. * Changed Figure 3-1 on page 7: changed GND to VSS and VCC to VDD to match labels used in pin descriptions. * Text edits in Section 5.1 on page 16. * Modified procedure for Programming the WAIT_N Register (Section 5.1.2 on page 23). * Inserted text and diagram regarding relative timing of SPI inputs in Section 5.3 on page 26. * Added section (Section 5.4.2 on page 31) describing bug affecting Power_Attenuator_Delay and Power_Correction_Delay circuits. Modified Figure 5-25 on page 33 to reflect this issue. * Revision number incremented to 1; i.e., rev_code changed to 178000CD. Affects Section 5.6 on page 34 and Table 6-3 on page 41. * Changed VT+ and VT- values to 2.2V min and 0.8V max, respectively, in DC Characteristics. Also, changed VTH to 0.87V typ. * IIH text edit in Table 8-1 on page 51. * added IDDOP (VDDI) and IDDOP (VDDO) in DC Characteristics. * Changed notes at start of AC Timing. * Removed Relative Timing Diagrams and table for serial interface in AC Timing. * Changed min/max loading from 0/40pF to 15/30pF on toe, tdp, toz, and trp, in Table 9-2 on page 54; toe, in Table 9-3 on page 55; and toe, top, and toz in Table 9-7 on page 59.
Issue 3
July, 2001
N/A
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
Released Digital Correction Signal Processor Data Sheet PMC-2001646 ISSUE 3
PMC-Sierra, Inc.
PM7800 PALADIN-10
Digital Correction Signal Processor
CONTENTS List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 PALADIN Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3 PALADIN-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3.1 System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3.2 Signal Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 PM7800 DCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4.2 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4.4 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 4 5 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.1 Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.2 Programming the WAIT_N Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 Data Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2.1 VREF Interface and FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2.2 VOBS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2.3 VD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2.4 Dual-Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2.5 Single-Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3.1 Serial Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.4 Hop Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.4.1 Power and Carrier Values and Hop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.4.2 Bug that affects Power_Attenuator_Delay and Power_Correction_Delay . . . 31 5.5 GPIO Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.5.1 Power Attenuator Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.5.2 Watchdog Timer Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.6 JTAG Test Access Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Test Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1 Full Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.2 RAMBIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
Release Digital Correction Signal Processor Data Sheet PMC-2001646 ISSUE 3
PMC-Sierra, Inc.
PM7800 PALADIN-10
Digital Correction Signal Processor
6.3 OE_N Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.4 JTAG Boundary Scan, IEEE 1149.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.4.1 TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.4.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.4.2.1 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.4.2.2 Identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.4.2.3 Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.4.3 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.4.4 Boundary Scan Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7 8 9 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.1 RESET_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.2 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.3 VREF, VOBS, VD Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.3.1 Dual-Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.3.2 Single-Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.4 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.4.1 Serial Interface AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.5 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.6 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
10 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11 Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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Release Digital Correction Signal Processor Data Sheet PMC-2001646 ISSUE 3
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PM7800 PALADIN-10
Digital Correction Signal Processor
LIST OF TABLES Table 1-1 Table 4-1 Table 5-1 Table 5-2 Table 5-3 Table 6-1 Table 6-2 Table 6-3 Table 6-4 Table 7-1 Table 8-1 Table 9-1 Table 9-2 Table 9-3 Table 9-4 Table 9-5 Table 9-6 Table 9-7 Table 9-8 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin Description and Cell Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Connection to C54xx Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Functional Timing for WAIT_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Programming the WAIT_N Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Full-Scan Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Input Observation Cell (IN_CELL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 D.C.Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 RESET_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 CPU Interface - DCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 CPU Interface - CPUCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Dual-Clock System timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Single-Clock System timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 AC Timing for Serial Inputs (SCLK, SCS_N, SD, HOP_N) . . . . . . . . . . . . . . . 58 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
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Release Digital Correction Signal Processor Data Sheet PMC-2001646 ISSUE 3
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PM7800 PALADIN-10
Digital Correction Signal Processor
LIST OF FIGURES Figure 1-1 Figure 2-1 Figure 3-1 Figure 5-1 Figure 5-2 Figure 5-3 Figure 5-4 Figure 5-5 Figure 5-6 Figure 5-7 Figure 5-8 Figure 5-9 Figure 5-10 Figure 5-11 Figure 5-12 Figure 5-13 Figure 5-14 Figure 5-15 Figure 5-16 Figure 5-17 Figure 5-18 Figure 5-19 Figure 5-20 Figure 5-21 Figure 5-22 Figure 5-23 Figure 5-24 Figure 5-25 Figure 5-26 Figure 5-27 Figure 6-1 Figure 6-2 Figure 6-3 Figure 6-4 Figure 6-5 Figure 9-1 Figure 9-2 Figure 9-3 Figure 9-4 Figure 9-5 Figure 9-6 Figure 9-7 System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 PM7800 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Diagram (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Read Cycle (CPUMODE0 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read Cycle (CPUMODE0 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Back-to-Back Read Cycles (CPUMODE0 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . 20 Back-to-Back Read Cycles (CPUMODE0 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . 20 Back-to-Back Write Cycles (CPUMODE0 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . 21 Back-to-Back Write Cycles (CPUMODE0 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . 21 WAIT_N Timing - Reads (CPUMODE0 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . 22 WAIT_N Timing - Reads (CPUMODE0 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 22 WAIT_N Timing - Writes (CPUMODE0 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . 22 WAIT_N Timing - Writes (CPUMODE0 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Data Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Dual-Clock System timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Single-Clock System timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Serial (SPI), Hop, and GPIO Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Relative Timing of SPI Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SPI carrier_stream (spi_clock_polarity = 0, falling edge of SCLK is active) . . 28 SPI carrier_stream (spi_clock_polarity = 1, rising edge of SCLK is active) . . . 28 SPI power_stream (spi_clock_polarity = 0, falling edge of SCLK is active) . . . 28 SPI power_stream (spi_clock_polarity = 1, rising edge of SCLK is active) . . . 28 SPI word_stream (spi_clock_polarity = 0, falling edge of SCLK is active) . . . 29 SPI word_stream (spi_clock_polarity = 1, rising edge of SCLK is active) . . . . 29 SPI hop_stream (spi_clock_polarity = 0, falling edge of SCLK is active) . . . . . 29 SPI hop_stream (spi_clock_polarity = 1, rising edge of SCLK is active) . . . . . 30 Power Attenuator Outputs - shown with active-low pulse on GPIO17 . . . . . . . 33 Watchdog Timer Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 JTAG and Scan Test Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Boundary-Scan Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 TAP Controller Finite State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Output Cell (OUT_CELL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Bi-directional Cell (IO_CELL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Layout of Output Enable and Bidirectional Cells . . . . . . . . . . . . . . . . . . . . . . . . 49 RESET_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 CPU Interface - DCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 CPU Interface - CPUCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Dual-Clock System timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Single-Clock System timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 AC Timing for Serial Inputs (SCLK, SCS_N, SD, HOP_N) . . . . . . . . . . . . . . . 58 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
Release Digital Correction Signal Processor Data Sheet PMC-2001646 ISSUE 3
PMC-Sierra, Inc.
PM7800 PALADIN-10
Digital Correction Signal Processor
Figure 9-8
JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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Release Digital Correction Signal Processor Data Sheet PMC-2001646 ISSUE 3
PMC-Sierra, Inc.
PM7800 PALADIN-10
Digital Correction Signal Processor
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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Release Digital Correction Signal Processor Data Sheet PMC-2001646 ISSUE 3
PMC-Sierra, Inc.
PM7800 PALADIN-10
Digital Correction Signal Processor
1 Introduction
This document describes the features, functionality, and physical characteristics of the PM7800 Digital Correction Signal Processor, which forms part of the PALADIN-10 system. 1.1 Definitions The following table defines the terms and abbreviations used in this data sheet.
Table 1-1 Definitions
Definition Adaptive Control Processing Compensation Engine Analog to Digital Converter Analog Quadrature Modulator Super Ball Grid Array, the type of package used by this chip Built-In Self-Test Base Transceiver Station (Node B in WCDMA) Complementary Metal Oxide Semiconductor Central Processing Unit - in this context, the CPU is the ACPCE and the terms are used interchangeably Digital to Analog Converter Digital Correction Signal Processor Digital Quadrature Modulator Digital-Signal Processor Enhanced Data Rates for GSM Evolution - 3rd generation GSM (Global System for Mobile Communications) First-In, First-Out - a queuing mechanism General-Purpose Input-Output pin Global System for Mobile Communications No Connect, indicates an unused pin Random-Access Memory Radio Resource Management Entity Wideband Code Division Multiple Access
Abbreviation ACPCE ADC AQM BGA BIST BTS
CMOS CPU DAC DCSP DQM DSP EDGE
FIFO GPIO GSM NC RAM RRME WCDMA
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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Release Digital Correction Signal Processor Data Sheet PMC-2001646 ISSUE 3
PMC-Sierra, Inc.
PM7800 PALADIN-10
Digital Correction Signal Processor
1.2 PALADIN Technologies PALADIN is a family of distortion elimination chip technologies that enables the development of higher performance, higher efficiency 2G and 3G base stations that utilize fewer and less expensive components. Based on proprietary Digital Signal Processing (DSP) architectures and techniques, PALADIN products feature: * Digital Adaptive Predistortion for wideband amplifier linearization; * Digital Correction for Analog Quadrature Modulation (AQM) distortion; and * Constant-Gain Mode to facilitate operation at higher efficiency. Emerging 3G wireless services require high capacity radio networks to deliver the high volume multi-media data traffic that is central to the new "wireless internet" paradigm. High spectral efficiency, the ability to maximize the data-carrying capacity of a limited amount of licensed spectrum, will be key to the success of 3G radio networks. However, spectral efficiency is fundamentally limited by distortion in the analog transmitter and power amplifier components of the Base Transceiver Station (BTS). PALADIN products eliminate distortion in the transmitter chain and power amplifier using fully digital methods, permitting designers to replace many expensive and difficult to manufacture analog IF and RF sub-systems, components which are often required to control distortion and aggregate signals in many existing BTS designs. In particular, PALADIN can transform an inexpensive, simple, narrow-band Class AB power amplifier into a wide-band, multi-carrier capable, high efficiency, digitally controlled amplifier unit which can replace the expensive, low efficiency, feedforward-based multi-carrier power amplifiers (MCPA) commonly used in many current 3G BTS designs. Furthermore, PALADIN opens the door to the development of new BTS architectures that could feature "standard sockets" for multiple air interfaces, multiple transmitter/amplifier "hot swap" redundancy, multiple amplifier efficiency management, and smart antenna transceivers. 1.3 PALADIN-10 PALADIN-10 is a wideband transceiver linearizer and distortion elimination chip solution for multi-carrier high power radio transmitter applications. Based on high speed digital signal processing (DSP), PALADIN-10 provides digital adaptive predistortion and preconditioning for complex modulation signals with instantaneous bandwidths up to 10MHz. PALADIN-10 consists of (1) the PM7800 Digital Correction Signal Processor (DCSP) chip and (2) the Adaptive Control Processor Compensation Engine (APCE) running on an industry-standard programmable DSP1.
1. TMS320C54xx
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Release Digital Correction Signal Processor Data Sheet PMC-2001646 ISSUE 3
PMC-Sierra, Inc.
PM7800 PALADIN-10
Digital Correction Signal Processor
1.3.1 System Diagram Figure 1-1 shows a simplified system diagram of PALADIN-10 operating in the transmitter chain of a typical multi-carrier base transceiver subsystem (BTS).
Basestation Modem
Open Loop Predistortion Signal Path
DAC
Baseband signal
V ref
PM7800 PALADIN-10 DCSP
VD
RF Upconverter
Main Amp
GPIO SPI HOP
CPU
V obs
ADC
RF Downconverter
BSC or RRME
Observation Signal Path local BTS Controller Command Interface PALADIN Adaptive Control SPI Processor Compensation Engine (ACPCE)
TMS320C5410
Figure 1-1
System Diagram
The PM7800 DCSP chip, also called the PALADIN predistortion kernel, is responsible for all the real-time operations on the complex modulation baseband signal, from the base station modem, that predistort and precondition it such that the modified signal at the main or power amplifier (PA) will cancel out the distortions due to non-linearities in the PA and transmitter chain. The PM7800 DCSP chip supports all 3G and 2G air interfaces, including WCDMA, cdma2000 and IS-95, and GSM/EDGE. The PM7800 DCSP chip is the very high speed "hardware" digital signal processor component of the PALADIN-10 system. The PALADIN ACPCE, also called the PALADIN predistortion firmware, is responsible for carrying out all the nonreal-time complex computations necessary to generate predictive parameters used inside the PM7800 DCSP. The PALADIN ACPCE is also responsible for control functions and acts as the Master, taking commands from the base station controller (BSC) or some radio resource management entity (RRME) and controlling the operation and functioning of the PM7800 DCSP chip. The ACPCE runs on an external programmable DSP processor chip (TMS320C5410), also referred to as the CPU. The ACPCE is fully software upgradeable via a
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Release Digital Correction Signal Processor Data Sheet PMC-2001646 ISSUE 3
PMC-Sierra, Inc.
PM7800 PALADIN-10
Digital Correction Signal Processor
serial interface from the BSC or RRME. The current version of the ACPCE supports the WCDMA air interface standard only. Versions supporting the other 2G and 3G air standards will be provided as software updates. The PALADIN-10 ACPCE is the highly complex adaptive "software" digital signal processor component of the PALADIN-10 system. 1.3.2 Signal Flow The signal flow through the PALADIN-10 system is as follows: In the forward direction, the composite (digitally combined single or multi-carrier complex baseband) signal from the base station modem enters the PM7800 through the Vref port, where it is interpolated to the correct rate, predistorted by the Digital Correction Signal (DCSP) Processor core using parameters provided by the Adaptive Control Processor Compensation Engine (ACPCE), and exits through the VD port. The predistorted signal output at the VD port is converted to analog, up-converted, amplified, and applied to the antenna. This is called the open-loop predistortion signal path, which is sometimes referred to as the transmit path or upconversion path. In the reverse direction, a small portion of the amplified signal is downconverted, re-sampled and re-digitized, and enters the PM7800 through the Vobs port. This is called the observation or sampling signal path, and is sometimes referred to as the downconversion path. The PM7800 concurrently captures the baseband signal (Vref) and observed signal (Vobs) for analysis by the Adaptive Control Processor Compensation Engine (running on a TMS320C5410 DSP). The CPU analyzes the captured data to monitor system performance, and adjusts the internal parameters of the PM7800 DCSP accordingly. 1.4 PM7800 DCSP The PM7800 DCSP chip is the very high speed "hardware" digital signal processor component of the PALADIN-10 system. The remainder of this document describes the PM7800 DCSP chip only. The ACPCE is described in a companion document: PMC-2002272, "PALADIN-10/PALADIN15 ACPCE Firmware User Manual." 1.4.1 Features * * * * * * * * predistortion kernel for linearization of power-amplifiers in wireless base-stations up to 80MHz data-rate interpolated up-conversion (1:N, where 1<=N<=10) of baseband input to the data-rate generic 16-bit microprocessor bus interface for configuration, control, and monitoring SPI serial interface for update of power and carrier values 48 general-purpose IO pins, eight of which are edge-triggered interrupt sources standard five-signal IEEE 1149.1 JTAG test port for boundary scan board test purposes low-power 1.8V CMOS core logic with 3.3V CMOS/TTL compatible digital inputs and digital outputs * Industrial temperature range (-40C to +85C)
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Release Digital Correction Signal Processor Data Sheet PMC-2001646 ISSUE 3
PMC-Sierra, Inc.
PM7800 PALADIN-10
Digital Correction Signal Processor
1.4.2 Interfaces The major interfaces to the PM7800 DCSP include: * * * * * Baseband interface to the base station modem (Vref) Digital IF or Digital Baseband interface to DAC(s) and RF Upconverter (VD) Digital IF or Digital Baseband interface from ADC(s) and RF Downconverter (Vobs) GPIO and Serial (SPI) interface for auxiliary monitor and control CPU interface to ACPCE processor (external C54xx DSP)
Note: The command interface to the BSC or RRME is through an SPI (serial) interface on the CPU (TMS320C5410). The command interface is separately detailed in the companion document: PMC-2002272, "PALADIN-10/PALADIN-15 ACPCE Firmware User Manual." 1.4.3 Applications * WCDMA Base Transceiver Subsystems (BTS) * CDMA2000 BTS (requires firmware upgrade) * GSM/TDMA/EDGE BTS (requires firmware upgrade)
1.4.4 References 1. TMS320VC5410 Fixed-Point Digital Signal Processor (Texas Instruments) 2. Section 8: Synchronous Serial Peripheral Interface, M68HC11 Reference Manual (Motorola) 3. PMC-2002272, "PALADIN-10/PALADIN-15 ACPCE Firmware User Manual."
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Release Digital Correction Signal Processor Data Sheet PMC-2001646 ISSUE 3
PMC-Sierra, Inc.
PM7800 PALADIN-10
Digital Correction Signal Processor
2 Block Diagram
A block diagram of the PM7800 DCSP, showing the major interfaces is shown below as:
PM 7800 D C SP
vd_fm t vref_i[15:0] vref_q[15:0 ] from B aseb and M odem res et_n m ute_n dclk refc lk gpio[23:0] gpio[47:24] hop_n sd sc lk sc s_n CPU V vobs_q[15:0]
obs
V
ref
V
D
vd_i[15:0] vd_q[15:0]
to D A C (s ) & R F
vobs_i[15:0]
from A D C (s ) & R F
(P S *) A22 A23
from ACPCE (TM S320C54xx)
READY IN T x A 1 7 -A 0 D 1 5 -D 0 (M S T R B *) R /(W *) CLKO UT
cs 0_n cs 1_n cs 2 w ait_n irq_n adr[17 :0] dat[15:0] strb1_n strb2_n cp uclk
tck trs tb tm s tdi tdo sc anse l sc anen oe_n
JT A G
S can T est
cp um ode[4:0]
Figure 2-1
PM7800 Block Diagram
3 Pin Diagram
The PM7800 is packaged in a 304-pin SBGA with a body size of 31mm x 31mm. The following pin diagram shows the pinout from the ball-side of the package. Note that, for readability, the aspect ratio of the diagram has been changed.
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Figure 3-1
Data Sheet PMC-2001646
Pin Diagram (Bottom View)
18
VSS SCANSEL VSS VDDI VOBS_I5 VOBS_I9 VSS VOBS_I15 VOBS_Q2 VOBS_Q5 VSS VOBS_Q12 VSS VDDI GPIO15 GPIO20 VSS VDD
23 A B C D
GPIO25 VDDI
22
21
20
19
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
VDD
VSS
GPIO9
GPIO12
OE_N
VSS
VDD
VSS
GPIO10
VDDI
TDO
SCANEN
TMS
VOBS_I1
VOBS_I4
VOBS_I8
VOBS_I11 VOBS_I14
VOBS_Q1
VOBS_Q4
VOBS_Q8
VOBS_Q11 VOBS_Q14 VOBS_Q15
GPIO17
VSS
VDD
VSS
GPIO7
VSS
VDD
VD_FMT
GPIO11
GPIO13
TDI
TRSTB
VOBS_I0
VOBS_I3
VOBS_I7
VOBS_I10 VOBS_I13
VOBS_Q0
VOBS_Q3
VOBS_Q7
VOBS_Q10 VOBS_Q13
GPIO16
GPIO19
VDD
VSS
GPIO22
Release Digital Correction Signal Processor
GPIO4
GPIO6
NC
VDD
GPIO8
VDD
GPIO14
TCK
VDD
VOBS_I2
VOBS_I6
VDD
VOBS_I12
VDDI
VDD
VOBS_Q6
VOBS_Q9
VDD
GPIO18
VDD
GPIO21
GPIO23
GPIO3
GPIO5
NC
VDDI
GPIO24
GPIO26
GPIO27
E
VSS
VSS
GPIO0
GPIO2
VDD
VDD
RESET_N
GPIO28
F
ISSUE 3
VD_I15
VD_I14
VD_I13
GPIO1
VREF_I12 VREF_I13 VREF_I14 VREF_I15
G
VREF_I10 VREF_I11 VSS
VSS
VD_I12
VD_I11
VD_I10
VREF_I9
H
VDD VREF_I6 VREF_I7 VREF_I8
VD_I9
VD_I8
VD_I7
VDD
J
VREF_I3 VREF_I4 VREF_I5 VDDI
VDDI
VD_I6
VD_I5
VD_I4
K
VREF_I0 VREF_I1 VREF_I2 REFCLK
VD_I3
VD_I2
VD_I1
VD_I0
L
VDD VREF_Q14 VREF_Q15 VSS
VSS
NC
NC
VDD
M
VREF_Q10 VREF_Q11 VREF_Q12 VREF_Q13
DCLK
NC
VD_Q15
VD_Q14
N
VREF_Q6 VREF_Q7 VREF_Q8 VREF_Q9
NC
VD_Q13
VD_Q12
VD_Q11
P
VDD VDDI VREF_Q4 VREF_Q5
PMC-Sierra, Inc.
VDDI
VD_Q10
VD_Q9
VDD
R
VREF_Q1 VREF_Q2 VREF_Q3 VSS
VSS
VD_Q8
VD_Q7
VD_Q6
T
HOP_N SCS_N SCLK VREF_Q0
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VD_Q5
VD_Q4
VD_Q3
VD_Q2
U
VDD VDDI GPIO29 VSS
Digital Correction Signal Processor
7
SD GPIO30 GPIO31 GPIO32 VDD ADR8 ADR11 VDD ADR17 CS2 VDD DAT1 DAT5 VDD DAT10 DAT14 VDD GPIO40 VDD CPUMODE0 GPIO33 GPIO34 ADR4 ADR7 ADR10 ADR14 ADR16 CS1_N STRB2_N DAT0 DAT4 DAT7 DAT9 DAT13 GPIO41 GPIO39 CPUMODE1 VDD VSS GPIO35 ADR3 ADR6 ADR9 ADR13 ADR15 CS0_N STRB1_N IRQ_N DAT3 DAT6 DAT8 DAT12 DAT15 GPIO38 CPUMODE2 VSS VDD VSS VSS ADR5 VSS ADR12 VDDI CPUCLK VSS WAIT_N DAT2 VDDI VSS DAT11 VSS VDDI GPIO37 GPIO36 VSS VDD
VSS
VD_Q1
NC
VDD
V W Y AA AB AC
VD_Q0
GPIO47
NC
VDDI
GPIO46
GPIO45
CPUMODE4
VDD
GPIO44
MUTE_N
VSS
VDD
CPUMODE3
ADR1
VSS
VDD
VSS
GPIO43
ADR2
PM7800 PALADIN-10
VDD
VSS
GPIO42
ADR0
VDDI
Release Digital Correction Signal Processor Data Sheet PMC-2001646 ISSUE 3
PMC-Sierra, Inc.
PM7800 PALADIN-10
Digital Correction Signal Processor
4 Pin Description
Table 4-1
Pin Name CPU Interface (47) STRB1_N I AB12 Hi-Z This signal is either used as an access strobe or as a write strobe, depending on the setting of the CPUMODE0 pin. If the CPUMODE0 pin is connected to VSS, this signal is treated as an access strobe, if the CPUMODE0 pin is connected to VDD, then this strobe is treated as a WRITE_N strobe. This signal is either used as an Read/Write_N cycle type indication or as a read strobe, depending on the setting of the CPUMODE0 pin. If the CPUMODE0 pin is connected to VSS, this signal is treated as an Read/Write_N indication, if the CPUMODE0 pin is connected to VDD, then this strobe is treated as a READ_N strobe. This signal is an active-low chip select. All three chip selects must be asserted for the chip to be accessed. This signal is an active-low chip select. All three chip selects must be asserted for the chip to be accessed. This signal is an active-high chip select. All three chip selects must be asserted for the chip to be accessed. This is the eighteen-bit word-address bus. The bus addresses 256k 16-bit words (512Kbytes) in the PM7800.
Pin Description and Cell Types
Type Pin # Default Functional Description
STRB2_N
I
AA12
Hi-Z
CS0_N
I
AB13
Hi-Z
CS1_N
I
AA13
Hi-Z
CS2
I
Y13
Hi-Z
ADR[17:0]
I
Y14, AA14, AB14, AA15, AB15, AC15, Y16, AA16, AB16, Y17, AA17, AB17, AC17, AA18, AB18, AB19, AA19, AC20
Hi-Z
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PMC-Sierra, Inc.
PM7800 PALADIN-10
Digital Correction Signal Processor
Table 4-1
Pin Name DAT[15:0]
Pin Description and Cell Types
Type IO Pin # AB6, Y7, AA7, AB7, AC7, Y8, AA8, AB8, AA9, AB9, Y10, AA10, AB10, AC10, Y11, AA11 AC11 Default Hi-Z Functional Description This is the 16-bit data bus.
WAIT_N
O
Output High
This is the external wait signal, required when DCLK on the PM7800 is slow. This output has programmable timing. See Programming the WAIT_N Register section 5.1.2. This is an active-low interrupt request pin.
IRQ_N
O
AB11
Output High Hi-Z Hi-Z
CPUCLK CPUMODE0
I I
AC13 Y3
CPU Clock Input. This is a Schmitt-trigger input. This pin configures the strobe-signalling mode of the PM7800. When this pin is connected to VSS, access strobe and R/W# indication signalling is used. When this pin is connected to VDD, read strobe and write strobe signaling is used. See CPU Interface section 5.1. If this pin is connected to VDD, the WAIT circuit deactivates the internal version of the CPU write strobe for a programmable number of CPUCLK cycles. See CPU Interface section 5.1. This input is reserved and must be connected to VDD. This pin, when connected to VDD, selects a mode of operation that can be used to support processors, e.g. ARM, that require the read strobe to be sampled on the falling edge of CPUCLK and the write strobe to be sampled on the rising edge. See CPU Interface section 5.1. This pin, when connected to VDD, enables additional delay on the WAIT_N output to provide more hold time. See CPU Interface section 5.1.
CPUMODE1
I
AA4
Hi-Z
CPUMODE2 CPUMODE3
I I
AB4 AA20
Hi-Z Hi-Z
CPUMODE4
I
Y21
Hi-Z
Data Interfaces (98) DCLK REFCLK I I N23 L1 Hi-Z Hi-Z Data clock. This is a Schmitt-trigger input. VREF clock. This is a Schmitt-trigger input. VREF is synchronous to this clock in 2-clock systems.
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Release Digital Correction Signal Processor Data Sheet PMC-2001646 ISSUE 3
PMC-Sierra, Inc.
PM7800 PALADIN-10
Digital Correction Signal Processor
Table 4-1
Pin Name
Pin Description and Cell Types
Type IO Pin # G1, G2, G3, G4, H2, H3, H4, J1, J2, J3, K2, K3, K4, L2, L3, L4 M2, M3, N1, N2, N3, N4, P1, P2, P3, P4, R1, R2, T2, T3, T4, U1 A11, B11, C11, D11, B12, C12, A13, B13, C13, D13, A14, B14, C14, D14, B15, C15 Default Hi-Z Functional Description In normal modes, this bus is the I-channel of the baseband input signal. In scan test mode, this bus is an output used for SCANOUT[31:16].
VREF_I[15:0]
VREF_Q[15:0]
IO
Hi-Z
In normal modes, this bus is the Q-channel of baseband input signal. In scan test mode, this bus is an output used for SCANOUT[15:0].
VOBS_I[15:0]
I
Hi-Z
Input: I-channel of observed signal from power amplifier.
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Release Digital Correction Signal Processor Data Sheet PMC-2001646 ISSUE 3
PMC-Sierra, Inc.
PM7800 PALADIN-10
Digital Correction Signal Processor
Table 4-1
Pin Name
Pin Description and Cell Types
Type I Pin # B5, B6, C6, A7, B7, C7, D7, B8, C8, D8, A9, B9, C9, A10, B10, C10 G23, G22, G21, H22, H21, H20, J23, J22, J21, K22, K21, K20, L23, L22, L21, L20 N21, N20, P22, P21, P20, R22, R21, T22, T21, T20, U23, U22, U21, U20, V22, W23 Default Hi-Z Functional Description Input: Q-channel of observed signal from power amplifier.
VOBS_Q[15:0]
VD_I[15:0]
IO
Hi-Z
In normal modes, this bus is the I-channel of output signal to the DAC. In scan test mode, this bus is an input used for SCANIN[31:16].
VD_Q[15:0]
IO
Hi-Z
In normal modes, this bus is the Q-channel of output signal to the DAC. In scan test mode, this bus is an input used for SCANIN[15:0].
Serial Port (4) SD I W4 Hi-Z Serial Data input for the serial port. If unused, this pin must be connected to VSS. Clock input for the serial port - Schmitt trigger. If unused, this pin must be connected to VSS.
SCLK
I
U2
Hi-Z
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PM7800 PALADIN-10
Digital Correction Signal Processor
Table 4-1
Pin Name SCS_N
Pin Description and Cell Types
Type I Pin # U3 Default Hi-Z Functional Description Chip Select for the serial port. This is a Schmitt-trigger input. If unused, this pin must be connected to VSS. This input can be used to activate the new carrier and power values. This is a Schmitt-trigger input. If unused, this pin must be connected to VSS.
HOP_N
I
U4
Hi-Z
JTAG and other test pins (8) TCK I D16 Hi-Z JTAG clock. In normal operation, this pin must be connected to VSS. JTAG reset signal - active low. This is a Schmitt-trigger input with internal pull-up resistor. In normal mode (non-JTAG) this pin must be connected to RESET_N. JTAG test mode select input with internal pull-up resistor. In normal operation, this pin must be driven high or left unconnected. JTAG test data input with internal pull-up resistor. In normal operation, this pin must be driven high or left unconnected. Tri-state output for JTAG test data. This is the only pin unaffected by OE_N. Scan MUX select. When high, this signal selects Scan test mode. This pin must be connected to VSS in normal operation. When high, this signal enables the Scan chain. This pin must be connected to VSS in normal operation. Forces all pins except TDO to high impedance. This is a Schmitt-trigger input with internal pull-down resistor. In normal operation, this pin must be driven low or left unconnected.
TRSTB
I
C16
Hi-Z pulled high
TMS
I
B16
Hi-Z pulled high Hi-Z pulled high Hi-Z Hi-Z
TDI
I
C17
TDO SCANSEL
O I
B18 A17
SCANEN
I
B17
Hi-Z
OE_N
I
A19
Hi-Z pulled low
Miscellaneous (50) RESET_N I F3 Hi-Z pulled high Hi-Z pulled high Hi-Z System reset signal - active low. This is a Schmitt-trigger input with internal pull-up resistor. Mute input - active-low. When low, this signal forces VD to zero. This is a Schmitt-trigger input with internal pull-up resistor. Configuration pin that sets the data format of the VD_I and VD_Q outputs: 0 -> offset-binary 1 -> 2s-complement.
MUTE_N
I
AA23
VD_FMT
I
C20
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Release Digital Correction Signal Processor Data Sheet PMC-2001646 ISSUE 3
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PM7800 PALADIN-10
Digital Correction Signal Processor
Table 4-1
Pin Name GPIO[47:32]
Pin Description and Cell Types
Type IO Pin # W22, Y23, Y22, Y19, AB20, AC21, AA6, Y5, AA5, AB5, AC4, AC3, AA1, Y1, Y2, W1 W2, W3, V2, F2 E2, E3, D1, E4 D2, C1, D3, A3, C4, D5 B4 Default Hi-Z Functional Description General-purpose IO pins.
GPIO[31:28]
IO
Hi-Z
General-purpose IO pins with rising-edge interrupt capability (see Interrupt_Enable2 register).
GPIO[27:24]
IO
Hi-Z
General-purpose IO pins with falling-edge interrupt capability (see Interrupt_Enable2 register).
GPIO[23:18]
IO
Hi-Z
General-purpose IO pins.
GPIO[17]
IO
Hi-Z
General-purpose IO pins or Power_Attenuator_Pulse output (see GPIO_Secondary_Function_Select registers). General-purpose IO pins or Watchdog_Timer_Output (see GPIO_Secondary_Function_Select registers). General-purpose IO pins or Power_Attenuator_Output[15:0] (see GPIO_Secondary_Function_Select registers).
GPIO[16]
IO
C5
Hi-Z
GPIO[15:0]
IO
A4, D17, C18, A20, C19, B20, A21, D19, C23, D22, E22, D23, E23, F21, G20, F22
Hi-Z
Power Supply (84)
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PM7800 PALADIN-10
Digital Correction Signal Processor
Table 4-1
Pin Name VSS
Pin Description and Cell Types
Type P Pin # A2 A6 A8 A12 A16 A18 A22 B1 B3 B21 B23 C2 C22 F1 F23 H1 H23 M1 M23 T1 T23 V1 V23 AA2 AA22 AB1 AB3 AB21 AB23 AC2 AC6 AC8 AC12 AC16 AC18 AC22 Default Ground supply. Functional Description
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PM7800 PALADIN-10
Digital Correction Signal Processor
Table 4-1
Pin Name VDD
Pin Description and Cell Types
Type P Pin # A1 A23 B2 B22 C3 C21 D4 D6 D9 D12 D15 D18 D20 F4 F20 J4 J20 M4 M20 R4 R20 V4 V20 Y4 Y6 Y9 Y12 Y15 Y18 Y20 AA3 AA21 AB2 AB22 AC1 AC23 E20, K23, R23, W20, AC19, AC14 AC9, AC5, V3, R3, K1, E1, A5, D10, A15, B19 Default 3.3V IO voltage supply. Functional Description
VDDI
P
1.8V Core voltage supply.
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PM7800 PALADIN-10
Digital Correction Signal Processor
5 Functional Description
5.1 CPU Interface
AC PC E (TM S320C 54xx)
PM 7800 DCSP
(P S *) A22 A23 READY IN T x A 1 7 -A 0 D 1 5 -D 0
a dr[1 7:0] d at[1 5:0] s trb1 _n s trb2 _n c pu clk
(M S TR B *) R /(W *) CLKO UT
c pu m o de [4 :0 ]
Figure 5-1
CPU Interface
The CPU interface is designed to "look" like the interface to a slow asynchronous SRAM device, with some added functionality to reduce glue logic. The CPU interface is primarily designed for a TI TMS320C54xx General Purpose DSP processor, but some flexibility is provided to support other processors.
Internally, the CPU access cycle is synchronized to the DCLK to allow a simultaneous CPU write to, and data path read from, the same memory location - this is to provide fail-safe operation of the internal dual-port RAM. This requirement significantly slows down the access speed of the CPU interface, especially at EDGE sample clock rates in the 13MHz range. The slow access speed can result in a longer access time than what can be generated by the internal wait-state machine of the processor when the processor is fast and DCLK is slow. To generate longer CPU access cycles, a wait signal (WAIT_N) is generated by the PM7800. The WAIT_N signal is generated by the wait circuit which is clocked by CPUCLK. The PM7800 needs to detect cycle-to-cycle transitions on the CPU bus. Detecting the cycle-tocycle change is complicated because the cycle-inactive indication (deassertion of the strobes) between cycles can be short for write-to-write cycles, and short or non-existent for read-to-read cycle transitions. To simplify the design and stay within synchronous design practices, cycle-toPROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE 16
CPU
c s0 _n c s1 _n c s2 w ait_n irq_ n
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cycle transition-detection is achieved by the direct approach of sampling the control signal(s) inactive, or by the indirect approach of sampling the control strobes a programmable number of clock cycles after the WAIT_N signal is deasserted - if the strobes are still active, then the start of another cycle is assumed. The operation of the wait circuit - clocked by CPUCLK - is as follows: sample control strobes active, assert WAIT_N for Assert_Wait_Cycles (register 0x0_0010 bits 6:0) CPUCLK's, negate WAIT_N for Negate_Wait_Cycles (register 0x0_0010 bits 11:8) CPUCLK's, then sample control strobes again. Another cycle has started if the control strobes are still active. The TI processor's internal wait-state circuit continues to count while WAIT_N is asserted. This results in the waitstate circuitry re-aligning itself with the TI cycle at each transition since the TI cycle will end as soon as it detects WAIT_N negated. Other processors' internal wait-state circuits may halt while WAIT_N is asserted: in this case, the Assert_Wait_Cycles and Negate_Wait_Cycles registers must be programmed so that they match the length of the processor accesses. To further support the case where the de-assertion period of the strobe signal between back-to-back writes is too short to be reliably detected by DCLK, the PM7800 must be programmed to temporarily deassert its internal version of the write strobe: CPUMODE1, when tied to VDD, selects this operation. The Fake_End_Length register (register 0x0_0010 bits 15:12) sets the duration, in CPUCLK's, for which the write strobe is deasserted. The C54xx interface has an access strobe (either I/O or memory), an area indication (either DS# or PS# for data or program memory or IS# for I/O space select), a R/W# indication, a data bus and an address bus. To support C54xx processors, STRB1_N and STRB2_N must be connected to the access strobe and R/W# indicator respectively, and CPUMODE0 must be tied to VSS. Processors with read and write strobes can be supported by tying CPUMODE0 to VDD, and connecting the write strobe to STRB1_N and the read strobe to STRB2_N. The CPUMODE2 pin is reserved and should be tied to VDD. The CPUMODE3 pin, when tied to VDD, selects a mode of operation that can be used to support processors, e.g. ARM, that require the read strobe to be sampled on the falling edge of CPUCLK and the write strobe to be sampled on the rising edge. The PM7800 can be configured to provide additional hold time from CPUCLK before negating WAIT_N - this may be required to support processors, e.g. ARM, that require longer hold times on WAIT_N. CPUMODE4, when tied to VDD, selects additional hold time.
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The following table describes how to connect the PM7800 to a C5410 processor.
Table 5-1
Signal (PM7800) MSTRB# R/W# PS# A22 -> A21
Connection to C54xx Processor
Connect To (TMS320C5410) STRB1_N STRB2_N CS0_N. CS1_N, and CS2. WAIT_N
Description This signal is the active-low program memory access strobe. This signal is the Read/Write# cycle type indication. This signal is the program space access strobe. Two of the upper address bits can be connected to the two other chip select inputs to provide basic address decoding of the program memory space. When the WAIT_N signal is asserted low, the TI chip extends the current cycle until the WAIT_N signal negated to a high state. INTx. is one of the four interrupt inputs. The TI bus is word addressed, as is the PM7800. Data is connected straight across. The master clock output for the TI processor. Maximum CPU clock frequency 125 MHz. The CPU signalling style is access strobe and read/write# indication. The WAIT circuit forces the internal version of the CPU write strobe inactive for a programmable number of CPUCLK cycles. Reserved. All inputs sampled on rising edge of CPUCLK. No additional delay on WAIT_N.
READY
INTx A[17:00] D[15:00] CLKOUT
IRQ_N ADR[17:00] DAT[15:00] CPUCLK
CPUMODE0 CPUMODE1
0 1
CPUMODE2 CPUMODE3 CPUMODE4
1 0 0
5.1.1 Functional Timing The following timing diagrams give functional timing for the CPU interface. Because this interface is asynchronous to DCLK, AC timing parameters (tis, tih, toe, top, toz, tw) are shown here for clarity but are defined in AC Timing section 9.
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Figure 5-2
Read Cycle (CPUMODE0 = 0)
0ns DCLK t is STRB1_N STRB2_N t oz t is CSx 20ns T0 T1 40ns T2 60ns T3 80ns T4 T5 100ns T6 t ih 120ns T7
5TDCLK
t ih
toz t is ADR[17:0] t oe DAT1[15:0] t op t ih
Figure 5-3
Read Cycle (CPUMODE0 = 1)
0ns DCLK STRB1_N t is STRB2_N t oz t is CSx toz t is ADR[17:0] t oe DAT1[15:0] t op t ih t ih 20ns T0 T1 40ns T2 60ns T3 80ns T4 T5 100ns T6 120ns T7
5TDCLK
t ih
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Figure 5-4
Back-to-Back Read Cycles (CPUMODE0 = 0) 0ns T0 DCLK tis STRB1_N STRB2_N tis CSx tis ADR[17:0] toe DAT[15:0] adr1 top data1 3TDCLK 5TDCLK tis adr2 top top toz 5TDCLK toz T1 50ns T2 T3 T4 100ns T5 T6 T7 T8 150ns 200ns
T9 T10 T11 T12 T13 T14
data2
Figure 5-5
Back-to-Back Read Cycles (CPUMODE0 = 1) 0ns T0 DCLK STRB1_N tis STRB2_N tis CSx tis ADR[17:0] toe DAT[15:0] adr1 top data1 3TDCLK 5TDCLK tis adr2 top top toz 5TDCLK toz T1 50ns T2 T3 T4 100ns T5 T6 T7 T8 150ns 200ns
T9 T10 T11 T12 T13 T14
data2
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Figure 5-6
Back-to-Back Write Cycles (CPUMODE0 = 0)
0ns DCLK 20ns T0 T1 40ns T2 60ns T3 t is t is STRB1_N t is STRB2_N t is CSx t is ADR[17:0] t is DAT[15:0] t ih t ih t is t ih t is t ih t ih t is
Note2
80ns T4 T5
100ns T6
120ns
t ih
t is
Figure 5-7
Back-to-Back Write Cycles (CPUMODE0 = 1)
0ns DCLK 20ns T0 T1 40ns T2 60ns T3 tis tis STRB1_N STRB2_N tis CSx tis ADR[17:0] tis DAT[15:0] tih tih tis tih tis tih tis
Note2
80ns T4 T5
100ns T6
120ns
tih
Note: 1. The system designer need not worry about violating tis and tih - all inputs are treated as asynchronous signals. Setup and hold times are specified here to identify the clock edge on which the signal is sampled. 2. If deassertion of the strobe cannot be detected by DCLK, CPUMODE1 must be tied to VDD to program the PM7800 to temporarily deactivate the internal write strobe - See Functional Description section 5. .
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Figure 5-8
WAIT_N Timing - Reads (CPUMODE0 = 0)
0ns CPUCLK STRB1_N STRB2_N
100ns
200ns 300ns
400ns
500ns
600ns
700ns 800ns
900ns
1
Twait_n_asserted Twait_n_delay WAIT_N Twait_n_negated
Figure 5-9
WAIT_N Timing - Reads (CPUMODE0 = 1)
0ns CPUCLK STRB1_N STRB2_N
100ns
200ns 300ns
400ns
500ns
600ns
700ns 800ns
900ns
1
Twait_n_asserted Twait_n_delay WAIT_N Twait_n_negated
Figure 5-10 WAIT_N Timing - Writes (CPUMODE0 = 0)
0ns CPUCLK STRB1_N STRB2_N
100ns
200ns
300ns
400ns
500ns
600ns
700ns
800ns
900ns
1
First rising edge of STRB1_N
Twait_n_delay Twait_n_asserted WAIT_N Tfake_end_length nternal_write_strobe Twait_n_negated
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Figure 5-11 WAIT_N Timing - Writes (CPUMODE0 = 1)
0ns CPUCLK STRB1_N STRB2_N
100ns
200ns
300ns
400ns
500ns
600ns
700ns
800ns
900ns
1
First rising edge of STRB1_N
Twait_n_delay Twait_n_asserted WAIT_N Tfake_end_length nternal_write_strobe Twait_n_negated
Table 5-2
Functional Timing for WAIT_N
min 2TCPUCLK (Assert_Wait_Cycles[6:0] + 1)TCPUCLK (Negate_Wait_Cycles[3:0] + 1) TCPUCLK (Fake_End_Length[3:0] + 1) TCPUCLK Description STRBx to WAIT_N delay WAIT_N pulse width WAIT_N negated width Internal fake_end length for back-to-back writes.
Parameter Twait_n_delay Twait_n_asserted Twait_n_negated Tfake_end_length
5.1.2 Programming the WAIT_N Register The following are guidelines for programming the WAIT_N register:
Table 5-3 Programming the WAIT_N Register
Formula Assert_Wait_Cycles = round-up {6Tdclk /Tcpuclk -1} Negate_Wait_Cycles = round-up {3 + 32 / Tcpuclk} Comment Must satisfy PM7800 read-access time of 6 dclk periods Must be long enough to allow the C54 to end the current cycle, and to flush the cycle_active out of the cpuclk synchronizers. The C54 must be programmed such that it will not start another cycle before WAIT_N can be reasserted.
internal_c54_wait > Negate_Wait_Cycles where internal_c54_wait is the number of wait cycles programmed in the C54xx processor. Fake_End_Length = round-up{max{[(Tdclk + 2ns) / Tcpuclk - 1] : [1.5 + 32 / Tcpuclk]}}
Must be long enough for the PM7800 to sample its internal fake_wait_inactive with dclk. Must also be long enough that fake_wait_inactive is held until past the rising edge of STRB1_N (shown in Figure 5-10 on page 22 and Figure 5-11 on page 23).
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5.2 Data Interfaces
B a se ba nd M od em
PM 7800 DCSP
V
ref
V
DAC DAC
vre f_ i[1 5:0] vre f_ q[15 :0 ]
D
vd_ i[1 5:0] vd_ q[15 :0 ]
R F U p co n ve rte r
M a in Amp
res et_n m ute_ n V d clk refclk vob s_ q[15 :0 ]
obs ADC ADC R F D o w n co n ve rte r
vob s_ i[1 5:0]
vd_ fm t
Figure 5-12 Data Interfaces
5.2.1 VREF Interface and FIFO The VREF interface is used to input the reference signal in either offset-binary or two'scomplement notation. In the case of offset-binary format, the VREF_Data_Format bit in the Mode register must be set to zero to instruct the PM7800 to convert the data to two's-complement format which is used throughout the chip. There are three modes of operation for the VREF interface: 1. VREF is clocked in by REFCLK and upsampled to the rate of the PM7800 clock, DCLK, where fDCLK = N * fREFCLK. In this case, a FIFO is used to handle the skew between REFCLK and DCLK, and to provide a steady supply of data to the interpolator. Set the Bypass_FIFO and Interpolator_Bypass bits to zero (default) in this case. 2. VREF is clocked in by REFCLK which is at the same rate as the PM7800 clock, DCLK, that is, fDCLK = fREFCLK. In this case, a FIFO is used to handle the skew between REFCLK and DCLK. The interpolator can be bypassed to reduce latency. Set the Bypass_FIFO bit to zero (default) and the Interpolator_Bypass bit to one in this case. 3. VREF is at the same rate as and synchronous to DCLK. In this case, the FIFO and interpolator can be bypassed to reduce system latency by setting the Bypass_FIFO and Interpolator_Bypass bits to one in the Mode register. The REFCLK input is ignored and should be connected to VSS.
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5.2.2 VOBS Interface The VOBS interface is used to input the observed signal from the ADC in either offset-binary or two's-complement notation. In the case of offset-binary format, the VOBS_Data_Format bit in the Mode register must be set to zero to instruct the PM7800 to convert the data to two's-complement format. 5.2.3 VD Interface The VD interface is used to output the predistorted signal to the DAC in either offset-binary or two's-complement notation. The VD_FMT pin selects offset-binary format when low, and two'scomplement format when high. 5.2.4 Dual-Clock System Use the dual-clock system when VREF is synchronous to REFCLK (usually when VREF is upsampled internally to the DCLK rate). TREFCLK must be an exact integer multiple of TDCLK, i.e. TREFCLK = nTDCLK, where n = 1,2,...,10. REFCLK must be created from DCLK. In this case, a FIFO and interpolator are used to upsample VREF to the DCLK rate. REFCLK must be created from DCLK such that there is no varying phase shift that may cause under-run or over-run, i.e. skew may exist between DCLK and REFCLK, but this skew must not vary over time by more than one DCLK period.
Figure 5-13 Dual-Clock System timing
0ns DCLK VOBS VD REFCLK VREF
20ns
40ns
60ns
80ns
100ns
120n
5.2.5 Single-Clock System Use the single-clock system when all signals are synchronous to DCLK and the data-rate of VREF is the same as the output data-rate of VD. In this case, connect the REFCLK pin to VSS, and bypass the FIFO and interpolator to reduce latency through the chip.
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Figure 5-14 Single-Clock System timing
0ns DCLK VREF VOBS VD
5.3 Serial Interface
10ns
20ns
30ns
40ns
50ns
60ns
70ns
80ns
9
PM 7800 DCSP
g pio [2 3:0] g pio [4 7:24 ] h op _n sd s clk s cs _n
Figure 5-15 Serial (SPI), Hop, and GPIO Interfaces
The serial interface is used to input the next_power, next_carrier values, hop_stream command, and general-purpose serial_word register. Also included in this interface is the HOP_N pin which can be used to delay the effect of the hop_stream to a more precise time. The PM7800 supports the SPI specification included in the M68HC11 Reference Manual (section 8). Only the modes where CPHA = 1 is supported. CPOL may be 0 or 1, and the spi_clock_polarity bit of the serial_mode register (0x0_0013 bit 2) is used to select the active clock edge. The PM7800 does not have a data output pin (MISO). The PM7800's SCS_N pin is equivalent to the /SS pin, and it can be tied to ground to reduce system pin requirements. A transfer can be reset by deactivating SCS_N. If SCS_N is tied low (always active) then another method must be used to reset the state machine. One way is to disable the serial interface by writing a zero to the serial_interface_enable bit in the Serial_Mode register. Another way is to set reg_serial_address[4:0] = 00000b (this is the default setting) and stream twenty-four 1's into the serial port: at some stage during the stream of 1's, the idle state will be reached and the interface
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will be held waiting for the first 0 of the address. Note that if the transfer is aborted after some data has been sent, that data will already be shifted into the respective data register. Relative timing of the SPI input signals is shown in Figure 5-16. Note that SCLK, SD, SCS_N can be asynchronous to DCLK: Figure 5-16 shows timing for the inputs relative to the DCLK edges on which they are detected. Notes: * SCLK, SD, SCS_N are debounced using DCLK, therefore they must be present for two consecutive DCLK edges to be properly detected. It is recommended that the minimum pulse-width be 3 TDCLK, i.e. TSCLK >= 6TDCLK. * SD and SCS_N are sampled by DCLK on the active edge of SCLK. Therefore, because of the asynchronous relationship, it is recommended that SD and SCS_N be valid for one DCLK either side of the active SCLK edge.
Figure 5-16 Relative Timing of SPI Inputs
Active edge of SCLK DCLK >=3TD SCLK >=TD SD, SCS_N >=3TD >=TD
5.3.1 Serial Operation All signal pins in the serial interface are synchronized to dclk and debounced to reject glitches shorter than a dclk period - see AC Timing. There are four serial streams recognized by this interface: 1. carrier_stream consists of three bytes as follows: * * * * five address bits corresponding to reg_serial_address[4:0] two bits = 00b, that indicate a carrier_stream a r/w bit that must be zero seven don't-care bits
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* nine bits of the next_carrier value - in the order of msb to lsb
Figure 5-17 SPI carrier_stream (spi_clock_polarity = 0, falling edge of SCLK is active)
0ns SCLK SD SCS_N
50ns
100ns
150ns
200ns
250
a7 a6 a5 a4 a3 0 0 0 x
x
xx
x x x c8 c7 c6 c5 c4 c3 c2 c1 c0
Figure 5-18 SPI carrier_stream (spi_clock_polarity = 1, rising edge of SCLK is active)
0ns SCLK SD SCS_N
50ns
100ns
150ns
200ns
250
a7 a6 a5 a4 a3 0 0 0 x
x
xx
x x x c8 c7 c6 c5 c4 c3 c2 c1 c0
2. power_stream consists of two bytes as follows: * * * * five address bits corresponding to reg_serial_address[4:0] two bits = 01b, that indicate a power_stream a r/w bit that must be zero eight bits of the next_power value - in the order of msb to lsb
Figure 5-19 SPI power_stream (spi_clock_polarity = 0, falling edge of SCLK is active)
0ns SCLK SD SCS_N
20ns
40ns
60ns
80ns
100ns
120ns
140ns
160ns
1
a7 a6 a5 a4 a3
0
1
0
p7 p6 p5 p4 p3 p2 p1 p0
Figure 5-20 SPI power_stream (spi_clock_polarity = 1, rising edge of SCLK is active)
0ns SCLK SD SCS_N
20ns
40ns
60ns
80ns
100ns
120ns
140ns
160ns
1
a7 a6 a5 a4 a3
0
1
0
p7 p6 p5 p4 p3 p2 p1 p0
3. word_stream consists of three bytes as follows:
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* * * *
five address bits corresponding to reg_serial_address[4:0] two bits = 10b, that indicate a word_stream a r/w bit that must be zero sixteen bits of the serial_word value - in the order of msb to lsb
Figure 5-21 SPI word_stream (spi_clock_polarity = 0, falling edge of SCLK is active)
0ns SCLK SD SCS_N a7 a6 a5 a4 a3 1 0 0 w15w14w13w12w11w10 w9 w8 w7 w6 w5 w4 w3 w2 w1 w0 50ns 100ns 150ns 200ns 250n
Figure 5-22 SPI word_stream (spi_clock_polarity = 1, rising edge of SCLK is active)
0ns SCLK SD SCS_N a7 a6 a5 a4 a3 1 0 0 w15w14w13w12w11w10 w9 w8 w7 w6 w5 w4 w3 w2 w1 w0 50ns 100ns 150ns 200ns 250n
4. hop_stream consists of one byte as follows: * five address bits corresponding to reg_serial_address[4:0] * two bits = 11b, that indicate a hop_stream * a r/w bit that must be zero
Figure 5-23 SPI hop_stream (spi_clock_polarity = 0, falling edge of SCLK is active)
0ns SCLK SD SCS_N HOP_N carrier/power a7
20ns
40ns
60ns
80ns
100ns
1
a6
a5
a4
a3
1
1
0
Figure 5-23 shows how HOP_N can be used to delay the new carrier/power values.
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Figure 5-24 SPI hop_stream (spi_clock_polarity = 1, rising edge of SCLK is active)
0ns SCLK SD SCS_N HOP_N carrier/power
10ns
20ns
30ns
40ns
50ns
60ns
70ns
80ns
90ns
1
a7
a6
a5
a4
a3
1
1
0
Figure 5-24 shows a case where HOP_N is tied active so that the new carrier/power values take effect immediately after the Hop_Stream.
5.4 Hop Generation The hop_state_machine generates the Hop pulse that propagates throughout the chip and activates the new carrier and power values. The Hop pulse is generated upon a write to the Hop bit in the Control register, or on the later of HOP_N and a Hop_Stream. There are three methods of operation: 1. The Hop bit in the Control register controls the activation point. The CPU writes to the next_carrier and/or next_power registers, then writes 1 to the Hop bit in the Control register. 2. HOP_N controls the activation point. Carrier_Stream and Power_Stream are immediately followed by a Hop_Stream. Then HOP_N is applied so that the new values are activated at the correct time. This is a likely scenario for Multi_Band_Mode (e.g. single-carrier EDGE systems). This is illustrated in Figure 5-23. 3. Hop_Stream controls the activation point. HOP_N is held active by connecting it to VSS, thereby reducing system pin requirements. The Hop_Stream is used to activated new values at the correct time. This is illustrated in Figure 5-24. Note that the final bit of the Hop_Stream can be delayed to the desired time. 5.4.1 Power and Carrier Values and Hop There are two parameters that are used throughout the device and must be explained here:
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* Power - Power selection by base station. This is an 8-bit integer value and its interpretation is configured by the Power_Attenuation_Table, the Power_Correction_Gain_Table, and the Carrier_Power_Map. * Carrier - Carrier (or frequency band) selection by base station. This is a 9-bit integer value and its interpretation is configured by the Carrier_Correction_Gain_Table and the Carrier_Power_Map. The Power and Carrier values can be input through the serial interface, or directly programmed by the CPU. In either case, the values entered are Next_Power and Next_Carrier, and they become active Power and Carrier values after the next Hop occurs (see Section 5.4, Hop Generation, on page 30). The new Power value propagates to the Power_Attenuation_Table after a delay controlled by the Power_Attenuator_Delay register. The new Power and Carrier values propagate to all other areas of the device after a delay controlled by the Power_Correction_Delay register. These two programmable delays are designed to allow some control over the effects of power changes throughout the system.
5.4.2 Bug that affects Power_Attenuator_Delay and Power_Correction_Delay
The Power_Attenuator_Delay and Power_Correction_Delay circuits were intended to operate so that: 1. if Power_Attenuator_Delay > Power_Correction_Delay, the Power_Attenuator output on GPIO[15:0] and the pulse output on GPIO17 are delayed with respect to the power_correction_gain value applied inside the chip. 2. if Power_Attenuator_Delay < Power_Correction_Delay, the Power_Attenuator output on GPIO[15:0] and the pulse output on GPIO17 are earlier than the power_correction_gain value applied inside the chip. The bug has two ramifications: * The relationship between these two delays must be such that Power_Attenuator_Delay >= Power_Correction_Delay + 1, i.e. (2) above is not possible. We recommend that Power_Correction_Delay is programmed to its default state of zero. * The Power_Attenuator output on GPIO[15:0] is not delayed but the pulse on GPIO17 is. Therefore, the external attenuator device must use the pulse to latch the new Power_Attenuator value. See Section 5.5.1, Power Attenuator Outputs, on page 33.
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Digital Correction Signal Processor
5.5 GPIO Pins These pins are general-purpose input-outputs. They are controlled and monitored through the PM7800 register set. Some of the pins have secondary functions. * GPIO[15:0] can be configured to output the value from the Power_Attenuator_Table. * GPIO16 can be configured to output an active-low pulse of 32TDCLK duration when the Watchdog Timer expires. * GPIO17 can be configured to output a 5TDCLK pulse when a Hop occurs. The pulse is positioned so that its leading edge is concurrent with changes in the value of the Power_Attenuator_Table output at GPIO[15:0] - see Functional Timing. The polarity of the pulse is selected by the Atten_Pulse_Polarity bit in the Mode register. * GPIO[23:18] have no secondary function. * GPIO[27:24] can be configured as falling-edge triggered interrupt sources. The interrupts are enabled using the GPIO_Interrupt_Enable bits in the Interrupt_Enable2 register. The interrupts are monitored and cleared in the Interrupt_Status_Clear register. * GPIO[31:28] can be configured as rising-edge triggered interrupt sources. The interrupts are enabled using the GPIO_Interrupt_Enable bits in the Interrupt_Enable2 register. The interrupts are monitored and cleared in the Interrupt_Status_Clear register. * GPIO[47:32] have no secondary function.
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PM7800 PALADIN-10
Digital Correction Signal Processor
5.5.1 Power Attenuator Outputs
DCLK p o w er_ correctio n _ g ain TD G P IO [1 5 :0 ] 5TD G P IO 1 7 p o w er_ atten u ato r_ d elay * T D
Figure 5-25 Power Attenuator Outputs - shown with active-low pulse on GPIO17
5.5.2 Watchdog Timer Output 0ns 50ns
DCLK
100ns
150ns
200ns
250ns
300ns
3
32TDCLK
GPIO16
Figure 5-26 Watchdog Timer Output
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PM7800 PALADIN-10
Digital Correction Signal Processor
5.6 JTAG Test Access Port
PM 7800 DCSP
tck trs tb tm s tdi tdo s ca ns el s ca ne n o e_ n
J TA G
S c an T es t
Figure 5-27 JTAG and Scan Test Interfaces
The JTAG Test Access Port block provides JTAG support for boundary scan. The standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions are supported. The PM7800 identification code is 178000CD hexadecimal. The JTAG port is described in detail in Test Features section 6.
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PM7800 PALADIN-10
Digital Correction Signal Processor
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PM7800 PALADIN-10
Digital Correction Signal Processor
6 Test Features
The PM7800 has four test modes: Full Scan, RAMBIST, OE_N Pin, and JTAG Boundary Scan. 6.1 Full Scan The core logic is tested using full scan. The following table describes the full-scan interface.
Table 6-1 Full-Scan Interface
Pin SCANSEL Description Selects full-scan mode: selects RESET_N to directly control all flop sets and resets; disables RAM BIST; configures the SCANIN and SCANOUT IO pads. Enables the scan chain. SCANIN bus. SCANIN bus. SCANIN bus. SCANOUT bus. SCANOUT bus. SCANOUT bus.
Full-Scan Signal SCANSEL
SCANEN SCANIN[55:32] SCANIN[31:16] SCANIN[15:0] SCANOUT[55:32] SCANOUT[31:16] SCANOUT[15:0]
SCANEN GPIO[47:24] VD_Q[15:0] VD_I[15:0] GPIO[23:0] VREF_Q[15:0] VREF_I[15:0]
6.2 RAMBIST These registers are for RAMBIST. They must remain in their default states during regular operation.
0x0_00F0 Name BISTTEST[7:0] BIST_Mode Type RW Size 8 Bits 7:0 Description BIST test pattern bus which is replicated over the RAM data bus. This bus is the seed used by the BIST to generate patterns during the bist test. It is also used in exercising the backdoor feature by providing a method to shift in/out data. This bit activates BIST testing. Reset 0
BISTEN
RW
1
8
0
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Digital Correction Signal Processor
0x0_00F0 Name BISTSIDE
BIST_Mode Type RW Size 1 Bits 9 Description BISTSIDE is used to select between port A and port B when performing a BIST test. Since Predistorter1 contains dual-port RAM, two BIST tests must be run, first with this bit = 0, and then with this bit = 1. 0: port A 1: port B BISTMODE configures the BIST in several different modes: 000: bistmode_hold 001: bistmode_shift 010: bistmode_bist 011: bistmode_run 100: bistmode_reset 101 ~ 111: Reserved. Reset 0
BISTMODE[2:0]
RW
3
12:10
0
0x0_00F2 Name BISTEND
BIST_Result1 Type RO Size 1 Bits 0 Description The BISTEND bit indicates the BIST test sequence has completed. When the BIST test is complete, bistend transitions from low to high. The BISTRESULT bit indicates whether all RAMs have passed or failed the BIST test. If BISTRESULT transitions from high to low, a RAM has experienced a compare failure (i.e. at least one of the bisterror bits have been asserted). Once a compare failure is detected, BISTRESULT transitions to a low state, and stays in that state for the remainder of the test. BISTERROR bus to indicate compare failure on a RAM word. Each bit corresponds to one of the RAMs in the device. The BISTERROR bit associated with each RAM toggles high each time a compare failure is detected. Reset 0
BISTRESULT
RO
1
1
0
BISTERROR[13:0]
RO
14
15:2
0
0x0_00F4 Name BISTERROR[20:14]
BIST_Result2 Type RO Size 7 Bits 6:0 Description BISTERROR bus to indicate compare failure on a RAM word. Each bit corresponds to one of the RAMs in the device. The BISTERROR bit associated with each RAM toggles high each time a compare failure is detected. Reset 0
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PM7800 PALADIN-10
Digital Correction Signal Processor
6.3 OE_N Pin The OE_N pin, when high, deactivates all pins except TDO. TDO is a tri-state output driven during boundary-scan testing only (see below); applying an active-low pulse to TRSTB ensures that TDO is inactive. 6.4 JTAG Boundary Scan, IEEE 1149.1 The PM7800 supports the IEEE Boundary Scan Specification as described in the IEEE 1149.1 standards. The PM7800 JTAG Test Access Port (TAP) allows access to the TAP controller and the four TAP registers: instruction, bypass, device identification and boundary scan. Using the TAP, device input logic levels can be read, device outputs can be forced, the device can be identified and the device scan path can be bypassed. The Test Access Port (TAP) consists of the five standard pins, TRSTB, TCK, TMS, TDI and TDO used to control the TAP controller and the boundary scan registers. The TRSTB input is the activelow reset signal used to reset the TAP controller. TCK is the test clock used to sample data on input, TDI and to output data on output, TDO. The TMS input is used to direct the TAP controller through its states. The boundary-can architecture is shown below.
TDI
Boundary Scan Register Device Identification Register Bypass Register
Instruction Register and Decode
Mux DFF
TDO
TMS
Test Access Port Controller
Control Select Tri-state Enable
TRSTB TCK
Figure 6-1
Boundary-Scan Architecture
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PM7800 PALADIN-10
Digital Correction Signal Processor
The boundary scan architecture consists of a TAP controller, an instruction register with instruction decode, a bypass register, a device identification register and a boundary scan register. The TAP controller interprets the TMS input and generates control signals to load the instruction and data registers. The instruction register with instruction decode block is used to select the test to be executed and/or the register to be accessed. The bypass register offers a single-bit delay from primary input, TDI to primary output, TDO. The device identification register contains the device identification code. The boundary scan register allows testing of board inter-connectivity. The boundary scan register consists of a shift register place in series with device inputs and outputs. Using the boundary scan register, all digital inputs can be sampled and shifted out on primary output, TDO. In addition, patterns can be shifted in on primary input, TDI and forced onto all digital outputs. 6.4.1 TAP Controller The TAP controller is a synchronous finite state machine clocked by the rising edge of primary input, TCK. All state transitions are controlled using primary input, TMS. The finite state machine is described below.
TRSTB=0 T e s t- L o g ic - R e s e t 1 0 1 R u n - T e s t- Id le 0 1 C a p tu re -D R 0 S h if t- D R 1 E x it1 - D R 0 P a u s e -D R 1 0 E x it2 - D R 1 U p d a te -D R 1 0 0 0 E x it2 - IR 1 U p d a t e - IR 1 0 0 1 E x it1 - IR 0 P a u s e - IR 1 0 S e le c t- D R - S c a n 0 1 C a p t u r e - IR 0 S h if t - IR 1 0 1 1 S e le c t- IR - S c a n 0 1
A ll t r a n s it io n s d e p e n d e n t o n in p u t T M S
Figure 6-2
TAP Controller Finite State Machine
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PM7800 PALADIN-10
Digital Correction Signal Processor
Test-Logic-Reset The test logic reset state is used to disable the TAP logic when the device is in normal mode operation. The state is entered asynchronously by asserting input, TRSTB. The state is entered synchronously regardless of the current TAP controller state by forcing input, TMS high for 5 TCK clock cycles. While in this state, the instruction register is set to the IDCODE instruction. Run-Test-Idle The run test/idle state is used to execute tests. Capture-DR The capture data register state is used to load parallel data into the test data registers selected by the current instruction. If the selected register does not allow parallel loads or no loading is required by the current instruction, the test register maintains its value. Loading occurs on the rising edge of TCK. Shift-DR The shift data register state is used to shift the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK. Update-DR The update data register state is used to load a test register's parallel output latch. In general, the output latches are used to control the device. For example, for the EXTEST instruction, the boundary scan test register's parallel output latches are used to control the device's outputs. The parallel output latches are updated on the falling edge of TCK. Capture-IR The capture instruction register state is used to load the instruction register with a fixed instruction. The load occurs on the rising edge of TCK. Shift-IR The shift instruction register state is used to shift both the instruction register and the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK. Update-IR
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Digital Correction Signal Processor
The update instruction register state is used to load a new instruction into the instruction register. The new instruction must be scanned in using the Shift-IR state. The load occurs on the falling edge of TCK. The Pause-DR and Pause-IR states are provided to allow shifting through the test data and/or instruction registers to be momentarily paused. 6.4.2 Registers
6.4.2.1 Instruction Register
Length = 3 bits
Table 6-2 Instruction Register
Selected Register Boundary Scan Identification Boundary Scan Bypass Bypass Boundary Scan Bypass Bypass Instruction Codes, IR[2:0] 000 001 010 011 100 101 110 111
Instructions EXTEST IDCODE SAMPLE BYPASS BYPASS STCTEST BYPASS BYPASS
6.4.2.2 Identification register
Length = 32 bits
Table 6-3 Identification Register
Length Version number Part Number Manufacturer's identification code Device identification 1h 7800h 0CDh 178000CDh 32 bits
6.4.2.3 Boundary Scan Register
Name Register Bit -------------------------------- -----------OEB_GPIO7 333 Cell Type --------OUT_CELL Device ID --------L
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Release Digital Correction Signal Processor Data Sheet PMC-2001646 GPIO7 OEB_GPIO6 GPIO6 OEB_GPIO4 GPIO4 OEB_GPIO5 GPIO5 OEB_GPIO2 GPIO2 OEB_GPIO1 GPIO1 OEB_GPIO3 GPIO3 OEB_GPIO0 GPIO0 OEB_VD_I13 VD_I13 OEB_VD_I10 VD_I10 OEB_VD_I14 VD_I14 OEB_VD_I11 VD_I11 OEB_VD_I15 VD_I15 OEB_VD_I12 VD_I12 OEB_VD_I7 VD_I7 OEB_VD_I8 VD_I8 OEB_VD_I4 VD_I4 OEB_VD_I9 VD_I9 OEB_VD_I5 VD_I5 OEB_VD_I6 VD_I6 OEB_VD_I0 VD_I0 OEB_VD_I1 VD_I1 OEB_VD_I2 VD_I2 OEB_VD_I3 VD_I3 DCLK OEB_VD_Q15 VD_Q15 OEB_VD_Q14 VD_Q14 OEB_VD_Q13 VD_Q13 OEB_VD_Q12 VD_Q12 OEB_VD_Q11 VD_Q11 OEB_VD_Q10 VD_Q10 OEB_VD_Q9 VD_Q9 OEB_VD_Q8 VD_Q8 OEB_VD_Q7 VD_Q7 OEB_VD_Q5 VD_Q5 OEB_VD_Q4 VD_Q4 OEB_VD_Q6 VD_Q6 OEB_VD_Q3 VD_Q3 OEB_VD_Q1 VD_Q1 OEB_VD_Q0 ISSUE 3
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IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL IN_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL
L L L L H H H H L L L L L L L L L L L L L L L H H L L H H L H -
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Release Digital Correction Signal Processor Data Sheet PMC-2001646 VD_Q0 OEB_VD_Q2 VD_Q2 OEB_GPIO47 GPIO47 OEB_GPIO46 GPIO46 OEB_GPIO45 GPIO45 MUTE_N CPUMODE4 CPUMODE3 OEB_GPIO44 GPIO44 OEB_GPIO42 GPIO42 OEB_GPIO43 GPIO43 ADR1 ADR0 ADR2 ADR4 ADR8 ADR3 ADR7 ADR11 ADR6 ADR10 ADR5 ADR9 ADR14 ADR13 ADR17 ADR12 ADR16 ADR15 CS2 CS1_N CS0_N CPUCLK STRB1_N STRB2_N OEB_WAIT_N WAIT_N OEB_IRQ_N IRQ_N OEB_DAT0 DAT0 OEB_DAT1 DAT1 OEB_DAT2 DAT2 OEB_DAT3 DAT3 OEB_DAT4 DAT4 OEB_DAT5 DAT5 OEB_DAT6 DAT6 OEB_DAT7 DAT7 OEB_DAT8 DAT8 OEB_DAT9 DAT9 OEB_DAT11 DAT11 OEB_DAT12 DAT12 OEB_DAT10 DAT10 OEB_DAT13 DAT13 OEB_DAT15 DAT15 OEB_DAT14 ISSUE 3
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IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL IN_CELL IN_CELL IN_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL
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Release Digital Correction Signal Processor Data Sheet PMC-2001646 DAT14 OEB_GPIO41 GPIO41 OEB_GPIO38 GPIO38 OEB_GPIO37 GPIO37 OEB_GPIO39 GPIO39 VSS OEB_GPIO36 GPIO36 OEB_GPIO40 GPIO40 CPUMODE1 CPUMODE0 OEB_SD SD OEB_GPIO35 GPIO35 OEB_GPIO33 GPIO33 OEB_GPIO30 GPIO30 OEB_GPIO34 GPIO34 OEB_GPIO31 GPIO31 HOP_N OEB_GPIO32 GPIO32 OEB_GPIO29 GPIO29 SCS_N OEB_VREF_Q1 VREF_Q1 SCLK OEB_VREF_Q2 VREF_Q2 OEB_VREF_Q0 VREF_Q0 OEB_VREF_Q3 VREF_Q3 OEB_VREF_Q4 VREF_Q4 OEB_VREF_Q6 VREF_Q6 OEB_VREF_Q5 VREF_Q5 OEB_VREF_Q7 VREF_Q7 OEB_VREF_Q8 VREF_Q8 OEB_VREF_Q9 VREF_Q9 OEB_VREF_Q10 VREF_Q10 OEB_VREF_Q11 VREF_Q11 OEB_VREF_Q12 VREF_Q12 OEB_VREF_Q13 VREF_Q13 OEB_VREF_Q15 VREF_Q15 OEB_VREF_Q14 VREF_Q14 REFCLK OEB_VREF_I2 VREF_I2 OEB_VREF_I1 VREF_I1 OEB_VREF_I0 VREF_I0 OEB_VREF_I5 VREF_I5 OEB_VREF_I4 ISSUE 3
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IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL IN_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL IN_CELL IN_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL IN_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL IN_CELL OUT_CELL IO_CELL IN_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL IN_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL
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Release Digital Correction Signal Processor Data Sheet PMC-2001646 VREF_I4 OEB_VREF_I8 VREF_I8 OEB_VREF_I3 VREF_I3 OEB_VREF_I7 VREF_I7 OEB_VREF_I6 VREF_I6 OEB_VREF_I11 VREF_I11 OEB_VREF_I10 VREF_I10 OEB_VREF_I15 VREF_I15 OEB_VREF_I14 VREF_I14 OEB_VREF_I9 VREF_I9 OEB_VREF_I13 VREF_I13 OEB_GPIO28 GPIO28 OEB_VREF_I12 VREF_I12 RESET_N OEB_GPIO27 GPIO27 OEB_GPIO25 GPIO25 OEB_GPIO26 GPIO26 OEB_GPIO23 GPIO23 OEB_GPIO22 GPIO22 OEB_GPIO24 GPIO24 OEB_GPIO21 GPIO21 OEB_GPIO19 GPIO19 OEB_GPIO18 GPIO18 OEB_GPIO20 GPIO20 OEB_GPIO17 GPIO17 OEB_GPIO16 GPIO16 OEB_GPIO15 GPIO15 VOBS_Q15 VOBS_Q13 VOBS_Q9 VOBS_Q14 VOBS_Q10 VOBS_Q6 VOBS_Q11 VOBS_Q7 VOBS_Q12 VOBS_Q8 VOBS_Q3 VOBS_Q4 VOBS_Q5 VOBS_Q0 VOBS_Q1 VOBS_Q2 VOBS_I12 VOBS_I13 VOBS_I14 VOBS_I15 VOBS_I11 VOBS_I10 VOBS_I9 VOBS_I8 VOBS_I7 ISSUE 3
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101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL IN_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL
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Release Digital Correction Signal Processor Data Sheet PMC-2001646 VOBS_I6 VOBS_I5 VOBS_I4 VOBS_I3 VOBS_I2 VOBS_I1 VOBS_I0 SCANSEL SCANEN OE_N OEB_GPIO14 GPIO14 OEB_GPIO13 GPIO13 OEB_GPIO12 GPIO12 OEB_GPIO11 GPIO11 OEB_GPIO10 GPIO10 OEB_GPIO9 GPIO9 OEB_GPIO8 GPIO8 VD_FMT ISSUE 3
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PM7800 PALADIN-10
Digital Correction Signal Processor
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL IN_CELL
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6.4.3 Instructions The following is an description of the standard instructions. Each instruction selects an serial test data register path between input, TDI and output, TDO. BYPASS The bypass instruction shifts data from input, TDI to output, TDO with one TCK clock period delay. The instruction is used to bypass the device. EXTEST The external test instruction allows testing of the interconnection to other devices. When the current instruction is the EXTEST instruction, the boundary scan register is place between input, TDI and output, TDO. Primary device inputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state. Primary device outputs can be controlled by loading patterns shifted in through input TDI into the boundary scan register using the Update-DR state. SAMPLE The sample instruction samples all the device inputs and outputs. For this instruction, the boundary scan register is placed between TDI and TDO. Primary device inputs and outputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state. IDCODE
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Digital Correction Signal Processor
The identification instruction is used to connect the identification register between TDI and TDO. The device's identification code can then be shifted out using the Shift-DR state. STCTEST The single transport chain instruction is used to test out the TAP controller and the boundary scan register during production test. When this instruction is the current instruction, the boundary scan register is connected between TDI and TDO. During the Capture-DR state, the device identification code is loaded into the boundary scan register. The code can then be shifted out output, TDO using the Shift-DR state. 6.4.4 Boundary Scan Cells
IDCODE Scan Chain Out
Input Pad
G1 G2 SHIFT-DR
INPUT to internal logic
I.D. Code bit CLOCK-DR
12 1 2 MUX 12 12
Scan Chain In
D C
Table 6-4
Input Observation Cell (IN_CELL)
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Scan Chain Out EXTEST Output or Enable from system logic IDOODE SHIFT-DR
G1 1 G1 G2 1 1 1 1 2 2 MUX 2 2 1
MUX
OUTPUT or Enable
D C
D C
I.D. code bit CLOCK-DR UPDATE-DR
Scan Chain In
Figure 6-3
Output Cell (OUT_CELL)
Scan Chain Out INPUT to internal logic
EXTEST OUTPUT from internal logic IDCODE SHIFT-DR INPUT from pin
G1 1 G1 G2 12 1 2 MUX 12 12 D C D C 1
MUX
OUTPUT to pin
I.D. code bit CLOCK-DR UPDATE-DR
Scan Chain In
Figure 6-4
Bi-directional Cell (IO_CELL)
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PMC-Sierra, Inc.
PM7800 PALADIN-10
Digital Correction Signal Processor
Scan Chain Out OUTPUT ENABLE from internal logic (0 = drive) INPUT to internal logic OUTPUT from internal logic
OUT_CELL
IO_CELL
I/O PAD
Scan Chain In
Figure 6-5
Layout of Output Enable and Bidirectional Cells
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PM7800 PALADIN-10
Digital Correction Signal Processor
7 Absolute Maximum Ratings
Maximum rating are the worst case limits that the device can withstand without sustaining permanent damage. They are not indicative of normal mode operation conditions.
Table 7-1 Absolute Maximum Ratings
Parameter Junction Temperature Junction Temperature under Bias (Operation) 1 Junction Temperature under Bias (Long-Term) 2 Storage Temperature Supply Voltage 3,4 Supply Voltage 3,4 Voltage on Any Pin Static Discharge Voltage Latch-Up Current DC Input Current Lead Temperature IIN Symbol TJ (Absolute) TJ (Operation) TJ (Long-Term) TST VVDDI VVDD VIN +150 -40 to +125 -40 to +105 -40 to +125 -0.3 to + 3.6 -0.3 to + 6.0 -0.3 to 6.0 1000 100 20 +230 Value C C C C VDC VDC VDC V mA mA C Units
Notes on Power Supplies: 1. Correct operation is not guaranteed outside these limits. 2. Long-term operation outside these limits will reduce reliability. 3. VDD must power up before VDDI. 4. VDD must not drop below VDDI except when VDDI is not powered.
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Release Digital Correction Signal Processor Data Sheet PMC-2001646 ISSUE 3
PMC-Sierra, Inc.
PM7800 PALADIN-10
Digital Correction Signal Processor
8 DC Characteristics
TJ = -40C to +125C, VVDD = 3.3 V 5%, VVDDI = 1.8V 5% (Typical Conditions: TJ = 25C, VVDD = 3.3 V, VVDDI = 1.8V)
Table 8-1
Symbol VDD VDDI VIL VIH VOL
D.C.Characteristics
Parameter Pin Power Supply Core Power Supply Input Low Voltage Input High Voltage Output or Bidirectional Low Voltage Min 3.15 1.71 0 2.0 0 0.1 0.4 Typ 3.3 1.8 Max 3.45 1.89 0.8 Units Volts Volts Volts Volts Volts VDD = min IOL = 4mA for * VREF_I[15:0], VREF_Q[15:0] (outputs in scan test mode only) IOL = 12mA for * * * * * IRQ_N VD_I[15:0], VD_Q[15:0] SD TDO GPIO[47:0] Conditions Tj = -40C to 125C Tj = -40C to 125C
IOL = 15mA for * DAT[15:0] * WAIT_N VOH Output or Bidirectional High Voltage 2.4 Volts VDD = min IOH = -4mA for * VREF_I[15:0], VREF_Q[15:0] (outputs in scan test mode only) IOH = -12mA for * IRQ_N * VD_I[15:0], VD_Q[15:0] * SD * TDO * GPIO[47:0] IOH = -15mA for * DAT[15:0] * WAIT_N VT+ Schmitt Input High Threshold Voltage VTSchmitt Input Low Threshold Voltage VTH Schmitt Input Hysteresis Voltage 0.87 Volts 0.8 Volts 2.2 Volts
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PM7800 PALADIN-10
Digital Correction Signal Processor
Table 8-1
Symbol IIL
D.C.Characteristics
Parameter Input Low Leak Current Min -10 Typ Max +10 Units A Conditions VIL = GND. Note 1
IIH
Input High Leak Current
-10
+10
A
VIH = VDD. Note 1
IILPD
Input Low Leak Current for input with pull-down.
-10
+10
A
VIL = GND. Note 1
IIHPD
Input High Leak Current for input with pull-down.
+50
+400
A
VIH = VDD. Note 1
IILPU
Input Low Leak Current for input with pull-up.
-300
-10
A
VIL = GND. Note 1
IIHPU
Input High Leak Current for input with pull-up.
-10
+10
A
VIH = VDD. Note 1
CIN COUT CIO
Input Capacitance Output Capacitance Bidirectional Capacitance
8 8 8
pF pF pF
IDDOP (VDDI)
Core Operating Current for PM7800
230 (VDDI = 1.80V)
560 (VDDI = 1.89V)
mA
DCLK = 80MHz
IDDOP (VDDO)
Nominal IO Operating Current for PM7800
132
mA
VDDO = 3.3V DCLK = 80MHz CL = 20pF
Notes on D.C. Characteristics: 1. Positive currents flow into the device (sinking), negative currents flow out of the device (sourcing).
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PM7800 PALADIN-10
Digital Correction Signal Processor
9 AC Timing
TJ = -40C to +125C, VVDD = 3.3 V 5%, VVDDI = 1.8V 5% Notes on Input Timing: 1. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 2. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input. 3. It is recommended that the transition time on all clock inputs is less than 15 ns. Notes on Output Timing: 1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 1. Output tristate delay is the time in nanoseconds from the 1.4 Volt point of the reference signal to the point where the total current delivered through the output is less than or equal to the leakage current.
9.1 RESET_N
Figure 9-1 RESET_N
0ns
20ns
40ns tw
60ns
80ns
100ns
12
RESET_N
Table 9-1
parameter tw
RESET_N
min 100 max units ns RESET_N pulse width. description notes
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PM7800 PALADIN-10
Digital Correction Signal Processor
9.2 CPU Interface
Figure 9-2 CPU Interface - DCLK Timing
0ns DCLK
5ns
10ns
15ns
20ns
25ns
30ns
3
tcs STRBx,CSx tas ADR[17:0] toe
tch
toz
tah
tdp DAT[15:0] trp IRQ_N
tds
tdh
Table 9-2
parameter TDCLK tcs tch tas tah tds tdh toe tdp toz trp
CPU Interface - DCLK Timing
min 12.5 3 max units ns ns DCLK Period. STRB1_N, STRB2_N, CS0_N, CS1_N, CS2 setup time to DCLK. STRB1_N, STRB2_N, CS0_N, CS1_N, CS2 hold time from DCLK. ADR setup time to DCLK. ADR hold time from DCLK. DAT input-setup time to DCLK. DAT input-hold time from DCLK. DAT driven delay from DCLK, 30pF load. DAT propagation delay from DCLK, 30pF load. DAT released delay from STRBx, CSx, 30pF load. IRQ_N propagation delay from DCLK, 30pF load. 1 description notes
2
ns
1
5 0 5 0 12 12 12 12
ns ns ns ns ns ns ns ns
1 1 1 1
1. The system designer need not worry about violating setup and hold times - all inputs are treated as asynchronous signals. Setup and hold times are specified here to identify the clock edge on which the signal is sampled.
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PM7800 PALADIN-10
Digital Correction Signal Processor
Figure 9-3
CPU Interface - CPUCLK Timing
0ns CPUCLK t cs STRBx,CSx t csx STRBx,CSx t wp WAIT_N t chx t ch 5ns 10ns 15ns 20ns 25ns 30ns 3
Table 9-3
parameter TCPUCLK tcs tch tcsx tchx
CPU Interface - CPUCLK Timing
min 8 3 max units ns ns CPUCLK Period. STRB1_N, STRB2_N, CS0_N, CS1_N, CS2 setup time to positive edge CPUCLK. STRB1_N, STRB2_N, CS0_N, CS1_N, CS2 hold time from posedge CPUCLK. STRB1_N, STRB2_N, CS0_N, CS1_N, CS2 setup time to negative edge CPUCLK (for reads operation with CPUMODE3 = 1). STRB1_N, STRB2_N, CS0_N, CS1_N, CS2 hold time from negative edge CPUCLK (for reads operation with CPUMODE3 = 1). WAIT_N propagation delay from CPUCLK (CPUMODE4 = 0). WAIT_N propagation delay from CPUCLK (CPUMODE4 = 1). description notes
2
ns
3
ns
2
ns
twp
2 (15pF) 5 (15pF)
10 (30pF) 16 (30pF)
ns ns
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PM7800 PALADIN-10
Digital Correction Signal Processor
9.3 VREF, VOBS, VD Interfaces 9.3.1 Dual-Clock System Use the dual-clock system when VREF is synchronous to REFCLK (usually when VREF is upsampled internally to the DCLK rate). In this case, a FIFO and interpolator are used to upsample VREF to the DCLK rate. REFCLK must be created from DCLK such that there is no varying phase shift that may cause under-run or over-run.
Figure 9-4 Dual-Clock System timing 0ns 5ns
DCLK tsvobs VOBS top VD T REFCLK tskew REFCLK tsref VREF thref thvobs
10ns T DCLK
15ns
20ns
25ns
Table 9-4
parameter TDCLK TREFCLK tskew tsvobs thvobs top tsref thref
Dual-Clock System timing
min 12.5 12.5 0 3 0 1.8 (15pF) 2 0 7.8 (30pF) TDCLK max units ns ns ns ns ns ns ns ns DCLK period. REFCLK period. DCLK to REFCLK skew. VOBS setup time to DCLK. VOBS hold time from DCLK. Output delay from DCLK. VREF setup time to REFCLK. VREF hold time from REFCLK. 1 2 description notes
Note: 1. TREFCLK must be an exact integer multiple of TDCLK, i.e. TREFCLK = nTDCLK, where n = 1,2,...,10. REFCLK must be created from DCLK.
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PM7800 PALADIN-10
Digital Correction Signal Processor
2. Skew may exist between DCLK and REFCLK, but this skew must not vary over time by more than one DCLK period. 9.3.2 Single-Clock System Use the single-clock system when all signals are synchronous to DCLK and the data-rate of VREF is the same as the output data-rate of VD. In this case, connect the REFCLK pin to VSS, and bypass the FIFO and interpolator to reduce latency through the chip.
Figure 9-5 Single-Clock System timing
0ns DCLK
5ns
10ns TDCLK tsvref
15ns
20ns
thvref thvobs top
VREF tsvobs VOBS VD
Table 9-5
parameter TDCLK tsvref thvref tsvobs thvobs top
Single-Clock System timing
min 12.5 3 0 3 0 1.8 (15pF) 7.8 (30pF) max units ns ns ns ns ns ns DCLK period. VREF setup time to DCLK. VREF hold time from DCLK. VOBS setup time to DCLK. VOBS hold time from DCLK. VD propagation delay from DCLK. description notes
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PM7800 PALADIN-10
Digital Correction Signal Processor
9.4 Serial Interface 9.4.1 Serial Interface AC Timing All serial inputs are debounced and synchronized to dclk. The minimum pulse width for all serial input signals is 2TDCLK + setup and hold.
Figure 9-6 AC Timing for Serial Inputs (SCLK, SCS_N, SD, HOP_N)
0ns dclk
10ns
20ns
30ns
40ns
50ns
60ns
70ns
80ns
90ns
100n
tw tih tnx PIN Debounced_PIN tis tis tw
Table 9-6
parameter tis tih tw tnx
AC Timing for Serial Inputs (SCLK, SCS_N, SD, HOP_N)
min 0 3 2TD + tis + tih TD - tis - tih max units ns ns ns ns Setup time to DCLK. Hold time from DCLK. Pulse width for input. Noise exclusion period. description notes 1 1 2 3
Note: 1. The system designer need not worry about violating tis and tih - all inputs are treated as asynchronous signals. Setup and hold times are specified here to identify the clock edge on which the signal is sampled. 2. The input signal must be stable for at least two rising edges of DCLK. 3. All serial inputs are debounced on rising and falling edges. The period of noise (bounce) must be smaller than TD - tis - tih.
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PM7800 PALADIN-10
Digital Correction Signal Processor
9.5 GPIO
Figure 9-7 GPIO
0ns DCLK top toe DAT[15:0]
10ns
20ns
30ns
40ns
tis toz data_out tw
tih
data_in
Table 9-7
parameter tis tih tw toe top toz
GPIO
min 3 2 2TDCLK + tis + tih 2 (15pF) 2 (15pF) 2 (15pF) 14 (30pF) 14 (30pF) 14 (30pF) max units ns ns ns ns ns ns description GPIO input-setup time to DCLK. GPIO input-hold time from DCLK. GPIO[31:24] signal width. GPIO output-driven delay from DCLK. GPIO output-propagation delay from DCLK. GPIO output-released delay from DCLK. notes 1 1 2
1. The system designer need not worry about violating tis and tih - all inputs are treated as asynchronous signals. Setup and hold times are specified here to identify the clock edge on which the signal is sampled. 2. GPIO[31:24] are debounced. The input signal must be stable for at least two rising edges of DCLK. The period of noise (bounce) must be smaller than TD - tis - tih.
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PMC-Sierra, Inc.
PM7800 PALADIN-10
Digital Correction Signal Processor
9.6 JTAG Interface
Figure 9-8 JTAG Interface
TCK tS TMS tS TDI tH tH
TMS
TMS
TDI
TDI
TCK tP TDO
TDO
tV TRSTB
TRSTB
Table 9-8
parameter
JTAG Interface
min 5 40 60 max units MHz % ns ns ns ns 50 ns ns TCK Frequency TCK Duty Cycle TMS Set-up time to TCK TMS Hold time to TCK TDI Set-up time to TCK TDI Hold time to TCK TCK Low to TDO Valid TRSTB Pulse Width description notes
tSTMS tHTMS tSTDI tHTDI tPTDO tVTRSTB
50 50 50 50 2 100
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PMC-Sierra, Inc.
PM7800 PALADIN-10
Digital Correction Signal Processor
10 Thermal
Forced Air (Linear Feet per Minute)
Theta JA @ 1.6W
Conv
100
200
300
400
500
Dense Board
23.4
20.7
18.9
17.8
17.3
17.1
JEDEC Board
15.7
14.0
12.8
12.0
11.4
10.9
Notes: 1. Dense Board is defined as a 3S3P board and consists of a 3x3 array of device PM7800 located as close to each other as board design rules allow. All PM7800 devices are assumed to be dissipating 1.6Watts. Theta-JA listed is for the device in the middle of the array. 2. JEDEC Board: Theta-JA is the measured value for a single thermal device in the same package on a 2S2P board following EIA/JESD 51-3.
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PM7800 PALADIN-10
Digital Correction Signal Processor
11 Mechanical
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PM7800 PALADIN-10
Digital Correction Signal Processor
CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place, Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com (604) 415-4533 http://www.pmc-sierra.com
Document Information: Corporation Information: Application Information:
Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 2001 PMC-Sierra, Inc. PMC-2001646 ( R3) Issue date: July, 2001
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