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INDEX PRELIMINARY
MX26C1024A
FEATURES
* * * * * * 64K words by 16-bit organization +5V operating power supply Electric erase instead of UV light erase +12V5% program/erase voltage Fast access time: 70/90/100/120 ns Low power consumption - 40mA maximum active current - 100uA maximum standby current * Command - driven program/erase mode - chip program 3 seconds typical - chip erase 3 seconds typical * 100 minimum erase/program cycles
1M-BIT [64K x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE ROM
* Compatible with JEDEC-standard word-wide EPROM pinouts * Package type: - 44-pin PLCC - 40-pin 10 x 14mm TSOP(I) - 40-pin PDIP
E PAT
D NTE
TEC
LO HNO
GY
GENERAL DESCRIPTION
The MX26C1024A is a 1M-bit MTP ROM TM (Multiple-Time Programmable Read Only Memory) organized as 64K words of 16 bits each. MXIC's MTP ROMs offer the most cost-effective and reliable read/write non-volatile random access memory. It is designed to be reprogrammed and erased insystem or in standard EPROM programmers. The standard MX26C1024A offers access times as fast as 70 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX26C1024A has separate chip enable (CE) and output enable (OE ) controls. MXIC's MTP ROMs augment EPROM functionality with in-circuit electrical erasure and programming. The MX26C1024A uses a command register to manage this functionality, while maintaining entirely compatible to EPROM/OTP pinout. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility. MXIC MTP ROM TM technology reliably stores memory contents after 100 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The MX26C1024A uses a 12.0V 5% VPP supply to perform the Program/Erase algorithms. The MX26C1024A MTP ROMTM is available in industry standard 40 pin dual-in-line package, 44 lead PLCC, 40 TSOP (I) package.
P/N: PM0457
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INDEX
MX26C1024A
PIN CONFIGURATIONS
40 PDIP
VPP CE Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 VSS Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC WE NC A15 A14 A13 A12 A11 A10 A9 VSS A8 A7 A6 A5 A4 A3 A2 A1 A0
40 TSOP(1)
A9 A10 A11 A12 A13 A14 A15 NC WE VCC VPP CE Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS A8 A7 A6 A5 A4 A3 A2 A1 A0 OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 VSS
MX26C1024A
MX26C1024A
44 PLCC
VCC VPP Q13 Q14 Q15 A15 A14 WE NC NC CE
PIN DESCRIPTION:
6 1 44 40 39
SYMBOL
A13 A12 A11 A10 A9
PIN NAME Address Input Data Input/Output Chip Enable Input Output Enable Input Write Enable Pin Program Supply Voltage Power Supply Pin (+5V) Ground Pin No Internal Connection
Q12 Q11 Q10 Q9 Q8 VSS NC Q7 Q6 Q5 Q4
7
A0~A15 Q0~Q15 CE OE WE VPP VCC VSS NC
12
MX26C1024A
34
VSS NC A8 A7 A6
17 18 Q3 Q2 Q1 Q0 OE
23 NC A0 A1 A2 A3
29 28 A4
A5
BLOCK DIAGRAM
CE WE OE
CONTROL LOGIC
OUTPUT BUFFERS
Q0~Q15
A0~A15 ADDRESS INPUTS
. . . . . . . .
Y-DECODER
X-DECODER
. . . . . . . .
Y-SELECT
1M BIT CELL MAXTRIX
VCC VSS
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MX26C1024A
COMMAND DEFINITIONS
When low voltage is applied to the VPP pin, the contents of the command register default to 0000H, enabling read-only operation. TABLE 1. COMMAND DEFINITIONS
COMMAND BUS CYCLES Read Memory Read Identified codes Setup Erase/ Erase 1 2 2 FIRST BUS CYCLE OPERATION Write Write Write ADDRESS X X X DATA XX00H XX90H XX20H Read Write IA X ID XX20H SECOND BUS CYCLE OPERATION ADDRESS DATA
Placing high voltage on the VPP pin enables read/ write/erase operations. Device operations are selected by writing specific data patterns into the command register. Table 1 defines these MX26C1024A register commands. Table 2 defines the bus operations of MX26C1024A.
Setup program/ program Reset
2
Write
X
XX40H
Write
PA
PD
2
Write
X
XXFFH
Write
X
XXFFH
Note: IA = Identifier address PA = Address of memory location to be programmed ID = Data read from location IA during device identification(Manufacture code = 00C2H, Device code = 00E3H) TABLE 2. MX26C1024 BUS OPERATIONS
OPERATION READ-ONLY Read Output Disable Standby READ/WRITE Read Standby(5) Output Disable Write VPP(1) VPPL VPPL VPPL VPPH VPPH VPPH VPPH
PD X
= Data to be programmed at location PA = X can be VIH or VIL
A0 A0 X X A0 X X A0
A9 A9 X X A9 X X A9
CE VIL VIL VIH VIL VIH VIL VIL
OE VIL VIH X VIL X VIH VIH
WE VIH VIH X VIH X VIH VIL
Q0-Q15 Data Out Tri-State Tri-State Data Out(4) Tri-State Tri-State Data In(6)
NOTES: 1. VPPL may be grounded, a no-connect with a resistor tied to ground, or < VCC + 2.0V. VPPH is the programming voltage specified for the device. When VPP = VPPL, memory contents can be read but not written or erased. 2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1. All other addresses are low.
P/N: PM0457
3. Read operations with VPP = VPPH may access array data or Silicon ID codes. 4. With VPP at high voltage, the standby current equals ICC + IPP (standby). 5. Refer to Table 1 for valid Data-In during a write operation. 6. X can be VIL or VIH.
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MX26C1024A
READ COMMAND
While VPP is high, for erasure and programming, memory contents can also be accessed via the read command. The read operation is initiated by writing XX00H into the command register. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the command register contents are altered. The default contents of the register upon VPP powerup is 0000H. This default value ensures that no spurious alteration of memory contents occurs during the VPP power transition. Where the VPP supply is hard-wired to the MX26C1024A, the device powers up and remains enabled for reads until the command register contents are changed. This two-step sequence of set-up followed by execution ensures that memory contents are not accidentally erased. Also, chip-erasure can only occur when high voltage is applied to the VPP pin. In the absence of this high voltage, memory contents are protected against erasure.
ERASE-VERIFY
After each erase operation, all words must be verified. Verification should be performed on the erased bits to detemine that they were correctly erased. The verification should be perfomed with OE and CE at VIL, and VPP at its erase voltage. The MX26C1024A applies an internally generated margin voltage to the addressed word. Reading FFFFH from the addressed word indicates that all bits in the word are erased. The process continues for each word in the array until a word does not return FFFFH data, or the last address is accessed.
SILICON-ID-READ COMMAND
MTP-memories are intended for use in applications where the local CPU alters memory contents. As such, manufacturer- and device-codes must be accessible while the device resides in the target system. The MX26C1024A contains a Silicon-ID-Read operation to supplement traditional PROM-programming methodology. The operation is initiated by writing XX90H into the command register. Following the command write, a read cycle from address 0000H retrieves the manufacturer code of 00C2H. A read cycle from address 0001H returns the device code of 00E3H. A Reset command should be issued in order to terminate the Silicon-ID-Read operation.
SET-UP PROGRAM/PROGRAM COMMANDS
Set-up program is a command-only operation that stages the device for byte programming. Writing XX40H into the command register performs the set-up operation. Once the program set-up operation is performed, the next WE pulse causes a transition to an active programming operation. Addresses are internally latched on the falling edge of the WE pulse. Data is internally latched on the rising edge of the WE pulse. After the second WE pulse, an internal latch will be triggered to maintain the programming mode. The microprocessor must count the programming time. After valid programming time(tPW) is reach, the microprocessor must toggle the CE a nd WE again to abort the internal latch, thus exit the programming mode.
SET-UP CHIP ERASE/ERASE COMMANDS
Set-up Chip Erase is a command-only operation that stages the device for electrical erasure of all bytes in the array. The set-up erase operation is performed by writing XX20H to the command register. To commence chip erasure, the erase command (XX20H) must again be written to the register. After the second write of erase command, an internal latch will be triggered to maintain the erase mode. The microprocessor must count the erase time. After valid erase time (tEW) is reach, the microprocessor must toggle the CE and WE again to abort the internal latch, thus exit the erase mode.
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MX26C1024A
PROGRAM-VERIFY The MX26C1024A is programmed on a word-by-word basis. Word programming may occur sequentially or at random. Following each programming operation, the word just programmed must be verified. Verification should be performed on the programed bits to detemine that they were correctly programed. The verification should be perfomed with OE and CE at VIL, and VPP at its programming voltage. The program-verify stages the device for verification of the byte last programmed. No new address information is latched. The 26C1024A applies an internally-generated margin voltage to the word. A microprocessor read cycle outputs the data. A successful comparison between the programmed word and true data means that the word is successfully programmed. To gurranttee better margin for change-retention, one more pulse for programming is necessary. Programming then proceeds to the next desired word location. The programming timing waveform, illustrates how commands are combined with bus operations to perform word programming.
SYSTEM CONSIDERATIONS
During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a 0.1uF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between VCC and GND, and between VPP and GND to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on MTP memory arrays, a 4.7uF bulk electrolytic capacitor should be used between VCC and GND for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array.
ABSOLUTE MAXIMUM RATINGS
RATING Ambient Operating Temperature Storage Temperature Applied Input Voltage Applied Output Voltage VALUE 0oC to 70oC -65oC to 125oC -0.5V to 7.0V -0.5V to 7.0V -0.5V to 7.0V -0.5V to 13.5V
RESET COMMAND
A reset command is provided as a means to safely abort the erase- or program-command sequences. Following either set-up command (erase or program) with two consecutive writes of XXFFH will safely abort the operation. Memory contents will not be altered. Should program-fail or erase-fail happen, two consecutive writes of XXFFH will reset the device to abort the operation. A valid command must then be written to place the device in the desired state.
VCC to Ground Potential VPP
NOTICE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. NOTICE: Specifications contained within the following tables are subject to change.
POWER-UP SEQUENCE
The MX26C1024A powers up in the read only mode. In addition, the memory contents may only be altered after successful completion of a two-step command sequence. At least, one of CE, OE or address pins should be toggled in order to sucessfully complete the first data read during power-up.
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MX26C1024A
CAPACITANCE TA = 25oC, f = 1.0 MHz(Sampled only)
SYMBOL CIN COUT CVPP PARAMETER Input Capacitance Output Capacitance VPP Capacitance MIN. TYP 8 8 25 MAX. 8 12 50 UNIT pF pF pF CONDITIONS VIN = 0V VOUT = 0V VPP= 0V
READ OPERATION DC CHARACTERISTICS TA = 0oC TO 70oC, VCC = 5V 10%, VPP = GND to VCC
SYMBOL ILI ILO IPP1 ISB1 ISB2 ICC1 VIL VIH VOL VOH PARAMETER Input Leakage Current Output Leakage Current VPP Current VCC Standby current VCC Power-Down Current VCC Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 2.4 -0.3(NOTE 1) 2.4 1 MIN. -10 -10 1 TYP MAX. 10 10 100 1 100 40 0.8 VCC + 0.3 0.45 UNIT uA uA uA mA uA mA V V V V (NOTE 2) IOL = 2.1mA IOH = -400mA CONDITIONS VIN = GND to VCC VOUT = GND to VCC VPP = 5.5V CE = VIH CE = VCC + 0.3V IOUT = 0mA, f=5MHz
NOTES: 1. VIL min. = -1.0V for pulse width 50 ns. VIL min. = -2.0V for pulse width 20 ns. 2. VIH max. = VCC + 1.5V for pulse width 20 ns If VIH is over the specified maximum value, read operation cannot be guaranteed.
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MX26C1024A
AC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V 10%, VPP = GND to VCC
26C1024A-70 26C1024A-90 26C1024A-10 26C1024A-12 SYMBOL PARAMETER tACC tCE tOE tDF tOH Address to Output Delay CE to Output Delay OE to Output Delay OE High to Output Float (Note1) 0 Address to Output hold 0 MIN. MAX. MIN. 70 70 35 20 0 0 NOTE: 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. MAX. MIN. 90 90 45 25 0 0 MAX. MIN. 100 100 50 30 0 0 MAX. 120 120 60 35 UNIT CONDITIONS ns ns ns ns ns CE=OE=VIL OE=VIL CE=VIL CE=VIL CE=OE=VIL
TEST CONDITIONS: * Input pulse levels: 0.45V/2.4V * Input rise and fall times: <10ns * Output load: 1 TTL gate + 100pF (Including scope and jig) * Reference levels for measuring timing: 0.8V, 2.0V
READ TIMING WAVEFORMS
ADDRESS
WE
CE STANDBY MODE
ACTIVE MODE tCE
STANDBY MODE
OE tDF tOE* tACC DATA OUT tOH
DATA OUT VALID
* If CE is kept low and address pins are kept at constant during power-up, the time period between OE going low and data out valid shoud be treated as tACC instead of tOE.
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INDEX
MX26C1024A
COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION DC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V 10%, VPP = 12.0V 5%
SYMBOL ILI ILO ISB1 ISB2 ICC1 (Read) ICC2 (Program) ICC3 (Erase) ICC4 (Program Verify) ICC5 (Erase Verify) IPP1 (Read) IPP2 (Program) IPP3 (Erase) IPP4 (Program Verify) IPP5 (Erase Verify) VIL VIH VOL VOH Input Low Voltage Input High Voltage Output LowVoltage Output High Voltage 2.4 -0.3 (Note 5) 2.0 VPP Current VCC Operating Current PARAMETER Input Leakage Current Output Leakage Current VCC Standby current 1 MIN. -10 -10 TYP MAX. 10 10 1 100 30 50 50 50 50 100 50 50 50 50 0.8 UNIT mA mA mA mA mA mA mA mA mA mA mA mA mA mA V CONDITIONS VIN=GND to VCC VOUT=GND to VCC CE=VIH CE=VCC 0.5V IOUT=0mA, f=1MHz In Programming In Erase In Program Verify In Erase Verify VPP=12.6V In Programming In Erase In Program Verify In Erase Verify
VCC+0.5V V 0.45 V V IOL=2.1mA IOH=-400mA
NOTES: 1. VCC must be applied before VPP and removed after VPP. 2. VPP must not exceed 14V including overshoot. 3. An influence may be had upon device reliability if the device is installed or removed while VPP=12V. 4. Do not alter VPP either VIL to 12V or 12V to VIL when CE=VIL. 5. VIL min. = -0.6V for pulse width < 20ns. 6. All currents are in RMS unless otherwise noted.(Sampled, not 100% tested.)
P/N: PM0457
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INDEX
MX26C1024A
AC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V 10%, VPP =12V 5%
26C1024A-70/90/100/120 SYMBOL PARAMETER
tVPS tOES tCWC tCEP tCEPH1 tAS tAH tDS tDH tCES tVPH tDF tEV tPV tCH tCS tPW tPR tEW tER tEVSL tEVSH tPVS VPP setup time OE setup time Command programming cycle WE programming pulse width WE programming pluse width High Address setup time Address hold time Data setup time Data hold time CE setup time VPP hold time Output disable time (Note 3) Erase verify access time Program verify access time CE Hold Time CE setup to WE going low Program Pulse Width Program Reovery Time Erase Pulse Width Erase Recovery Time Erase Verify Setup Pulse Width Low Erase Verify Setup Pulse Width High Program Verify Setup Time 0 0 20 2 0.95 0.5 50 2 0 1.05 30
MIN.
2.0 2.0 90 45 20 0 45 45 10 0 100
MAX.
UNIT
us us ns ns ns ns ns ns ns ns ns
CONTIONS
20 90 90
ns ns ns ns ns us us s s ns us us
NOTES: 1. CE and OE must be fixed high during VPP transition from 5V to 12V or from 12V to 5V. 2. Refer to read operation when VPP=VCC about read operation while VPP 12V. 3. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.
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INDEX
MX26C1024A
SWITCHING TEST CIRCUITS
DEVICE UNDER TEST
1.8K ohm +5V
CL 6.2K ohm
DIODES = IN3064 OR EQUIVALENT
CL = 100 pF including jig capacitance(30pF for 70 ns parts)
SWITCHING TEST WAVEFORMS
2.4V
2.0V TEST POINTS 0.8V
0.4V
2.0V 0.8V OUTPUT
INPUT
AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.4V for a logic "0". Input pulse rise and fall times are <20ns.
SWITCHING TEST WAVEFORMS
3.0V 1.5V 0V
TEST POINTS INPUT OUTPUT
1.5V
AC TESTING: (1) Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0". Input pulse rise and fall times are < 10ns. (2) For MX26C1024A-70 only
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MX26C1024A
PROGRAMMING TIMING WAVEFORM
One word data is programmed. Control verification and additional programming externally according to programming flow chart.
Setup chip program/ program command Chip Program Program Verify
Vcc 5V 12V Vpp 0V
tVPS
Valid Address Valid Address
tVPH
A0 ~ A15 WE
tCWC
tAS tAH
tPVS
CE
tOES tCEP tCEPH1 tCEP tPW
OE
tDS tDH tDS tDH
tPR tPV tDF
Data valid
Q0~Q15
Command in
Data in
Command #XX40H
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INDEX
MX26C1024A
PROGRAMMING FLOW CHART
START
APPLY VPP = VPPH
N=0
WORD PROGRAM SUB-FLOW N= N+1
FAIL VERIFY WORD PASS N= 25?
NO
YES DEVICE FAILED
WORD PROGRAM SUB-FLOW
END INCREMENT ADDRESS NO LAST WORD YES
PROGRAM COMPLETED
WORD PROGRAM SUB-FLOW
START
WRITE SETUP PROGRAM COMMAND (XX40H)
WRITE PROGRAM COMMAND (A/D)
WAIT 25 us
END
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MX26C1024A
CHIP ERASE TIMING WAVEFORM
All data in chip are erased. Control verification and additional erasure externally according to chip erase flowchart.
Setup chip erase/ erase command Chip erase Erase Verify
Vcc 5V 12V Vpp 0V
tVPS
A0 ~ A15 WE
tEVSL tCWC tEVSH
CE
tOES tCEP tCEPH1 tCEP tEW tER tCEP
OE
tDS tDH tDS tDH
Data valid
Q0~Q15
Command in
Command in
Command #XX20H Command #XX20H tEV
tDF
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MX26C1024A
CHIP ERASE FLOWCHART
START
ALL BITS PGM "0"
APPLY VPP =VPPH
N=0
CHIP ERASE SUB-FLOW N = N+1
FAIL ERSVFY FLOW ALL BITS VERIFIED APPLY VPP = VCC END N = 200? YES CHIP ERASE FAIL
NO
CHIP ERASE COMPLETE
CHIP ERASE SUB-FLOW
START
WRITE SETUP CHIP ERASE COMMAND ( XX20H )
CHIP ERASE COMMAND ( XX20H )
WAIT 0.5 s
END
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MX26C1024A
ERASE VERIFY FLOW
START
APPLY VPP = VPPH
ADDRESS = FIRST LOCATION OR LAST VERIFY FAILED ADDRESS
ERASE VERIFY
INCREMENT ADDRESS
ERSVFY FFFFH ?
NO
YES NO LAST ADDRESS ?
YES ERASE VERIFY COMPLETE GO TO ERASE FLOW AGAIN OR ABORT
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MX26C1024A
VPP HIGH READ TIMING WAVEFORM
Vcc 5V 12V Vpp 0V A0 - A15
tVPS
tVPH
Address valid
tCWC
WE
tACC
CE
tOES tCEP tCEPH1
tCE tDF
OE
tDS tDH
tOE
tOH
Q0-Q15
Command in
Command #XX00H
Data out valid
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INDEX
MX26C1024A
VPP HIGH ID CODE READ TIMING WAVEFORM
Vcc 5V 12V Vpp 0V A0
tVPS
tVPH
Address Valid 0 or 1
A1 - A15
tCWC
WE
tACC
CE
tOES tCEP tCEPH2
tCE
OE
tDF tDS tDH tOE tOH
Q0-Q15
Command in
Command #XX90H
Data out valid
00C2H or 00E3H
RESET TIMING WAVEFORM
Vcc 5V 12V Vpp 0V A0 - A16 WE CE
tOES tCEP tCEPH1 tCEP tCWC
tVPS
OE
tDS tDH tDS tDH
Command in
Command in
Command #XXFFH
Q0-Q15
Command #XXFFH
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MX26C1024A
ORDERING INFORMATION PLASTIC PACKAGE
PART NO. ACCESS TIME OPERATING CURRENT (ns) MX26C1024APC-70 MX26C1024AQC-70 MX26C1024ATC-70 MX26C1024APC-90 MX26C1024AQC-90 MX26C1024ATC-90 MX26C1024APC-10 MX26C1024AQC-10 MX26C1024ATC-10 MX26C1024APC-12 MX26C1024AQC-12 MX26C1024ATC-12 70 70 70 90 90 90 100 100 100 120 120 120 MAX.(mA) 40 40 40 40 40 40 40 40 40 40 40 40 STANDBY CURRENT MAX.(uA) 100 100 100 100 100 100 100 100 100 100 100 100 40 Pin PDIP 44 lead PLCC 40 lead TSOP 40 Pin PDIP 44 lead PLCC 40 lead TSOP 40 Pin PDIP 44 lead PLCC 40 lead TSOP 40 Pin PDIP 44 lead PLCC 40 lead TSOP PACKAGE ERASE/PROGRAM CYCLE MIN.(time) 100 100 100 100 100 100 100 100 100 100 100 100
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MX26C1024A
PACKAGE INFORMATION
40-PIN PLASTIC DIP
ITEM A B C D E F G H I J K L M
NOTE:
MILLIMETERS 52.54 max. 0.76 [REF] 2.54 [TP] .46 [Typ.] 50.76 1.27 [Typ.] 3.30 . 25 .51 [REF] 3.94 . 25 5.33 max. 15.22 .25 13.97 .25 .25 [Typ.]
INCHES 2.070 max. .030 [REF] .100 [TP] .018 [Typ.] 2.000 .050 [Typ.] .130 .010 .020 [REF] .155 .010 .210 max. .600 .010 .550 .010 .010 [Typ.]
40
21
1 A
20 K L I H F D E B M J G
C
0~15
Each lead centerline is located within .25 mm[.01 inch] of its true position [TP] at a maximum material condition.
44-PIN PLASTIC LEADED CHIP CARRIER (PLCC)
A 6 7 B 1 44 40 39
ITEM A B C D E F G H I J K L M N
NOTE:
MILLIMETERS 17.53 .12 16.59 .12 16.59 .12 17.53 .12 1.95 4.70 max. 2.55 .25 .51 min. 1.27 [Typ.] .71 .10 .46 .10 15.50 .51 .63 R .25 [Typ.]
INCHES .690 .005 .653 .005 .653 .005 .690 .005 .077 .185 max .100 .010 .020 min. .050 [Typ.] .028 .004 .018 .004 .610 .020 .025 R .010 [Typ.]
FG H I K 17 18 13
33
CD
29 23 28 E N M J L
Each lead centerline is located within .25 mm[.01 inch] of its true position [TP] at a maximum material condition.
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MX26C1024A
40-PIN PLASTIC TSOP
ITEM A B C D E F G H I J K L M N
NOTE:
MILLIMETERS 14.0 .20 12.4 .10 10.1 max. 0.125 [Typ.] .80 [Typ.] .20 .10 .30 .10 .50 [Typ.] .45 max. 0 ~.20 1.00 .10 1.2 max. .50 0 ~ 10
INCHES 0.551 .008 0.488 .004 0.398 max. 0.005 [Typ.] .031 [Typ.] .008 .004 .012 .004 .020[Typ.] 0.18 max. 0 ~ .008 .039 .004 0.047 max. .020 0 ~ 10
D E F G H I J K L N M C A B
Each lead centerline is located within .25 mm[.01 inch] of its true position [TP] at maximum material condition.
P/N: PM0457
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MX26C1024A
Revision History
Revision # 1.2 Description Chip erase timing waveform: OE toggle during erase verify. Change Part Name: 26C1024 ---> 26C1024A. Delete SOP package. Modify CE and OE waveforms for chip erase timing waveform. Delete tEVS spec and add tEVSL and tEVSH spec for AC characteristics. Modify AC CHARACTERISTICS 1.modify the silicom-ID-Read command description 2.modify the power-Up SEQUENCE description 3.Add comment on READ TIMING WAVEFORMS 4.correct the AC characteristics of tER Modify CE and OE waveforms for Program Verify of programming timing waveform. 1.Correct active current to 40mA in page 6 and page 18 2.modify the power-up sequence description and CVPP value Page Date 11/05/1997
1.3 1.4 1.5
P13 P9 P7
12/10/1997 02/18/1998 06/11/1998
1.6 1.7
P11 P6,P18 P5,P6
10/27/1998 12/07/1998
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MX26C1024A
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-8888 FAX:+886-3-578-8887
EUROPE OFFICE:
TEL:+32-2-456-8020 FAX:+32-2-456-8021
JAPAN OFFICE:
TEL:+81-44-246-9100 FAX:+81-44-246-9105
SINGAPORE OFFICE:
TEL:+65-747-2309 FAX:+65-748-4090
TAIPEI OFFICE:
TEL:+886-3-509-3300 FAX:+886-3-509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-453-8088 FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900 FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice.
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Price & Availability of 26C1024A

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